diff --git a/Makefile b/Makefile
index 78eff14..a54eedb 100644
--- a/Makefile
+++ b/Makefile
@@ -15,22 +15,28 @@
 # SPDX-License-Identifier: Apache-2.0
 MAKEFLAGS+=--warn-undefined-variables
 
-CARAVEL_ROOT?=$(PWD)/caravel
+export CARAVEL_ROOT?=$(PWD)/caravel
 PRECHECK_ROOT?=${HOME}/mpw_precheck
-MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+export MCW_ROOT?=$(PWD)/mgmt_core_wrapper
 SIM?=RTL
 DUMP?=OFF
 RISC_CORE ?=0
 
-export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-export OPEN_PDKS_COMMIT=7519dfb04400f224f140749cda44ee7de6f5e095
-export PDK_MAGIC_COMMIT=7d601628e4e05fd17fcb80c3552dacb64e9f6e7b
-export OPENLANE_TAG=2022.02.23_02.50.41
-
 # Install lite version of caravel, (1): caravel-lite, (0): caravel
 CARAVEL_LITE?=1
 
-MPW_TAG ?= mpw-5c
+# PDK switch varient
+export PDK?=sky130A
+#export PDK?=gf180mcuC
+export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
+
+
+ifeq ($(PDK),sky130A)
+	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+	export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPENLANE_TAG?=2022.10.20
+	MPW_TAG ?= mpw-7g
 
 ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
@@ -42,8 +48,7 @@
 	CARAVEL_TAG := $(MPW_TAG)
 endif
 
-# Install caravel as submodule, (1): submodule, (0): clone
-SUBMODULE?=1
+endif
 
 #RISCV COMPLIANCE test Environment
 COREMARK_DIR   = verilog/dv/riscv_regress/dependencies/coremark
@@ -58,6 +63,36 @@
 RISCV_COMP_BRANCH =  d51259b2a949be3af02e776c39e135402675ac9b
 RISCV_TEST_BRANCH =  e30978a71921159aec38eeefd848fca4ed39a826
 
+ifeq ($(PDK),sky130B)
+	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+	export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPENLANE_TAG?=2022.10.20
+	MPW_TAG ?= mpw-7g
+
+ifeq ($(CARAVEL_LITE),1)
+	CARAVEL_NAME := caravel-lite
+	CARAVEL_REPO := https://github.com/efabless/caravel-lite
+	CARAVEL_TAG := $(MPW_TAG)
+else
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel
+	CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+ifeq ($(PDK),gf180mcuC)
+
+	MPW_TAG ?= gfmpw-0a
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu
+	CARAVEL_TAG := $(MPW_TAG)
+	#OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
+	export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPENLANE_TAG?=2022.11.17
+
+endif
+
 # Include Caravel Makefile Targets
 .PHONY: % : check-caravel
 %:
@@ -78,13 +113,13 @@
 	docker pull riscduino/dv_setup:mpw6
 
 .PHONY: setup
-setup: install check-env install_mcw pdk openlane
+setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
 
 # Openlane
 blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
 .PHONY: $(blocks)
 $(blocks): % :
-	export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
+	$(MAKE) -C openlane $*
 
 
 PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
@@ -111,6 +146,11 @@
 # Install Openlane
 .PHONY: openlane
 openlane:
+	@if [ "$$(realpath $${OPENLANE_ROOT})" = "$$(realpath $$(pwd)/openlane)" ]; then\
+		echo "OPENLANE_ROOT is set to '$$(pwd)/openlane' which contains openlane config files"; \
+		echo "Please set it to a different directory"; \
+		exit 1; \
+	fi
 	cd openlane && $(MAKE) openlane
 
 #### Not sure if the targets following are of any use
@@ -225,40 +265,65 @@
 	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
 
-## New Task from Caravel Makefile
-LVS_GDS_BLOCKS = $(foreach block, $(BLOCKS), lvs-gds-$(block))
-$(LVS_GDS_BLOCKS): lvs-gds-% : ./gds/%.gds ./verilog/gl/%.v
-	echo "Extracting $*"
-	mkdir -p ./gds/tmp
-	echo "	gds flatglob \"*_example_*\";\
-		gds flatten true;\
-		gds read ./$*.gds;\
-		load $* -dereference;\
-		select top cell;\
-		extract no all;\
-		extract do local;\
-		extract unique;\
-		extract;\
-		ext2spice lvs;\
-		ext2spice $*.ext;\
-		feedback save extract_$*.log;\
-		exit;" > ./gds/extract_$*.tcl
-	cd gds && \
-		magic -rcfile ${PDK_ROOT}/$(PDK)/libs.tech/magic/$(PDK).magicrc -noc -dnull extract_$*.tcl < /dev/null
-	mv ./gds/$*.spice ./spi/lvs
-	rm ./gds/*.ext
-	mv -f ./gds/extract_$*.tcl ./gds/tmp
-	mv -f ./gds/extract_$*.log ./gds/tmp
-	####
-	mkdir -p ./spi/lvs/tmp
-	MAGIC_EXT_USE_GDS=1 sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
-	@echo ""
-	python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.lvs.summary.log
-	mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
-	mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
-	mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
-	@echo ""
-	@echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
-	@echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
-	@awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
 
+export CUP_ROOT=$(shell pwd)
+export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
+timing-scripts-repo=https://github.com/efabless/timing-scripts.git
+
+$(TIMING_ROOT):
+	@mkdir -p $(CUP_ROOT)/deps
+	@git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
+.PHONY: setup-timing-scripts
+setup-timing-scripts: $(TIMING_ROOT)
+	@( cd $(TIMING_ROOT) && git pull )
+	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
+	@python3 -m venv ./venv 
+		. ./venv/bin/activate && \
+		python3 -m pip install --upgrade pip && \
+		python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
+		deactivate
+
+./verilog/gl/user_project_wrapper.v:
+	$(error you don't have $@)
+
+./env/spef-mapping.tcl: 
+	@echo "run the following:"
+	@echo "make extract-parasitics"
+	@echo "make create-spef-mapping"
+	exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./env/spef-mapping.tcl \
+			--pdk-path $(PDK_ROOT)/$(PDK) \
+			--macro-parent mprj \
+			--project-root "$(CUP_ROOT)" && \
+		deactivate
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/get_macros.py \
+		-i ./verilog/gl/user_project_wrapper.v \
+		-o ./tmp-macros-list \
+		--project-root "$(CUP_ROOT)" \
+		--pdk-path $(PDK_ROOT)/$(PDK) && \
+		deactivate
+		@cat ./tmp-macros-list | cut -d " " -f2 \
+			| xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+				-f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+	@cat ./tmp-macros-list
+	@rm ./tmp-macros-list
+	
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/README.md b/README.md
index 71b2b80..5086ae1 100644
--- a/README.md
+++ b/README.md
@@ -545,6 +545,67 @@
    make user_project_wrapper
 ```
 
+#Timing Analysis
+## Timing Analysis setup
+   
+``` sh
+   make setup-timing-scripts
+   make install
+   make install_mcw
+```
+his will update Caravel design files and install the scripts for running timing.
+
+## Running Timing Analysis
+
+``` sh
+make extract-parasitics
+make create-spef-mapping
+make caravel-sta
+```
+#Other Miscellaneous Targets
+The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow.
+
+Run make help to display available targets.
+
+Run lvs on the mag view,
+
+``` sh
+make lvs-<macro_name>
+```
+
+Run lvs on the gds,
+
+``` sh
+make lvs-gds-<macro_name>
+```
+
+Run lvs on the maglef,
+
+``` sh
+make lvs-maglef-<macro_name>
+```
+
+Run drc using magic,
+
+``` sh
+make drc-<macro_name>
+```
+
+Run antenna check using magic,
+
+``` sh
+make antenna-<macro_name>
+```
+
+Run XOR check,
+
+``` sh
+make xor-wrapper
+```
+
+
+
+
 # Tool Sets
 
 Riscduino Soc flow uses Openlane tool sets.
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2c_usb_spi_top/base.sdc
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/base.sdc
rename to openlane/uart_i2c_usb_spi_top/base.sdc
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2c_usb_spi_top/config.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/config.tcl
rename to openlane/uart_i2c_usb_spi_top/config.tcl
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/uart_i2c_usb_spi_top/pdn.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/pdn.tcl
rename to openlane/uart_i2c_usb_spi_top/pdn.tcl
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/pin_order.cfg
rename to openlane/uart_i2c_usb_spi_top/pin_order.cfg
diff --git a/openlane/uart_i2cm_usb_spi_top/sta.tcl b/openlane/uart_i2c_usb_spi_top/sta.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/sta.tcl
rename to openlane/uart_i2c_usb_spi_top/sta.tcl
diff --git a/signoff/clk_buf/OPENLANE_VERSION b/signoff/clk_buf/OPENLANE_VERSION
deleted file mode 100644
index a2633b1..0000000
--- a/signoff/clk_buf/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane rc7
diff --git a/signoff/clk_buf/PDK_SOURCES b/signoff/clk_buf/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/clk_buf/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/clk_buf/final_summary_report.csv b/signoff/clk_buf/final_summary_report.csv
deleted file mode 100644
index f6ee716..0000000
--- a/signoff/clk_buf/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_buf,clk_buf,clk_buf,Flow_completed,0h1m2s,0h0m26s,925.925925925926,0.0018,555.5555555555555,3,382.24,1,0,0,0,0,0,0,0,0,0,0,0,45,4,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,49267,0.0,0.58,0.26,0.0,-1,-1,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,14,13,0,27,90.9090909090909,11,10,AREA 0,5,60,1,30,30,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/clk_skew_adjust/OPENLANE_VERSION b/signoff/clk_skew_adjust/OPENLANE_VERSION
deleted file mode 100644
index ad796aa..0000000
--- a/signoff/clk_skew_adjust/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane v0.21-6-gbc3b032
diff --git a/signoff/clk_skew_adjust/PDK_SOURCES b/signoff/clk_skew_adjust/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/clk_skew_adjust/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv
deleted file mode 100644
index 6c84744..0000000
--- a/signoff/clk_skew_adjust/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m15s,0h0m36s,7500.0,0.01,3000.0,5,391.95,30,0,0,0,0,0,0,0,0,0,0,0,2812,197,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,6.42,6.62,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,64,102,0,166,90.9090909090909,11,10,AREA 0,5,40,1,20,20,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/digital_pll/OPENLANE_VERSION b/signoff/digital_pll/OPENLANE_VERSION
deleted file mode 100644
index b5bf449..0000000
--- a/signoff/digital_pll/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/digital_pll/PDK_SOURCES b/signoff/digital_pll/PDK_SOURCES
deleted file mode 100644
index f9d0f46..0000000
--- a/signoff/digital_pll/PDK_SOURCES
+++ /dev/null
@@ -1 +0,0 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION
deleted file mode 100644
index ad796aa..0000000
--- a/signoff/glbl_cfg/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane v0.21-6-gbc3b032
diff --git a/signoff/glbl_cfg/PDK_SOURCES b/signoff/glbl_cfg/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/glbl_cfg/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
deleted file mode 100644
index 68bccb3..0000000
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h15m36s,0h9m28s,45883.33333333334,0.12,22941.66666666667,40,569.11,2753,0,0,0,0,0,0,0,0,0,-1,0,131923,23407,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,25.3,27.26,0.31,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/mbist/OPENLANE_VERSION b/signoff/mbist/OPENLANE_VERSION
deleted file mode 100644
index 80c7664..0000000
--- a/signoff/mbist/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane N/A
diff --git a/signoff/mbist/PDK_SOURCES b/signoff/mbist/PDK_SOURCES
deleted file mode 100644
index ca3684a..0000000
--- a/signoff/mbist/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist/final_summary_report.csv b/signoff/mbist/final_summary_report.csv
deleted file mode 100644
index 78824ce..0000000
--- a/signoff/mbist/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/mbist,mbist_top,mbist,flow_completed,0h11m2s,-1,20833.333333333336,0.3,10416.666666666668,13.1,663.13,3125,0,0,0,0,0,0,0,10,0,0,-1,458568,43437,-0.67,-6.26,-1,-1.39,-1,-0.67,-3033.14,-1,-1.39,-1,372704250.0,1.47,48.85,12.24,20.92,0.0,-1,2382,6613,753,4936,0,0,0,2339,0,0,0,0,0,0,0,4,849,672,17,130,3852,0,3982,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/mbist_wrapper/OPENLANE_VERSION b/signoff/mbist_wrapper/OPENLANE_VERSION
deleted file mode 100644
index 80c7664..0000000
--- a/signoff/mbist_wrapper/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane N/A
diff --git a/signoff/mbist_wrapper/PDK_SOURCES b/signoff/mbist_wrapper/PDK_SOURCES
deleted file mode 100644
index ca3684a..0000000
--- a/signoff/mbist_wrapper/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist_wrapper/final_summary_report.csv b/signoff/mbist_wrapper/final_summary_report.csv
deleted file mode 100644
index b6c97f9..0000000
--- a/signoff/mbist_wrapper/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/mbist_wrapper,mbist_wrapper,mbist_wrapper,flow_completed,0h14m13s,-1,26073.260073260073,0.273,13036.630036630037,16.48,695.21,3559,0,0,0,0,0,0,-1,16,0,0,-1,445806,47865,-0.67,-5.91,-1,-1.78,-1,-0.67,-2737.45,-1,-1.78,-1,357342288.0,5.91,47.85,15.03,24.02,0.01,-1,2596,7282,753,5382,0,0,0,2664,0,0,0,0,0,0,0,4,1049,798,17,138,3514,0,3652,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/sar_adc/OPENLANE_VERSION b/signoff/sar_adc/OPENLANE_VERSION
deleted file mode 100644
index bab6e84..0000000
--- a/signoff/sar_adc/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane v0.21-9-g94fe743
diff --git a/signoff/sar_adc/PDK_SOURCES b/signoff/sar_adc/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/sar_adc/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/sar_adc/final_summary_report.csv b/signoff/sar_adc/final_summary_report.csv
deleted file mode 100644
index 17383a9..0000000
--- a/signoff/sar_adc/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sar_adc,sar_adc,sar_adc,Flow_completed,0h1m45s,0h0m56s,1653.3333333333335,0.15,826.6666666666667,1,440.52,124,0,0,0,0,0,0,0,0,13,-1,0,14549,1000,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,12946929,0.0,3.68,1.92,0.36,0.0,-1,102,186,48,132,0,0,0,124,0,0,0,1,12,0,0,32,19,26,5,204,1768,0,1972,10.0,100.0,100,AREA 0,5,50,1,45,40,0.01,0.15,sky130_fd_sc_hd,4,4
diff --git a/signoff/sdc/caravel.sdc b/signoff/sdc/caravel.sdc
new file mode 100644
index 0000000..fbcf82d
--- /dev/null
+++ b/signoff/sdc/caravel.sdc
@@ -0,0 +1,318 @@
+### Caravel Signoff SDC
+### Rev 3
+### Date: 28/10/2022
+
+## MASTER CLOCKS
+create_clock -name clk -period 25 [get_ports {clock}] 
+
+create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ] 
+create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
+# hk_serial_clk period is x2 core clock
+
+### User Project Clocks
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name int_pll_clock -period 5.0000  [get_pins {mprj/u_pinmux/int_pll_clock}]
+
+create_clock -name wbs_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_clk_i   -period 10.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
+
+create_clock -name cpu_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_clk     -period 10.0000  [get_pins {mprj/u_wb_host/cpu_clk}]
+
+create_clock -name rtc_ref_clk -period 50.0000  [get_pins {mprj/u_pinmux/u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk     -period 50.0000  [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+
+create_clock -name pll_ref_clk -period 20.0000  [get_pins {mprj/u_pinmux/pll_ref_clk}]
+create_clock -name pll_clk_0   -period 5.0000   [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 5.0000   [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name usb_clk     -period 20.0000  [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_usb.u_buf/X}]
+create_clock -name uarts0_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk   -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+set_clock_uncertainty 0.1000 [all_clocks]
+
+set_clock_groups \
+   -name clock_group \
+   -logically_exclusive \
+   -group [get_clocks {wb_clk clk}]\
+   -group [get_clocks {hk_serial_clk}]\
+   -group [get_clocks {hk_serial_load}]\
+   -group [get_clocks {hkspi_clk}]\
+   -group [get_clocks {int_pll_clock}]\
+   -group [get_clocks {wbs_clk_i}]\
+   -group [get_clocks {wbs_ref_clk}]\
+   -group [get_clocks {cpu_clk}]\
+   -group [get_clocks {cpu_ref_clk}]\
+   -group [get_clocks {rtc_clk}]\
+   -group [get_clocks {usb_ref_clk}]\
+   -group [get_clocks {pll_ref_clk}]\
+   -group [get_clocks {pll_clk_0}]\
+   -group [get_clocks {usb_clk}]\
+   -group [get_clocks {uarts0_clk}]\
+   -group [get_clocks {uarts1_clk}]\
+   -group [get_clocks {uartm_clk}]\
+   -group [get_clocks {dbg_ref_clk}]\
+   -group [get_clocks {rtc_ref_clk}]\
+   -comment {Async Clock group}
+
+# clock <-> hk_serial_clk/load no paths
+# future note: CDC stuff
+# clock <-> hkspi_clk no paths with careful methods (clock is off)
+
+set_propagated_clock [all_clocks]
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 4
+set output_delay_value 4
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
+
+#set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_input_delay $input_delay_value  -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value  -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
+
+#set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
+
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
+
+# set_output_delay $output_delay_value  -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_max_fanout 12 [current_design]
+# synthesis max fanout should be less than 12 (7 maybe)
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled 
+set_case_analysis 0 [get_pins housekeeping/_3936_/S]
+set_case_analysis 0 [get_pins housekeeping/_3937_/S]
+
+# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
+
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
+set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
+
+# the following pads are set as inputs
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]]
+
+
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
+set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
+
+#################################################################
+## User Case analysis
+#################################################################
+
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+
+# clock skew cntrl-2
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[0]}]
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+
+## Async USB/I2C Interrupt, Double Sync added inside glbl block
+set_false_path -through [get_pins {mprj/u_pinmux/usb_intr}]
+set_false_path -through [get_pins {mprj/u_pinmux/i2cm_intr}]
+
+# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
+# reset_path -from [get_ports mprj_io[4]] 
+# reset_path -from [get_ports mprj_io[2]] 
+#reset_path is not supported in PT read_sdc ^
+
+set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
+set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
+set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
+set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]]
+set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]]
+set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]]
+set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]]
+set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]]
+set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]]
+set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]]
+set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]]
+set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]]
+set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]]
+set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]]
+set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]]
+set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]]
+set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]]
+set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]]
+set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]]
+set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]]
+set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]]
+set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]]
+set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]]
+set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]]
+set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]]
+set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]]
+set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]]
+set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]]
+set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]]
+set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]]
+set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]]
+set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]]
+set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]]
+set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]]
+set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]]
+set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]]
+
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
+set_false_path -from [get_ports gpio]
+
+# add loads for output ports (pads)
+set min_cap 5
+set max_cap 10
+puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
+# set_load 10 [all_outputs]
+set_load -min $min_cap [all_outputs] 
+set_load -max $max_cap [all_outputs] 
+
+#add input transition for the inputs ports (pads)
+# set_input_transition 2 [all_inputs]
+#add exception for power pads as 2ns on them results in max_tran violations (false viol)
+# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]] 
+# remove_from_collection is not supported in PT read_sdc ^
+# set_input_transition 2 [all_inputs] 
+# set_input_transition 0 [get_ports v*]
+
+set min_in_tran 1
+set max_in_tran 4
+puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
+set_input_transition -min $min_in_tran [all_inputs] 
+set_input_transition -min 0 [get_ports v*]
+set_input_transition -max $max_in_tran [all_inputs]
+set_input_transition -max 0 [get_ports v*]
+
+# check ocv table (not provided) -- maybe try 8% 
+set derate 0.0375
+puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
+set_timing_derate -early [expr 1-$derate]
+set_timing_derate -late [expr 1+$derate]
+
+# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
+# apply the constraint to hd cells at the ss corner only
+# if {$::env(PROC_CORNER) == "s"} {
+#    set max_tran 1.5
+#    set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
+#    set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
+#    set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
+#    puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
+# }
+# -filter not supported in PT read_sdc ^
diff --git a/signoff/sdram/OPENLANE_VERSION b/signoff/sdram/OPENLANE_VERSION
deleted file mode 100644
index bab6e84..0000000
--- a/signoff/sdram/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane v0.21-9-g94fe743
diff --git a/signoff/sdram/PDK_SOURCES b/signoff/sdram/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/sdram/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
deleted file mode 100644
index 24acce0..0000000
--- a/signoff/sdram/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h17m16s,0h6m17s,40708.57142857143,0.35,20354.285714285714,30,662.62,7124,0,0,0,0,0,0,0,0,0,-1,0,316920,56671,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,242866426,0.0,25.86,16.86,2.54,-1,-1,7028,7287,1219,1478,0,0,0,7124,196,107,83,98,352,210,34,2240,1267,1186,23,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/spi_master/OPENLANE_VERSION b/signoff/spi_master/OPENLANE_VERSION
deleted file mode 100644
index bab6e84..0000000
--- a/signoff/spi_master/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane v0.21-9-g94fe743
diff --git a/signoff/spi_master/PDK_SOURCES b/signoff/spi_master/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/spi_master/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
deleted file mode 100644
index 8e28748..0000000
--- a/signoff/spi_master/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h20m39s,0h10m39s,58438.46153846153,0.26,29219.230769230766,47,664.71,7597,0,0,0,0,0,0,0,0,3,-1,0,384228,67124,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,294776771,0.0,31.33,39.79,0.04,-1,-1,7537,7673,1268,1404,0,0,0,7597,245,0,169,100,1051,210,32,2443,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/syntacore/OPENLANE_VERSION b/signoff/syntacore/OPENLANE_VERSION
deleted file mode 100644
index 80c7664..0000000
--- a/signoff/syntacore/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane N/A
diff --git a/signoff/syntacore/PDK_SOURCES b/signoff/syntacore/PDK_SOURCES
deleted file mode 100644
index ca3684a..0000000
--- a/signoff/syntacore/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
deleted file mode 100644
index 04c97bd..0000000
--- a/signoff/syntacore/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h41m48s,-1,53830.971659919036,0.7904,26915.485829959518,30.93,1195.5,21274,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1674760,240681,-2.04,-17.8,-1,0.0,-1,-2459.49,-21655.63,-1,0.0,-1,1322263875.0,0.0,62.03,24.69,26.16,0.01,-1,18597,30067,1067,12430,0,0,0,21980,0,0,0,0,0,0,0,4,5240,5924,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart/OPENLANE_VERSION b/signoff/uart/OPENLANE_VERSION
deleted file mode 100644
index a2633b1..0000000
--- a/signoff/uart/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane rc7
diff --git a/signoff/uart/PDK_SOURCES b/signoff/uart/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/uart/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
deleted file mode 100644
index 5d02b7b..0000000
--- a/signoff/uart/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h6m24s,0h4m13s,46166.66666666667,0.12,23083.333333333336,35,545.14,2770,0,0,0,0,0,0,0,0,0,-1,0,93784,20982,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm/OPENLANE_VERSION b/signoff/uart_i2cm/OPENLANE_VERSION
deleted file mode 100644
index a2633b1..0000000
--- a/signoff/uart_i2cm/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane rc7
diff --git a/signoff/uart_i2cm/PDK_SOURCES b/signoff/uart_i2cm/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/uart_i2cm/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart_i2cm/final_summary_report.csv b/signoff/uart_i2cm/final_summary_report.csv
deleted file mode 100644
index 6a4c74e..0000000
--- a/signoff/uart_i2cm/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm,uart_i2c_top,uart_i2cm,Flow_completed,0h5m42s,0h3m37s,59350.0,0.12,29675.0,47,561.56,3561,0,0,0,0,0,0,0,0,0,-1,0,124117,27523,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,81974377,0.0,25.57,25.46,0.33,-1,-1,3562,3582,623,643,0,0,0,3561,98,10,58,70,423,155,27,836,589,556,17,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb/OPENLANE_VERSION b/signoff/uart_i2cm_usb/OPENLANE_VERSION
deleted file mode 100644
index bab6e84..0000000
--- a/signoff/uart_i2cm_usb/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane v0.21-9-g94fe743
diff --git a/signoff/uart_i2cm_usb/PDK_SOURCES b/signoff/uart_i2cm_usb/PDK_SOURCES
deleted file mode 100644
index 8b58bd5..0000000
--- a/signoff/uart_i2cm_usb/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
--ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
--ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv
deleted file mode 100644
index 2c0683d..0000000
--- a/signoff/uart_i2cm_usb/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,Flow_completed,0h25m24s,0h9m59s,59157.14285714286,0.42,29578.57142857143,45,758.68,12423,0,0,0,0,0,0,0,0,0,-1,0,522443,99881,-3.16,-3.16,-3.07,-3.07,-3.11,-91.08,-91.08,-91.67,-91.67,-91.56,390283627,0.0,31.24,29.46,0.31,-1,-1,12407,12476,2262,2331,0,0,0,12423,364,10,202,244,2118,325,79,2692,2224,2170,26,498,5146,0,5644,76.27765064836004,13.11,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
deleted file mode 100644
index 80c7664..0000000
--- a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane N/A
diff --git a/signoff/uart_i2cm_usb_spi/PDK_SOURCES b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
deleted file mode 100644
index ca3684a..0000000
--- a/signoff/uart_i2cm_usb_spi/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
deleted file mode 100644
index 1c71b64..0000000
--- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h16m31s,-1,64462.85714285714,0.35,32231.42857142857,37.52,801.87,11281,0,0,0,0,0,0,0,1,0,-1,-1,442250,99040,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,270825594.0,3.05,31.16,29.59,1.14,0.29,-1,8696,13075,1555,5877,0,0,0,9816,0,0,0,0,0,0,0,4,2700,2702,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
deleted file mode 100644
index b5bf449..0000000
--- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
deleted file mode 100644
index f9d0f46..0000000
--- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
+++ /dev/null
@@ -1 +0,0 @@
-open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
deleted file mode 100644
index ca6c2a3..0000000
--- a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h30m23s0ms,0h22m25s0ms,78025.69303583504,0.36975,39012.84651791752,44.35,1490.59,14425,0,0,0,0,0,0,0,-1,0,-1,-1,702950,122604,0.0,-0.0,0.0,0.0,0.0,0.0,-0.0,0.0,0.0,0.0,442593619.0,0.0,56.86,57.94,21.95,25.41,-1,10340,15543,1940,7056,0,0,0,11580,425,250,279,358,2406,481,113,1133,2832,2749,18,516,4940,0,5456,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/yifive/OPENLANE_VERSION b/signoff/yifive/OPENLANE_VERSION
deleted file mode 100644
index 80c7664..0000000
--- a/signoff/yifive/OPENLANE_VERSION
+++ /dev/null
@@ -1 +0,0 @@
-openlane N/A
diff --git a/signoff/yifive/PDK_SOURCES b/signoff/yifive/PDK_SOURCES
deleted file mode 100644
index ca3684a..0000000
--- a/signoff/yifive/PDK_SOURCES
+++ /dev/null
@@ -1,6 +0,0 @@
--ne openlane 
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk 
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks 
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv
deleted file mode 100644
index 9ce9289..0000000
--- a/signoff/yifive/final_summary_report.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h23m37s,-1,54940.642179905975,1.2551,27470.321089952988,30.97,1607.58,34478,0,0,0,0,0,0,0,33,0,-1,-1,2753267,389772,-15.47,-48.52,-1,-1.05,-1,-34117.75,-19828.04,-1,-6.64,-1,2065115550.0,17.89,40.67,58.45,4.63,5.31,-1,28633,48324,1779,21063,0,0,0,34183,0,0,0,0,0,0,0,4,8286,8734,54,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4