diff --git a/openlane/aes_top/base.sdc b/openlane/aes_top/base.sdc
new file mode 100644
index 0000000..f81deda
--- /dev/null
+++ b/openlane/aes_top/base.sdc
@@ -0,0 +1,276 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov  7 16:29:34 2022
+###############################################################################
+current_design aes_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_int}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_out}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/aes_top/config.tcl b/openlane/aes_top/config.tcl
new file mode 100755
index 0000000..036e145
--- /dev/null
+++ b/openlane/aes_top/config.tcl
@@ -0,0 +1,125 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) aes_top
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/core/aes_cipher_top.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/core/aes_inv_cipher_top.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/core/aes_inv_sbox.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/core/aes_key_expand_128.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/core/aes_rcon.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/core/aes_sbox.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/top/aes_top.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/security_core/verilog/rtl/aes128/top/aes_reg.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 850 650"
+
+set ::env(GRT_ADJUSTMENT) 0.2
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.42"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+#set ::env(FP_IO_VEXTEND) 4
+#set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {0}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/aes_top/pin_order.cfg b/openlane/aes_top/pin_order.cfg
new file mode 100644
index 0000000..1d8dedd
--- /dev/null
+++ b/openlane/aes_top/pin_order.cfg
@@ -0,0 +1,97 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#W
+
+mclk               0100 0 2
+rst_n 
+cfg_cska\[3\]
+cfg_cska\[2\]
+cfg_cska\[1\]
+cfg_cska\[0\]
+wbd_clk_int
+wbd_clk_out
+
+
+
+#S
+dmem_req_ack    690 0 2
+dmem_req         
+dmem_cmd  
+dmem_width\[1\]
+dmem_width\[0\]
+dmem_addr\[6\]     
+dmem_addr\[5\]     
+dmem_addr\[4\]     
+dmem_addr\[3\]     
+dmem_addr\[2\]     
+dmem_addr\[1\]     
+dmem_addr\[0\]   
+dmem_wdata\[31\]
+dmem_wdata\[30\]
+dmem_wdata\[29\]
+dmem_wdata\[28\]
+dmem_wdata\[27\]
+dmem_wdata\[26\]
+dmem_wdata\[25\]
+dmem_wdata\[24\]
+dmem_wdata\[23\]
+dmem_wdata\[22\]
+dmem_wdata\[21\]
+dmem_wdata\[20\]
+dmem_wdata\[19\]
+dmem_wdata\[18\]
+dmem_wdata\[17\]
+dmem_wdata\[16\]
+dmem_wdata\[15\]
+dmem_wdata\[14\]
+dmem_wdata\[13\]
+dmem_wdata\[12\]
+dmem_wdata\[11\]
+dmem_wdata\[10\]
+dmem_wdata\[9\]
+dmem_wdata\[8\]
+dmem_wdata\[7\]
+dmem_wdata\[6\]
+dmem_wdata\[5\]
+dmem_wdata\[4\]
+dmem_wdata\[3\]
+dmem_wdata\[2\]
+dmem_wdata\[1\]
+dmem_wdata\[0\]
+dmem_rdata\[31\]
+dmem_rdata\[30\]
+dmem_rdata\[29\]
+dmem_rdata\[28\]
+dmem_rdata\[27\]
+dmem_rdata\[26\]
+dmem_rdata\[25\]
+dmem_rdata\[24\]
+dmem_rdata\[23\]
+dmem_rdata\[22\]
+dmem_rdata\[21\]
+dmem_rdata\[20\]
+dmem_rdata\[19\]
+dmem_rdata\[18\]
+dmem_rdata\[17\]
+dmem_rdata\[16\]
+dmem_rdata\[15\]
+dmem_rdata\[14\]
+dmem_rdata\[13\]
+dmem_rdata\[12\]
+dmem_rdata\[11\]
+dmem_rdata\[10\]
+dmem_rdata\[9\]
+dmem_rdata\[8\]
+dmem_rdata\[7\]
+dmem_rdata\[6\]
+dmem_rdata\[5\]
+dmem_rdata\[4\]
+dmem_rdata\[3\]
+dmem_rdata\[2\]
+dmem_rdata\[1\]
+dmem_rdata\[0\]
+dmem_resp\[1\]
+dmem_resp\[0\]
diff --git a/openlane/fpu_wrapper/base.sdc b/openlane/fpu_wrapper/base.sdc
new file mode 100644
index 0000000..9a5897d
--- /dev/null
+++ b/openlane/fpu_wrapper/base.sdc
@@ -0,0 +1,271 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov  7 16:29:34 2022
+###############################################################################
+current_design fpu_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_int}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_out}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/fpu_wrapper/config.tcl b/openlane/fpu_wrapper/config.tcl
new file mode 100755
index 0000000..801561e
--- /dev/null
+++ b/openlane/fpu_wrapper/config.tcl
@@ -0,0 +1,125 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) fpu_wrapper
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu_wrapper/src/fpu_wrapper.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu_wrapper/src/fpu_reg.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_top.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_mul.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_div.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_add.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_f2i.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_i2f.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 550 550"
+
+set ::env(GRT_ADJUSTMENT) 0.2
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.43"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+#set ::env(FP_IO_VEXTEND) 4
+#set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {0}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/fpu_wrapper/pin_order.cfg b/openlane/fpu_wrapper/pin_order.cfg
new file mode 100644
index 0000000..3cf0a29
--- /dev/null
+++ b/openlane/fpu_wrapper/pin_order.cfg
@@ -0,0 +1,95 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#W
+
+mclk               0100 0 2
+rst_n 
+cfg_cska\[3\]
+cfg_cska\[2\]
+cfg_cska\[1\]
+cfg_cska\[0\]
+wbd_clk_int
+wbd_clk_out
+
+
+
+#S
+dmem_req_ack    
+dmem_req         
+dmem_cmd  
+dmem_width\[1\]
+dmem_width\[0\]
+dmem_addr\[4\]     
+dmem_addr\[3\]     
+dmem_addr\[2\]     
+dmem_addr\[1\]     
+dmem_addr\[0\]   
+dmem_wdata\[31\]
+dmem_wdata\[30\]
+dmem_wdata\[29\]
+dmem_wdata\[28\]
+dmem_wdata\[27\]
+dmem_wdata\[26\]
+dmem_wdata\[25\]
+dmem_wdata\[24\]
+dmem_wdata\[23\]
+dmem_wdata\[22\]
+dmem_wdata\[21\]
+dmem_wdata\[20\]
+dmem_wdata\[19\]
+dmem_wdata\[18\]
+dmem_wdata\[17\]
+dmem_wdata\[16\]
+dmem_wdata\[15\]
+dmem_wdata\[14\]
+dmem_wdata\[13\]
+dmem_wdata\[12\]
+dmem_wdata\[11\]
+dmem_wdata\[10\]
+dmem_wdata\[9\]
+dmem_wdata\[8\]
+dmem_wdata\[7\]
+dmem_wdata\[6\]
+dmem_wdata\[5\]
+dmem_wdata\[4\]
+dmem_wdata\[3\]
+dmem_wdata\[2\]
+dmem_wdata\[1\]
+dmem_wdata\[0\]
+dmem_rdata\[31\]
+dmem_rdata\[30\]
+dmem_rdata\[29\]
+dmem_rdata\[28\]
+dmem_rdata\[27\]
+dmem_rdata\[26\]
+dmem_rdata\[25\]
+dmem_rdata\[24\]
+dmem_rdata\[23\]
+dmem_rdata\[22\]
+dmem_rdata\[21\]
+dmem_rdata\[20\]
+dmem_rdata\[19\]
+dmem_rdata\[18\]
+dmem_rdata\[17\]
+dmem_rdata\[16\]
+dmem_rdata\[15\]
+dmem_rdata\[14\]
+dmem_rdata\[13\]
+dmem_rdata\[12\]
+dmem_rdata\[11\]
+dmem_rdata\[10\]
+dmem_rdata\[9\]
+dmem_rdata\[8\]
+dmem_rdata\[7\]
+dmem_rdata\[6\]
+dmem_rdata\[5\]
+dmem_rdata\[4\]
+dmem_rdata\[3\]
+dmem_rdata\[2\]
+dmem_rdata\[1\]
+dmem_rdata\[0\]
+dmem_resp\[1\]
+dmem_resp\[0\]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 667b5a5..f30df93 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -105,7 +105,7 @@
 set ::env(PL_TIME_DRIVEN) 1
 set ::env(PL_TARGET_DENSITY) "0.38"
 set ::env(CELL_PAD) "8"
-#set ::env(GRT_ADJUSTMENT) {0.2}
+set ::env(GRT_ADJUSTMENT) {0.2}
 
 
 ######################################################################################
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 1cd2a7e..e83bae6 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -101,22 +101,20 @@
 ## Placement
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
-
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 2
 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
 
 ## Routing
 set ::env(GRT_ADJUSTMENT) 0.1
 set ::env(DPL_CELL_PADDING) 1
 
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
-
 set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
-set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
-
 set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
 
 #LVS Issue - DEF Base looks to having issue
 set ::env(MAGIC_EXT_USE_GDS) {0}
@@ -128,20 +126,16 @@
 set ::env(MAGIC_GENERATE_LEF) {1}
 set ::env(MAGIC_WRITE_FULL_LEF) {0}
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "1"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
-
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000"
-set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
-set ::env(PL_RESIZER_MAX_CAP_MARGIN) "5"
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 6.2
-set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 873ac0a..679443f 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -34,7 +34,7 @@
 #DMEM Constraints
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
 set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
-set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
 
diff --git a/openlane/ycr_iconnect/base.sdc b/openlane/ycr_iconnect/base.sdc
index b0dcaa5..69f6f25 100644
--- a/openlane/ycr_iconnect/base.sdc
+++ b/openlane/ycr_iconnect/base.sdc
@@ -3,6 +3,9 @@
 ###############################################################################
 create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
 
+create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm clock0} [get_ports sram0_clk0]
+create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm clock1} [get_ports sram0_clk1]
+
 set_clock_transition 0.1500 [all_clocks]
 set_clock_uncertainty -setup 0.5000 [all_clocks]
 set_clock_uncertainty -hold 0.2500 [all_clocks]
@@ -12,11 +15,14 @@
 set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
+set_case_analysis 0 [get_ports {cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_ports {cfg_sram_lphase[1]}]
+
 #CORE-0 IMEM Constraints
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
 
 set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
 set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
@@ -30,11 +36,11 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
 
 #CORE-0 DMEM Constraints
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
 
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
@@ -48,6 +54,32 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
 
+## PORT-0 TCM I/F
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_din0[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_dout0[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_dout0[*]}]
+
+
+## PORT-1 TCM1 I/F
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_addr1[*]}]
+
+set_output_delay -max 1.000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_addr1[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_dout1[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_dout1[*]}]
 
 ###############################################################################
 # Environment
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl
index fdcd6df..2646b19 100644
--- a/openlane/ycr_iconnect/config.tcl
+++ b/openlane/ycr_iconnect/config.tcl
@@ -65,7 +65,7 @@
 
 set ::env(PL_TARGET_DENSITY) 0.20
 set ::env(CELL_PAD) 8
-#set ::env(GRT_ADJUSTMENT) {0.2}
+set ::env(GRT_ADJUSTMENT) {0.2}
 
 
 #set ::env(PL_ROUTABILITY_DRIVEN) "1"
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index f8eb2c5..b03c508 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -2,7 +2,6 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
-create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
 create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
 
 create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
@@ -21,18 +20,26 @@
 
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
- -group [get_clocks {rtc_clk}]\
  -group [get_clocks {wb_clk}] -comment {Async Clock group}
 
+# Set case analysis
+set_case_analysis  0 [get_ports {cfg_ccska[3]}]
+set_case_analysis  0 [get_ports {cfg_ccska[2]}]
+set_case_analysis  0 [get_ports {cfg_ccska[1]}]
+set_case_analysis  0 [get_ports {cfg_ccska[0]}]
+
+set_case_analysis  0 [get_ports {cfg_wcska[3]}]
+set_case_analysis  0 [get_ports {cfg_wcska[2]}]
+set_case_analysis  0 [get_ports {cfg_wcska[1]}]
+set_case_analysis  0 [get_ports {cfg_wcska[0]}]
+
 #Assumed config are static
 set_false_path -from  [get_ports {cfg_dcache_force_flush}]
 set_false_path -from  [get_ports {cfg_dcache_pfet_dis}]
 set_false_path -from  [get_ports {cfg_icache_ntag_pfet_dis}]
 set_false_path -from  [get_ports {cfg_icache_pfet_dis}]
-set_false_path -from  [get_ports {cfg_cska_riscv[3]}]
-set_false_path -from  [get_ports {cfg_cska_riscv[2]}]
-set_false_path -from  [get_ports {cfg_cska_riscv[1]}]
-set_false_path -from  [get_ports {cfg_cska_riscv[0]}]
+
+
 set_false_path -from  [get_ports {cfg_sram_lphase[1]}]
 set_false_path -from  [get_ports {cfg_sram_lphase[0]}]
 
@@ -51,19 +58,19 @@
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
 
 
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
 
 #Wishbone ICACHE I/F
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
@@ -102,17 +109,17 @@
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
 set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
 
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
 
 
 # Data memory interface from router to WB bridge
@@ -160,21 +167,21 @@
 
 
 ## ICACHE PORT-0 SRAM Memory I/F
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
 
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
 
 ## ICACHE PORT-1 SRAM Memory I/F
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
-set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
 set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
 set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
 
@@ -199,39 +206,39 @@
 set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
 set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
 
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
 
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
-set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
 
 ## DCACHE PORT-0 SRAM I/F
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
 
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
 
 set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
 set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
 
 
 ## DCACHE PORT-1 SRAM I/F
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
-set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
 
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
-set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
 
 set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
 set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 2f2e6d0..b77103e 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -65,7 +65,8 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 set ::env(FP_SIZING) absolute
 set ::env(DIE_AREA) "0 0 810 640 "
-set ::env(CELL_PAD) "6"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) {0.2}
 
 set ::env(PL_TARGET_DENSITY) 0.37
 
diff --git a/sta/scripts/aes_top_timing.tcl b/sta/scripts/aes_top_timing.tcl
new file mode 100644
index 0000000..2c6b8b6
--- /dev/null
+++ b/sta/scripts/aes_top_timing.tcl
@@ -0,0 +1,49 @@
+
+    set ::env(USER_ROOT)    ".."
+    set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
+
+    read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/aes_top.v
+
+
+	link_design aes_top
+
+
+	## User Project Spef
+    read_spef  $::env(USER_ROOT)/spef/aes_top.spef
+
+	read_sdc -echo ./sdc/aes_top.sdc	
+	set_propagated_clock [all_clocks]
+
+    report_annotated_check -list_annotated
+    report_annotated_check -list_not_annotated
+
+	check_setup  -verbose >  unconstraints.aes.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.aes.rpt
+
+
+
diff --git a/sta/scripts/ycr_iconnect.tcl b/sta/scripts/ycr_iconnect.tcl
new file mode 100644
index 0000000..e80cf39
--- /dev/null
+++ b/sta/scripts/ycr_iconnect.tcl
@@ -0,0 +1,50 @@
+
+    set ::env(USER_ROOT)    ".."
+    set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
+
+    read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+    read_verilog $::env(USER_ROOT)/verilog/gl/ycr_iconnect.v
+
+
+	link_design ycr_iconnect
+
+
+	## User Project Spef
+    read_spef  $::env(USER_ROOT)/spef/ycr_iconnect.spef
+
+
+	read_sdc -echo ./sdc/ycr_iconnect.sdc	
+	set_propagated_clock [all_clocks]
+
+    report_annotated_check -list_annotated
+    report_annotated_check -list_not_annotated
+
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
+
+
diff --git a/sta/scripts/ycr_intf.tcl b/sta/scripts/ycr_intf.tcl
new file mode 100644
index 0000000..8c444b1
--- /dev/null
+++ b/sta/scripts/ycr_intf.tcl
@@ -0,0 +1,50 @@
+
+    set ::env(USER_ROOT)    ".."
+    set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
+
+    read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+    read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+
+
+	link_design ycr_intf
+
+
+	## User Project Spef
+    read_spef  $::env(USER_ROOT)/spef/ycr_intf.spef
+
+
+	read_sdc -echo ./sdc/ycr_intf.sdc	
+	set_propagated_clock [all_clocks]
+
+    report_annotated_check -list_annotated
+    report_annotated_check -list_not_annotated
+
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
+
+
diff --git a/sta/sdc/aes_top.sdc b/sta/sdc/aes_top.sdc
new file mode 100644
index 0000000..f81deda
--- /dev/null
+++ b/sta/sdc/aes_top.sdc
@@ -0,0 +1,276 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov  7 16:29:34 2022
+###############################################################################
+current_design aes_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_int}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_out}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sta/sdc/ycr_iconnect.sdc b/sta/sdc/ycr_iconnect.sdc
new file mode 100644
index 0000000..69f6f25
--- /dev/null
+++ b/sta/sdc/ycr_iconnect.sdc
@@ -0,0 +1,98 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+
+create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm clock0} [get_ports sram0_clk0]
+create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm clock1} [get_ports sram0_clk1]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_case_analysis 0 [get_ports {cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_ports {cfg_sram_lphase[1]}]
+
+#CORE-0 IMEM Constraints
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -min 2.0000  -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
+
+#CORE-0 DMEM Constraints
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
+
+## PORT-0 TCM I/F
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_din0[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_dout0[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {sram0_clk0}] -add_delay  [get_ports {sram0_dout0[*]}]
+
+
+## PORT-1 TCM1 I/F
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_addr1[*]}]
+
+set_output_delay -max 1.000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_addr1[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_dout1[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {sram0_clk1}] -add_delay  [get_ports {sram0_dout1[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sta/sdc/ycr_intf.sdc b/sta/sdc/ycr_intf.sdc
new file mode 100644
index 0000000..3d913e6
--- /dev/null
+++ b/sta/sdc/ycr_intf.sdc
@@ -0,0 +1,260 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock1} [get_ports dcache_mem_clk1]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock0} [get_ports icache_mem_clk0]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
+
+# Set case analysis
+set_case_analysis  0 [get_ports {cfg_ccska[3]}]
+set_case_analysis  0 [get_ports {cfg_ccska[2]}]
+set_case_analysis  0 [get_ports {cfg_ccska[1]}]
+set_case_analysis  0 [get_ports {cfg_ccska[0]}]
+
+set_case_analysis  0 [get_ports {cfg_wcska[3]}]
+set_case_analysis  0 [get_ports {cfg_wcska[2]}]
+set_case_analysis  0 [get_ports {cfg_wcska[1]}]
+set_case_analysis  0 [get_ports {cfg_wcska[0]}]
+
+#Assumed config are static
+set_false_path -from  [get_ports {cfg_dcache_force_flush}]
+set_false_path -from  [get_ports {cfg_dcache_pfet_dis}]
+set_false_path -from  [get_ports {cfg_icache_ntag_pfet_dis}]
+set_false_path -from  [get_ports {cfg_icache_pfet_dis}]
+
+
+set_false_path -from  [get_ports {cfg_sram_lphase[1]}]
+set_false_path -from  [get_ports {cfg_sram_lphase[0]}]
+
+#All reset has reset synchronization logic inside block ??
+set_false_path -from  [get_ports {cpu_intf_rst_n}]
+set_false_path -from  [get_ports {pwrup_rst_n}]
+set_false_path -from  [get_ports {wb_rst_n}]
+
+#CORE Instruction Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
+
+
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+
+#Wishbone ICACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -max 2.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_err_i}]
+
+
+
+# CORE Data Memory Interface
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
+
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+
+
+# Data memory interface from router to WB bridge
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_wdata[*]}]
+
+#WB Data Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_sel_o[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_sel_o[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_err_i}]
+
+
+## ICACHE PORT-0 SRAM Memory I/F
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+
+## ICACHE PORT-1 SRAM Memory I/F
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_dout1[*]}]
+
+
+# Wishbone DCACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_cyc_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+
+## DCACHE PORT-0 SRAM I/F
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
+
+
+## DCACHE PORT-1 SRAM I/F
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 001bd66..58419e2 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -296,29 +296,6 @@
 
 logic [7:0]   pwm_gpio_in;
 
-assign reg_rdata = (reg_addr[9:7] == `SEL_GLBL)  ? {reg_glbl_rdata} : 
-	               (reg_addr[9:7] == `SEL_GPIO)  ? {reg_gpio_rdata} :
-	               (reg_addr[9:7] == `SEL_PWM)   ? {reg_pwm_rdata}  :
-	               (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_rdata  : 
-	               (reg_addr[9:7] == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
-	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_rdata     : 
-	               (reg_addr[9:7] == `SEL_D2A)   ? reg_d2a_rdata    : 'h0;
-
-assign reg_ack   = (reg_addr[9:7] == `SEL_GLBL)  ? reg_glbl_ack   : 
-	               (reg_addr[9:7] == `SEL_GPIO)  ? reg_gpio_ack   : 
-	               (reg_addr[9:7] == `SEL_PWM)   ? reg_pwm_ack    : 
-	               (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_ack  : 
-	               (reg_addr[9:7] == `SEL_SEMA)  ? reg_sema_ack   : 
-	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_ack     : 
-	               (reg_addr[9:7] == `SEL_D2A)   ? reg_d2a_ack    : 1'b0;
-
-wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
-wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
-wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
-wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
-wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
-wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS)   ? reg_cs : 1'b0;
-wire reg_d2a_cs   = (reg_addr[9:7] == `SEL_D2A)  ? reg_cs : 1'b0;
 
 //---------------------------------------------------------------------
 
@@ -662,6 +639,44 @@
 
          );
 
+//-------------------------------------------------
+// Register Block Selection Logic
+//-------------------------------------------------
+reg [2:0] reg_blk_sel;
+
+always @(posedge mclk or negedge s_reset_ssn)
+begin
+   if(s_reset_ssn == 1'b0) begin
+     reg_blk_sel <= 'h0;
+   end
+   else begin
+      if(reg_cs) reg_blk_sel <= reg_addr[9:7];
+   end
+end
+
+assign reg_rdata = (reg_blk_sel == `SEL_GLBL)  ? {reg_glbl_rdata} : 
+	               (reg_blk_sel == `SEL_GPIO)  ? {reg_gpio_rdata} :
+	               (reg_blk_sel == `SEL_PWM)   ? {reg_pwm_rdata}  :
+	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata  : 
+	               (reg_blk_sel == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
+	               (reg_blk_sel == `SEL_WS)    ? reg_ws_rdata     : 
+	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_rdata    : 'h0;
+
+assign reg_ack   = (reg_blk_sel == `SEL_GLBL)  ? reg_glbl_ack   : 
+	               (reg_blk_sel == `SEL_GPIO)  ? reg_gpio_ack   : 
+	               (reg_blk_sel == `SEL_PWM)   ? reg_pwm_ack    : 
+	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack  : 
+	               (reg_blk_sel == `SEL_SEMA)  ? reg_sema_ack   : 
+	               (reg_blk_sel == `SEL_WS)    ? reg_ws_ack     : 
+	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_ack    : 1'b0;
+
+wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
+wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
+wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
+wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
+wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
+wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS)   ? reg_cs : 1'b0;
+wire reg_d2a_cs   = (reg_addr[9:7] == `SEL_D2A)  ? reg_cs : 1'b0;
 endmodule 
 
 
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 4dfe03c..faf789f 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -8,10 +8,10 @@
 // Software Reg-2: Poject Revison 5.1 = 0005200
 parameter CHIP_REVISION   = 32'h0005_7000;
 
-parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1100;
+parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_0111_1010_1000_1001_1100;
 parameter CLK_SKEW2_RESET_VAL = 32'b0000;
 
-parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1010_0000;
+parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
 
 /*****************************************************
 pad_strap_in decoding
@@ -41,8 +41,8 @@
                  0 - Cache Enable
                  1 - Bypass cache  (Default)
      bit [10]  - Riscv SRAM clock edge selection
-                 0 - Normal
-                 1 - Invert        (Default)
+                 0 - Normal      (Default)
+                 1 - Invert        
      bit [12:11] - Skew selection
                  2'b00 - Default value  (Default)
                  2'b01 - Default value + 2               
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 74017e8..65f8427 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -41,6 +41,7 @@
 ////      14. UART Master                                         ////
 ////      15. SPI Slave (As Arduino ISP)                          ////
 ////      16. AES 126 Encription/Decryption                       ////
+////      17. FPU (Single Precision)                              ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////