diff --git a/README.md b/README.md
index 4a747ec..176670f 100644
--- a/README.md
+++ b/README.md
@@ -193,41 +193,41 @@
   <tr align="center"> <td> ATMGA328 Pin No</td> <td> Functionality           </td> <td> Arudino Pin Name</td> <td> Carvel Pin Mapping                   </td></tr>
   <tr align="center"> <td> Pin-1           </td> <td> PC6/RESET              </td> <td>                 </td> <td> digital_io[5]                        </td></tr>
   <tr align="center"> <td> Pin-2           </td> <td> PD0/RXD[0]             </td> <td>  D0             </td> <td> digital_io[6]                        </td></tr>
-  <tr align="center"> <td> Pin-3           </td> <td> PD1/TXD[0]             </td> <td>  D1             </td> <td> digital_io[7]                        </td></tr>
-  <tr align="center"> <td> Pin-4           </td> <td> PD2/RXD[1]/INT0        </td> <td>  D2             </td> <td> digital_io[8]                        </td></tr>
-  <tr align="center"> <td> Pin-5           </td> <td> PD3/INT1/OC2B(PWM0)    </td> <td>  D3             </td> <td> digital_io[9]                        </td></tr>
-  <tr align="center"> <td> Pin-6           </td> <td> PD4/TXD[1]             </td> <td>  D4             </td> <td> digital_io[10]                        </td></tr>
+  <tr align="center"> <td> Pin-3           </td> <td> PD1/TXD[0]             </td> <td>  D1             </td> <td> digital_io[7]/analog_io[0]           </td></tr>
+  <tr align="center"> <td> Pin-4           </td> <td> PD2/RXD[1]/INT0        </td> <td>  D2             </td> <td> digital_io[8]/analog_io[1]           </td></tr>
+  <tr align="center"> <td> Pin-5           </td> <td> PD3/INT1/OC2B(PWM0)    </td> <td>  D3             </td> <td> digital_io[9]/analog_io[2]           </td></tr>
+  <tr align="center"> <td> Pin-6           </td> <td> PD4/TXD[1]             </td> <td>  D4             </td> <td> digital_io[10]/analog_io[3]          </td></tr>
   <tr align="center"> <td> Pin-7           </td> <td> VCC                    </td> <td>                 </td> <td>  -                                   </td></tr>
   <tr align="center"> <td> Pin-8           </td> <td> GND                    </td> <td>                 </td> <td>  -                                   </td></tr>
-  <tr align="center"> <td> Pin-9           </td> <td> PB6/XTAL1/TOSC1        </td> <td>                 </td> <td> digital_io[11]                        </td></tr>
-  <tr align="center"> <td> Pin-10          </td> <td> PB7/XTAL2/TOSC2        </td> <td>                 </td> <td> digital_io[12]                        </td></tr>
-  <tr align="center"> <td> Pin-11          </td> <td> PD5/SS[3]/OC0B(PWM1)/T1      </td> <td> D5        </td> <td> digital_io[13]                        </td></tr>
-  <tr align="center"> <td> Pin-12          </td> <td> PD6/SS[2]/OC0A(PWM2)/AIN0    </td> <td> D6        </td> <td> digital_io[14] /analog_io[2]          </td></tr>
-  <tr align="center"> <td> Pin-13          </td> <td> PD7/A1N1               </td> <td> D7              </td> <td> digital_io[15]/analog_io[3]          </td></tr>
-  <tr align="center"> <td> Pin-14          </td> <td> PB0/CLKO/ICP1          </td> <td> D8              </td> <td> digital_io[16]                       </td></tr>
-  <tr align="center"> <td> Pin-15          </td> <td> PB1/SS[1]OC1A(PWM3)         </td> <td> D9         </td> <td> digital_io[17]                       </td></tr>
-  <tr align="center"> <td> Pin-16          </td> <td> PB2/SS[0]/OC1B(PWM4)      </td> <td> D10          </td> <td> digital_io[18]                       </td></tr>
-  <tr align="center"> <td> Pin-17          </td> <td> PB3/MOSI/OC2A(PWM5)    </td> <td> D11             </td> <td> digital_io[19]                       </td></tr>
-  <tr align="center"> <td> Pin-18          </td> <td> PB4/MISO               </td> <td> D12             </td> <td> digital_io[20]                       </td></tr>
-  <tr align="center"> <td> Pin-19          </td> <td> PB5/SCK                </td> <td> D13             </td> <td> digital_io[21]                       </td></tr>
+  <tr align="center"> <td> Pin-9           </td> <td> PB6/XTAL1/TOSC1        </td> <td>                 </td> <td> digital_io[11]/analog_io[4]          </td></tr>
+  <tr align="center"> <td> Pin-10          </td> <td> PB7/XTAL2/TOSC2        </td> <td>                 </td> <td> digital_io[12]/analog_io[5]          </td></tr>
+  <tr align="center"> <td> Pin-11          </td> <td> PD5/SS[3]/OC0B(PWM1)/T1      </td> <td> D5        </td> <td> digital_io[13]/analog_io[6]          </td></tr>
+  <tr align="center"> <td> Pin-12          </td> <td> PD6/SS[2]/OC0A(PWM2)/AIN0    </td> <td> D6        </td> <td> digital_io[14]/analog_io[7]          </td></tr>
+  <tr align="center"> <td> Pin-13          </td> <td> PD7/A1N1               </td> <td> D7              </td> <td> digital_io[15]/analog_io[8]          </td></tr>
+  <tr align="center"> <td> Pin-14          </td> <td> PB0/CLKO/ICP1          </td> <td> D8              </td> <td> digital_io[16]/analog_io[9]          </td></tr>
+  <tr align="center"> <td> Pin-15          </td> <td> PB1/SS[1]OC1A(PWM3)         </td> <td> D9         </td> <td> digital_io[17]/analog_io[10]         </td></tr>
+  <tr align="center"> <td> Pin-16          </td> <td> PB2/SS[0]/OC1B(PWM4)      </td> <td> D10          </td> <td> digital_io[18]/analog_io[11]         </td></tr>
+  <tr align="center"> <td> Pin-17          </td> <td> PB3/MOSI/OC2A(PWM5)    </td> <td> D11             </td> <td> digital_io[19]/analog_io[12]         </td></tr>
+  <tr align="center"> <td> Pin-18          </td> <td> PB4/MISO               </td> <td> D12             </td> <td> digital_io[20]/analog_io[13]         </td></tr>
+  <tr align="center"> <td> Pin-19          </td> <td> PB5/SCK                </td> <td> D13             </td> <td> digital_io[21]/analog_io[14]         </td></tr>
   <tr align="center"> <td> Pin-20          </td> <td> AVCC                   </td> <td>                 </td> <td> -                                    </td></tr>
-  <tr align="center"> <td> Pin-21          </td> <td> AREF                   </td> <td>                 </td> <td> analog_io[10]                        </td></tr>
+  <tr align="center"> <td> Pin-21          </td> <td> AREF                   </td> <td>                 </td> <td> analog_io[23]                        </td></tr>
   <tr align="center"> <td> Pin-22          </td> <td> GND                    </td> <td>                 </td> <td> -                                    </td></tr>
-  <tr align="center"> <td> Pin-23          </td> <td> PC0/uartm_rxd/ADC0     </td> <td>  A0             </td> <td> digital_io[22]/analog_io[11]         </td></tr>
-  <tr align="center"> <td> Pin-24          </td> <td> PC1/uartm/ADC1         </td> <td>  A1             </td> <td> digital_io[23]/analog_io[12]         </td></tr>
-  <tr align="center"> <td> Pin-25          </td> <td> PC2/usb_dp/ADC2        </td> <td>  A2             </td> <td> digital_io[24]/analog_io[13]         </td></tr>
-  <tr align="center"> <td> Pin-26          </td> <td> PC3/usb_dn/ADC3        </td> <td>  A3             </td> <td> digital_io[25]/analog_io[14]         </td></tr>
-  <tr align="center"> <td> Pin-27          </td> <td> PC4/ADC4/SDA           </td> <td>  A4             </td> <td> digital_io[26]/analog_io[15]         </td></tr>
-  <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[27]/analog_io[16]         </td></tr>
+  <tr align="center"> <td> Pin-23          </td> <td> PC0/uartm_rxd/ADC0     </td> <td>  A0             </td> <td> digital_io[22]/analog_io[15]         </td></tr>
+  <tr align="center"> <td> Pin-24          </td> <td> PC1/uartm/ADC1         </td> <td>  A1             </td> <td> digital_io[23]/analog_io[16]         </td></tr>
+  <tr align="center"> <td> Pin-25          </td> <td> PC2/usb_dp/ADC2        </td> <td>  A2             </td> <td> digital_io[24]/analog_io[17]         </td></tr>
+  <tr align="center"> <td> Pin-26          </td> <td> PC3/usb_dn/ADC3        </td> <td>  A3             </td> <td> digital_io[25]/analog_io[18]         </td></tr>
+  <tr align="center"> <td> Pin-27          </td> <td> PC4/ADC4/SDA           </td> <td>  A4             </td> <td> digital_io[26]/analog_io[19]         </td></tr>
+  <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[27]/analog_io[20]         </td></tr>
   <tr align="center"> <td colspan="4">   Additional Pad used for Externam ROM/RAM/USB </td></tr>
-  <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[28]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[29]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1             </td> <td>                 </td> <td> digital_io[30]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[31]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[32]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[33]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[34]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[35]                       </td></tr>
+  <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[28]/Analog[21]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[29]/Analog[22]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1/AREF        </td> <td>                 </td> <td> digital_io[30]/Analog[23]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[31]/Analog[24]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[32]/Analog[25]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[33]/Analog[26]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[34]/Analog[27]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[35]/Analog[28]            </td></tr>
   <tr align="center"> <td> SFlash          </td> <td> sflash_io3             </td> <td>                 </td> <td> digital_io[36]                       </td></tr>
   <tr align="center"> <td> DEBUG           </td> <td> dbg_clk_mon            </td> <td>                 </td> <td> digital_io[37]                       </td></tr>
   <tr align="center"> <td> SPARE           </td> <td> PA0                    </td> <td>                 </td> <td> digital_io[0]                       </td></tr>
diff --git a/openlane/clk_skew_adjust/config.tcl b/openlane/clk_skew_adjust/config.tcl
index 8abd1f4..c4c3320 100644
--- a/openlane/clk_skew_adjust/config.tcl
+++ b/openlane/clk_skew_adjust/config.tcl
@@ -33,7 +33,8 @@
 
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
-	$script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv"
+	$::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+	$::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv"
 
 ## Clock configurations
 #set ::env(CLOCK_PORT) "clk_in"
diff --git a/openlane/digital_pll/base.sdc b/openlane/digital_pll/base.sdc
new file mode 100644
index 0000000..062e55d
--- /dev/null
+++ b/openlane/digital_pll/base.sdc
@@ -0,0 +1,36 @@
+
+
+current_design digital_pll
+
+create_clock [get_pins {"ringosc.ibufp01/Y"} ] -name "pll_control_clock"  -period 6.6666666666667 
+
+set_propagated_clock [get_clocks {pll_control_clock}] 
+
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs]
+set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_control_clock}]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_control_clock}]
+
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
diff --git a/openlane/digital_pll/config.tcl b/openlane/digital_pll/config.tcl
new file mode 100644
index 0000000..a56efd0
--- /dev/null
+++ b/openlane/digital_pll/config.tcl
@@ -0,0 +1,87 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) digital_pll
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/digital_pll.v \
+                          $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/digital_pll_controller.v \
+                          $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/ring_osc2x13.v"
+
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_TREE_SYNTH) 0
+
+# Synthesis
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+
+# Timing configuration
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc 
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 90 100"
+
+#set ::env(TOP_MARGIN_MULT) 2
+#set ::env(BOTTOM_MARGIN_MULT) 2
+
+#LVS Issue - DEF Base looks to having issue
+#set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(CELL_PAD)  0
+
+## PDN 
+set ::env(FP_PDN_VPITCH) 40
+set ::env(FP_PDN_HPITCH) 40
+
+## Placement
+set ::env(PL_TARGET_DENSITY) 0.82
+
+## Routing 
+#set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+#set ::env(GLB_RT_ADJUSTMENT) 0
+
+#set ::env(GLB_RT_MINLAYER) 2
+#set ::env(GLB_RT_MAXLAYER) 6
+set ::env(RT_MAX_LAYER) {met4}
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+set ::env(DIODE_INSERTION_STRATEGY) 0
+#set ::env(FILL_INSERTION) 0
+#set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+
+## Diode Insertion
+#set ::env(DIODE_INSERTION_STRATEGY) "4"
+
+set ::env(FP_PDN_VOFFSET) "5"
+set ::env(FP_PDN_VPITCH) "40"
+set ::env(FP_PDN_HOFFSET) "5"
+set ::env(FP_PDN_HPITCH) "40"
+set ::env(FP_PDN_HWIDTH) {6.2}
+set ::env(FP_PDN_VWIDTH) {6.2}
+set ::env(FP_PDN_HSPACING) {15}
+set ::env(FP_PDN_VSPACING) {15}
diff --git a/openlane/digital_pll/interactive.tcl b/openlane/digital_pll/interactive.tcl
new file mode 100755
index 0000000..32e355e
--- /dev/null
+++ b/openlane/digital_pll/interactive.tcl
@@ -0,0 +1,468 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+
+proc run_placement_step {args} {
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_placement {args} {
+    # |----------------------------------------------------|
+    # |----------------   3. PLACEMENT   ------------------|
+    # |----------------------------------------------------|
+    set ::env(CURRENT_STAGE) placement
+
+    if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
+        set old_pl_target_density $::env(PL_TARGET_DENSITY)
+        set ::env(PL_TARGET_DENSITY) $::env(PL_TARGET_DENSITY_CELLS)
+    }
+
+    if { $::env(PL_RANDOM_GLB_PLACEMENT) } {
+        # useful for very tiny designs
+        random_global_placement
+    } else {
+        global_placement_or
+    }
+
+    if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
+        set ::env(PL_TARGET_DENSITY) $old_pl_target_density
+    }
+
+    run_resizer_design
+    remove_buffers_from_nets
+
+    detailed_placement_or -def $::env(placement_results)/$::env(DESIGN_NAME).def -log $::env(placement_logs)/detailed.log
+
+    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(placement_logs)/screenshot.log
+}
+
+
+proc global_placement_or {args} {
+    increment_index
+    TIMER::timer_start
+    set log [index_file $::env(placement_logs)/global.log]
+    puts_info "Running Global Placement (log: [relpath . $log])..."
+
+    set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/global.def]
+
+    # random initial placement
+    if { $::env(PL_RANDOM_INITIAL_PLACEMENT) } {
+        random_global_placement
+        set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
+    }
+
+    run_openroad_script $::env(SCRIPTS_DIR)/openroad/gpl.tcl -indexed_log $log
+
+    # sometimes replace fails with a ZERO exit code; the following is a workaround
+    # until the cause is found and fixed
+    if { ! [file exists $::env(SAVE_DEF)] } {
+        puts_err "Global placement has failed to produce a DEF file."
+        flow_fail
+    }
+
+    check_replace_divergence
+
+    TIMER::timer_stop
+    exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "global placement - openroad"
+    set_def $::env(SAVE_DEF)
+}
+
+
+
+proc run_cts_step {args} {
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+}
+
+proc run_routing_step {args} {
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    if { $::env(ECO_ENABLE) == 0 } {
+        run_routing
+    }
+}
+
+proc run_parasitics_sta_step {args} {
+    if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+        set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+    }
+
+    if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+        run_parasitics_sta
+    }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+    if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+        run_antenna_check
+        heal_antenna_violators; # modifies the routed DEF
+    }
+
+}
+
+proc run_irdrop_report_step {args} {
+    if { $::env(RUN_IRDROP_REPORT) } {
+        run_irdrop_report
+    }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+
+    if { $lvs_enabled && $::env(RUN_LVS) } {
+        run_magic_spice_export;
+        run_lvs; # requires run_magic_spice_export
+    }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+    if { $drc_enabled } {
+        if { $::env(RUN_MAGIC_DRC) } {
+            run_magic_drc
+        }
+        if {$::env(RUN_KLAYOUT_DRC)} {
+            run_klayout_drc
+        }
+    }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+    if { $antenna_check_enabled } {
+        run_antenna_check
+    }
+}
+
+proc run_eco_step {args} {
+    if { $::env(ECO_ENABLE) == 1 } {
+        run_eco_flow
+    }
+}
+
+proc run_magic_step {args} {
+    if {$::env(RUN_MAGIC)} {
+        run_magic
+    }
+}
+
+proc run_klayout_step {args} {
+    if {$::env(RUN_KLAYOUT)} {
+        run_klayout
+    }
+    if {$::env(RUN_KLAYOUT_XOR)} {
+        run_klayout_gds_xor
+    }
+}
+
+proc run_post_run_hooks {} {
+    if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+        puts_info "Running post run hook"
+        set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+        puts_info "$result"
+    } else {
+        puts_info "hooks/post_run.py not found, skipping"
+    }
+}
+
+proc run_magic_drc_batch {args} {
+    set options {
+        {-magicrc optional}
+        {-tech optional}
+        {-report required}
+        {-design required}
+        {-gds required}
+    }
+    set flags {}
+    parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+    if { [info exists arg_values(-magicrc)] } {
+        set magicrc [file normalize $arg_values(-magicrc)]
+    }
+    if { [info exists arg_values(-tech)] } {
+        set ::env(TECH) [file normalize $arg_values(-tech)]
+    }
+    set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+    set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+    set ::env(DESIGN_NAME) $arg_values(-design)
+
+    if { [info exists magicrc] } {
+        exec magic \
+            -noconsole \
+            -dnull \
+            -rcfile $magicrc \
+            $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+            </dev/null |& tee /dev/tty
+    } else {
+        exec magic \
+            -noconsole \
+            -dnull \
+            $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+            </dev/null |& tee /dev/tty
+    }
+}
+
+proc run_lvs_batch {args} {
+    # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+    # extracts gds only if EXT_NETLIST does not exist
+    set options {
+        {-design required}
+        {-gds optional}
+        {-net optional}
+    }
+    set flags {}
+    parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+    prep {*}$args
+
+    if { [info exists arg_values(-gds)] } {
+        set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+    } else {
+        set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+    }
+    if { [info exists arg_values(-net)] } {
+        set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+    }
+
+    assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+
+    set ::env(MAGIC_EXT_USE_GDS) 1
+    set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+    if { [file exists $::env(EXT_NETLIST)] } {
+        puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+    } else {
+        run_magic_spice_export
+    }
+
+    run_lvs
+}
+
+
+proc run_file {args} {
+    set ::env(TCLLIBPATH) $::auto_path
+    exec tclsh {*}$args >&@stdout
+}
+
+proc run_floorplan {args} {
+    # |----------------------------------------------------|
+    # |----------------   2. FLOORPLAN   ------------------|
+    # |----------------------------------------------------|
+    #
+    # intial fp
+    init_floorplan
+
+    # check for deprecated io variables
+    if { [info exists ::env(FP_IO_HMETAL)]} {
+        set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+        puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+    }
+
+    if { [info exists ::env(FP_IO_VMETAL)]} {
+        set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+        puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+        puts_warn "We recommend you update your configuration as follows:"
+        puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+    }
+
+
+    # place io
+    if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+        place_io_ol
+    } else {
+        if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+            place_io
+            global_placement_or
+            place_contextualized_io \
+                -lef $::env(FP_CONTEXT_LEF) \
+                -def $::env(FP_CONTEXT_DEF)
+        } else {
+            place_io
+        }
+    }
+
+    apply_def_template
+
+    #if { [info exist ::env(EXTRA_LEFS)] } {
+        if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+            file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+            manual_macro_placement -f
+        } else {
+        #    global_placement_or
+        #    basic_macro_placement
+        }
+    #}
+
+    tap_decap_or
+
+    scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+    run_power_grid_generation
+}
+
+
+
+
+proc run_flow {args} {
+    set options {
+        {-design optional}
+        {-from optional}
+        {-to optional}
+        {-save_path optional}
+        {-override_env optional}
+    }
+    set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+    parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+    prep {*}$args
+    # signal trap SIGINT save_state;
+
+    if { [info exists flags_map(-gui)] } {
+        or_gui
+        return
+    }
+    if { [info exists arg_values(-override_env)] } {
+        load_overrides $arg_values(-override_env)
+    }
+
+    set LVS_ENABLED 1
+    set DRC_ENABLED 1
+
+    set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+    set steps [dict create \
+        "synthesis" "run_synthesis" \
+        "floorplan" "run_floorplan" \
+        "placement" "run_placement_step" \
+        "cts" "run_cts_step" \
+        "routing" "run_routing_step" \
+        "parasitics_sta" "run_parasitics_sta_step" \
+        "eco" "run_eco_step" \
+        "diode_insertion" "run_diode_insertion_2_5_step" \
+        "irdrop" "run_irdrop_report_step" \
+        "gds_magic" "run_magic_step" \
+        "gds_klayout" "run_klayout_step" \
+        "lvs" "run_lvs_step $LVS_ENABLED " \
+        "drc" "run_drc_step $DRC_ENABLED " \
+        "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+        "cvc" "run_lef_cvc"
+    ]
+
+    if { [info exists arg_values(-from) ]} {
+        puts_info "Starting flow at $arg_values(-from)..."
+        set ::env(CURRENT_STEP) $arg_values(-from)
+    } elseif {  [info exists ::env(CURRENT_STEP) ] } {
+        puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+    } else {
+        set ::env(CURRENT_STEP) "synthesis"
+    }
+
+    set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+    set_if_unset arg_values(-to) "cvc"
+
+    set exe 0;
+    dict for {step_name step_exe} $steps {
+        if { [ string equal $arg_values(-from) $step_name ] } {
+            set exe 1;
+        }
+
+        if { $exe } {
+            # For when it fails
+            set ::env(CURRENT_STEP) $step_name
+            [lindex $step_exe 0] [lindex $step_exe 1] ;
+        }
+
+        if { [ string equal $arg_values(-to) $step_name ] } {
+            set exe 0:
+            break;
+        }
+
+    }
+
+    # for when it resumes
+    set steps_as_list [dict keys $steps]
+    set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+    set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+    # Saves to <RUN_DIR>/results/final
+    save_final_views
+
+    # Saves to design directory or custom
+    if {  [info exists flags_map(-save) ] } {
+        if { ! [info exists arg_values(-save_path)] } {
+            set arg_values(-save_path) $::env(DESIGN_DIR)
+        }
+        save_final_views\
+            -save_path $arg_values(-save_path)\
+            -tag $::env(RUN_TAG)
+    }
+    calc_total_runtime
+    save_state
+    generate_final_summary_report
+
+    check_timing_violations
+
+    if { [info exists arg_values(-save_path)]\
+        && $arg_values(-save_path) != "" } {
+        set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+    } else {
+        set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+    }
+
+    if {[info exists flags_map(-run_hooks)]} {
+        run_post_run_hooks
+    }
+
+    puts_success "Flow complete."
+
+    show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/digital_pll/macro.cfg b/openlane/digital_pll/macro.cfg
new file mode 100644
index 0000000..927d153
--- /dev/null
+++ b/openlane/digital_pll/macro.cfg
@@ -0,0 +1,110 @@
+
+ringosc.iss.reseten0	7.82	10.88	FN
+ringosc.iss.ctrlen0	    14.72	10.88	FN
+ringosc.iss.const1	    19.78	10.88	FN
+
+ringosc.iss.delaybuf0	7.82	13.60	S
+ringosc.iss.delayen1	11.5	13.60	S
+ringosc.iss.delayint0	19.78	13.60	FS
+ringosc.iss.delayenb1	7.82	16.32	FN
+ringosc.iss.delayen0	13.34	16.32	FN
+ringosc.iss.delayenb0	19.78	16.32	FN
+			
+ringosc.dstage\[0\].id.delaybuf0	7.82	19.04	FS
+ringosc.dstage\[0\].id.delaybuf1	11.5	19.04	S
+ringosc.dstage\[0\].id.delayen1		14.72	19.04	S
+ringosc.dstage\[0\].id.delayint0	20.24	19.04	FS
+ringosc.dstage\[0\].id.delayenb1	7.82	21.76	FN
+ringosc.dstage\[0\].id.delayen0		13.34	21.76	FN
+ringosc.dstage\[0\].id.delayenb0	19.78	21.76	FN
+			
+ringosc.dstage\[1\].id.delaybuf0	7.82	24.48	FS
+ringosc.dstage\[1\].id.delaybuf1	11.5	24.48	S
+ringosc.dstage\[1\].id.delayen1		14.72	24.48	S
+ringosc.dstage\[1\].id.delayint0	20.24	24.48	FS
+ringosc.dstage\[1\].id.delayenb1	7.82	27.2	FN
+ringosc.dstage\[1\].id.delayen0		13.34	27.2	FN
+ringosc.dstage\[1\].id.delayenb0	19.78	27.2	FN
+			
+ringosc.dstage\[2\].id.delaybuf0	7.82	29.92	FS
+ringosc.dstage\[2\].id.delaybuf1	11.5	29.92	S
+ringosc.dstage\[2\].id.delayen1		14.72	29.92	S
+ringosc.dstage\[2\].id.delayint0	20.24	29.92	FS
+ringosc.dstage\[2\].id.delayenb1	7.82	32.64	FN
+ringosc.dstage\[2\].id.delayen0		13.34	32.64	FN
+ringosc.dstage\[2\].id.delayenb0	19.78	32.64	FN
+			
+ringosc.dstage\[3\].id.delaybuf0	7.82	35.36	FS
+ringosc.dstage\[3\].id.delaybuf1	11.5	35.36	S
+ringosc.dstage\[3\].id.delayen1		14.72	35.36	S
+ringosc.dstage\[3\].id.delayint0	20.24	35.36	FS
+ringosc.dstage\[3\].id.delayenb1	7.82	38.08	FN
+ringosc.dstage\[3\].id.delayen0		13.34	38.08	FN
+ringosc.dstage\[3\].id.delayenb0	19.78	38.08	FN
+			
+ringosc.dstage\[4\].id.delaybuf0	7.82	40.8	FS
+ringosc.dstage\[4\].id.delaybuf1	11.5	40.8	S
+ringosc.dstage\[4\].id.delayen1		14.72	40.8	S
+ringosc.dstage\[4\].id.delayint0	20.24	40.8	FS
+ringosc.dstage\[4\].id.delayenb1	7.82	43.52	FN
+ringosc.dstage\[4\].id.delayen0		13.34	43.52	FN
+ringosc.dstage\[4\].id.delayenb0	19.78	43.52	FN
+			
+ringosc.dstage\[5\].id.delaybuf0	7.82	46.24	FS
+ringosc.dstage\[5\].id.delaybuf1	11.5	46.24	S
+ringosc.dstage\[5\].id.delayen1		14.72	46.24	S
+ringosc.dstage\[5\].id.delayint0	20.24	46.24	FS
+ringosc.dstage\[5\].id.delayenb1	7.82	48.96	FN
+ringosc.dstage\[5\].id.delayen0		13.34	48.96	FN
+ringosc.dstage\[5\].id.delayenb0	19.78	48.96	FN
+			
+ringosc.dstage\[6\].id.delaybuf0	31.74	48.96	FN
+ringosc.dstage\[6\].id.delaybuf1	35.42	48.96	N
+ringosc.dstage\[6\].id.delayen1		38.64	48.96	N
+ringosc.dstage\[6\].id.delayint0	45.54	48.96	FN
+ringosc.dstage\[6\].id.delayenb1	32.66	46.24	FS
+ringosc.dstage\[6\].id.delayen0		38.18	46.24	FS
+ringosc.dstage\[6\].id.delayenb0	44.62	46.24	FS
+			
+ringosc.dstage\[7\].id.delaybuf0	31.74	43.52	FN
+ringosc.dstage\[7\].id.delaybuf1	35.42	43.52	N
+ringosc.dstage\[7\].id.delayen1		38.64	43.52	N
+ringosc.dstage\[7\].id.delayint0	45.54	43.52	FN
+ringosc.dstage\[7\].id.delayenb1	32.66	40.8	FS
+ringosc.dstage\[7\].id.delayen0		38.18	40.8	FS
+ringosc.dstage\[7\].id.delayenb0	44.62	40.8	FS
+			
+ringosc.dstage\[8\].id.delaybuf0	31.74	38.08	FN
+ringosc.dstage\[8\].id.delaybuf1	35.42	38.08	N
+ringosc.dstage\[8\].id.delayen1		38.64	38.08	N
+ringosc.dstage\[8\].id.delayint0	45.54	38.08	FN
+ringosc.dstage\[8\].id.delayenb1	32.66	35.36	FS
+ringosc.dstage\[8\].id.delayen0		38.18	35.36	FS
+ringosc.dstage\[8\].id.delayenb0	44.62	35.36	FS
+			
+ringosc.dstage\[9\].id.delaybuf0	31.74	32.64	FN
+ringosc.dstage\[9\].id.delaybuf1	35.42	32.64	N
+ringosc.dstage\[9\].id.delayen1		38.64	32.64	N
+ringosc.dstage\[9\].id.delayint0	45.54	32.64	FN
+ringosc.dstage\[9\].id.delayenb1	32.66	29.92	FS
+ringosc.dstage\[9\].id.delayen0		38.18	29.92	FS
+ringosc.dstage\[9\].id.delayenb0	44.62	29.92	FS
+			
+ringosc.dstage\[10\].id.delaybuf0	31.74	27.2	FN
+ringosc.dstage\[10\].id.delaybuf1	35.42	27.2	N
+ringosc.dstage\[10\].id.delayen1	38.64	27.2	N
+ringosc.dstage\[10\].id.delayint0	45.54	27.2	FN
+ringosc.dstage\[10\].id.delayenb1	32.66	24.48	FS
+ringosc.dstage\[10\].id.delayen0	38.18	24.48	FS
+ringosc.dstage\[10\].id.delayenb0	44.62	24.48	FS
+			
+ringosc.dstage\[11\].id.delaybuf0	31.74	21.76	FN
+ringosc.dstage\[11\].id.delaybuf1	35.42	21.76	N
+ringosc.dstage\[11\].id.delayen1	38.64	21.76	N
+ringosc.dstage\[11\].id.delayint0	45.54	21.76	FN
+ringosc.dstage\[11\].id.delayenb1	32.66	19.04	FS
+ringosc.dstage\[11\].id.delayen0	38.18	19.04	FS
+ringosc.dstage\[11\].id.delayenb0	44.62	19.04	FS
+
+			
+
diff --git a/openlane/digital_pll/pin_order.cfg b/openlane/digital_pll/pin_order.cfg
new file mode 100644
index 0000000..b4d381d
--- /dev/null
+++ b/openlane/digital_pll/pin_order.cfg
@@ -0,0 +1,45 @@
+#N
+ext_trim\[7\]
+ext_trim\[8\]
+ext_trim\[9\]
+ext_trim\[19\]
+ext_trim\[18\]
+ext_trim\[17\]
+ext_trim\[16\]
+ext_trim\[15\]
+ext_trim\[14\]
+ext_trim\[13\]
+ext_trim\[12\]
+ext_trim\[11\]
+ext_trim\[10\]
+
+#E
+ext_trim\[25\]
+ext_trim\[24\]
+ext_trim\[23\]
+ext_trim\[22\]
+ext_trim\[21\]
+ext_trim\[20\]
+
+#W
+clockp\[1\]
+clockp\[0\]
+div\[4\]
+div\[3\]
+div\[2\]
+div\[1\]
+div\[0\]
+enable
+dco
+ext_trim\[6\]
+ext_trim\[5\]
+ext_trim\[4\]
+ext_trim\[3\]
+ext_trim\[2\]
+ext_trim\[1\]
+ext_trim\[0\]
+
+#S
+resetb 
+osc  
+
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 9326c1a..de3eda0 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -64,6 +64,7 @@
      $::env(DESIGN_DIR)/../../verilog/rtl/ws281x/src/ws281x_reg.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/strap_ctrl.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_rst_reg.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/dig2ana/src/dig2ana_reg.sv \
      $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv   \
      $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv   \
      $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v          \
@@ -102,7 +103,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.37"
+set ::env(PL_TARGET_DENSITY) "0.38"
 set ::env(CELL_PAD) "8"
 #set ::env(GRT_ADJUSTMENT) {0.2}
 
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index 25515be..72106cb 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -303,7 +303,44 @@
 
 
 #N
-digital_io_oen\[37\]  000 0 4
+
+cfg_dac3_mux_sel\[7\]
+cfg_dac3_mux_sel\[6\]
+cfg_dac3_mux_sel\[5\]
+cfg_dac3_mux_sel\[4\]
+cfg_dac3_mux_sel\[3\]
+cfg_dac3_mux_sel\[2\]
+cfg_dac3_mux_sel\[1\]
+cfg_dac3_mux_sel\[0\]
+
+cfg_dac2_mux_sel\[7\]
+cfg_dac2_mux_sel\[6\]
+cfg_dac2_mux_sel\[5\]
+cfg_dac2_mux_sel\[4\]
+cfg_dac2_mux_sel\[3\]
+cfg_dac2_mux_sel\[2\]
+cfg_dac2_mux_sel\[1\]
+cfg_dac2_mux_sel\[0\]
+
+cfg_dac1_mux_sel\[7\]
+cfg_dac1_mux_sel\[6\]
+cfg_dac1_mux_sel\[5\]
+cfg_dac1_mux_sel\[4\]
+cfg_dac1_mux_sel\[3\]
+cfg_dac1_mux_sel\[2\]
+cfg_dac1_mux_sel\[1\]
+cfg_dac1_mux_sel\[0\]
+
+cfg_dac0_mux_sel\[7\]
+cfg_dac0_mux_sel\[6\]
+cfg_dac0_mux_sel\[5\]
+cfg_dac0_mux_sel\[4\]
+cfg_dac0_mux_sel\[3\]
+cfg_dac0_mux_sel\[2\]
+cfg_dac0_mux_sel\[1\]
+cfg_dac0_mux_sel\[0\]
+
+digital_io_oen\[37\]  100 0 4
 digital_io_out\[37\]
 digital_io_in\[37\]
 digital_io_oen\[36\]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 86a397e..9870805 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -128,6 +128,15 @@
 #LVS Issue - DEF Base looks to having issue
 set ::env(MAGIC_EXT_USE_GDS) {1}
 
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "1"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index d1a637e..bb6ae69 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -75,6 +75,7 @@
 	    $::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
 	    $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
 	    "
 
 set ::env(EXTRA_LEFS) "\
@@ -88,6 +89,7 @@
 	$lef_root/ycr_iconnect.lef \
 	$lef_root/digital_pll.lef \
 	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+	$lef_root/dac_top.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -100,7 +102,7 @@
 	$gds_root/ycr_core_top.gds \
 	$gds_root/ycr_iconnect.gds \
 	$gds_root/digital_pll.gds \
-	$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+	$gds_root/dac_top.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -121,13 +123,13 @@
 set ::env(FP_PDN_HORIZONTAL_HALO) "10"
 set ::env(FP_PDN_VERTICAL_HALO) "10"
 set ::env(FP_PDN_VOFFSET) "5"
-set ::env(FP_PDN_VPITCH) "60"
+set ::env(FP_PDN_VPITCH) "80"
 set ::env(FP_PDN_HOFFSET) "5"
-set ::env(FP_PDN_HPITCH) "60"
+set ::env(FP_PDN_HPITCH) "80"
 set ::env(FP_PDN_HWIDTH) {6.2}
 set ::env(FP_PDN_VWIDTH) {6.2}
-set ::env(FP_PDN_HSPACING) {20}
-set ::env(FP_PDN_VSPACING) {20}
+set ::env(FP_PDN_HSPACING) {33.8}
+set ::env(FP_PDN_VSPACING) {33.8}
 
 set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
 set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
@@ -167,7 +169,8 @@
 	u_wb_host                   vccd1 vssd1 vccd1 vssd1,\
 	u_riscv_top.i_core_top_0    vccd1 vssd1 vccd1 vssd1, \
 	u_riscv_top.u_connect       vccd1 vssd1 VPWR  VGND, \
-	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1 \
+	u_riscv_top.u_intf          vccd1 vssd1 vccd1 vssd1, \
+	u_4x8bit_dac                vccd1 vssd1 vccd1 vssd1
       	"
 
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index e702974..a5faf73 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,7 +1,8 @@
+u_4x8bit_dac                1850            2500            N
 u_qspi_master                2250             650           N
 u_uart_i2c_usb_spi           2250            1350           N
 u_pinmux                     2250            2250           N
-u_pll                        2500            3148           N
+u_pll                        2500            3228           N
 
 u_riscv_top.i_core_top_0    50	            1400 	       N
 u_riscv_top.u_connect       735	            1400	       N
diff --git a/signoff/digital_pll/OPENLANE_VERSION b/signoff/digital_pll/OPENLANE_VERSION
new file mode 100644
index 0000000..b5bf449
--- /dev/null
+++ b/signoff/digital_pll/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane b6bacc9d1ab469917fda7ceea61ea3a18984b818
diff --git a/signoff/digital_pll/PDK_SOURCES b/signoff/digital_pll/PDK_SOURCES
new file mode 100644
index 0000000..f9d0f46
--- /dev/null
+++ b/signoff/digital_pll/PDK_SOURCES
@@ -0,0 +1 @@
+open_pdks 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
diff --git a/sta/scripts/pinmux_timing.tcl b/sta/scripts/pinmux_timing.tcl
index 17786bc..00778b1 100644
--- a/sta/scripts/pinmux_timing.tcl
+++ b/sta/scripts/pinmux_timing.tcl
@@ -1,38 +1,19 @@
 
-        set ::env(USER_ROOT)    "/home/dinesha/workarea/opencore/git/riscduino"
-        #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
-        #set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
-        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
-        set ::env(CARAVEL_PDK_ROOT)  "/opt/pdk_mpw4"
+    set ::env(USER_ROOT)    ".."
+    set ::env(PDK_ROOT)     "/opt/pdk_mpw7/sky130B"
+    define_corners ss tt ff
 
-        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
-	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+    read_liberty -corner tt $::env(PDK_ROOT)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
 
 	# User project netlist
-        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v  
+    read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v  
 
 
-	link_design pinmux
+	link_design pinmux_top
 
 
 	## User Project Spef
-        read_spef  $::env(USER_ROOT)/spef/pinmux.spef
+    read_spef  -corner tt $::env(USER_ROOT)/spef/pinmux_top.spef
 
 
 	read_sdc -echo ./sdc/pinmux.sdc	
diff --git a/sta/scripts/user_project_wrapper.tcl b/sta/scripts/user_project_wrapper.tcl
new file mode 100644
index 0000000..54bd008
--- /dev/null
+++ b/sta/scripts/user_project_wrapper.tcl
@@ -0,0 +1,279 @@
+
+        set ::env(USER_ROOT)    ".."
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
+        set ::env(CARAVEL_PDK_ROOT)     "/opt/pdk_mpw7/sky130B"
+        set ::env(TECH_LEF) {/opt/pdk_mpw7/sky130B/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
+
+
+    read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+	read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v	
+	read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v	
+	read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/ycr_iconnect.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v  
+
+
+	link_design caravel	
+
+	read_spef -path soc/DFFRAM_0                        $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef	
+	read_spef -path soc/core                            $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core.spef	
+	read_spef -path soc                                 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core_wrapper.spef	
+	read_spef -path padframe                            $::env(CARAVEL_ROOT)/spef/chip_io.spef	
+	read_spef -path rstb_level                          $::env(CARAVEL_ROOT)/spef/xres_buf.spef	
+	read_spef -path pll                                 $::env(CARAVEL_ROOT)/spef/digital_pll.spef	
+	read_spef -path housekeeping                        $::env(CARAVEL_ROOT)/spef/housekeeping.spef	
+	read_spef -path mgmt_buffers/powergood_check        $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef	
+	read_spef -path mgmt_buffers/mprj_logic_high_inst   $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef	
+	read_spef -path mgmt_buffers/mprj2_logic_high_inst  $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef	
+	read_spef -path clocking                            $::env(CARAVEL_ROOT)/spef/caravel_clocking.spef
+	read_spef -path mgmt_buffers                        $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef	
+	read_spef -path \gpio_control_bidir_1[0]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_1[1]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_2[1]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_2[2]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[0]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[10]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[1]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[2]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[3]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[4]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[5]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[6]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[7]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[8]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[9]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[0]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[1]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[2]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[3]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[4]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[5]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[0]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[10]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[11]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[12]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[13]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[14]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[15]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[1]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[2]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[3]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[4]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[5]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[6]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[7]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[8]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[9]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path gpio_defaults_block_0[0]            $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_0[1]            $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_5               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_6               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_7               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_8               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_9               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_10              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_11              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_12              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_13              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_14              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_15              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_16              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_17              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_18              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_19              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_20              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_21              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_22              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_23              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_24              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_25              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_26              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_27              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_28              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_29              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_2[0]            $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_2[1]            $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_2[2]            $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_30              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_31              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_32              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_33              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_34              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_35              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_36              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_37              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+
+	## User Project Spef
+
+        read_spef -path mprj/u_riscv_top.u_connect            $::env(USER_ROOT)/spef/ycr_iconnect.spef
+        read_spef -path mprj/u_riscv_top.u_intf               $::env(USER_ROOT)/spef/ycr_intf.spef
+        read_spef -path mprj/u_riscv_top.i_core_top_0         $::env(USER_ROOT)/spef/ycr_core_top.spef
+        read_spef -path mprj/u_pinmux                         $::env(USER_ROOT)/spef/pinmux_top.spef
+        read_spef -path mprj/u_qspi_master                    $::env(USER_ROOT)/spef/qspim_top.spef
+        read_spef -path mprj/u_uart_i2c_usb_spi               $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+        read_spef -path mprj/u_wb_host                        $::env(USER_ROOT)/spef/wb_host.spef
+        read_spef -path mprj/u_intercon                       $::env(USER_ROOT)/spef/wb_interconnect.spef
+	read_spef -path mprj/u_pll                            $::env(USER_ROOT)/spef/digital_pll.spef	
+        read_spef -path mprj                                  $::env(USER_ROOT)/spef/user_project_wrapper.spef  
+
+
+	read_sdc -echo ./sdc/caravel.sdc	
+	set_propagated_clock [all_clocks]
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
+	echo "Wishbone Interface Timing.................." > wb.max.rpt
+	echo "Wishbone Interface Timing.................." > wb.min.rpt
+	set wb_port [get_pins {mprj/wbs_adr_i[*]}]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_cyc_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_i[*]}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_sel_i[*]}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_stb_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_we_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_ack_o}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_o[*]}]]
+	foreach pin $wb_port {
+	   echo "Wishbone Interface Timing for : [get_full_name $pin]"  >> wb.max.rpt
+           report_checks -path_delay max -fields {slew cap input nets fanout} -through $pin  >> wb.max.rpt 
+        }
+	foreach pin $wb_port {
+	   echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> wb.min.rpt
+        }
+       
+	echo "SRAM Interface Timing.................." > sram.min.rpt
+	echo "SRAM Interface Timing.................." > sram.min.summary.rpt
+
+    ### Caravel SRAM Path ######################################
+    #set sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/din0[*]}]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/addr0[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/addr1[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/csb0[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/csb1[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/web0[*]}]]
+	#set sram_iport [concat $sram_iport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/wmask0[*]}]]
+ 
+    #set sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout0[*]}]
+	#set sram_oport [concat $sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout1[*]}]]
+    ### Caravel SRAM Path ######################################
+   
+    #TCM SRAM 
+    set tsram_iport [get_pins {mprj/u_tsram0_2kb/din0[*]}]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/addr0[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/addr1[*]}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb0}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/csb1}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/web0}]]
+	set tsram_iport [concat $tsram_iport [get_pins {mprj/u_tsram0_2kb/wmask0[*]}]]
+
+    set tsram_oport [get_pins {mprj/u_tsram0_2kb/dout0[*]}]
+	set tsram_oport [concat $tsram_oport [get_pins {mprj/u_tsram0_2kb/dout1[*]}]]
+
+	foreach pin $tsram_iport {
+	   echo "SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+	foreach pin $tsram_oport {
+	   echo "SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+    #ICACHE SRAM 
+    set isram_iport [                     get_pins {mprj/u_icache_2kb/din0[*]}]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/addr0[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/addr1[*]}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb0}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/csb1}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/web0}]]
+	set isram_iport [concat $isram_iport [get_pins {mprj/u_icache_2kb/wmask0[*]}]]
+
+    set isram_oport [                     get_pins {mprj/u_icache_2kb/dout0[*]}]
+	set isram_oport [concat $isram_oport [get_pins {mprj/u_icache_2kb/dout1[*]}]]
+
+	foreach pin $isram_iport {
+	   echo "ICAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+	foreach pin $isram_oport {
+	   echo "ICAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+    #DCACHE SRAM 
+    set dsram_iport [                     get_pins {mprj/u_dcache_2kb/din0[*]}]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/addr0[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/addr1[*]}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb0}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/csb1}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/web0}]]
+	set dsram_iport [concat $isram_iport [get_pins {mprj/u_dcache_2kb/wmask0[*]}]]
+
+    set dsram_oport [                     get_pins {mprj/u_dcache_2kb/dout0[*]}]
+	set dsram_oport [concat $isram_oport [get_pins {mprj/u_dcache_2kb/dout1[*]}]]
+
+	foreach pin $dsram_iport {
+	   echo "DCAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
+	foreach pin $dsram_oport {
+	   echo "DCAHCE SRAM Interface Timing for : [get_full_name $pin]"  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> sram.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin -format summary >> sram.min.summary.rpt
+        }
+
diff --git a/sta/scripts/ycr_core_timing.tcl b/sta/scripts/ycr_core_timing.tcl
index 62484ae..610b788 100644
--- a/sta/scripts/ycr_core_timing.tcl
+++ b/sta/scripts/ycr_core_timing.tcl
@@ -36,6 +36,9 @@
 	read_sdc -echo ./sdc/ycr_core_top.sdc	
 	set_propagated_clock [all_clocks]
 
+    report_annotated_check -list_annotated
+    report_annotated_check -list_not_annotated
+
 	check_setup  -verbose >  unconstraints.rpt
 	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
 	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 047d5a6..327fed6 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -1,5 +1,4 @@
 set ::env(IO_PCT) "0.2"
-set ::env(SYNTH_MAX_FANOUT) "5"
 set ::env(SYNTH_CAP_LOAD) "1"
 set ::env(SYNTH_TIMING_DERATE) 0.01
 set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25
@@ -12,9 +11,11 @@
 create_generated_clock -name csclk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -invert -comment {csclk} [get_pins housekeeping/_8847_/X]
 #create_clock [get_pins  clocking/pll_clk ] -name "pll_clk"  -period 25
 #create_clock [get_pins  clocking/pll_clk90 ] -name "pll_clk90"  -period 25
-create_clock [get_pins  housekeeping/serial_clock ] -name "serial_clock"  -period 50
-create_clock [get_pins  housekeeping/serial_load ]  -name "serial_load"  -period 50
+#create_clock [get_pins  housekeeping/serial_clock ] -name "serial_clock"  -period 50
+#create_clock [get_pins  housekeeping/serial_load ]  -name "serial_load"  -period 50
 
+create_generated_clock -name serial_clock -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 2 -comment {Serial Shift Clock} [get_pins housekeeping/serial_clock]
+create_generated_clock -name serial_load -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 2 -comment {Serial Shift Clock} [get_pins housekeeping/serial_load]
 
 
 create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
@@ -86,6 +87,10 @@
 #disable clock gating check at static clock select pins
 #set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S]
 
+set_false_path -through [get_pins housekeeping/serial_resetn]
+#set_case_analysis 0 [get_pins housekeeping/serial_bb_enable]
+set_case_analysis 0 [get_pins housekeeping/_9787_/Q]
+
 set_propagated_clock [all_clocks]
 
 #set_multicycle_path -setup -from [get_clocks {master_clock}] -to [get_clocks {csclk}] 2
@@ -93,8 +98,9 @@
 
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {wb_clk master_clock}]\
- -group [get_clocks {csclk}]\
- -group [get_clocks {serial_clock serial_load }]\
+ -group [get_clocks {csclk} ]\
+ -group [get_clocks {serial_clock} ]\
+ -group [get_clocks {serial_load} ]\
  -group [get_clocks {user_clk2}]\
  -group [get_clocks {int_pll_clock}]\
  -group [get_clocks {wbs_clk_i}]\
@@ -162,7 +168,6 @@
 set_output_delay $output_delay_value  -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_io0}]
 set_output_delay $output_delay_value  -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_io1}]
 
-set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
 
 ## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled 
 set_case_analysis 0 [get_pins housekeeping/_4449_/S]
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index c4b21ff..46e8d54 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -157,7 +157,7 @@
 	end
 
 // SSPI Slave I/F
-assign io_in[0]  = 1'b1; // RESET
+assign io_in[5]  = 1'b1; // RESET
 assign io_in[16] = 1'b0 ; // SPIS SCK 
 
 `ifndef GL // Drive Power for Hold Fix Buf
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index 02d493d..abbaa1d 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -124,8 +124,6 @@
        `endif
 
 
-	wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines;
-
 
 
 	initial begin
diff --git a/verilog/dv/common/agents/uart_agent.v b/verilog/dv/common/agents/uart_agent.v
index 5ca1813..0aab170 100644
--- a/verilog/dv/common/agents/uart_agent.v
+++ b/verilog/dv/common/agents/uart_agent.v
@@ -146,10 +146,9 @@
 
 ////////////////////////////////////////////////////////////////////////////////
 task read_char_chk;
-input 	expected_data;
+input [7:0]	expected_data;
 
 integer i;
-reg	[7:0] expected_data;
 reg 	[7:0] data;
 reg	parity;
 
@@ -340,7 +339,6 @@
 
 
 integer i;
-reg	[7:0] expected_data;
 reg 	[7:0] data;
 reg	parity;
 
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index bf2f2fb..8425b64 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@
 begin
    // Run in Fast Sim Mode
    `ifdef GL
-       force u_top.u_wb_host.u_reg._09718_.Q= 1'b1; 
+       force u_top.u_wb_host._09718_.Q= 1'b1; 
    `else
        force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1; 
     `endif
@@ -204,6 +204,7 @@
 
 //---------------------------------------------------------
 // Create Pull Up/Down Based on Reset Strap Parameter
+// System strap are in io_in[13] to [20] and 29 to [36]
 //---------------------------------------------------------
 genvar gCnt;
 generate
@@ -222,6 +223,13 @@
        end
     end
  end 
+ // Add Non Strap with pull-up to avoid unkown propagation during gate sim 
+ for(gCnt=0; gCnt<13; gCnt++) begin : g_nostrap1
+    pullup(io_in[gCnt]); 
+ end 
+ for(gCnt=21; gCnt<29; gCnt++) begin : g_nostrap2
+    pullup(io_in[gCnt]); 
+ end 
 endgenerate
 
 `ifdef RISC_BOOT // RISCV Based Test case
@@ -449,6 +457,32 @@
  baud_div = baud_div-1;
  end
  endtask
+ 
+/*************************************************************************
+ * This is I2C Prescale value computation logic
+ * Note: from I2c Logic 3 Prescale value SCL = 0, and 2 Prescale value SCL=1
+ *       Filtering logic uses two sample of Precale/4-1 period.
+ *       I2C Clock = System Clock / ((5*(Prescale-1)) + (2 * ((Prescale/4)-1)))
+ *   for 50Mhz system clock, 400Khz I2C clock
+ *       400,000 =  50,000,000 * (5*(Prescale-1) + 2*(Prescale/4+1)+2)
+ *      5*Prescale -5 + 2*Prescale/4 + 2 + 2= 50,000,000/400,000
+ *      5*prescale -5 + Prescale/2 + 4 = 125
+ *      (10*prescale+Prescale)/2 - 1 = 125
+ *      (11 *Prescale)/2 = 125+1
+ *      Prescale = 126*2/11
+
+ * *************************************************************************/
+ task tb_set_i2c_prescale;
+ input [31:0] ref_clk;
+ input [31:0] rate;
+ output [15:0] prescale;
+ reg   [15:0] prescale;
+ begin 
+   prescale   = ref_clk/rate; 
+   prescale = prescale +1; 
+   prescale = (prescale *2)/11; 
+ end
+ endtask
 
 /**
 `ifdef GL
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index c4d81b8..feab774 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -622,7 +622,7 @@
 begin
    //force clock_mon = u_top.u_wb_host.pll_clk_out[0];
    `ifdef GL
-      force clock_mon = u_top.u_wb_host.pll_clk_out[0];
+      force clock_mon = u_top.u_wb_host.int_pll_clock;
     `else
       force clock_mon = u_top.u_wb_host.int_pll_clock;
 
@@ -635,7 +635,11 @@
 task uartm_clock_monitor;
 input real exp_period;
 begin
+   `ifdef GL
+   force clock_mon = u_top.u_wb_host._09314_.Q;
+    `else
    force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
+    `endif
    check_clock_period("UART CLock",exp_period);
    release clock_mon;
 end
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 0547990..c4b27a9 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -76,6 +76,7 @@
 
 `include "user_tasks.sv"
 
+reg [15:0] prescale;
 
 //----------------------------------
 // Uart Configuration
@@ -119,9 +120,12 @@
     @(posedge  clock);
     $display("---------- Initialize I2C Master ----------"); 
 
+    // Sysclock: 50Mhz, I2C : 400Khz
+    tb_set_i2c_prescale(50000000,400000,prescale);
+    
     //Wrire Prescale registers
-     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7);  
-     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),8'h00);  
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),prescale[7:0]);  
+     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),prescale[15:8]);  
     // Core Enable
      wb_user_core_write(`ADDR_SPACE_I2CM+(8'h2<<2),8'h80);  
     
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 73f44ad..c33eee1 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -33,10 +33,20 @@
 int i = 0; 
 int clk = 0;
 
+void putdword(uint32_t Data)
+{
+	reg_uart_data = Data >> 24; // MSB [31:24];
+	reg_uart_data = Data >> 16; // MSB [23:16];
+	reg_uart_data = Data >> 8;  // MSB [15:8];
+	reg_uart_data = Data;       // MSB [7:0];
+}
+
+
 void main()
 {
 
 	int bFail = 0;
+    char DataIn[5];
 	/* 
 	IO Control Registers
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
@@ -127,4 +137,5 @@
     } else {
         reg_mprj_datal = 0xAB600000;
     }
+    putdword(reg_mprj_datal);
 }
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 75065f4..0dee772 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -32,6 +32,11 @@
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v
+
+-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
+
+-v $(USER_PROJECT_VERILOG)/rtl/dig2ana/src/dig2ana_reg.sv
+
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
 -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
diff --git a/verilog/rtl/dac/src/dac_top.v b/verilog/rtl/dac/src/dac_top.v
new file mode 100644
index 0000000..951076d
--- /dev/null
+++ b/verilog/rtl/dac/src/dac_top.v
@@ -0,0 +1,24 @@
+module dac_top (Vout0,
+    Vout1,
+    Vout2,
+    Vout3,
+    Vref,
+    vccd1,
+    vssd1,
+    DIn0,
+    DIn1,
+    DIn2,
+    DIn3);
+ output Vout0;
+ output Vout1;
+ output Vout2;
+ output Vout3;
+ input Vref;
+ input vccd1;
+ input vssd1;
+ input [7:0] DIn0;
+ input [7:0] DIn1;
+ input [7:0] DIn2;
+ input [7:0] DIn3;
+
+endmodule
diff --git a/verilog/rtl/dig2ana/src/dig2ana_reg.sv b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
new file mode 100644
index 0000000..ba7b364
--- /dev/null
+++ b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
@@ -0,0 +1,206 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Digital To Analog Register                                  ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////     Manages all the analog related config                    ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 29rd Sept 2022, Dinesh A                            ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+
+module dig2ana_reg #(   
+                        parameter DW = 32,    // DATA WIDTH
+                        parameter AW = 4,     // ADDRESS WIDTH
+                        parameter BW = 4      // BYTE WIDTH
+                    ) (
+                       // System Signals
+                       // Inputs
+		               input logic           mclk                 ,
+                       input logic           h_reset_n            ,
+
+		               // Reg Bus Interface Signal
+                       input logic           reg_cs               ,
+                       input logic           reg_wr               ,
+                       input logic [AW-1:0]  reg_addr             ,
+                       input logic [DW-1:0]  reg_wdata            ,
+                       input logic [BW-1:0]  reg_be               ,
+
+                       // Outputs
+                       output logic [DW-1:0] reg_rdata            ,
+                       output logic          reg_ack              ,
+
+                       output logic [7:0]    cfg_dac0_mux_sel     ,
+                       output logic [7:0]    cfg_dac1_mux_sel     ,
+                       output logic [7:0]    cfg_dac2_mux_sel     ,
+                       output logic [7:0]    cfg_dac3_mux_sel     
+
+
+
+                ); 
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic          sw_rd_en              ;
+logic          sw_wr_en              ;
+logic [AW-1:0] sw_addr               ; 
+logic [DW-1:0] sw_reg_wdata          ;
+logic [BW-1:0] sw_be                 ;
+
+logic [DW-1:0] reg_out               ;
+logic [DW-1:0] reg_0                 ; 
+logic [DW-1:0] reg_1                 ; 
+logic [DW-1:0] reg_2                 ; 
+logic [DW-1:0] reg_3                 ; 
+
+
+assign       sw_addr       = reg_addr;
+assign       sw_be         = reg_be;
+assign       sw_rd_en      = reg_cs & !reg_wr;
+assign       sw_wr_en      = reg_cs & reg_wr;
+assign       sw_reg_wdata  = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire   sw_wr_en_0  = sw_wr_en  & (sw_addr == 4'h0);
+wire   sw_wr_en_1  = sw_wr_en  & (sw_addr == 4'h1);
+wire   sw_wr_en_2  = sw_wr_en  & (sw_addr == 4'h2);
+wire   sw_wr_en_3  = sw_wr_en  & (sw_addr == 4'h3);
+
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+   if (h_reset_n == 1'b0) begin
+      reg_rdata  <= 'h0;
+      reg_ack    <= 1'b0;
+   end else if (reg_cs && !reg_ack && sw_rd_en) begin
+      reg_rdata  <= reg_out[DW-1:0] ;
+      reg_ack    <= 1'b1;
+   end else begin
+      reg_ack    <= 1'b0;
+   end
+end
+
+//-----------------------------------------------------------------------
+//   reg-0
+//-----------------------------------------------------------------
+
+assign cfg_dac0_mux_sel = reg_0[7:0];
+generic_register #(8,8'h0  ) u_reg0_be0 (
+	      .we            ({8{sw_wr_en_0 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_0[7:0]        )
+          );
+
+assign reg_0[31:24] = 'h0;
+
+//-----------------------------------------------------------------------
+//   reg-1
+//-----------------------------------------------------------------
+
+assign cfg_dac1_mux_sel = reg_1[7:0];
+generic_register #(8,8'h0  ) u_reg1_be0 (
+	      .we            ({8{sw_wr_en_1 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_1[7:0]        )
+          );
+
+assign reg_1[31:24] = 'h0;
+
+//-----------------------------------------------------------------------
+//   reg-2
+//-----------------------------------------------------------------
+
+assign cfg_dac2_mux_sel = reg_2[7:0];
+generic_register #(8,8'h0  ) u_reg2_be0 (
+	      .we            ({8{sw_wr_en_2 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_2[7:0]        )
+          );
+
+assign reg_2[31:24] = 'h0;
+
+//-----------------------------------------------------------------------
+//   reg-3
+//-----------------------------------------------------------------
+
+assign cfg_dac3_mux_sel = reg_3[7:0];
+generic_register #(8,8'h0  ) u_reg3_be0 (
+	      .we            ({8{sw_wr_en_3 & 
+                             sw_be[0]   }}  ),		 
+	      .data_in       (sw_reg_wdata[7:0]    ),
+	      .reset_n       (h_reset_n           ),
+	      .clk           (mclk              ),
+	      
+	      //List of Outs
+	      .data_out      (reg_3[7:0]        )
+          );
+
+assign reg_3[31:24] = 'h0;
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin 
+  reg_out [31:0] = 32'h0;
+
+  case (sw_addr [3:0])
+    4'b0000 : reg_out [31:0] = reg_0  ;     
+    4'b0001 : reg_out [31:0] = reg_1  ;    
+    4'b0010 : reg_out [31:0] = reg_2  ;     
+    4'b0011 : reg_out [31:0] = reg_3  ;    
+    default  : reg_out [31:0] = 32'h0;
+  endcase
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/reset_sync.sv b/verilog/rtl/lib/reset_sync.sv
index 5a56a93..5b5c7fa 100644
--- a/verilog/rtl/lib/reset_sync.sv
+++ b/verilog/rtl/lib/reset_sync.sv
@@ -95,7 +95,7 @@
       in_data_2s <= in_data_s;
    end
 end
-
+//assign srst_n =  (scan_mode) ? arst_n : in_data_2s;
 ctech_mux2x1 u_buf  (.A0(in_data_2s), .A1(arst_n), .S(scan_mode), .X(srst_n));
 
 endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 491a4a0..0a78310 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -196,8 +196,14 @@
                output logic[4:0]       cfg_pll_fed_div    , // PLL feedback division ratio
                output logic            cfg_dco_mode       , // Run PLL in DCO mode
                output logic[25:0]      cfg_dc_trim        , // External trim for DCO mode
-               output logic            pll_ref_clk         // Input oscillator to match
+               output logic            pll_ref_clk        , // Input oscillator to match
 
+               
+               // DAC Config
+               output logic [7:0]    cfg_dac0_mux_sel     ,
+               output logic [7:0]    cfg_dac1_mux_sel     ,
+               output logic [7:0]    cfg_dac2_mux_sel     ,
+               output logic [7:0]    cfg_dac3_mux_sel     
 
    ); 
 
@@ -261,6 +267,7 @@
 `define SEL_TIMER   3'b011   // TIMER REGISTER
 `define SEL_SEMA    3'b100   // SEMAPHORE REGISTER
 `define SEL_WS      3'b101   // WS281x  REGISTER
+`define SEL_D2A     3'b110   // Digital2Analog  REGISTER
 
 
 //----------------------------------------
@@ -284,6 +291,9 @@
 logic [31:0]  reg_ws_rdata;
 logic         reg_ws_ack;
 
+logic [31:0]  reg_d2a_rdata;
+logic         reg_d2a_ack;
+
 logic [7:0]   pwm_gpio_in;
 
 assign reg_rdata = (reg_addr[9:7] == `SEL_GLBL)  ? {reg_glbl_rdata} : 
@@ -291,21 +301,24 @@
 	               (reg_addr[9:7] == `SEL_PWM)   ? {reg_pwm_rdata}  :
 	               (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_rdata  : 
 	               (reg_addr[9:7] == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
-	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_rdata     : 'h0;
+	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_rdata     : 
+	               (reg_addr[9:7] == `SEL_D2A)   ? reg_d2a_rdata    : 'h0;
 
 assign reg_ack   = (reg_addr[9:7] == `SEL_GLBL)  ? reg_glbl_ack   : 
 	               (reg_addr[9:7] == `SEL_GPIO)  ? reg_gpio_ack   : 
 	               (reg_addr[9:7] == `SEL_PWM)   ? reg_pwm_ack    : 
 	               (reg_addr[9:7] == `SEL_TIMER) ? reg_timer_ack  : 
 	               (reg_addr[9:7] == `SEL_SEMA)  ? reg_sema_ack   : 
-	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_ack     : 1'b0;
+	               (reg_addr[9:7] == `SEL_WS)    ? reg_ws_ack     : 
+	               (reg_addr[9:7] == `SEL_D2A)   ? reg_d2a_ack    : 1'b0;
 
 wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
 wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
 wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
 wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
 wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
-wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS) ? reg_cs : 1'b0;
+wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS)   ? reg_cs : 1'b0;
+wire reg_d2a_cs   = (reg_addr[9:7] == `SEL_D2A)  ? reg_cs : 1'b0;
 
 //---------------------------------------------------------------------
 
@@ -621,6 +634,34 @@
 
    ); 
 
+//-----------------------------------------------------------------------
+// Digital To Analog Register
+//-----------------------------------------------------------------------
+dig2ana_reg  u_d2a(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (s_reset_ssn                ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_d2a_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[5:2]              ),
+              .reg_wdata                (reg_wdata[15:0]            ),
+              .reg_be                   (reg_be[1:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_d2a_rdata              ),
+              .reg_ack                  (reg_d2a_ack                ),
+
+              .cfg_dac0_mux_sel         (cfg_dac0_mux_sel           ),
+              .cfg_dac1_mux_sel         (cfg_dac1_mux_sel           ),
+              .cfg_dac2_mux_sel         (cfg_dac2_mux_sel           ),
+              .cfg_dac3_mux_sel         (cfg_dac3_mux_sel           )
+
+
+         );
+
 endmodule 
 
 
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 325c436..4c63893 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h1409_2022;
+parameter CHIP_RELEASE_DATE = 32'h2909_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0005_5000;
+parameter CHIP_REVISION   = 32'h0005_6000;
 
 parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_0111;
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 048116a..2a12a4b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -280,7 +280,9 @@
 ////          2'b00 - Auto, 2'b01 - 50Mhz, 2'b10 - 4Mhz,          ////
 ////          2'b11 - LA control                                  ////
 ////          B. digital_pll is re-synth with maual placement     ////
-////                                                              ////
+////    5.6  Sept 29 2022, Dinesh A                               ////
+////         A. 4x 8bit DAC Integration                           ////
+////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -762,6 +764,14 @@
 wire                           s_reset_n                              ;
 wire                           cfg_strap_pad_ctrl                     ;
 
+//----------------------------------------------------------------------
+// DAC Config
+//----------------------------------------------------------------------
+wire [7:0]                     cfg_dac0_mux_sel                       ;
+wire [7:0]                     cfg_dac1_mux_sel                       ;
+wire [7:0]                     cfg_dac2_mux_sel                       ;
+wire [7:0]                     cfg_dac3_mux_sel                       ;
+
 //---------------------------------------------------------------------
 // Strap
 //---------------------------------------------------------------------
@@ -1494,68 +1504,25 @@
        .cfg_pll_fed_div        (cfg_pll_fed_div         ), 
        .cfg_dco_mode           (cfg_dco_mode            ), 
        .cfg_dc_trim            (cfg_dc_trim             ),
-       .pll_ref_clk            (pll_ref_clk             )
+       .pll_ref_clk            (pll_ref_clk             ),
 
+       .cfg_dac0_mux_sel       (cfg_dac0_mux_sel        ),
+       .cfg_dac1_mux_sel       (cfg_dac1_mux_sel        ),
+       .cfg_dac2_mux_sel       (cfg_dac2_mux_sel        ),
+       .cfg_dac3_mux_sel       (cfg_dac3_mux_sel        )
 
    ); 
 
-/***
-sar_adc  u_adc (
-`ifdef USE_POWER_PINS
-        .vccd1 (vccd1),// User area 1 1.8V supply
-        .vssd1 (vssd1),// User area 1 digital ground
-        .vccd2 (vccd1), // (vccd2),// User area 2 1.8V supply (analog) - DOTO: Need Fix
-        .vssd2 (vssd1), // (vssd2),// User area 2 ground      (analog) - DOTO: Need Fix
-`endif
 
-    
-        .clk           (wbd_clk_adc_rp ),// The clock (digital)
-        .reset_n       (wbd_int_rst_n   ),// Active low reset (digital)
-
-    // Reg Bus Interface Signal
-        .reg_cs        (wbd_adc_stb_o   ),
-        .reg_wr        (wbd_adc_we_o    ),
-        .reg_addr      (wbd_adc_adr_o[7:0] ),
-        .reg_wdata     (wbd_adc_dat_o   ),
-        .reg_be        (wbd_adc_sel_o   ),
-
-    // Outputs
-        .reg_rdata     (wbd_adc_dat_i   ),
-        .reg_ack       (wbd_adc_ack_i   ),
-
-        .pulse1m_mclk  (pulse1m_mclk),
-
-
-	// DAC I/F
-        .sar2dac         (sar2dac       ), 
-        //.analog_dac_out  (analog_dac_out) ,  // TODO: Need to connect to DAC O/P
-        .analog_dac_out  (analog_io[6]) , 
-
-        // ADC Input 
-        .analog_din(analog_io[5:0])    // (Analog)
-
-);
-***/
-
-/****
-* TODO: Need to uncomment the DAC
-DAC_8BIT u_dac (
-     `ifdef USE_POWER_PINS
-        .vdd(vccd2),
-        .gnd(vssd2),
-    `endif 
-        .d0(sar2dac[0]),
-        .d1(sar2dac[1]),
-        .d2(sar2dac[2]),
-        .d3(sar2dac[3]),
-        .d4(sar2dac[4]),
-        .d5(sar2dac[5]),
-        .d6(sar2dac[6]),
-        .d7(sar2dac[7]),
-        .inp1(analog_io[6]),
-        .out_v(analog_dac_out)
-    );
-
-**/
-
+dac_top  u_4x8bit_dac(
+    .Vref (analog_io[23]),
+    .DIn0 (cfg_dac0_mux_sel),
+    .DIn1 (cfg_dac1_mux_sel),
+    .DIn2 (cfg_dac2_mux_sel),
+    .DIn3 (cfg_dac3_mux_sel),
+    .Vout0(analog_io[15]   ),
+    .Vout1(analog_io[16]   ),
+    .Vout2(analog_io[17]   ),
+    .Vout3(analog_io[18]   )
+   );
 endmodule : user_project_wrapper