diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 37b0dcc..4cb1011 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,14 +19,20 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 riscv_regress
+PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master  user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2
 
 all:  ${PATTERNS}
-	echo "################# Test case Summary #####################" > regression.rpt
+	echo "################# RTL Test case Summary #####################" > regression.rpt
 	xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt & 
 	for i in ${PATTERNS}; do \
-		( cd $$i && make | tee run.log && grep Monitor run.log | grep $$i >> ../regression.rpt) ; \
+		( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
 	done
+	#echo "################# GL Test case Summary #####################" >> regression.rpt
+	#\rm -rf */*.vvp
+	#for i in ${PATTERNS}; do \
+	#	( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+	#done
+	echo "################# End of Test case Summary #####################" >> regression.rpt
 
 DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
 $(DV_PATTERNS): verify-% : 
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index 5152893..b618915 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -121,36 +121,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
 	initial begin
         uart_data_bit           = 2'b11;
         uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
index 275b18b..7f5b1c0 100644
--- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -150,35 +150,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
 
 	initial begin
         uart_data_bit           = 2'b11;
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
index 23e360e..30797d1 100644
--- a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
+++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -186,36 +186,6 @@
            // Uart pins io_in[2], io_in[1] are excluded
           } = (u_top.p_reset_n == 0) ? 23'hZZ_ZZZZ: arduino_din; // Tri-state untill Strap pull completed
                     
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
     reg[7:0] pinmap[0:22]; //ardiono to gpio pinmaping
 
 	initial begin
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 44b41db..d1141a8 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -122,36 +122,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
 	initial begin
                uart_data_bit           = 2'b11;
                uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index ace2a5b..72c3fbe 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -127,36 +127,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
 	initial begin
         uart_data_bit           = 2'b11;
         uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
index 3c94c7d..40f9df8 100644
--- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -127,36 +127,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
 	initial begin
         uart_data_bit           = 2'b11;
         uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp b/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp
index c857650..21cfce6 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp
@@ -24,11 +24,8 @@
 */
 
 
-#line 25 "/tmp/.arduinoIDE-unsaved202266-51666-8e7jjt.yj22m/MultiSerial/MultiSerial.ino"
 void setup();
-#line 31 "/tmp/.arduinoIDE-unsaved202266-51666-8e7jjt.yj22m/MultiSerial/MultiSerial.ino"
 void loop();
-#line 25 "/tmp/.arduinoIDE-unsaved202266-51666-8e7jjt.yj22m/MultiSerial/MultiSerial.ino"
 void setup() {
   // initialize both serial ports:
   Serial.begin(288000);
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index fc55f4c..45fe601 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -121,36 +121,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
 	initial begin
                uart_data_bit           = 2'b11;
                uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index 34247b0..c4b21ff 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -115,7 +115,7 @@
 
         wait_riscv_boot();
 
-        repeat (5000) @(posedge clock);  // wait for Processor Get Ready
+        repeat (10000) @(posedge clock);  // wait for Processor Get Ready
 
 
 		$display("Monitor: Reading Back the expected value");
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
index a02727a..567a67c 100644
--- a/verilog/dv/arduino_string/arduino_string_tb.v
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -125,36 +125,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
 	initial begin
         uart_data_bit           = 2'b11;
         uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
index 3432fca..8493415 100644
--- a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -150,36 +150,6 @@
 	   end
        `endif
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
      /************* Port-D Mapping **********************************
       *             Arduino-No
       *   Pin-2        0         PD0/RXD[0]                digital_io[6]
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index 043a19a..02d493d 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -128,37 +128,6 @@
 
 
 
-       /*************************************************************************
-       * This is Baud Rate to clock divider conversion for Test Bench
-       * Note: DUT uses 16x baud clock, where are test bench uses directly
-       * baud clock, Due to 16x Baud clock requirement at RTL, there will be
-       * some resolution loss, we expect at lower baud rate this resolution
-       * loss will be less. For Quick simulation perpose higher baud rate used
-       * *************************************************************************/
-       task tb_set_uart_baud;
-       input [31:0] ref_clk;
-       input [31:0] baud_rate;
-       output [31:0] baud_div;
-       reg   [31:0] baud_div;
-       begin
-	  // for 230400 Baud = (50Mhz/230400) = 216.7
-	  baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
-	  // Baud 16x = 216/16 = 13
-          baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
-	  // Test bench baud clock , 16x of above value
-	  // 13 * 16 = 208,  
-	  // (Note if you see original value was 216, now it's 208 )
-          baud_div = baud_div * 16;
-	  // Test bench half cycle counter to toggle it 
-	  // 208/2 = 104
-           baud_div = baud_div/2;
-	  //As counter run's from 0 , substract from 1
-	   baud_div = baud_div-1;
-       end
-       endtask
-       
-
-
 	initial begin
 
 
diff --git a/verilog/dv/uart_master_test1/uart_master_test1_tb.v b/verilog/dv/uart_master_test1/uart_master_test1_tb.v
index 2a99ff7..fe63f38 100644
--- a/verilog/dv/uart_master_test1/uart_master_test1_tb.v
+++ b/verilog/dv/uart_master_test1/uart_master_test1_tb.v
@@ -18,8 +18,8 @@
 `timescale 1 ns / 1 ps
 `include "uart_agent.v"
 
-`define TB_HEX "uart_master.hex"
-`define TB_TOP  uart_master_tb
+`define TB_HEX "uart_master_test1.hex"
+`define TB_TOP  uart_master_test1_tb
 module `TB_TOP;
 	reg clock;
 	reg RSTB;
@@ -75,8 +75,8 @@
 		$dumpfile("simx.vcd");
 		$dumpvars(2, `TB_TOP);
 		$dumpvars(0, `TB_TOP.tb_master_uart);
+		$dumpvars(1, `TB_TOP.u_top.mprj.u_wb_host);
 		$dumpvars(0, `TB_TOP.u_top.mprj.u_wb_host.u_uart2wb);
-		$dumpvars(1, `TB_TOP.tb_master_uart);
 		$dumpvars(0, `TB_TOP.u_top.mprj.u_pinmux);
 	end
        `endif
@@ -103,7 +103,7 @@
 	initial begin
 
             strap_in = 0;
-            strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA
+            strap_in[`PSTRAP_UARTM_CFG] = 2'b11; // uart master config control - load from LA
             apply_strap(strap_in);
 
             uart_data_bit           = 2'b11;
@@ -244,7 +244,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("uart_master.hex")
+		.FILENAME(`TB_HEX)
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 2a1858d..c4d81b8 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -74,6 +74,7 @@
 `timescale 1 ns/1 ps
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
 `include "user_params.svh"
 
 `define TB_TOP user_basic_tb
@@ -100,7 +101,6 @@
 
 reg [15:0]     uart_rx_nu           ;
 reg [15:0]     uart_tx_nu           ;
-reg [7:0]      uart_write_data [0:39];
 reg 	       uart_fifo_enable     ;	// fifo mode disable
 
 wire           clock_mon;
@@ -109,8 +109,10 @@
 wire [31:0]    strap_sticky;
 reg  [7:0]     test_id;
 reg  [25:0]    bcount;
+wire uart_txd,uart_rxd;
+reg            flag;
 
-assign io_in = {26'h0,xtal_clk,11'h0};
+assign io_in = {26'h0,xtal_clk,4'h0,uart_rxd,6'h0};
 
 wire [14:0] pstrap_select;
 
@@ -317,7 +319,9 @@
        $display("Step-5, Checking the uart Master baud-16x clock is 9600* 16");
        test_id = 5;
 
-       apply_strap(16'h10); // [4] -  // uart master config control - constant value based on system clock selection
+       strap_in = 0;
+       strap_in[`PSTRAP_UARTM_CFG] = 2'b01; // constant value based on system clock-50Mhz
+       apply_strap(strap_in); 
 
        repeat (10) @(posedge clock);
        uartm_clock_monitor(6510); // 1/(9600*16) = 6510 ns, Assumption is user_clock1 = 40Mhz
@@ -329,13 +333,97 @@
        end
        $display("##########################################################");
 
+       $display("##########################################################");
+       $display("Step-6, Checking the uart Master Auto Detect Mode");
+       test_id = 6;
 
+       strap_in = 0;
+       strap_in[`PSTRAP_UARTM_CFG] = 2'b00; // Auto Detect Mode
+       apply_strap(strap_in); 
+
+       tb_master_uart.uart_init;
+       uart_data_bit           = 2'b11;
+       uart_stop_bits          = 1; // 0: 1 stop bit; 1: 2 stop bit;
+       uart_stick_parity       = 0; // 1: force even parity
+       uart_parity_en          = 0; // parity enable
+       uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+       uart_divisor            = 15;// divided by n * 16
+       uart_timeout            = 600;// wait time limit
+       uart_fifo_enable        = 0;	// fifo mode disable
+       tb_master_uart.debug_mode = 0; // disable debug display
+	   tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 288000
+       tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
+
+       repeat (10) @(posedge clock);
+       tb_master_uart.write_char(8'hA); // New line for auto detect
+
+       repeat (10) @(posedge clock);
+       uartm_clock_monitor(200); // 1/(28800*16) = 217 ns - Adjusting 20ns (50Mhz) boundary => 200 
+
+       // Wait for Initial command from uart master
+       flag = 0;
+       while(flag == 0)
+       begin
+            tb_master_uart.read_char(read_data,flag);
+            $write ("%c",read_data);
+       end
+       uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,CHIP_SIGNATURE);
+
+       if(test_fail == 1) begin
+          $display("ERROR: Step-6,  Checking the uart Master Auto Detect baud-28800 - FAILED");
+       end else begin
+          $display("STATUS: Step-6,  Checking the uart Master Auto Detect baud-28800  - PASSED");
+       end
+       $display("##########################################################");
+
+       $display("##########################################################");
+       $display("Step-7, Checking the uart Master Auto Detect Mode");
+       test_id = 7;
+
+       strap_in = 0;
+       strap_in[`PSTRAP_UARTM_CFG] = 2'b00; // Auto Detect Mode
+       apply_strap(strap_in); 
+
+       tb_master_uart.uart_init;
+       uart_data_bit           = 2'b11;
+       uart_stop_bits          = 1; // 0: 1 stop bit; 1: 2 stop bit;
+       uart_stick_parity       = 0; // 1: force even parity
+       uart_parity_en          = 0; // parity enable
+       uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+       uart_divisor            = 15;// divided by n * 16
+       uart_timeout            = 600;// wait time limit
+       uart_fifo_enable        = 0;	// fifo mode disable
+       tb_master_uart.debug_mode = 0; // disable debug display
+	   tb_set_uart_baud(50000000,38400,uart_divisor);// 50Mhz Ref clock, Baud Rate: 38400
+       tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
+
+       repeat (10) @(posedge clock);
+       tb_master_uart.write_char(8'hA); // New line for auto detect
+
+       repeat (10) @(posedge clock);
+       uartm_clock_monitor(1620); // 1/(38400*16) = 1627.6 ns, Adjusting to 20ns boundary => 1620
+   
+       // Wait for Initial command from uart master
+       flag = 0;
+       while(flag == 0)
+       begin
+            tb_master_uart.read_char(read_data,flag);
+            $write ("%c",read_data);
+       end
+       uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,CHIP_SIGNATURE);
+
+       if(test_fail == 1) begin
+          $display("ERROR: Step-7,  Checking the uart Master Auto Detect baud-38400 - FAILED");
+       end else begin
+          $display("STATUS: Step-7,  Checking the uart Master Auto Detect baud-38400  - PASSED");
+       end
+       $display("##########################################################");
         
        `ifndef GL  
        $display("###################################################");
-       $display("Step-5,Monitor: Checking the PLL:");
+       $display("Step-8,Monitor: Checking the PLL:");
        $display("###################################################");
-       test_id = 5;
+       test_id = 8;
        // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03
        // Checking the expression
        //   Internal PLL delay = 1.168 + 0.012 * $itor(bcount)
@@ -361,18 +449,18 @@
        pll_clock_monitor(5);
        */
        if(test_fail == 1) begin
-          $display("ERROR: Step-5, Checking the PLL - FAILED");
+          $display("ERROR: Step-8, Checking the PLL - FAILED");
        end else begin
-          $display("STATUS: Step-5, Checking the PLL - PASSED");
+          $display("STATUS: Step-8, Checking the PLL - PASSED");
        end
        $display("##########################################################");
        
        
        $display("###################################################");
-       $display("Step-6,Monitor: PLL Monitor Clock output:");
+       $display("Step-9,Monitor: PLL Monitor Clock output:");
        $display("###################################################");
        $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
-       test_id = 6;
+       test_id = 9;
        test_step = 13;
        init();
        repeat (10) @(posedge clock);
@@ -384,34 +472,34 @@
        dbg_clk_monitor();
           
        if(test_fail == 1) begin
-          $display("ERROR: Step-6, PLL Monitor Clock output - FAILED");
+          $display("ERROR: Step-9, PLL Monitor Clock output - FAILED");
        end else begin
-          $display("STATUS: Step-6, PLL Monitor Clock output - PASSED");
+          $display("STATUS: Step-9, PLL Monitor Clock output - PASSED");
        end
       
        `endif
        $display("##########################################################");
-        $display("Step-7,Monitor: Checking the chip signature :");
+        $display("Step-10,Monitor: Checking the chip signature :");
         $display("###################################################");
-       test_id = 7;
+       test_id = 10;
         test_step = 14;
         // Remove Wb/PinMux Reset
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
-         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343);
-         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h0709_2022);
-         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_4000);
+         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
+         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
+         wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
          if(test_fail == 1) begin
-            $display("ERROR: Step-7,Monitor: Checking the chip signature - FAILED");
+            $display("ERROR: Step-10,Monitor: Checking the chip signature - FAILED");
          end else begin
-            $display("STATUS: Step-7,Monitor: Checking the chip signature - PASSED");
+            $display("STATUS: Step-10,Monitor: Checking the chip signature - PASSED");
 
          $display("##########################################################");
 
           end
       end
       begin
-         repeat (30000) @(posedge clock);
+         repeat (500000) @(posedge clock);
    	       // $display("+1000 cycles");
          test_fail = 1;
       end
@@ -438,6 +526,19 @@
       $finish;
 end
 
+//---------------------------
+//  UART Agent integration
+// --------------------------
+
+assign uart_txd   = io_out[7];
+//assign io_in[6]  = uart_rxd ; // Assigned at top-level
+ 
+uart_agent tb_master_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
 
 
 task clock_monitor2;
@@ -615,5 +716,6 @@
 
 
 
+`include "uart_master_tasks.sv"
 endmodule
 `default_nettype wire
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index 0efe8fe..1e313c4 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -245,6 +245,9 @@
         // Disable Multi func
         wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h000);
 
+		// config 1us based on system clock - 1000/25ns = 40 
+        wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
+
 		/************* GPIO As Output ******************/
 		$display("#####################################");
 		$display("Step-1: Testing GPIO As Output ");
@@ -255,15 +258,15 @@
 		cmp_gpio_output(8'h55,8'h55,8'h55,8'h55);
 
 		// Set the GPIO Output data: 0xAAAAAAAA
-                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hAAAAAAAA);
+        wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hAAAAAAAA);
 		cmp_gpio_output(8'hAA,8'hAA,8'hAA,8'hAA);
 
 		// Set the GPIO Output data: 0x5A5A5A5A5A5A
-                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h5A5A5A5A);
+        wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h5A5A5A5A);
 		cmp_gpio_output(8'h5A,8'h5A,8'h5A,8'h5A);
 		
 		// Set the GPIO Output data: 0xA5A5A5A5A5A5
-                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hA5A5A5A5);
+        wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hA5A5A5A5);
 		cmp_gpio_output(8'hA5,8'hA5,8'hA5,8'hA5);
 
 		/************* GPIO As Input ******************/
@@ -324,9 +327,10 @@
 		// Drive GPIO with 0xA5
 		cmp_gpio_neg_intr(8'hA5,8'hA5,8'hA5,8'hA5);
 
-	        repeat (200) @(posedge clock);
+	     repeat (200) @(posedge clock);
+        check_fast_dglitch();
 
-
+        check_slow_dglitch();
 		repeat (100) @(posedge clock);
 			// $display("+1000 cycles");
 
@@ -420,6 +424,7 @@
     port_c_out  = port_c;
     port_d_out  = port_d;
 
+	repeat (200) @(posedge clock); // for de-glitch period
     wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
 end
 endtask
@@ -543,6 +548,143 @@
 end
 endtask
 
+// Check for slow De-Glitch (1us based sampling)
+task check_slow_dglitch;
+reg [7:0] port_a;
+reg [7:0] port_b;
+reg [7:0] port_c;
+reg [7:0] port_d;
+begin
+    $display("STATUS: Testing Slow De-Glitch Mode");
+    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,32'h0);
+    port_a = 8'hAA;
+    port_b = 8'hAA;
+    port_c = 8'hAA;
+    port_d = 8'hAA;
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+
+	repeat (200) @(posedge clock); // for de-glitch period
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+
+    port_a_out = $random();
+    port_b_out = $random();
+    port_c_out = $random();
+    port_d_out = $random();
+	repeat (10) @(posedge clock); 
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (10) @(posedge clock); 
+    port_a_out = $random();
+    port_b_out = $random();
+    port_c_out = $random();
+    port_d_out = $random();
+	repeat (10) @(posedge clock); 
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (10) @(posedge clock); 
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+
+    port_a = 8'h11;
+    port_b = 8'h22;
+    port_c = 8'h33;
+    port_d = 8'h44;
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (200) @(posedge clock); 
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+    
+    port_a = 8'h55;
+    port_b = 8'h66;
+    port_c = 8'h77;
+    port_d = 8'h88;
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (200) @(posedge clock); 
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+end
+endtask
+
+
+// Check for slow De-Glitch (system clock based sampling)
+task check_fast_dglitch;
+reg [7:0] port_a;
+reg [7:0] port_b;
+reg [7:0] port_c;
+reg [7:0] port_d;
+begin
+    $display("STATUS: Testing Fast De-Glitch Mode");
+    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,32'h100);
+    port_a = 8'h55;
+    port_b = 8'h55;
+    port_c = 8'h55;
+    port_d = 8'h55;
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+
+	repeat (10) @(posedge clock); // for de-glitch period
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+
+    port_a_out = $random();
+    port_b_out = $random();
+    port_c_out = $random();
+    port_d_out = $random();
+
+	repeat (2) @(posedge clock); 
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (2) @(posedge clock); 
+
+    port_a_out = $random();
+    port_b_out = $random();
+    port_c_out = $random();
+    port_d_out = $random();
+	repeat (2) @(posedge clock); 
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (2) @(posedge clock); 
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+
+    port_a = 8'h11;
+    port_b = 8'h22;
+    port_c = 8'h33;
+    port_d = 8'h44;
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (10) @(posedge clock); 
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+    
+    port_a = 8'h55;
+    port_b = 8'h66;
+    port_c = 8'h77;
+    port_d = 8'h88;
+    port_a_out  = port_a;
+    port_b_out  = port_b;
+    port_c_out  = port_c;
+    port_d_out  = port_d;
+	repeat (10) @(posedge clock); 
+    wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,port_a & 8'h1F});
+
+end
+endtask
 
 endmodule
 `default_nettype wire
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index 8d7a20a..2cdec85 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -72,7 +72,7 @@
 
 
 module user_pwm_tb;
-parameter real CLK1_PERIOD  = 25;
+parameter real CLK1_PERIOD  = 20; // 50Mhz
 parameter real CLK2_PERIOD = 2.5;
 parameter real IPLL_PERIOD = 5.008;
 parameter real XTAL_PERIOD = 6;
@@ -81,14 +81,16 @@
 
 
 
-	reg [31:0] OneMsPeriod;
+	reg [31:0] pwm0_period;
+	reg [31:0] pwm1_period;
+	reg [31:0] pwm2_period;
+	reg [31:0] pwm3_period;
+	reg [31:0] pwm4_period;
+	reg [31:0] pwm5_period;
     integer    test_step;
     wire       clock_mon;
 
 
-	initial begin
-		OneMsPeriod = 1000;
-	end
 
 	`ifdef WFDUMP
 	   initial begin
@@ -128,15 +130,110 @@
 	    repeat (200) @(posedge clock);
         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
 
-	    $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7");
+	    $display("########################################");
+	    $display("Step-1, PWM Square Waveform");
+        pwm0_period = 20*256;
+        pwm1_period = 20*2*256;
+        pwm2_period = 20*4*256;
+        pwm3_period = 20*8*256;
+        pwm4_period = 20*16*256;
+        pwm5_period = 20*32*256;
 	    test_step = 1;
-        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_0,'h0000_0000);
-        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_1,'h0000_0001);
-        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_2,'h0001_0001);
-        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_3,'h0001_0002);
-        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_4,'h0002_0002);
-        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_5,'h0002_0003);
-	    pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7);
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_8000); // No Scale 
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_8001); // Scale 2^1 = 2
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_8002); // Scale 2^2 = 4
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG0,'h0000_8003); // Scale 2^3 = 8
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG0,'h0000_8004); // Scale 2^4 = 16
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG0,'h0000_8005); // Scale 2^5 = 32
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG2,'h0000_007F); // COMP0 = 0xFF
+        
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_003F); // Enable PWM
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_003F); // Enable PWM Interrupt
+	    pwm_monitor(pwm0_period,pwm1_period,pwm2_period,pwm3_period,pwm4_period,pwm5_period);
+        wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_003F); // Check Interrupt Status
+        wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_003F); // Clear Interrupt
+        wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status
+        wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status
+
+       if(test_fail == 1) begin
+          $display("ERROR: Step-1, PWM Square Waveform - FAILED");
+       end else begin
+          $display("STATUS: Step-1, PWM Square Waveform - PASSED");
+       end
+	    $display("########################################");
+	    $display("Step-2, PWM One Shot");
+        pwm0_period = 20*256;
+        pwm1_period = 20*2*256;
+        pwm2_period = 20*4*256;
+        pwm3_period = 20*8*256;
+        pwm4_period = 20*16*256;
+        pwm5_period = 20*32*256;
+	    test_step = 2;
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG0,'h0000_8010); // No Scale 
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK0_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG0,'h0000_8011); // Scale 2^1 = 2
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK1_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG0,'h0000_8012); // Scale 2^2 = 4
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK2_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG0,'h0000_8013); // Scale 2^3 = 8
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK3_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG0,'h0000_8014); // Scale 2^4 = 16
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK4_CFG2,'h0000_007F); // COMP0 = 0xFF
+
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG0,'h0000_8015); // Scale 2^5 = 32
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG1,'h0000_00FF); // Period 0xFFFF
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_BLK5_CFG2,'h0000_007F); // COMP0 = 0xFF
+        
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_003F); // Enable PWM
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_MASK,'h0000_003F); // Enable PWM Interrupt
+        read_data = 8'h3F;
+        while(read_data  != 8'h00) begin // Wait for De-assertion on Enable
+            wb_user_core_read(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,read_data);
+             repeat (100) @(posedge clock);
+        end
+
+        wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_003F); // Check Interrupt Status
+        wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0020); // Check Global Interrupt Status
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_CFG0,'h0000_0000); // Disable PWM
+        wb_user_core_write(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,'h0000_003F); // Clear Interrupt
+        wb_user_core_read_check(`ADDR_SPACE_PWM+`PWM_GLBL_INTR_STAT,read_data,'h0000_0000); // Check Interrupt Status
+        wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h0000_0020); // Check Global Interrupt Status
+        wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,'h0000_0000); // Check Global Interrupt Status
+
+       if(test_fail == 1) begin
+          $display("ERROR: Step-2, PWM One Shot - FAILED");
+       end else begin
+          $display("STATUS: Step-2, PWM One Shot - PASSED");
+       end
+
 
 		repeat (100) @(posedge clock);
 			// $display("+1000 cycles");
@@ -217,12 +314,12 @@
    repeat(2) @(posedge clock_mon);
    next_t  = $realtime;
    periodd = (next_t-prev_t)/2;
-   periodd = (periodd)/1e3;
+   periodd = (periodd);
    if(clk_period != periodd) begin
-       $display("STATUS: FAIL => %s Exp Period: %d ms Rxd: %d ms",clk_name,clk_period,periodd);
+       $display("STATUS: FAIL => %s Exp Period: %d ns Rxd: %d ns",clk_name,clk_period,periodd);
        test_fail = 1;
    end else begin
-       $display("STATUS: PASS => %s  Period: %d ms ",clk_name,clk_period);
+       $display("STATUS: PASS => %s  Period: %d ns ",clk_name,clk_period);
    end
 end
 endtask
diff --git a/verilog/dv/user_sram_exec/user_sram_exec.c b/verilog/dv/user_sram_exec/user_sram_exec.c
index b4a1db5..0f0fa12 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec.c
+++ b/verilog/dv/user_sram_exec/user_sram_exec.c
@@ -64,5 +64,6 @@
     reg_glbl_soft_reg_5 = 0x66778899; // Sig-5
 
     // Signal end of test
+   reg_glbl_mail_box = 0xff << (bthread_get_core_id() * 8); // Start of Main 
 }
 
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
index 277dae2..6e2bcf4 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -118,6 +118,7 @@
 
 
         wait_riscv_boot();
+        wait_riscv_exit();
 
 		$display("Monitor: Reading Back the expected value");
 		// User RISC core expect to write these value in global
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 2a07067..70af457 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -90,6 +90,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.o *.dump
 
 .PHONY: clean hex all
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 33277cb..25cbfd3 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -116,7 +116,7 @@
 initial
 begin
    strap_in = 0;
-   strap_in[`PSTRAP_UARTM_CFG] = 2'b11; // uart master config control - load from LA
+   strap_in[`PSTRAP_UARTM_CFG] = 2'b00; // uart master config control - load from LA
    apply_strap(strap_in);
 
    uart_data_bit           = 2'b11;
@@ -144,6 +144,8 @@
    tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
 	                          uart_stick_parity, uart_timeout, uart_divisor);
 
+
+    tb_master_uart.write_char('\n'); // for uart baud auto detect purpose
    //$write ("\n(%t)Response:\n",$time);
    flag = 0;
    while(flag == 0)
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 86bcabc..75065f4 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -10,21 +10,25 @@
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_driver.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_reg.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/strap_ctrl.sv
 -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_rst_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_dglicth.sv
+-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_intr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pwm/src/pwm_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pwm/src/pwm_glbl_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pwm/src/pwm_blk_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pwm/src/pwm_cfg_dglitch.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pwm/src/pwm_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pwm/src/pwm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/timer/src/timer_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/timer/src/timer_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/timer/src/timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/ws281x/src/ws281x_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/ws281x/src/ws281x_driver.sv
+-v $(USER_PROJECT_VERILOG)/rtl/ws281x/src/ws281x_reg.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v
@@ -130,6 +134,7 @@
 -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv 
 -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv 
 -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v 
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_auto_det.sv
 -v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
 -v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/digital_pll/src/digital_pll.v
index a4f189b..79cb52e 100644
--- a/verilog/rtl/digital_pll/src/digital_pll.v
+++ b/verilog/rtl/digital_pll/src/digital_pll.v
@@ -15,8 +15,12 @@
 
 
 /*****************************************************************
+Formula clock period: 1.168 + (bcount * 0.012)
 
-Offset	bcount	4x clock period	clock period (ns)	clock (Mhz)
+Example for bcount: 10
+        clock period = 1.168 + (10 *0.012) = 1.288
+
+Offset	bcount	clock period	 4xclock period (ns)	clock (Mhz)
 1.168	0	    1.168	            4.672	        214.041095890411
 1.168	1	    1.18	            4.72	        211.864406779661
 1.168	2	    1.192	            4.768	        209.731543624161
diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/digital_pll/src/digital_pll_controller.v
index ae13d9d..73b5d05 100644
--- a/verilog/rtl/digital_pll/src/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll/src/digital_pll_controller.v
@@ -97,40 +97,43 @@
           (tint == 5'd25) ? 26'b1111101111111_1111111111111 :
                     26'b1111111111111_1111111111111;
    
-    always @(posedge clock or posedge reset) begin
-    if (reset == 1'b1) begin
+    always @(posedge clock or posedge reset) begin // {
+    if (reset == 1'b1) begin // {
         tval <= 7'd0;	// Note:  trim[0] must be zero for startup to work.
         oscbuf <= 3'd0;
         prep <= 3'd0;
         count0 <= 5'd0;
         count1 <= 5'd0;
 
-    end else begin
+    end  // }
+    else begin // {
         oscbuf <= {oscbuf[1:0], osc};
 
-        if (oscbuf[2] != oscbuf[1]) begin
-        count1 <= count0;
-        count0 <= 5'b00001;
-        prep <= {prep[1:0], 1'b1};
+        if (oscbuf[2] != oscbuf[1]) begin // {
+             count1 <= count0;
+             count0 <= 5'b00001;
+             prep   <= {prep[1:0], 1'b1};
 
-        if (prep == 3'b111) begin
-            if (sum > div) begin
-		if (tval < 127) begin
-            	    tval <= tval + 1;
-		end
-            end else if (sum < div) begin
-		if (tval > 0) begin
-            	    tval <= tval - 1;
-		end
-            end
-        end
-        end else begin
-        if (count0 != 5'b11111) begin
-                count0 <= count0 + 1;
-        end
-        end
-    end
-    end
+             if (prep == 3'b111) begin // {
+                if (sum > div) begin  // {
+		           if (tval < 127) begin // {
+                      tval <= tval + 1;
+		           end // }
+                end  // }
+                else if (sum < div) begin // {
+		           if (tval > 0) begin // {
+                      tval <= tval - 1;
+		           end // }
+                end // }
+             end  // }
+           end // } 
+           else begin  // {
+               if (count0 != 5'b11111) begin // {
+                 count0 <= count0 + 1;
+             end // }
+           end // }
+       end // }
+    end // }
 
 endmodule	// digital_pll_controller
 `default_nettype wire
diff --git a/verilog/rtl/digital_pll/src/ring_osc2x13.v b/verilog/rtl/digital_pll/src/ring_osc2x13.v
index f20110e..ce76830 100644
--- a/verilog/rtl/digital_pll/src/ring_osc2x13.v
+++ b/verilog/rtl/digital_pll/src/ring_osc2x13.v
@@ -42,7 +42,7 @@
 	.Z(d1)
     );
 
-    sky130_fd_sc_hd__einvn_4 delayenb1 (
+    sky130_fd_sc_hd__einvn_2 delayenb1 (
 	.A(ts),
 	.TE_B(trim[1]),
 	.Z(d1)
@@ -86,7 +86,7 @@
 	.Z(d1)
     );
 
-    sky130_fd_sc_hd__einvn_4 delayenb1 (
+    sky130_fd_sc_hd__einvn_2 delayenb1 (
 	.A(in),
 	.TE_B(trim[1]),
 	.Z(d1)
diff --git a/verilog/rtl/uart2wb/src/uart_msg_handler.v b/verilog/rtl/uart2wb/src/uart_msg_handler.v
index e6436e5..860c073 100755
--- a/verilog/rtl/uart2wb/src/uart_msg_handler.v
+++ b/verilog/rtl/uart2wb/src/uart_msg_handler.v
@@ -44,6 +44,7 @@
 module uart_msg_handler (  
         reset_n ,
         sys_clk ,
+        cfg_uart_enb,
 
 
     // UART-TX Information
@@ -69,16 +70,17 @@
 
 
 // Define the Message Hanlde States
-`define IDLE	         4'h0
-`define IDLE_TX_MSG1	 4'h1
-`define IDLE_TX_MSG2	 4'h2
-`define RX_CMD_PHASE	 4'h3
-`define ADR_PHASE	 4'h4
-`define WR_DATA_PHASE	 4'h5
-`define SEND_WR_REQ	 4'h6
-`define SEND_RD_REQ	 4'h7
-`define SEND_RD_DATA	 4'h8
-`define TX_MSG           4'h9
+`define POWERON_WAIT	 4'h0
+`define IDLE     	     4'h1
+`define IDLE_TX_MSG1	 4'h2
+`define IDLE_TX_MSG2	 4'h3
+`define RX_CMD_PHASE	 4'h4
+`define ADR_PHASE	     4'h5
+`define WR_DATA_PHASE	 4'h6
+`define SEND_WR_REQ	     4'h7
+`define SEND_RD_REQ	     4'h8
+`define SEND_RD_DATA	 4'h9
+`define TX_MSG           4'hA
      
 `define BREAK_CHAR       8'h0A
 
@@ -88,6 +90,7 @@
 
 input        reset_n               ; // line reset
 input        sys_clk               ; // line clock
+input        cfg_uart_enb          ;
 
 
 //--------------------------------------
@@ -131,7 +134,7 @@
 reg  [31:0]     reg_wdata          ; // reg_addr
 reg             reg_wr             ; // 1 -> Reg Write request, 0 -> Read Requestion
 reg             reg_req            ; // 1 -> Register request
-
+reg   [7:0]     wait_cnt           ;
 
 wire rx_ready = 1; 
 /****************************************************************
@@ -164,17 +167,27 @@
       reg_addr       <= 0;
       reg_wr        <= 1'b0; // Read request
       reg_wdata     <= 0;
-      State         <= `IDLE;
-      NextState     <= `IDLE;
+      State         <= `POWERON_WAIT;
+      NextState     <= `POWERON_WAIT;
+      wait_cnt      <= 'h0;
    end else begin
    case(State)
       // Send Default Message
+      `POWERON_WAIT: begin
+         if(cfg_uart_enb) begin
+           if(wait_cnt == 8'hff) begin
+	           State         <= `IDLE;
+           end else begin
+               wait_cnt      <= wait_cnt+1;
+           end
+         end
+       end
       `IDLE: begin
-   	  TxMsgBuf      <= "Command Format:\n";  // Align to 16 character format by appending space character
-          TxMsgSize     <= 16;
-	  tx_data_avail <= 0;
-	  State         <= `TX_MSG;
-	  NextState     <= `IDLE_TX_MSG1;
+   	       TxMsgBuf      <= "Command Format:\n";  // Align to 16 character format by appending space character
+           TxMsgSize     <= 16;
+	       tx_data_avail <= 0;
+	       State         <= `TX_MSG;
+	       NextState     <= `IDLE_TX_MSG1;
        end
 
       // Send Default Message (Contd..)
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f832c7e..090578d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -273,7 +273,13 @@
 ////          boot up config                                      ////
 ////          2'b00 - 50Mhz, 2'b01 - 40Mhz, 2'b10 - 50Mhz,        ////
 ////          2'b11 - LA control                                  ////
-////                                                              ////
+////    5.5  Sept 14 2022, Dinesh A                               ////
+////          A. Auto Baud detection added in uart master as      ////
+////          power on user_clock1 is not decided, strap def      ////
+////          changed                                             ////
+////          2'b00 - Auto, 2'b01 - 50Mhz, 2'b10 - 4Mhz,          ////
+////          2'b11 - LA control                                  ////
+////          B. digital_pll is re-synth with maual placement     ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index ff6a316..28b4293 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -68,13 +68,34 @@
 //--------------------------------------------------
 // PWM Register
 // -------------------------------------------------
-`define PWM_GLBL_CFG          8'h00  // reg_0 - PWM Global Config
-`define PWM_CFG_PWM_0         8'h04  // reg_1 - PWM Reg-0
-`define PWM_CFG_PWM_1         8'h08  // reg_2 - PWM Reg-1
-`define PWM_CFG_PWM_2         8'h0C  // reg_3 - PWM Reg-2
-`define PWM_CFG_PWM_3         8'h10  // reg_4 - PWM Reg-3
-`define PWM_CFG_PWM_4         8'h14  // reg_5 - PWM Reg-4
-`define PWM_CFG_PWM_5         8'h18  // reg_6 - PWM Reg-5
+`define PWM_GLBL_CFG0         8'h00  // reg_0 - PWM Global Config-0
+`define PWM_GLBL_CFG1         8'h04  // reg_1 - PWM Global Config-1
+`define PWM_GLBL_INTR_MASK    8'h08  // reg_2 - PWM Global Interrupt Status
+`define PWM_GLBL_INTR_STAT    8'h0C  // reg_3 - PWM Global Interrupt Mask
+`define PWM_BLK0_CFG0         8'h10  // reg_0 - PWM BLK-0 Reg-0
+`define PWM_BLK0_CFG1         8'h14  // reg_1 - PWM BLK-0 Reg-1
+`define PWM_BLK0_CFG2         8'h18  // reg_2 - PWM BLK-0 Reg-2
+`define PWM_BLK0_CFG3         8'h1C  // reg_3 - PWM BLK-0 Reg-3
+`define PWM_BLK1_CFG0         8'h20  // reg_0 - PWM BLK-1 Reg-0
+`define PWM_BLK1_CFG1         8'h24  // reg_1 - PWM BLK-1 Reg-1
+`define PWM_BLK1_CFG2         8'h28  // reg_2 - PWM BLK-1 Reg-2
+`define PWM_BLK1_CFG3         8'h2C  // reg_3 - PWM BLK-1 Reg-3
+`define PWM_BLK2_CFG0         8'h30  // reg_0 - PWM BLK-2 Reg-0
+`define PWM_BLK2_CFG1         8'h34  // reg_1 - PWM BLK-2 Reg-1
+`define PWM_BLK2_CFG2         8'h38  // reg_2 - PWM BLK-2 Reg-2
+`define PWM_BLK2_CFG3         8'h3C  // reg_3 - PWM BLK-2 Reg-3
+`define PWM_BLK3_CFG0         8'h40  // reg_0 - PWM BLK-3 Reg-0
+`define PWM_BLK3_CFG1         8'h44  // reg_1 - PWM BLK-3 Reg-1
+`define PWM_BLK3_CFG2         8'h48  // reg_2 - PWM BLK-3 Reg-2
+`define PWM_BLK3_CFG3         8'h4C  // reg_3 - PWM BLK-3 Reg-3
+`define PWM_BLK4_CFG0         8'h50  // reg_0 - PWM BLK-4 Reg-0
+`define PWM_BLK4_CFG1         8'h54  // reg_1 - PWM BLK-4 Reg-1
+`define PWM_BLK4_CFG2         8'h58  // reg_2 - PWM BLK-4 Reg-2
+`define PWM_BLK4_CFG3         8'h5C  // reg_3 - PWM BLK-4 Reg-3
+`define PWM_BLK5_CFG0         8'h60  // reg_0 - PWM BLK-5 Reg-0
+`define PWM_BLK5_CFG1         8'h64  // reg_1 - PWM BLK-5 Reg-1
+`define PWM_BLK5_CFG2         8'h68  // reg_2 - PWM BLK-5 Reg-2
+`define PWM_BLK5_CFG3         8'h6C  // reg_3 - PWM BLK-5 Reg-3
 
 //--------------------------------------------------
 // TIMER Register