diff --git a/.gitmodules b/.gitmodules
index 3d2b0f8..4185575 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "verilog/rtl/fpu"]
 	path = verilog/rtl/fpu
 	url = https://github.com/dineshannayya/fpu
+[submodule "verilog/rtl/rtc"]
+	path = verilog/rtl/rtc
+	url = https://github.com/dineshannayya/rtc
diff --git a/README.md b/README.md
index 5086ae1..55fdf54 100644
--- a/README.md
+++ b/README.md
@@ -73,6 +73,9 @@
     * 3 x Timer (16 Bit), 1us/1ms/1second resolution
     * 2 x ws281x driver
     * 16 Hardware Semaphore
+    * FPU (SP) Core
+    * AES 128 Bit Core
+    * RTC Core
     * Pin Compatbible to arduino uno
     * Wishbone compatible design
     * Written in System Verilog
@@ -405,16 +408,16 @@
     - flow automatically pull the required docker based on MPW version.
     - RTL to gds docker is hardcoded inside File: openlane/Makefile
 ```bash
-     OPENLANE_TAG = mpw6
+     OPENLANE_TAG = mpw7
      OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
 ```
 ## Note-1.1: View the RTL to GDS Docker content
-    - for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker 
+    - for MPW-7 caravel pdk and openlane avaible inside riscduino/openlane:mpw7 docker 
     - caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
     - To view the docker contents
 ```bash
-    docker run -ti --rm riscduino/openlane:mpw6  bash
-    cd /opt/pdk_mpw6     -  pdk folder
+    docker run -ti --rm riscduino/openlane:mpw7  bash
+    cd /opt/pdk_mpw7     -  pdk folder
     cd /opt/caravel      -  caravel folder 
     cd /openlane         -  openlane folder
     env   - Show the internally defined env's
@@ -431,12 +434,12 @@
 	    docker pull riscduino/dv_setup:mpw6
 
 ## Note-2.1: View the RTL Simulation Docker content
-    - for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
+    - for MPW-7 caravel and pdk avaible inside riscduino/dv_setup:mpw7 docker this is used for RTL to gds flows
     - caravel and pdk envionment are automatically pointed to internal docker pointer
     - To view the docker contents
 ```bash
-    docker run -ti --rm riscduino/dv_setup:mpw6  bash
-    cd /opt/pdk_mpw6     -  pdk folder
+    docker run -ti --rm riscduino/dv_setup:mpw7  bash
+    cd /opt/pdk_mpw7     -  pdk folder
     cd /opt/caravel      -  caravel folder 
     env   - Show the internally defined env's
         CARAVEL_ROOT=/opt/caravel
@@ -466,7 +469,10 @@
 * **15.user_cache_bypass**  - Riscv Boot without icache and dcache
 * **16.user_pwm**            -Standalone pwm Test
 * **17.user_sema**           -Standalone validation of hardware Semaphore function
-* **18.riscv_regress**       - Standalone riscv compliance and regression test suite
+* **18.riscv_regress**       -Standalone riscv compliance and regression test suite
+* **19.user_rtc**            -Standalone RTC core test
+* **20.user_aes_core**       -Standalone AES Core test
+* **21.user_fpu_core**       -Standalone FPU(SP) Core test
 
 ## Caravel+RISCDUINO Integrated Specific Test case 
 * **1.wb_port**             - Complete caravel User Wishbone validation
diff --git a/deps/timing-scripts/env/f.tcl b/deps/timing-scripts/env/f.tcl
new file mode 100644
index 0000000..867427b
--- /dev/null
+++ b/deps/timing-scripts/env/f.tcl
@@ -0,0 +1,20 @@
+set libs "
+    $::env(PDK_REF_PATH)/${std_cell_library}/lib/${std_cell_library}__ff_n40C_1v95.lib
+    $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ff_n40C_5v50.lib
+    $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ff_n40C_4v40_lv1v95.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_gpiov2_ff_ff_n40C_1v95_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_hvc_wpad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_lvc_wpad_ff_n40C_1v95_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_power_lvc_wpad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vddio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib
+    $::env(PDK_REF_PATH)/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+"
diff --git a/deps/timing-scripts/env/s.tcl b/deps/timing-scripts/env/s.tcl
new file mode 100644
index 0000000..9b61eeb
--- /dev/null
+++ b/deps/timing-scripts/env/s.tcl
@@ -0,0 +1,21 @@
+set libs "
+    $::env(PDK_REF_PATH)/${std_cell_library}/lib/${std_cell_library}__ss_100C_1v60.lib
+    $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ss_100C_1v65.lib
+    $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ss_100C_1v65_lv1v60.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_gpiov2_ss_ss_100C_1v60_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_hvc_wpad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_lvc_wpad_ss_100C_1v60_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_power_lvc_wpad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vddio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib
+    $::env(PDK_REF_PATH)/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+"
+
diff --git a/deps/timing-scripts/env/t.tcl b/deps/timing-scripts/env/t.tcl
new file mode 100644
index 0000000..c9eea15
--- /dev/null
+++ b/deps/timing-scripts/env/t.tcl
@@ -0,0 +1,21 @@
+set libs "
+    $::env(PDK_REF_PATH)/${std_cell_library}/lib/${std_cell_library}__tt_025C_1v80.lib
+    $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__tt_025C_3v30.lib
+    $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__tt_025C_3v30_lv1v80.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vddio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+    $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+    $::env(PDK_REF_PATH)/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+"
+
diff --git a/docs/source/_static/Riscduino_Soc.png b/docs/source/_static/Riscduino_Soc.png
index 9fae63f..d5ad87d 100644
--- a/docs/source/_static/Riscduino_Soc.png
+++ b/docs/source/_static/Riscduino_Soc.png
Binary files differ
diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
index 671b62a..27748c4 100644
--- a/env/spef-mapping.tcl
+++ b/env/spef-mapping.tcl
@@ -2,6 +2,7 @@
 set spef_mapping(mprj/u_aes) "$::env(PROJECT_ROOT)/signoff/aes_top/openlane-signoff/spef/aes_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_fpu) "$::env(PROJECT_ROOT)/signoff/fpu_wrapper/openlane-signoff/spef/fpu_wrapper.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_intercon) "$::env(PROJECT_ROOT)/signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_peri) "$::env(PROJECT_ROOT)/signoff/peri_top/openlane-signoff/spef/peri_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_pinmux) "$::env(PROJECT_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_pll) "$::env(PROJECT_ROOT)/signoff/dg_pll/openlane-signoff/spef/dg_pll.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_qspi_master) "$::env(PROJECT_ROOT)/signoff/qspim_top/openlane-signoff/spef/qspim_top.$::env(RCX_CORNER).spef"
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 96021bd..f69ee1b 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 446379b..5a1770e 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/aes_top/pin_order.cfg b/openlane/aes_top/pin_order.cfg
index 847e469..d3bacc9 100644
--- a/openlane/aes_top/pin_order.cfg
+++ b/openlane/aes_top/pin_order.cfg
@@ -3,21 +3,17 @@
 #MANUAL_PLACE
 
 
-#E
-
-mclk               0100 0 2
-rst_n 
+#S
+rst_n          550 0 2
+mclk               
+wbd_clk_out
 cfg_cska\[3\]
 cfg_cska\[2\]
 cfg_cska\[1\]
 cfg_cska\[0\]
-wbd_clk_int
-wbd_clk_out
 
-
-
-#S
-dmem_req_ack    690 0 2
+wbd_clk_int     590 0 2
+dmem_req_ack    
 dmem_req         
 dmem_cmd  
 dmem_width\[1\]
diff --git a/openlane/bus_rep_north/config.tcl b/openlane/bus_rep_north/config.tcl
index 4168921..e66bac5 100755
--- a/openlane/bus_rep_north/config.tcl
+++ b/openlane/bus_rep_north/config.tcl
@@ -49,7 +49,8 @@
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 "
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 \ 
+                             BUS_BUF_WD=42 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 #set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
diff --git a/openlane/bus_rep_north/pin_order.cfg b/openlane/bus_rep_north/pin_order.cfg
index d6472e3..3fc1b58 100644
--- a/openlane/bus_rep_north/pin_order.cfg
+++ b/openlane/bus_rep_north/pin_order.cfg
@@ -32,7 +32,95 @@
 ch_in\[26\]
 
 #S
-ch_in\[0\]    2000 0 64
+buf_in\[0\]    0100 0 4
+buf_out\[1\]
+buf_out\[2\]
+buf_in\[3\]    
+buf_out\[4\]
+buf_out\[5\]
+buf_in\[6\]    
+buf_out\[7\]
+buf_out\[8\]
+buf_in\[9\]    
+buf_out\[10\]
+buf_out\[11\]
+buf_in\[12\]    
+buf_out\[13\]
+buf_out\[14\]
+buf_in\[15\]    
+buf_out\[16\]
+buf_out\[17\]
+buf_in\[18\]    
+buf_out\[19\]
+buf_out\[20\]
+buf_in\[21\]    
+buf_out\[22\]
+buf_out\[23\]
+buf_in\[24\]    
+buf_out\[25\]
+buf_out\[26\]
+buf_in\[27\]    
+buf_out\[28\]
+buf_out\[29\]
+buf_in\[30\]    
+buf_out\[31\]
+buf_out\[32\]
+buf_in\[33\]    
+buf_out\[34\]
+buf_out\[35\]
+buf_in\[36\]    
+buf_out\[37\]
+buf_out\[38\]
+buf_in\[39\]    
+buf_out\[40\]
+buf_out\[41\]
+
+buf_in\[41\]  2000 0 4
+buf_in\[40\]
+buf_out\[39\]    
+buf_in\[38\]
+buf_in\[37\]
+buf_out\[36\]    
+buf_in\[35\]
+buf_in\[34\]
+buf_out\[33\]    
+buf_in\[32\]
+buf_in\[31\]
+buf_out\[30\]    
+buf_in\[29\]
+buf_in\[28\]
+buf_out\[27\]    
+buf_in\[26\]
+buf_in\[25\]
+buf_out\[24\]    
+buf_in\[23\]
+buf_in\[22\]
+buf_out\[21\]    
+buf_in\[20\]
+buf_in\[19\]
+buf_out\[18\]    
+buf_in\[17\]
+buf_in\[16\]
+buf_out\[15\]    
+buf_in\[14\]
+buf_in\[13\]
+buf_out\[12\]    
+buf_in\[11\]
+buf_in\[10\]
+buf_out\[9\]    
+buf_in\[8\]
+buf_in\[7\]
+buf_out\[6\]    
+buf_in\[5\]
+buf_in\[4\]
+buf_out\[3\]    
+buf_in\[2\]
+buf_in\[1\]
+buf_out\[0\]    
+
+
+
+ch_in\[0\]    2400 0 16
 ch_in\[1\]
 ch_out\[2\]
 ch_in\[3\]    
diff --git a/openlane/fpu_wrapper/pin_order.cfg b/openlane/fpu_wrapper/pin_order.cfg
index edb7b03..1ad7fde 100644
--- a/openlane/fpu_wrapper/pin_order.cfg
+++ b/openlane/fpu_wrapper/pin_order.cfg
@@ -3,20 +3,18 @@
 #MANUAL_PLACE
 
 
-#E
+#S
 
-mclk               0100 0 2
-rst_n 
+rst_n             00 0 2
 cfg_cska\[3\]
 cfg_cska\[2\]
 cfg_cska\[1\]
 cfg_cska\[0\]
-wbd_clk_int
 wbd_clk_out
+mclk               
 
 
-
-#S
+wbd_clk_int     050 0 2
 dmem_req_ack    
 dmem_req         
 dmem_cmd  
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index fff23e7..bcdbeb5 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -69,7 +69,6 @@
 int_pll_clock
 xtal_clk
 s_reset_n
-rtc_clk
 usb_clk
 
 pinmux_debug\[0\] 0300 0  2
@@ -226,6 +225,7 @@
 
 reg_cs            260 0  2
 reg_wr           
+reg_addr\[10\]    
 reg_addr\[9\]    
 reg_addr\[8\]    
 reg_addr\[7\]    
@@ -308,44 +308,7 @@
 
 
 #N
-
-cfg_dac3_mux_sel\[7\]
-cfg_dac3_mux_sel\[6\]
-cfg_dac3_mux_sel\[5\]
-cfg_dac3_mux_sel\[4\]
-cfg_dac3_mux_sel\[3\]
-cfg_dac3_mux_sel\[2\]
-cfg_dac3_mux_sel\[1\]
-cfg_dac3_mux_sel\[0\]
-
-cfg_dac2_mux_sel\[7\]
-cfg_dac2_mux_sel\[6\]
-cfg_dac2_mux_sel\[5\]
-cfg_dac2_mux_sel\[4\]
-cfg_dac2_mux_sel\[3\]
-cfg_dac2_mux_sel\[2\]
-cfg_dac2_mux_sel\[1\]
-cfg_dac2_mux_sel\[0\]
-
-cfg_dac1_mux_sel\[7\]
-cfg_dac1_mux_sel\[6\]
-cfg_dac1_mux_sel\[5\]
-cfg_dac1_mux_sel\[4\]
-cfg_dac1_mux_sel\[3\]
-cfg_dac1_mux_sel\[2\]
-cfg_dac1_mux_sel\[1\]
-cfg_dac1_mux_sel\[0\]
-
-cfg_dac0_mux_sel\[7\]
-cfg_dac0_mux_sel\[6\]
-cfg_dac0_mux_sel\[5\]
-cfg_dac0_mux_sel\[4\]
-cfg_dac0_mux_sel\[3\]
-cfg_dac0_mux_sel\[2\]
-cfg_dac0_mux_sel\[1\]
-cfg_dac0_mux_sel\[0\]
-
-digital_io_oen\[37\]  100 0 4
+digital_io_oen\[37\]  000 0 2
 digital_io_out\[37\]
 digital_io_in\[37\]
 digital_io_oen\[36\]
@@ -374,9 +337,109 @@
 digital_io_in\[29\]
 digital_io_oen\[28\]
 digital_io_out\[28\]
+digital_io_in\[28\]  
+digital_io_oen\[27\]
+digital_io_out\[27\]
+digital_io_in\[27\]
+digital_io_oen\[26\]
+digital_io_out\[26\]
+digital_io_in\[26\]
+digital_io_oen\[25\]
+digital_io_out\[25\]
+digital_io_in\[25\]
+digital_io_oen\[24\]
+digital_io_out\[24\]
+digital_io_in\[24\]
+
+rtc_clk               150 0 2
+rtc_intr              
+
+reg_peri_cs            200 0  2
+reg_peri_wr           
+reg_peri_addr\[10\]    
+reg_peri_addr\[9\]    
+reg_peri_addr\[8\]    
+reg_peri_addr\[7\]    
+reg_peri_addr\[6\]    
+reg_peri_addr\[5\]    
+reg_peri_addr\[4\]    
+reg_peri_addr\[3\]    
+reg_peri_addr\[2\]    
+reg_peri_addr\[1\]    
+reg_peri_addr\[0\]    
+reg_peri_be\[3\]    
+reg_peri_be\[2\]    
+reg_peri_be\[1\]    
+reg_peri_be\[0\]    
+reg_peri_wdata\[31\]   
+reg_peri_wdata\[30\]   
+reg_peri_wdata\[29\]   
+reg_peri_wdata\[28\]   
+reg_peri_wdata\[27\]   
+reg_peri_wdata\[26\]   
+reg_peri_wdata\[25\]   
+reg_peri_wdata\[24\]   
+reg_peri_wdata\[23\]   
+reg_peri_wdata\[22\]   
+reg_peri_wdata\[21\]   
+reg_peri_wdata\[20\]   
+reg_peri_wdata\[19\]   
+reg_peri_wdata\[18\]   
+reg_peri_wdata\[17\]   
+reg_peri_wdata\[16\]   
+reg_peri_wdata\[15\]   
+reg_peri_wdata\[14\]   
+reg_peri_wdata\[13\]   
+reg_peri_wdata\[12\]  
+reg_peri_wdata\[11\]  
+reg_peri_wdata\[10\]  
+reg_peri_wdata\[9\]   
+reg_peri_wdata\[8\]   
+reg_peri_wdata\[7\]   
+reg_peri_wdata\[6\]   
+reg_peri_wdata\[5\]   
+reg_peri_wdata\[4\]   
+reg_peri_wdata\[3\]   
+reg_peri_wdata\[2\]   
+reg_peri_wdata\[1\]   
+reg_peri_wdata\[0\]   
+reg_peri_rdata\[31\]  
+reg_peri_rdata\[30\]  
+reg_peri_rdata\[29\]  
+reg_peri_rdata\[28\]  
+reg_peri_rdata\[27\]  
+reg_peri_rdata\[26\]  
+reg_peri_rdata\[25\]  
+reg_peri_rdata\[24\]  
+reg_peri_rdata\[23\]  
+reg_peri_rdata\[22\]  
+reg_peri_rdata\[21\]  
+reg_peri_rdata\[20\]  
+reg_peri_rdata\[19\]  
+reg_peri_rdata\[18\]  
+reg_peri_rdata\[17\]  
+reg_peri_rdata\[16\]  
+reg_peri_rdata\[15\]  
+reg_peri_rdata\[14\]  
+reg_peri_rdata\[13\]  
+reg_peri_rdata\[12\]  
+reg_peri_rdata\[11\]  
+reg_peri_rdata\[10\]  
+reg_peri_rdata\[9\]  
+reg_peri_rdata\[8\]  
+reg_peri_rdata\[7\]  
+reg_peri_rdata\[6\]  
+reg_peri_rdata\[5\]  
+reg_peri_rdata\[4\]  
+reg_peri_rdata\[3\]  
+reg_peri_rdata\[2\]  
+reg_peri_rdata\[1\]  
+reg_peri_rdata\[0\]  
+reg_peri_ack       
 
 
-cfg_dco_mode         0200 0 2
+
+cfg_dco_mode         0300 0 2
 cfg_pll_enb
 pll_ref_clk
 cfg_pll_fed_div\[4\]
@@ -411,19 +474,6 @@
 cfg_dc_trim\[1\]
 cfg_dc_trim\[0\]
 
-digital_io_in\[28\]  0300 0 2
-digital_io_oen\[27\]
-digital_io_out\[27\]
-digital_io_in\[27\]
-digital_io_oen\[26\]
-digital_io_out\[26\]
-digital_io_in\[26\]
-digital_io_oen\[25\]
-digital_io_out\[25\]
-digital_io_in\[25\]
-digital_io_oen\[24\]
-digital_io_out\[24\]
-digital_io_in\[24\]
 
 
 digital_io_in\[23\]     400  0
@@ -474,7 +524,7 @@
 sflash_di\[2\]      
 sflash_di\[3\]      
 
-digital_io_in\[0\]   0200 0 4
+digital_io_in\[0\]   0300 0 4
 digital_io_out\[0\]
 digital_io_oen\[0\]
 digital_io_in\[1\]
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index 8c81d46..afea1d2 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -23,7 +23,7 @@
 
 
 #W
-cfg_cska_sp_co\[3\]   0200 0 2
+cfg_cska_sp_co\[3\]   0300 0 2
 cfg_cska_sp_co\[2\]
 cfg_cska_sp_co\[1\]
 cfg_cska_sp_co\[0\]
@@ -35,7 +35,7 @@
 wbd_clk_spi
 mclk                   
 
-wbd_stb_i              0300 0 2
+wbd_stb_i              0350 0 2
 wbd_we_i               
 wbd_adr_i\[31\]        
 wbd_adr_i\[30\]        
@@ -161,7 +161,7 @@
 strap_flash\[1\]
 strap_flash\[0\]
 
-spi_debug\[0\]        0200 0  2
+spi_debug\[0\]        0050 0  2
 spi_debug\[1\]        
 spi_debug\[2\]        
 spi_debug\[3\]        
diff --git a/openlane/uart_i2c_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
index b518404..cbc75a4 100644
--- a/openlane/uart_i2c_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@
 #MANUAL_PLACE
 
 #W
-cfg_cska_uart\[3\]     0200 0  2
+cfg_cska_uart\[3\]     0300 0  2
 cfg_cska_uart\[2\]
 cfg_cska_uart\[1\]
 cfg_cska_uart\[0\]
@@ -10,7 +10,7 @@
 wbd_clk_uart
 app_clk                
 
-reg_cs                 0300 0  2
+reg_cs                 0400 0  2
 reg_wr                 
 reg_addr\[8\]          
 reg_addr\[7\]          
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index b912548..d6180b3 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -82,6 +82,7 @@
 	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_north.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_east.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_west.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/peri_top.v \
 	    "
 
 set ::env(EXTRA_LEFS) "\
@@ -102,6 +103,7 @@
 	$lef_root/bus_rep_north.lef \
 	$lef_root/bus_rep_east.lef \
 	$lef_root/bus_rep_west.lef \
+	$lef_root/peri_top.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -122,6 +124,7 @@
 	$gds_root/bus_rep_north.gds \
 	$gds_root/bus_rep_east.gds \
 	$gds_root/bus_rep_west.gds \
+	$gds_root/peri_top.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -201,7 +204,8 @@
 	u_rp_south                  vccd1 vssd1 vccd1 vssd1,\
 	u_rp_north                  vccd1 vssd1 vccd1 vssd1,\
 	u_rp_east                   vccd1 vssd1 vccd1 vssd1,\
-	u_rp_west                   vccd1 vssd1 vccd1 vssd1
+	u_rp_west                   vccd1 vssd1 vccd1 vssd1,\
+	u_peri                      vccd1 vssd1 vccd1 vssd1
       	"
 
 
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index c464041..1f6639d 100755
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -258,7 +258,7 @@
     set steps [dict create \
         "synthesis" "run_synthesis" \
         "floorplan" "run_floorplan" \
-        "placement" "run_placement_step"\
+        "placement" "run_placement_step" \
         "cts" "run_cts_step" \
         "routing" "run_routing_step" \
         "parasitics_sta" "run_parasitics_sta_step" \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index c1e83c0..0e89ff2 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,8 +1,9 @@
 u_4x8bit_dac                 1850            2500        N
-u_qspi_master                2250             450        N
-u_uart_i2c_usb_spi           2250            1100        N
-u_pinmux                     2250            2000        N
-u_pll                        2500            3028        N
+u_qspi_master                2250             350        N
+u_uart_i2c_usb_spi           2250            1000        N
+u_pinmux                     2250            1900        N
+u_peri                       2200            3000        N
+u_pll                        2650            3000        N
 
 u_fpu                       1100            2600         N
 u_aes                       150             2600         N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index 8d53f9c..8f4fe2d 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -158,7 +158,7 @@
 define_pdn_grid \
     -macro \
     -name macro_1 \
-    -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu" \
+    -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu u_peri" \
     -starts_with POWER \
     -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
 
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8ac589d..60315f0 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -153,12 +153,8 @@
 
 #N
 
-cfg_clk_skew_ctrl1\[31\]   0000 0 2
-cfg_clk_skew_ctrl1\[30\]
-cfg_clk_skew_ctrl1\[29\]
-cfg_clk_skew_ctrl1\[28\]
 
-cfg_clk_skew_ctrl1\[7\]
+cfg_clk_skew_ctrl1\[7\]      0000 0 2
 cfg_cska_wh\[3\]
 cfg_clk_skew_ctrl1\[6\]
 cfg_cska_wh\[2\]
@@ -335,7 +331,12 @@
 wbs_cyc_o      
 
 
-cfg_clk_skew_ctrl2\[31\]   325 0 2 
+cfg_clk_skew_ctrl1\[31\]   325 0 2
+cfg_clk_skew_ctrl1\[30\]
+cfg_clk_skew_ctrl1\[29\]
+cfg_clk_skew_ctrl1\[28\]
+
+cfg_clk_skew_ctrl2\[31\]   
 cfg_clk_skew_ctrl2\[30\]
 cfg_clk_skew_ctrl2\[29\]
 cfg_clk_skew_ctrl2\[28\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index a87255c..743d701 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -54,8 +54,8 @@
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=14\
-	                 CH_DATA_WD=154 \
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=8\
+	                 CH_DATA_WD=158 \
 			 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 51bfa57..af8e9cf 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,16 +3,9 @@
 #MANUAL_PLACE
 
 #S
-ch_clk_in\[13\]  000 0 2
-ch_clk_in\[12\]
-ch_clk_in\[11\]
-ch_clk_in\[10\]
-ch_clk_in\[9\]
-ch_clk_in\[8\]
-ch_clk_in\[7\]
+ch_clk_in\[7\]  000 0 2
 ch_clk_in\[6\]
 ch_clk_in\[5\]
-ch_clk_in\[4\]
 
 
 rst_n                020  0 2
@@ -66,6 +59,7 @@
 cfg_cska_wi\[1\]     
 cfg_cska_wi\[0\] 
 
+ch_clk_in\[4\]
 ch_clk_in\[3\]
 ch_clk_in\[2\]
 ch_clk_in\[1\]
@@ -182,7 +176,13 @@
 m0_wbd_err_o        
 m0_wbd_cyc_i        
 
-ch_data_in\[153\]  225 0 2
+
+ch_data_in\[157\]  225 0 2
+ch_data_in\[156\]  
+ch_data_in\[155\]  
+ch_data_in\[154\]
+
+ch_data_in\[153\]  
 ch_data_in\[152\]  
 ch_data_in\[151\]  
 ch_data_in\[150\]
@@ -272,7 +272,7 @@
 ch_data_out\[22\] 
 ch_data_out\[21\] 
 ch_data_out\[20\] 
-ch_clk_out\[4\]
+ch_clk_out\[5\]
 
 ch_data_out\[3\]   050 0 2
 ch_data_out\[2\]
@@ -600,33 +600,29 @@
 ch_data_out\[42\] 
 ch_data_out\[41\] 
 ch_data_out\[40\] 
-ch_clk_out\[9\]
 
 ch_data_out\[39\] 
 ch_data_out\[38\] 
 ch_data_out\[37\] 
 ch_data_out\[36\] 
-ch_clk_out\[8\]
 
 ch_data_out\[35\] 
 ch_data_out\[34\] 
 ch_data_out\[33\] 
 ch_data_out\[32\] 
 
-ch_clk_out\[7\]
 
 ch_data_out\[31\] 
 ch_data_out\[30\] 
 ch_data_out\[29\] 
 ch_data_out\[28\] 
 
-ch_clk_out\[6\]
 
 ch_data_out\[27\]  750 0 2
 ch_data_out\[26\] 
 ch_data_out\[25\] 
 ch_data_out\[24\] 
-ch_clk_out\[5\]
+ch_clk_out\[6\]
 
 ch_data_out\[76\]   1600 0 2
 ch_data_out\[75\] 
@@ -666,13 +662,11 @@
 ch_data_out\[148\]  
 ch_data_out\[147\]  
 ch_data_out\[146\]  
-ch_clk_out\[10\]
 
 ch_data_out\[153\]  1750 0 2
 ch_data_out\[152\]  
 ch_data_out\[151\]  
 ch_data_out\[150\]  
-ch_clk_out\[11\]
 
 #E
 ch_data_out\[19\]   0000 0  2  
@@ -685,7 +679,7 @@
 ch_data_out\[4\]
 ch_clk_out\[1\]
 
-s0_wbd_stb_o         0100 0 2
+s0_wbd_stb_o         0050 0 2
 s0_wbd_we_o         
 s0_wbd_adr_o\[31\]  
 s0_wbd_adr_o\[30\]  
@@ -892,7 +886,9 @@
 s1_wbd_cyc_o  
 
 
-ch_data_in\[145\]  1350 0 2
+
+
+ch_data_in\[145\]  1250 0 2
 ch_data_in\[144\]  
 ch_data_in\[143\]  
 ch_data_in\[142\]  
@@ -966,7 +962,7 @@
 ch_data_out\[78\]  
 ch_data_out\[77\]  
 
-ch_data_in\[76\]  1550 0 2
+ch_data_in\[76\]  1450 0 2
 ch_data_in\[75\]  
 ch_data_in\[74\]  
 ch_data_in\[73\]  
@@ -1006,8 +1002,9 @@
 ch_data_out\[12\]
 ch_clk_out\[3\]
 
-s2_wbd_stb_o         1610 0 2
+s2_wbd_stb_o         1510 0 2
 s2_wbd_we_o         
+s2_wbd_adr_o\[10\]   
 s2_wbd_adr_o\[9\]   
 s2_wbd_adr_o\[8\]   
 s2_wbd_adr_o\[7\]   
@@ -1089,6 +1086,10 @@
 s2_wbd_ack_i        
 s2_wbd_cyc_o        
 
-ch_clk_out\[12\]
-ch_clk_out\[13\]
+ch_clk_out\[7\]
 
+ch_clk_out\[4\]           1750 0 2
+ch_data_out\[154\]
+ch_data_out\[155\]
+ch_data_out\[156\]
+ch_data_out\[157\]
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index f3daaa8..54bb33f 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,22 +1,21 @@
 #BUS_SORT
 #MANUAL_PLACE
 #E
-pwrup_rst_n       
+pwrup_rst_n               0000 00 2
 rst_n
-
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-
-clk
-clk_o
 core_rst_n_o
 core_rdc_qlfy_o
 
-core_uid\[1\]              0200 00 2
+cfg_ccska\[3\]             0180 00 2
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_skew
+clk
+clk_o
+
+core_clk_int               0200 00 2
+core_uid\[1\]              
 core_uid\[0\]   
 imem2core_req_ack_i
 core2imem_req_o
diff --git a/openlane/ycr_iconnect/pin_order.cfg b/openlane/ycr_iconnect/pin_order.cfg
index 981fcbd..32cefd4 100644
--- a/openlane/ycr_iconnect/pin_order.cfg
+++ b/openlane/ycr_iconnect/pin_order.cfg
@@ -128,7 +128,8 @@
 sram0_dout1\[1\]
 sram0_dout1\[0\]
 
-core0_uid\[1\]   0200 00 2
+core0_clk        0200 00 2
+core0_uid\[1\]   
 core0_uid\[0\]   
 core0_imem_req_ack
 core0_imem_req
@@ -867,6 +868,7 @@
 
 
 #N
+cpu_clk_aes
 aes_dmem_req_ack
 aes_dmem_req
 aes_dmem_cmd
@@ -947,8 +949,8 @@
 aes_dmem_resp\[0\]
 
 
-
-fpu_dmem_req_ack 0200 0 2
+cpu_clk_fpu      0200 0 2
+fpu_dmem_req_ack 
 fpu_dmem_req
 fpu_dmem_cmd
 fpu_dmem_width\[1\]
diff --git a/sdc/aes_top.sdc b/sdc/aes_top.sdc
index 725f0aa..079fe70 100644
--- a/sdc/aes_top.sdc
+++ b/sdc/aes_top.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sat Nov 26 13:19:42 2022
+# Thu Dec  8 05:54:24 2022
 ###############################################################################
 current_design aes_top
 ###############################################################################
diff --git a/sdc/bus_rep_north.sdc b/sdc/bus_rep_north.sdc
index 5017a1d..1da8fbc 100644
--- a/sdc/bus_rep_north.sdc
+++ b/sdc/bus_rep_north.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sat Dec  3 06:21:56 2022
+# Thu Dec  8 10:01:16 2022
 ###############################################################################
 current_design bus_rep_north
 ###############################################################################
@@ -8,6 +8,48 @@
 ###############################################################################
 create_clock -name __VIRTUAL_CLK__ -period 10.0000 
 set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[9]}]
 set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
 set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
 set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
@@ -35,6 +77,48 @@
 set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
 set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
 set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[9]}]
 set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
 set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
 set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
@@ -65,6 +149,48 @@
 ###############################################################################
 # Environment
 ###############################################################################
+set_load -pin_load 0.0334 [get_ports {buf_out[41]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[40]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[39]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[38]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[37]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[36]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[35]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[34]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[33]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[32]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[31]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[30]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[29]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[28]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[27]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[26]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[25]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[24]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[23]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[22]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[21]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[20]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[19]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[18]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[17]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[16]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[15]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[14]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[13]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[12]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[11]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[10]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[9]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[8]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[7]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[6]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[5]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[4]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[3]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[2]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[1]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[0]}]
 set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
 set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
 set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
@@ -92,6 +218,48 @@
 set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
 set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
 set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[0]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
index 3290cbf..a3cac12 100644
--- a/sdc/caravel.sdc
+++ b/sdc/caravel.sdc
@@ -17,7 +17,7 @@
 create_clock -name int_pll_clock -period 5.0000  [get_pins {mprj/u_pinmux/int_pll_clock}]
 
 create_clock -name wbs_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
-create_clock -name wbs_clk_i   -period 26.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
+create_clock -name wbs_clk_i   -period 30.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
 
 create_clock -name cpu_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
 create_clock -name cpu_clk     -period 40.0000  [get_pins {mprj/u_wb_host/cpu_clk}]
@@ -156,6 +156,10 @@
 #################################################################
 ## User Case analysis
 #################################################################
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[3]}]
+set_case_analysis 1 [get_pins {mprj/u_peri/cfg_cska_peri[2]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[1]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[0]}]
 
 set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
 set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
@@ -175,7 +179,7 @@
 set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
 set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
 set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
-set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
 
 set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
 set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
@@ -223,8 +227,8 @@
 set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
 set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
 
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
 set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
 set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
 
diff --git a/sdc/fpu_wrapper.sdc b/sdc/fpu_wrapper.sdc
index 37eada1..abee4ee 100644
--- a/sdc/fpu_wrapper.sdc
+++ b/sdc/fpu_wrapper.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Mon Dec  5 08:54:08 2022
+# Wed Dec  7 15:08:32 2022
 ###############################################################################
 current_design fpu_wrapper
 ###############################################################################
diff --git a/sdc/peri_top.sdc b/sdc/peri_top.sdc
new file mode 100644
index 0000000..b0df2c9
--- /dev/null
+++ b/sdc/peri_top.sdc
@@ -0,0 +1,401 @@
+###############################################################################
+# Created by write_sdc
+# Thu Dec  8 11:11:44 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {s_reset_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {s_reset_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_date_d}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_date_d}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_time_s}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_time_s}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {rtc_intr}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {rtc_intr}]
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_peri}] 3.5000
+set_max_delay\
+    -to [get_ports {wbd_clk_peri}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
index 1e3d2e0..4b9af44 100644
--- a/sdc/pinmux_top.sdc
+++ b/sdc/pinmux_top.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sun Dec  4 03:05:47 2022
+# Thu Dec  8 10:57:01 2022
 ###############################################################################
 current_design pinmux_top
 ###############################################################################
@@ -55,6 +55,8 @@
  -group [get_clocks {user_clock2}] -comment {Async Clock group}
 set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
 set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
 set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
 set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
 set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
@@ -237,6 +239,8 @@
 set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
 set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
 set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_cs}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wr}]
 set_load -pin_load 0.0334 [get_ports {rtc_clk}]
 set_load -pin_load 0.0334 [get_ports {soft_irq}]
 set_load -pin_load 0.0334 [get_ports {spim_mosi}]
@@ -251,38 +255,6 @@
 set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
 set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
 set_load -pin_load 0.0334 [get_ports {xtal_clk}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
 set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[25]}]
 set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[24]}]
 set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[23]}]
@@ -474,6 +446,53 @@
 set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
 set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
 set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[0]}]
 set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
 set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
 set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
@@ -563,7 +582,9 @@
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {p_reset_n}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_ack}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_intr}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
@@ -619,6 +640,7 @@
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
@@ -633,6 +655,38 @@
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[0]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
diff --git a/sdc/qspim_top.sdc b/sdc/qspim_top.sdc
index e7836ed..a379561 100644
--- a/sdc/qspim_top.sdc
+++ b/sdc/qspim_top.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Thu Dec  1 11:16:57 2022
+# Thu Dec  8 07:24:05 2022
 ###############################################################################
 current_design qspim_top
 ###############################################################################
diff --git a/sdc/uart_i2c_usb_spi_top.sdc b/sdc/uart_i2c_usb_spi_top.sdc
index e2ff4b3..b86e030 100644
--- a/sdc/uart_i2c_usb_spi_top.sdc
+++ b/sdc/uart_i2c_usb_spi_top.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Thu Dec  1 09:40:58 2022
+# Thu Dec  8 05:43:45 2022
 ###############################################################################
 current_design uart_i2c_usb_spi_top
 ###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 59aa356..7913d31 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Mon Dec  5 13:17:23 2022
+# Thu Dec  8 16:36:06 2022
 ###############################################################################
 current_design user_project_wrapper
 ###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
index c694960..4e29404 100644
--- a/sdc/wb_host.sdc
+++ b/sdc/wb_host.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Mon Dec  5 12:28:59 2022
+# Thu Dec  8 15:54:53 2022
 ###############################################################################
 current_design wb_host
 ###############################################################################
diff --git a/sdc/wb_interconnect.sdc b/sdc/wb_interconnect.sdc
index b207707..ca11f99 100644
--- a/sdc/wb_interconnect.sdc
+++ b/sdc/wb_interconnect.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sat Nov 26 13:13:45 2022
+# Wed Dec  7 15:28:15 2022
 ###############################################################################
 current_design wb_interconnect
 ###############################################################################
@@ -1063,6 +1063,8 @@
 set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_we_o}]
 set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[0]}]
 set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[10]}]
 set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[1]}]
 set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[1]}]
 set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[2]}]
@@ -1192,12 +1194,6 @@
 set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
 set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
 set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
-set_load -pin_load 0.0334 [get_ports {ch_clk_out[13]}]
-set_load -pin_load 0.0334 [get_ports {ch_clk_out[12]}]
-set_load -pin_load 0.0334 [get_ports {ch_clk_out[11]}]
-set_load -pin_load 0.0334 [get_ports {ch_clk_out[10]}]
-set_load -pin_load 0.0334 [get_ports {ch_clk_out[9]}]
-set_load -pin_load 0.0334 [get_ports {ch_clk_out[8]}]
 set_load -pin_load 0.0334 [get_ports {ch_clk_out[7]}]
 set_load -pin_load 0.0334 [get_ports {ch_clk_out[6]}]
 set_load -pin_load 0.0334 [get_ports {ch_clk_out[5]}]
@@ -1206,6 +1202,10 @@
 set_load -pin_load 0.0334 [get_ports {ch_clk_out[2]}]
 set_load -pin_load 0.0334 [get_ports {ch_clk_out[1]}]
 set_load -pin_load 0.0334 [get_ports {ch_clk_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[154]}]
 set_load -pin_load 0.0334 [get_ports {ch_data_out[153]}]
 set_load -pin_load 0.0334 [get_ports {ch_data_out[152]}]
 set_load -pin_load 0.0334 [get_ports {ch_data_out[151]}]
@@ -1611,6 +1611,7 @@
 set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}]
 set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}]
 set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[10]}]
 set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[9]}]
 set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[8]}]
 set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}]
@@ -1683,12 +1684,6 @@
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[8]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[7]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[6]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[5]}]
@@ -1697,6 +1692,10 @@
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[2]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[1]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[157]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[156]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[155]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[154]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[153]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[152]}]
 set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[151]}]
diff --git a/sdc/ycr_core_top.sdc b/sdc/ycr_core_top.sdc
index b415685..e805073 100644
--- a/sdc/ycr_core_top.sdc
+++ b/sdc/ycr_core_top.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sat Nov 26 13:21:59 2022
+# Wed Dec  7 15:05:48 2022
 ###############################################################################
 current_design ycr_core_top
 ###############################################################################
diff --git a/sdc/ycr_iconnect.sdc b/sdc/ycr_iconnect.sdc
index a08db15..b484aa1 100644
--- a/sdc/ycr_iconnect.sdc
+++ b/sdc/ycr_iconnect.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sat Nov 26 13:14:33 2022
+# Wed Dec  7 14:01:07 2022
 ###############################################################################
 current_design ycr_iconnect
 ###############################################################################
@@ -613,6 +613,7 @@
 set_load -pin_load 0.0334 [get_ports {aes_dmem_cmd}]
 set_load -pin_load 0.0334 [get_ports {aes_dmem_req}]
 set_load -pin_load 0.0334 [get_ports {cfg_dcache_force_flush}]
+set_load -pin_load 0.0334 [get_ports {core0_clk}]
 set_load -pin_load 0.0334 [get_ports {core0_dmem_req_ack}]
 set_load -pin_load 0.0334 [get_ports {core0_imem_req_ack}]
 set_load -pin_load 0.0334 [get_ports {core0_irq_soft}]
@@ -624,6 +625,8 @@
 set_load -pin_load 0.0334 [get_ports {core_dmem_req}]
 set_load -pin_load 0.0334 [get_ports {core_icache_cmd}]
 set_load -pin_load 0.0334 [get_ports {core_icache_req}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk_aes}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk_fpu}]
 set_load -pin_load 0.0334 [get_ports {fpu_dmem_cmd}]
 set_load -pin_load 0.0334 [get_ports {fpu_dmem_req}]
 set_load -pin_load 0.0334 [get_ports {sram0_clk0}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 132a65f..c4c1e1e 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_basic user_spi_isp user_timer user_uart_master  user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core user_aes
+PATTERNS = user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_basic user_spi_isp user_timer user_uart_master  user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core user_aes user_rtc
 
 all:  ${PATTERNS}
 	echo "################# RTL Test case Summary #####################" > regression.rpt
diff --git a/verilog/dv/user_rtc/Makefile b/verilog/dv/user_rtc/Makefile
new file mode 100755
index 0000000..f3485a3
--- /dev/null
+++ b/verilog/dv/user_rtc/Makefile
@@ -0,0 +1,85 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_rtc
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	iverilog-vpi pli_rtc.c
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp -M. -m pli_rtc $< 
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.vpi *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_rtc/pli_rtc.c b/verilog/dv/user_rtc/pli_rtc.c
new file mode 100644
index 0000000..461e40d
--- /dev/null
+++ b/verilog/dv/user_rtc/pli_rtc.c
@@ -0,0 +1,295 @@
+#include <stdlib.h> /* ANSI C standard library */
+#include <stdio.h> /* ANSI C standard input/output library */
+#include <time.h>  
+#include <stdarg.h> /* ANSI C standard arguments library */
+#include  "vpi_user.h"  /*  IEEE 1364 PLI VPI routine library  */
+
+#define CMD_RTC_INIT        0
+#define CMD_RTC_NEXT_SECOND 1
+#define CMD_RTC_NEXT_DATE 2
+
+/* prototypes of PLI application routine names */
+PLI_INT32 PLIbook_RtcSizetf(PLI_BYTE8  *user_data);
+PLI_INT32 PLIbook_RtcCalltf(PLI_BYTE8  *user_data);
+PLI_INT32 PLIbook_RtcCompiletf(PLI_BYTE8  *user_data);
+PLI_INT32 PLIbook_RtcStartOfSim(s_cb_data  *callback_data);
+
+   /* tm structure */
+   /* struct tm {
+       int tm_sec;         // seconds,  range 0 to 59          
+       int tm_min;         // minutes, range 0 to 59           
+       int tm_hour;        // hours, range 0 to 23             
+       int tm_mday;        // day of the month, range 1 to 31  
+       int tm_mon;         // month, range 0 to 11             
+       int tm_year;        // The number of years since 1900   
+       int tm_wday;        // day of the week, range 0 to 6    
+       int tm_yday;        // day in the year, range 0 to 365  
+       int tm_isdst;       // daylight saving time             
+    }; */
+struct tm tm = {0};
+
+/*******************************************
+* Sizetf application
+* *****************************************/
+PLI_INT32  PLIbook_RtcSizetf(PLI_BYTE8  *user_data)
+{
+   return(32); /* $rtc returns 32-bit values */
+}
+
+/*********************************************
+* compiletf application to verify valid systf args.
+* *************************************************/
+PLI_INT32  PLIbook_RtcCompiletf(PLI_BYTE8  *user_data)
+{
+   s_vpi_value value_s;
+   vpiHandle systf_handle, arg_itr, arg_handle;
+   PLI_INT32 tfarg_type;
+   PLI_INT32 cmd;
+
+   int err_flag = 0;
+   do { /* group all tests, so can break out of group on error */
+       systf_handle = vpi_handle(vpiSysTfCall, NULL);
+       arg_itr = vpi_iterate(vpiArgument, systf_handle);
+       if (arg_itr == NULL) {
+           vpi_printf("ERROR: $c_rtc requires 7 arguments; has none\n");
+           err_flag = 1;
+           break;
+      }
+      arg_handle = vpi_scan(arg_itr);
+      tfarg_type = vpi_get(vpiType, arg_handle);
+      if ( (tfarg_type != vpiReg) &&
+          (tfarg_type != vpiIntegerVar) &&
+          (tfarg_type != vpiConstant) ) {
+          vpi_printf("ERROR: $c_rtc arg1 must be number, variable or net\n");
+          err_flag = 1;
+          break;
+      }
+      value_s.format = vpiIntVal;
+      vpi_get_value(arg_handle, &value_s);
+      cmd = value_s.value.integer;
+ 
+      // RTC Init has 7 Parameter 
+      if(cmd == CMD_RTC_INIT) { 
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg2 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg3 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg4 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg5 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg6 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg7 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+
+          arg_handle = vpi_scan(arg_itr);
+          if (arg_handle != NULL) {
+              vpi_printf("ERROR: $c_rtc requires 7 arguments; has too many\n");
+              vpi_free_object(arg_itr);
+              err_flag = 1;
+              break;
+          }
+        } else { // CMD_RTC_NEXT_SECOND & CMD_RTC_NEXT_DATE has only 1 arguments
+
+          arg_handle = vpi_scan(arg_itr);
+          if (arg_handle != NULL) {
+              vpi_printf("ERROR: $c_rtc requires 1 arguments; has too many\n");
+              vpi_free_object(arg_itr);
+              err_flag = 1;
+              break;
+          }
+       }
+   } while (0 == 1); /* end of test group; only executed once */
+   if (err_flag) {
+      vpi_control(vpiFinish, 1);  /* abort simulation */
+   }
+   return(0);
+}
+
+/******************************************************************
+* calltf to calculate floating point addr
+* ******************************************************************/
+#include <stdio.h> 
+#include <time.h>  
+#include <stdlib.h>
+
+PLI_INT32  PLIbook_RtcCalltf(PLI_BYTE8  *user_data)
+{
+   s_vpi_value value_s;
+   vpiHandle systf_handle,  arg_itr,  arg_handle;
+   PLI_INT32 cmd,year, month, date, hour,minute,second;
+   float result;
+   systf_handle = vpi_handle(vpiSysTfCall, NULL);
+   arg_itr = vpi_iterate(vpiArgument, systf_handle);
+   if (arg_itr == NULL) {
+       vpi_printf("ERROR:  $c_rtc failed to obtain systf arg handles\n");
+       return(0);
+   }
+   /* read cmd from systf arg 1 (compiletf has already verified) */
+   arg_handle = vpi_scan(arg_itr);
+   value_s.format = vpiIntVal;
+   vpi_get_value(arg_handle, &value_s);
+   cmd = value_s.value.integer;
+
+
+   if(cmd == CMD_RTC_INIT) {
+      /* read input1 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      year = value_s.value.integer;
+
+      /* read input2 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      month = value_s.value.integer;
+
+      /* read input2 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      date = value_s.value.integer;
+
+      /* read input3 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      hour = value_s.value.integer;
+
+      /* read input4 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      minute = value_s.value.integer;
+
+      /* read input5 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      second = value_s.value.integer;
+
+      // initialize the Structure
+      tm.tm_year = year-1900;
+      tm.tm_mon  = month-1; /* C Month start from 0 to 11 and RTL 1 to 12 */
+      tm.tm_mday = date;
+      tm.tm_hour = hour;
+      tm.tm_min  = minute;
+      tm.tm_sec  = second;
+    }
+
+   // vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+   //          tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
+   //          tm.tm_hour, tm.tm_min, tm.tm_sec,
+   //          tm.tm_wday, tm.tm_yday);
+
+   if(cmd == CMD_RTC_NEXT_SECOND)
+      tm.tm_sec  = tm.tm_sec + 1;
+   else if(cmd == CMD_RTC_NEXT_DATE)
+      tm.tm_mday  = tm.tm_mday + 1;
+   mktime(&tm);
+
+   //vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+   //         tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
+   //         tm.tm_hour, tm.tm_min, tm.tm_sec,
+   //         tm.tm_wday, tm.tm_yday);
+
+   char str[80];
+   if(cmd == CMD_RTC_NEXT_SECOND)
+      sprintf(str,"%02d%02d%02d%02d",tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec);
+   else if(cmd == CMD_RTC_NEXT_DATE)
+      sprintf(str,"%04d%02d%02d",tm.tm_year+1900,tm.tm_mon+1,tm.tm_mday);
+
+   vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+            tm.tm_year + 1900, tm.tm_mon+1, tm.tm_mday,
+            tm.tm_hour, tm.tm_min, tm.tm_sec,
+            tm.tm_wday, tm.tm_yday);
+
+   ///* write result to simulation as return value $fpu_add */
+   int c = (int)strtol(str, NULL, 16); 
+
+   value_s.value.integer =  (PLI_INT32)c;
+   vpi_put_value(systf_handle,  &value_s, NULL, vpiNoDelay);
+   return(0);
+}
+
+
+/**
+* Start-of-simulation application
+****/
+PLI_INT32  PLIbook_RtcStartOfSim(s_cb_data  *callback_data)
+{
+   vpi_printf("\n$c_rtc PLI application is being used.\n\n");
+   return(0);
+}
+
+/**********************************************************
+    $fpu_add Registration Data
+(add this function name to the vlog_startup_routines array)
+***********************************************************/
+void  PLIbook_fpu_add_register()
+{
+    s_vpi_systf_data tf_data;
+    s_cb_data cb_data_s;
+    vpiHandle callback_handle;
+    
+    tf_data.type = vpiSysFunc;
+    tf_data.sysfunctype = vpiSysFuncSized;
+    tf_data.tfname =  "$c_rtc";
+    tf_data.calltf = PLIbook_RtcCalltf;
+    tf_data.compiletf = PLIbook_RtcCompiletf;
+    tf_data.sizetf = PLIbook_RtcSizetf;
+    tf_data.user_data = NULL;
+    vpi_register_systf(&tf_data);
+    cb_data_s.reason = cbStartOfSimulation;
+    cb_data_s.cb_rtn = PLIbook_RtcStartOfSim;
+    cb_data_s.obj = NULL;
+    cb_data_s.time = NULL;
+    cb_data_s.value = NULL;
+    cb_data_s.user_data = NULL;
+    callback_handle = vpi_register_cb(&cb_data_s);
+    vpi_free_object(callback_handle); /* don’t need callback handle */
+}
+
+void (*vlog_startup_routines[])() = {
+    PLIbook_fpu_add_register,
+    0
+};
+
diff --git a/verilog/dv/user_rtc/user_rtc_tb.v b/verilog/dv/user_rtc/user_rtc_tb.v
new file mode 100644
index 0000000..d53aefe
--- /dev/null
+++ b/verilog/dv/user_rtc/user_rtc_tb.v
@@ -0,0 +1,317 @@
+/*********************************************************************************
+ SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+ 
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+      http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+ SPDX-License-Identifier: Apache-2.0
+ SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+
+***********************************************************************************/
+/**********************************************************************************
+                                                              
+                   RTC Test Bench
+                                                              
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesh.annayya@gmail.com                 
+                                                              
+  Revision :                                                  
+     0.0  - Nov 16, 2022 
+            Initial Version 
+     0.1  - Nov 21, 2022 
+            A.Sys-clk and RTC clock domain are seperated.
+            B.Register are moved to seperate module
+            
+************************************************************************************/
+/************************************************************************************
+                      Copyright (C) 2000-2002 
+              Dinesh Annayya <dinesh.annayya@gmail.com>
+                                                             
+       This source file may be used and distributed without        
+       restriction provided that this copyright statement is not   
+       removed from the file and that any derivative work contains 
+       the original copyright notice and the associated disclaimer.
+                                                                   
+           THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     
+       EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   
+       TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   
+       FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      
+       OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    
+       (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   
+       GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        
+       BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
+       LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
+       OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
+       POSSIBILITY OF SUCH DAMAGE.                                 
+                                                             
+************************************************************************************/
+
+`timescale 1 ns / 1 ps
+
+
+
+`define  CMD_C_INIT       4'h0 // Initialize the C PLI Timer
+`define  CMD_C_NEXT_TIME  4'h1 // Get Next Second Value
+`define  CMD_C_NEXT_DATE  4'h2 // Het Next Date value
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+
+`define TB_TOP user_rtc_tb
+
+module `TB_TOP;
+
+parameter real CLK1_PERIOD  = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+parameter RTC_PERIOD = 30518; // 32768 Hz
+
+`include "user_tasks.sv"
+
+reg		    rtc_clk;
+reg		    rst_n;
+reg [15:0]  error_cnt;
+
+//---------------------
+// Register I/F
+wire        trig_s  = u_top.u_peri.inc_time_s;
+wire        trig_d  = u_top.u_peri.inc_date_d;
+
+
+// Wishbone Interface
+
+always #(RTC_PERIOD/2) rtc_clk = ~rtc_clk;
+
+assign io_in[11] = rtc_clk;
+
+	initial begin
+		test_fail = 0;
+        wbd_ext_cyc_i ='h0;  // strobe/request
+        wbd_ext_stb_i ='h0;  // strobe/request
+        wbd_ext_adr_i ='h0;  // address
+        wbd_ext_we_i  ='h0;  // write
+        wbd_ext_dat_i ='h0;  // data output
+        wbd_ext_sel_i ='h0;  // byte enable
+	    rtc_clk       = 0;
+	    error_cnt     = 0;
+	end
+
+initial
+   begin
+	$value$plusargs("risc_core_id=%d", d_risc_id);
+    init();
+
+	$display("\n\n");
+	$display("*****************************************************");
+	$display("* RTC Test bench ...");
+	$display("*****************************************************");
+	$display("\n");
+
+
+    normal_test;
+    fast_test1;
+    fast_test2;
+
+	repeat(1000)	@(posedge clock);
+
+    if(error_cnt > 0) test_fail = 1;
+
+    $display("###################################################");
+    if(test_fail == 0) begin
+       `ifdef GL
+           $display("Monitor: %m (GL) Passed");
+       `else
+           $display("Monitor: %m (RTL) Passed");
+       `endif
+    end else begin
+        `ifdef GL
+            $display("Monitor: %m (GL) Failed");
+        `else
+            $display("Monitor: %m (RTL) Failed");
+        `endif
+     end
+    $display("###################################################");
+	repeat(10)	@(posedge clock);
+	$finish;
+end
+
+`ifdef WFDUMP
+   initial begin
+   	  $dumpfile("simx.vcd");
+   	  $dumpvars(0, `TB_TOP);
+   end
+`endif
+
+
+
+wire [7:0] rtl_time   = {1'b0, u_top.u_peri.u_rtc.time_ts,u_top.u_peri.u_rtc.time_s};
+wire [7:0] rtl_minute = {1'b0, u_top.u_peri.u_rtc.time_tm,u_top.u_peri.u_rtc.time_m};
+wire [7:0] rtl_hour   = {1'b0, u_top.u_peri.u_rtc.time_th,u_top.u_peri.u_rtc.time_h};
+wire [7:0] rtl_dow    = {5'b0, u_top.u_peri.u_rtc.time_dow};
+
+wire [7:0] rtl_date   = {2'b0,u_top.u_peri.u_rtc.date_td,u_top.u_peri.u_rtc.date_d};
+wire [7:0] rtl_month  = {2'b0,u_top.u_peri.u_rtc.date_tm,u_top.u_peri.u_rtc.date_m};
+wire [15:0] rtl_year  = {u_top.u_peri.u_rtc.date_tc,u_top.u_peri.u_rtc.date_c,u_top.u_peri.u_rtc.date_ty,u_top.u_peri.u_rtc.date_y};
+wire [7:0] rtl_cent   = {u_top.u_peri.u_rtc.date_tc,u_top.u_peri.u_rtc.date_c};
+
+//---------------------------
+// Normal Test Without any Over-ride
+task normal_test;
+reg [31:0] exp_time;
+reg [31:0] cfg_time;
+reg [31:0] cfg_date;
+integer i;
+begin
+    //initialize the Timer Structure in C-PLI
+   $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+   init();
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+   for(i=0; i < 10; i = i+1) begin
+     repeat(1)	@(negedge trig_s);
+     exp_time = $c_rtc(1);
+     wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b10});
+     wb_user_core_read(`ADDR_SPACE_RTC+`RTC_TIME,cfg_time);
+     wb_user_core_read(`ADDR_SPACE_RTC+`RTC_DATE,cfg_date);
+
+     if(exp_time == {cfg_date[7:0],cfg_time[23:0]}) begin
+        $display("STATUS: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                      exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],cfg_date[7:0],cfg_time[23:16],cfg_time[15:8],cfg_time[7:0]);
+     end else begin
+        error_cnt = error_cnt+1;
+        $display("ERROR: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                      exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],cfg_date[7:0],cfg_time[23:16],cfg_time[15:8],cfg_time[7:0]);
+        repeat(10) @(posedge clock);
+        $finish;
+     end
+   end
+   if(error_cnt > 0)
+      $display("STATUS: Normal Test[Day, Hour,Minute,Second] without Over-ride Failed");
+   else
+      $display("STATUS: Normal Test[Day, Hour, Minute,Second] without Over-ride Passed");
+
+
+end
+endtask
+
+//------------------------------------------------------
+// Fast Time Test With Over-ride fast_sim_time=1
+//------------------------------------------------------
+task fast_test1;
+reg [31:0] exp_time;
+integer i;
+begin
+  //initialize the Timer Structure in C-PLI
+   $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+
+   init();
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+   fork
+   begin
+      //fast_sim_time=1;
+      wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b01,14'h400});
+   end
+   begin
+      for(i=0; i < (65536*10); i = i+1) begin
+        repeat(1)	@(negedge trig_s);
+        exp_time = $c_rtc(`CMD_C_NEXT_TIME);
+        if(exp_time == {rtl_date,rtl_hour,rtl_minute,rtl_time}) begin
+           $display("STATUS: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Year:%04x Month: %02x Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                         exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],rtl_year,rtl_month,rtl_date,rtl_hour,rtl_minute,rtl_time);
+        end else begin
+           error_cnt = error_cnt+1;
+           $display("ERROR: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Year:%04x Month: %02x Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                         exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],rtl_year,rtl_month,rtl_date,rtl_hour,rtl_minute,rtl_time);
+           repeat(10) @(posedge clock);
+           $finish;
+        end
+      end
+    end
+    join
+
+   //fast_sim_time=0;
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b00,14'h400});
+
+   if(error_cnt > 0)
+      $display("STATUS: Fast Test1 with (Fast Time) Over-ride Failed");
+   else
+      $display("STATUS: Fast Test1 with (Fast Time) Over-ride Passed");
+end
+endtask
+
+//------------------------------------------------------
+// Fast Time Test With Over-ride fast_sim_date=1
+//------------------------------------------------------
+task fast_test2;
+reg [31:0] exp_date;
+integer i;
+begin
+  //initialize the Timer Structure in C-PLI
+   $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+
+   init();
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+   fork
+   begin
+      wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b10,14'h400});
+      repeat(1) @(posedge clock);
+   end
+   begin
+      for(i=0; i < (65536*10); i = i+1) begin
+        repeat(1)	@(negedge trig_d);
+        exp_date = $c_rtc(`CMD_C_NEXT_DATE);
+        if(exp_date == {rtl_year,rtl_month,rtl_date}) begin
+           $display("STATUS: Exp: [Year: %04x Month: %02x Date: %02x] RTL: [Year:%04x Month: %02x Day: %02x]",
+                         exp_date[31:16],exp_date[15:8],exp_date[7:0],rtl_year,rtl_month,rtl_date);
+        end else begin
+           error_cnt = error_cnt+1;
+           $display("ERROR: Exp: [Year: %04x Month: %02x Date: %02x] RTL: [Year:%04x Month: %02x Day: %02x]",
+                         exp_date[31:16],exp_date[15:8],exp_date[7:0],rtl_year,rtl_month,rtl_date);
+           repeat(10) @(posedge clock);
+           $finish;
+        end
+      end
+   end
+   join
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b00,14'h0});
+
+   if(error_cnt > 0)
+      $display("STATUS: Fast Test2 with (Fast Date) Over-ride Failed");
+   else
+      $display("STATUS: Fast Test2 with (Fast Date) Over-ride Passed");
+end
+endtask
+
+
+
+
+
+
+
+endmodule
+
+
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 0b03478..f7ab685 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index d579af4..1ddeecc 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -224,6 +224,7 @@
 $(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
 $(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
 $(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
+$(USER_PROJECT_VERILOG)/gl/peri_top.v
 
 -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
 
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index e7d042f..415bafd 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -171,3 +171,10 @@
 -v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_north.sv
 -v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_east.sv
 -v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_west.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/peripheral/src/peri_top.sv
+
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_top.sv
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_core.sv
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_reg.sv
+
diff --git a/verilog/rtl/bus_rep/bus_rep_north.sv b/verilog/rtl/bus_rep/bus_rep_north.sv
index bb13510..cbc3f24 100644
--- a/verilog/rtl/bus_rep/bus_rep_north.sv
+++ b/verilog/rtl/bus_rep/bus_rep_north.sv
@@ -19,7 +19,8 @@
 //               Bus Repater                                        //
 //////////////////////////////////////////////////////////////////////
 module bus_rep_north #(
-	parameter BUS_REP_WD = 7
+	parameter BUS_REP_WD = 7,
+	parameter BUS_BUF_WD = 42
         ) (
 `ifdef USE_POWER_PINS
          input logic            vccd1,    // User area 1 1.8V supply
@@ -27,7 +28,10 @@
 `endif
 	 // Bus repeaters
 	 input  [BUS_REP_WD-1:0]  ch_in,
-	 output [BUS_REP_WD-1:0] ch_out
+	 output [BUS_REP_WD-1:0]  ch_out,
+     // Bus Buffering 
+	 input  [BUS_BUF_WD-1:0]  buf_in,
+	 output [BUS_BUF_WD-1:0]  buf_out
       );
 
 // channel repeater
@@ -35,6 +39,7 @@
 `ifndef SYNTHESIS
 
 assign ch_out = ch_in;
+assign buf_out = buf_in;
 
 `else
 
@@ -45,6 +50,8 @@
     end
  endgenerate
 
+assign buf_out = buf_in;
+
 `endif
 
 
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
index 8312ed8..41fc3f4 100644
--- a/verilog/rtl/bus_repeater.sv
+++ b/verilog/rtl/bus_repeater.sv
@@ -549,47 +549,47 @@
 **********************************************/
 
 wire [41:0] ch_in_west = {
-                          io_oeb_int[37],
-                          io_out_int[37],
+                          io_oeb_rp1[37],
+                          io_out_rp1[37],
                           io_in[37],
-                          io_oeb_int[36],
-                          io_out_int[36],
+                          io_oeb_rp1[36],
+                          io_out_rp1[36],
                           io_in[36],
-                          io_oeb_int[35],
-                          io_out_int[35],
+                          io_oeb_rp1[35],
+                          io_out_rp1[35],
                           io_in[35],
-                          io_oeb_int[34],
-                          io_out_int[34],
+                          io_oeb_rp1[34],
+                          io_out_rp1[34],
                           io_in[34],
-                          io_oeb_int[33],
-                          io_out_int[33],
+                          io_oeb_rp1[33],
+                          io_out_rp1[33],
                           io_in[33],
-                          io_oeb_int[32],
-                          io_out_int[32],
+                          io_oeb_rp1[32],
+                          io_out_rp1[32],
                           io_in[32],
-                          io_oeb_int[31],
-                          io_out_int[31],
+                          io_oeb_rp1[31],
+                          io_out_rp1[31],
                           io_in[31],
-                          io_oeb_int[30],
-                          io_out_int[30],
+                          io_oeb_rp1[30],
+                          io_out_rp1[30],
                           io_in[30],
-                          io_oeb_int[29],
-                          io_out_int[29],
+                          io_oeb_rp1[29],
+                          io_out_rp1[29],
                           io_in[29],
-                          io_oeb_int[28],
-                          io_out_int[28],
+                          io_oeb_rp1[28],
+                          io_out_rp1[28],
                           io_in[28],
-                          io_oeb_int[27],
-                          io_out_int[27],
+                          io_oeb_rp1[27],
+                          io_out_rp1[27],
                           io_in[27],
-                          io_oeb_int[26],
-                          io_out_int[26],
+                          io_oeb_rp1[26],
+                          io_out_rp1[26],
                           io_in[26],
-                          io_oeb_int[25],
-                          io_out_int[25],
+                          io_oeb_rp1[25],
+                          io_out_rp1[25],
                           io_in[25],
-                          io_oeb_int[24],
-                          io_out_int[24],
+                          io_oeb_rp1[24],
+                          io_out_rp1[24],
                           io_in[24]
                          };
 
@@ -597,46 +597,46 @@
 assign  {
                           io_oeb[37],
                           io_out[37],
-                          io_in_rp[37],
+                          io_in_rp1[37],
                           io_oeb[36],
                           io_out[36],
-                          io_in_rp[36],
+                          io_in_rp1[36],
                           io_oeb[35],
                           io_out[35],
-                          io_in_rp[35],
+                          io_in_rp1[35],
                           io_oeb[34],
                           io_out[34],
-                          io_in_rp[34],
+                          io_in_rp1[34],
                           io_oeb[33],
                           io_out[33],
-                          io_in_rp[33],
+                          io_in_rp1[33],
                           io_oeb[32],
                           io_out[32],
-                          io_in_rp[32],
+                          io_in_rp1[32],
                           io_oeb[31],
                           io_out[31],
-                          io_in_rp[31],
+                          io_in_rp1[31],
                           io_oeb[30],
                           io_out[30],
-                          io_in_rp[30],
+                          io_in_rp1[30],
                           io_oeb[29],
                           io_out[29],
-                          io_in_rp[29],
+                          io_in_rp1[29],
                           io_oeb[28],
                           io_out[28],
-                          io_in_rp[28],
+                          io_in_rp1[28],
                           io_oeb[27],
                           io_out[27],
-                          io_in_rp[27],
+                          io_in_rp1[27],
                           io_oeb[26],
                           io_out[26],
-                          io_in_rp[26],
+                          io_in_rp1[26],
                           io_oeb[25],
                           io_out[25],
-                          io_in_rp[25],
+                          io_in_rp1[25],
                           io_oeb[24],
                           io_out[24],
-                          io_in_rp[24]
+                          io_in_rp1[24]
 
          } = ch_out_west;
 
@@ -690,46 +690,147 @@
 
 wire [26:0] ch_out_north ;
 assign  {
-           io_in_rp[15],
+           io_in_rp1[15],
            io_out[15],
            io_oeb[15],
-           io_in_rp[16],
+           io_in_rp1[16],
            io_out[16],
            io_oeb[16],
-           io_in_rp[17],
+           io_in_rp1[17],
            io_out[17],
            io_oeb[17],
-           io_in_rp[18],
+           io_in_rp1[18],
            io_out[18],
            io_oeb[18],
-           io_in_rp[19],
+           io_in_rp1[19],
            io_out[19],
            io_oeb[19],
-           io_in_rp[20],
+           io_in_rp1[20],
            io_out[20],
            io_oeb[20],
-           io_in_rp[21],
+           io_in_rp1[21],
            io_out[21],
            io_oeb[21],
-           io_in_rp[22],
+           io_in_rp1[22],
            io_out[22],
            io_oeb[22],
-           io_in_rp[23],
+           io_in_rp1[23],
            io_out[23],
            io_oeb[23]
           } = ch_out_north;
 
+//--------------------------------------------------------------------------------
+// As West boundary is far from Pinmux module, there is feed through created
+// through the north repeater block
+// Buffering from Pinmux to PAD , feed through Pinmux <=> north <=> west
+//--------------------------------------------------------------------------------
+
+wire [41:0] buf_in_north = {
+                          io_oeb_int[37],
+                          io_out_int[37],
+                          io_in_rp1[37],
+                          io_oeb_int[36],
+                          io_out_int[36],
+                          io_in_rp1[36],
+                          io_oeb_int[35],
+                          io_out_int[35],
+                          io_in_rp1[35],
+                          io_oeb_int[34],
+                          io_out_int[34],
+                          io_in_rp1[34],
+                          io_oeb_int[33],
+                          io_out_int[33],
+                          io_in_rp1[33],
+                          io_oeb_int[32],
+                          io_out_int[32],
+                          io_in_rp1[32],
+                          io_oeb_int[31],
+                          io_out_int[31],
+                          io_in_rp1[31],
+                          io_oeb_int[30],
+                          io_out_int[30],
+                          io_in_rp1[30],
+                          io_oeb_int[29],
+                          io_out_int[29],
+                          io_in_rp1[29],
+                          io_oeb_int[28],
+                          io_out_int[28],
+                          io_in_rp1[28],
+                          io_oeb_int[27],
+                          io_out_int[27],
+                          io_in_rp1[27],
+                          io_oeb_int[26],
+                          io_out_int[26],
+                          io_in_rp1[26],
+                          io_oeb_int[25],
+                          io_out_int[25],
+                          io_in_rp1[25],
+                          io_oeb_int[24],
+                          io_out_int[24],
+                          io_in_rp1[24]
+                         };
+
+wire [41:0] buf_out_north ;
+assign  {
+                          io_oeb_rp1[37],
+                          io_out_rp1[37],
+                          io_in_rp2[37],
+                          io_oeb_rp1[36],
+                          io_out_rp1[36],
+                          io_in_rp2[36],
+                          io_oeb_rp1[35],
+                          io_out_rp1[35],
+                          io_in_rp2[35],
+                          io_oeb_rp1[34],
+                          io_out_rp1[34],
+                          io_in_rp2[34],
+                          io_oeb_rp1[33],
+                          io_out_rp1[33],
+                          io_in_rp2[33],
+                          io_oeb_rp1[32],
+                          io_out_rp1[32],
+                          io_in_rp2[32],
+                          io_oeb_rp1[31],
+                          io_out_rp1[31],
+                          io_in_rp2[31],
+                          io_oeb_rp1[30],
+                          io_out_rp1[30],
+                          io_in_rp2[30],
+                          io_oeb_rp1[29],
+                          io_out_rp1[29],
+                          io_in_rp2[29],
+                          io_oeb_rp1[28],
+                          io_out_rp1[28],
+                          io_in_rp2[28],
+                          io_oeb_rp1[27],
+                          io_out_rp1[27],
+                          io_in_rp2[27],
+                          io_oeb_rp1[26],
+                          io_out_rp1[26],
+                          io_in_rp2[26],
+                          io_oeb_rp1[25],
+                          io_out_rp1[25],
+                          io_in_rp2[25],
+                          io_oeb_rp1[24],
+                          io_out_rp1[24],
+                          io_in_rp2[24]
+
+         } = buf_out_north;
+
 bus_rep_north  #(
 `ifndef SYNTHESIS
-.BUS_REP_WD(27)
+.BUS_REP_WD(27),
+.BUS_BUF_WD(42)
 `endif
       ) u_rp_north(
 `ifdef USE_POWER_PINS
     .vccd1                 (vccd1                  ),
     .vssd1                 (vssd1                  ),
 `endif
-    .ch_in (ch_in_north),
-    .ch_out (ch_out_north)
+    .ch_in  (ch_in_north),
+    .ch_out (ch_out_north),
+    .buf_in  (buf_in_north),
+    .buf_out (buf_out_north)
    );
 
 /*********************************************
@@ -787,49 +888,49 @@
 
 wire [44:0] ch_out_east ;
 assign  {
-                            io_in_rp[0],
+                            io_in_rp1[0],
                             io_out[0],
                             io_oeb[0],
-                            io_in_rp[1],
+                            io_in_rp1[1],
                             io_out[1],
                             io_oeb[1],
-                            io_in_rp[2],
+                            io_in_rp1[2],
                             io_out[2],
                             io_oeb[2],
-                            io_in_rp[3],
+                            io_in_rp1[3],
                             io_out[3],
                             io_oeb[3],
-                            io_in_rp[4],
+                            io_in_rp1[4],
                             io_out[4],
                             io_oeb[4],
-                            io_in_rp[5],
+                            io_in_rp1[5],
                             io_out[5],
                             io_oeb[5],
-                            io_in_rp[6],
+                            io_in_rp1[6],
                             io_out[6],
                             io_oeb[6],
-                            io_in_rp[7],
+                            io_in_rp1[7],
                             io_out[7],
                             io_oeb[7],
-                            io_in_rp[8],
+                            io_in_rp1[8],
                             io_out[8],
                             io_oeb[8],
-                            io_in_rp[9],
+                            io_in_rp1[9],
                             io_out[9],
                             io_oeb[9],
-                            io_in_rp[10],
+                            io_in_rp1[10],
                             io_out[10],
                             io_oeb[10],
-                            io_in_rp[11],
+                            io_in_rp1[11],
                             io_out[11],
                             io_oeb[11],
-                            io_in_rp[12],
+                            io_in_rp1[12],
                             io_out[12],
                             io_oeb[12],
-                            io_in_rp[13],
+                            io_in_rp1[13],
                             io_out[13],
                             io_oeb[13],
-                            io_in_rp[14],
+                            io_in_rp1[14],
                             io_out[14],
                             io_oeb[14]
         } = ch_out_east;
@@ -852,8 +953,8 @@
 //---------------------------------------------------------
 //assign io_oeb[14:0]    = io_oeb_int[14:0];
 //assign io_out[14:0]    = io_out_int[14:0];
-//assign io_in_rp[14:0]  = io_in[14:0];
+assign io_in_rp[37:0]    = {io_in_rp2[37:24],io_in_rp1[23:0]};
 
 //assign io_oeb[37:24]    = io_oeb_int[37:24];
 //assign io_out[37:24]    = io_out_int[37:24];
-//assign io_in_rp[37:24]  = io_in[37:24];
+//assign io_in_rp1[37:24]  = io_in[37:24];
diff --git a/verilog/rtl/lib/async_reg_bus.sv b/verilog/rtl/lib/async_reg_bus.sv
index 3392cbf..02dca1d 100644
--- a/verilog/rtl/lib/async_reg_bus.sv
+++ b/verilog/rtl/lib/async_reg_bus.sv
@@ -58,9 +58,10 @@
           out_reg_rdata              ,
           out_reg_ack
    );
-parameter AW = 26 ; // Address width
-parameter DW = 32 ; // DATA WIDTH
-parameter BEW = 4 ; // Byte enable width
+parameter AW = 26         ; // Address width
+parameter DW = 32         ; // DATA WIDTH
+parameter BEW = 4         ; // Byte enable width
+parameter TIMEOUT_ENB = 1 ; // TIMEOUT Generation enabled
 
 //----------------------------------------
 // Reg Bus reg inout declration
@@ -191,17 +192,18 @@
 		in_reg_ack          <= 1'b1;
                 in_state           <= INI_WAIT_TAR_DONE;
              end
-             else begin
-                 if(in_timer == 9'h1FF) begin
-                    in_flag          <= 1'b0;
-                    in_reg_ack       <= 1'b1;
-                    in_reg_rdata     <= 32'h0;
-                    in_reg_timeout   <= 1'b1;
-                    in_state         <= INI_IDLE;
-                 end
-                 else begin
-                     in_timer       <= in_timer + 1;
-                 end
+             else begin if(TIMEOUT_ENB) begin
+                    if(in_timer == 9'h1FF ) begin
+                       in_flag          <= 1'b0;
+                       in_reg_ack       <= 1'b1;
+                       in_reg_rdata     <= 32'h0;
+                       in_reg_timeout   <= 1'b1;
+                       in_state         <= INI_IDLE;
+                    end
+                    else begin
+                        in_timer       <= in_timer + 1;
+                    end
+                end
              end
            end
       INI_WAIT_TAR_DONE :
diff --git a/verilog/rtl/peripheral/src/peri_top.sv b/verilog/rtl/peripheral/src/peri_top.sv
new file mode 100755
index 0000000..352d0b4
--- /dev/null
+++ b/verilog/rtl/peripheral/src/peri_top.sv
@@ -0,0 +1,186 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Peripheral Top                                              ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////      Hold the All the Misc IP Integration                    ////
+////        A. dig2ang                                            ////
+////        B. RTC                                                ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 07 Dec 2022, Dinesh A                               ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+`include "user_params.svh"
+module peri_top (
+                    `ifdef USE_POWER_PINS
+                       input logic             vccd1,// User area 1 1.8V supply
+                       input logic             vssd1,// User area 1 digital ground
+                    `endif
+                        // clock skew adjust
+                       input logic [3:0]       cfg_cska_peri,
+                       input logic	           wbd_clk_int,
+                       output logic	           wbd_clk_peri,
+
+                       // System Signals
+                       // Inputs
+		               input logic             mclk,
+                       input logic             s_reset_n              ,  // soft reset
+
+		       // Reg Bus Interface Signal
+                       input logic             reg_cs,
+                       input logic             reg_wr,
+                       input logic [10:0]      reg_addr,
+                       input logic [31:0]      reg_wdata,
+                       input logic [3:0]       reg_be,
+
+                       // Outputs
+                       output logic [31:0]     reg_rdata,
+                       output logic            reg_ack,
+
+                       // RTC Clock Domain
+                       input  logic            rtc_clk,
+                       output logic            rtc_intr,
+
+                       output logic            inc_time_s,
+                       output logic            inc_date_d,
+               
+                      // DAC Config
+                       output logic [7:0]      cfg_dac0_mux_sel,
+                       output logic [7:0]      cfg_dac1_mux_sel,
+                       output logic [7:0]      cfg_dac2_mux_sel,
+                       output logic [7:0]      cfg_dac3_mux_sel     
+
+   ); 
+
+
+
+logic         s_reset_ssn;  // Sync Reset
+
+
+//----------------------------------------
+//  Register Response Path Mux
+//  --------------------------------------
+
+logic [31:0]  reg_d2a_rdata;
+logic         reg_d2a_ack;
+logic         reg_d2a_cs;
+
+logic [31:0]  reg_rtc_rdata;
+logic         reg_rtc_ack;
+logic         reg_rtc_cs;
+
+assign reg_rdata  = (reg_addr[10:7] == `SEL_D2A) ? reg_d2a_rdata :
+                    (reg_addr[10:7] == `SEL_RTC) ? reg_rtc_rdata :
+                     'h0;
+assign reg_ack    = (reg_addr[10:7] == `SEL_D2A) ? reg_d2a_ack   :
+                    (reg_addr[10:7] == `SEL_RTC) ? reg_rtc_ack   :
+                    1'b0;
+assign reg_d2a_cs = (reg_addr[10:7] == `SEL_D2A)  ? reg_cs : 1'b0;
+assign reg_rtc_cs = (reg_addr[10:7] == `SEL_RTC)  ? reg_cs : 1'b0;
+
+
+// peri clock skew control
+clk_skew_adjust u_skew_peri
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	           .clk_in     (wbd_clk_int                ), 
+	           .sel        (cfg_cska_peri              ), 
+	           .clk_out    (wbd_clk_peri               ) 
+       );
+
+reset_sync  u_rst_sync (
+	      .scan_mode  (1'b0           ),
+          .dclk       (mclk           ), // Destination clock domain
+	      .arst_n     (s_reset_n      ), // active low async reset
+          .srst_n     (s_reset_ssn    )
+          );
+
+
+//-----------------------------------------------------------------------
+// Digital To Analog Register
+//-----------------------------------------------------------------------
+dig2ana_reg  u_d2a(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (s_reset_ssn                ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_d2a_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[5:2]              ),
+              .reg_wdata                (reg_wdata[31:0]            ),
+              .reg_be                   (reg_be[3:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_d2a_rdata              ),
+              .reg_ack                  (reg_d2a_ack                ),
+
+              .cfg_dac0_mux_sel         (cfg_dac0_mux_sel           ),
+              .cfg_dac1_mux_sel         (cfg_dac1_mux_sel           ),
+              .cfg_dac2_mux_sel         (cfg_dac2_mux_sel           ),
+              .cfg_dac3_mux_sel         (cfg_dac3_mux_sel           )
+         );
+
+//-----------------------------------------------------------------------
+// RTC
+//-----------------------------------------------------------------------
+rtc_top  u_rtc(
+              // System Signals
+              // Inputs
+		      .sys_clk                  ( mclk                      ),
+              .rst_n                    (s_reset_ssn                ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_rtc_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[4:0]              ),
+              .reg_wdata                (reg_wdata[31:0]            ),
+              .reg_be                   (reg_be[3:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_rtc_rdata              ),
+              .reg_ack                  (reg_rtc_ack                ),
+
+              .rtc_clk                  (rtc_clk                    ),
+              .rtc_intr                 (rtc_intr                   ),
+
+              .inc_date_d               (inc_date_d                 ),
+              .inc_time_s               (inc_time_s                 )
+
+         );
+
+endmodule 
+
+
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index 6ff2dac..1897697 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -94,6 +94,7 @@
 		               input  logic            usb_intr               ,
 		               input  logic            i2cm_intr              ,
 		               input  logic            pwm_intr              ,
+		               input  logic            rtc_intr              ,
 
 		               output logic [15:0]     cfg_riscv_ctrl         ,
                        output  logic [31:0]    cfg_multi_func_sel     ,// multifunction pins
@@ -370,6 +371,7 @@
 
 logic usb_intr_s,usb_intr_ss;   // Usb Interrupt Double Sync
 logic i2cm_intr_s,i2cm_intr_ss; // I2C Interrupt Double Sync
+logic rtc_intr_s,rtc_intr_ss;
 
 always @ (posedge mclk or negedge s_reset_n)
 begin  
@@ -378,15 +380,19 @@
      usb_intr_ss  <= 'h0;
      i2cm_intr_s  <= 'h0;
      i2cm_intr_ss <= 'h0;
+     rtc_intr_s  <= 'h0;
+     rtc_intr_ss <= 'h0;
    end else begin
      usb_intr_s   <= usb_intr;
      usb_intr_ss  <= usb_intr_s;
      i2cm_intr_s  <= i2cm_intr;
      i2cm_intr_ss <= i2cm_intr_s;
+     rtc_intr_s   <= rtc_intr;
+     rtc_intr_ss  <= rtc_intr_s;
    end
 end
 
-wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
+wire [31:0] hware_intr_req = {gpio_intr[31:8], 1'b0,rtc_intr_ss,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
 
 generic_intr_stat_reg #(.WD(32),
 	                .RESET_DEFAULT(0)) u_reg4 (
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index f8143ed..cfb0312 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -508,8 +508,7 @@
      else if(cfg_port_d_dir_sel[4])  digital_io_oen[10]   = 1'b0;
 
      //Pin-9        PB6/WS[1]/XTAL1/TOSC1     digital_io[11]
-     if   (cfg_uart_enb[1])          digital_io_oen[11]   = 1'b1;
-     else if(cfg_port_b_port_type[6]) digital_io_oen[11]   = 1'b1;
+     if(cfg_port_b_port_type[6])       digital_io_oen[11]   = 1'b1;
      else if(cfg_port_b_dir_sel[6])    digital_io_oen[11]   = 1'b0;
 
      // Pin-10       PB7/WS[1]/XTAL2/TOSC2     digital_io[12]
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 58419e2..0fb87ca 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -119,7 +119,7 @@
 		       // Reg Bus Interface Signal
                        input logic             reg_cs,
                        input logic             reg_wr,
-                       input logic [9:0]       reg_addr,
+                       input logic [10:0]      reg_addr,
                        input logic [31:0]      reg_wdata,
                        input logic [3:0]       reg_be,
 
@@ -198,13 +198,19 @@
                output logic[25:0]      cfg_dc_trim        , // External trim for DCO mode
                output logic            pll_ref_clk        , // Input oscillator to match
 
-               
-               // DAC Config
-               output logic [7:0]    cfg_dac0_mux_sel     ,
-               output logic [7:0]    cfg_dac1_mux_sel     ,
-               output logic [7:0]    cfg_dac2_mux_sel     ,
-               output logic [7:0]    cfg_dac3_mux_sel     
+		       // Peripheral Reg Bus Interface Signal
+               output logic             reg_peri_cs,
+               output logic             reg_peri_wr,
+               output logic [10:0]      reg_peri_addr,
+               output logic [31:0]      reg_peri_wdata,
+               output logic [3:0]       reg_peri_be,
 
+               // Input
+               input logic [31:0]       reg_peri_rdata,
+               input logic              reg_peri_ack,
+
+               input logic              rtc_intr
+               
    ); 
 
 
@@ -258,17 +264,6 @@
 
 assign      pinmux_debug = '0; // Todo: Need to fix
 
-//------------------------------------------------------
-// Register Map Decoding
-
-`define SEL_GLBL    3'b000   // GLOBAL REGISTER
-`define SEL_GPIO    3'b001   // GPIO REGISTER
-`define SEL_PWM     3'b010   // PWM REGISTER
-`define SEL_TIMER   3'b011   // TIMER REGISTER
-`define SEL_SEMA    3'b100   // SEMAPHORE REGISTER
-`define SEL_WS      3'b101   // WS281x  REGISTER
-`define SEL_D2A     3'b110   // Digital2Analog  REGISTER
-
 
 //----------------------------------------
 //  Register Response Path Mux
@@ -296,6 +291,15 @@
 
 logic [7:0]   pwm_gpio_in;
 
+logic         reg_glbl_cs ;
+logic         reg_gpio_cs ;
+logic         reg_pwm_cs  ;
+logic         reg_timer_cs;
+logic         reg_sema_cs ;
+logic         reg_ws_cs   ;
+
+
+
 
 //---------------------------------------------------------------------
 
@@ -389,6 +393,7 @@
           .usb_intr                     (usb_intr                ),
           .i2cm_intr                    (i2cm_intr               ),
           .pwm_intr                     (pwm_intr                ),
+          .rtc_intr                     (rtc_intr                ),
 
 
 
@@ -611,38 +616,11 @@
 
    ); 
 
-//-----------------------------------------------------------------------
-// Digital To Analog Register
-//-----------------------------------------------------------------------
-dig2ana_reg  u_d2a(
-              // System Signals
-              // Inputs
-		      .mclk                     ( mclk                      ),
-              .h_reset_n                (s_reset_ssn                ),
-
-		      // Reg Bus Interface Signal
-              .reg_cs                   (reg_d2a_cs                 ),
-              .reg_wr                   (reg_wr                     ),
-              .reg_addr                 (reg_addr[5:2]              ),
-              .reg_wdata                (reg_wdata[31:0]            ),
-              .reg_be                   (reg_be[3:0]                ),
-
-              // Outputs
-              .reg_rdata                (reg_d2a_rdata              ),
-              .reg_ack                  (reg_d2a_ack                ),
-
-              .cfg_dac0_mux_sel         (cfg_dac0_mux_sel           ),
-              .cfg_dac1_mux_sel         (cfg_dac1_mux_sel           ),
-              .cfg_dac2_mux_sel         (cfg_dac2_mux_sel           ),
-              .cfg_dac3_mux_sel         (cfg_dac3_mux_sel           )
-
-
-         );
 
 //-------------------------------------------------
 // Register Block Selection Logic
 //-------------------------------------------------
-reg [2:0] reg_blk_sel;
+reg [3:0] reg_blk_sel;
 
 always @(posedge mclk or negedge s_reset_ssn)
 begin
@@ -650,33 +628,46 @@
      reg_blk_sel <= 'h0;
    end
    else begin
-      if(reg_cs) reg_blk_sel <= reg_addr[9:7];
+      if(reg_cs) reg_blk_sel <= reg_addr[10:7];
    end
 end
 
-assign reg_rdata = (reg_blk_sel == `SEL_GLBL)  ? {reg_glbl_rdata} : 
-	               (reg_blk_sel == `SEL_GPIO)  ? {reg_gpio_rdata} :
-	               (reg_blk_sel == `SEL_PWM)   ? {reg_pwm_rdata}  :
-	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata  : 
-	               (reg_blk_sel == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
-	               (reg_blk_sel == `SEL_WS)    ? reg_ws_rdata     : 
-	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_rdata    : 'h0;
+assign reg_rdata = (reg_blk_sel    == `SEL_GLBL)  ? {reg_glbl_rdata} : 
+	               (reg_blk_sel    == `SEL_GPIO)  ? {reg_gpio_rdata} :
+	               (reg_blk_sel    == `SEL_PWM)   ? {reg_pwm_rdata}  :
+	               (reg_blk_sel    == `SEL_TIMER) ? reg_timer_rdata  : 
+	               (reg_blk_sel    == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
+	               (reg_blk_sel    == `SEL_WS)    ? reg_ws_rdata     : 
+	               (reg_blk_sel[3] == `SEL_PERI)  ? reg_peri_rdata   : 'h0;
 
-assign reg_ack   = (reg_blk_sel == `SEL_GLBL)  ? reg_glbl_ack   : 
-	               (reg_blk_sel == `SEL_GPIO)  ? reg_gpio_ack   : 
-	               (reg_blk_sel == `SEL_PWM)   ? reg_pwm_ack    : 
-	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack  : 
-	               (reg_blk_sel == `SEL_SEMA)  ? reg_sema_ack   : 
-	               (reg_blk_sel == `SEL_WS)    ? reg_ws_ack     : 
-	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_ack    : 1'b0;
+assign reg_ack   = (reg_blk_sel    == `SEL_GLBL)  ? reg_glbl_ack   : 
+	               (reg_blk_sel    == `SEL_GPIO)  ? reg_gpio_ack   : 
+	               (reg_blk_sel    == `SEL_PWM)   ? reg_pwm_ack    : 
+	               (reg_blk_sel    == `SEL_TIMER) ? reg_timer_ack  : 
+	               (reg_blk_sel    == `SEL_SEMA)  ? reg_sema_ack   : 
+	               (reg_blk_sel    == `SEL_WS)    ? reg_ws_ack     : 
+	               (reg_blk_sel[3] == `SEL_PERI)  ? reg_peri_ack   : 1'b0;
 
-wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
-wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
-wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
-wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
-wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
-wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS)   ? reg_cs : 1'b0;
-wire reg_d2a_cs   = (reg_addr[9:7] == `SEL_D2A)  ? reg_cs : 1'b0;
+assign reg_glbl_cs  = (reg_addr[10:7] == `SEL_GLBL) ? reg_cs : 1'b0;
+assign reg_gpio_cs  = (reg_addr[10:7] == `SEL_GPIO) ? reg_cs : 1'b0;
+assign reg_pwm_cs   = (reg_addr[10:7] == `SEL_PWM)  ? reg_cs : 1'b0;
+assign reg_timer_cs = (reg_addr[10:7] == `SEL_TIMER)? reg_cs : 1'b0;
+assign reg_sema_cs  = (reg_addr[10:7] == `SEL_SEMA) ? reg_cs : 1'b0;
+assign reg_ws_cs    = (reg_addr[10:7] == `SEL_WS)   ? reg_cs : 1'b0;
+assign reg_peri_cs  = (reg_addr[10]   == `SEL_PERI) ? reg_cs : 1'b0;
+
+assign  reg_peri_wr    = reg_wr;
+assign  reg_peri_addr  = reg_addr;
+assign  reg_peri_wdata = reg_wdata;
+assign  reg_peri_be    = reg_be;
+
+
+
+
+
+
+
+
 endmodule 
 
 
diff --git a/verilog/rtl/rtc b/verilog/rtl/rtc
new file mode 160000
index 0000000..6e2ff09
--- /dev/null
+++ b/verilog/rtl/rtc
@@ -0,0 +1 @@
+Subproject commit 6e2ff09c3037ff83ea0ced2b87823361ca8daa78
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 924332e..d6a7c4c 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,12 +4,12 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h0412_2022;
+parameter CHIP_RELEASE_DATE = 32'h0712_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0006_2000;
+parameter CHIP_REVISION   = 32'h0006_3000;
 
-parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_0111_1000_1110_1000_0011;
-parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_0100_0111_1110;
+parameter CLK_SKEW1_RESET_VAL = 32'b0100_0000_0100_0111_1001_1110_1000_0011;
+parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_0100_1011_1110;
 
 parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
 
@@ -149,6 +149,17 @@
 `define STRAP_QSPI_INIT_BYPASS     30
 `define STRAP_SOFT_REBOOT_REQ      31
 
+//------------------------------------------------------
+// Pinumux/PeriPheral Register Map Decoding
 
+`define SEL_GLBL    4'b0000   // GLOBAL REGISTER
+`define SEL_GPIO    4'b0001   // GPIO REGISTER
+`define SEL_PWM     4'b0010   // PWM REGISTER
+`define SEL_TIMER   4'b0011   // TIMER REGISTER
+`define SEL_SEMA    4'b0100   // SEMAPHORE REGISTER
+`define SEL_WS      4'b0101   // WS281x  REGISTER
+`define SEL_PERI    1'b1      // Peripheral
+`define SEL_D2A     4'b1000   // Digital2Analog  REGISTER
+`define SEL_RTC     4'b1001   // RTC     REGISTER
 `endif // USER_PARMS
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 6a818d1..a2b6681 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -42,6 +42,7 @@
 ////      15. SPI Slave (As Arduino ISP)                          ////
 ////      16. AES 126 Encription/Decryption                       ////
 ////      17. FPU (Single Precision)                              ////
+////      18. RTC                                                 ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -301,6 +302,9 @@
 ////    6.2  Dec 4, 2022, Dinesh A                                ////
 ////         Bus repeater north/south/east/west added for better  ////
 ////         global buffering                                     ////
+////    6.3  Dec 7, 2022, Dinesh A                                ////
+////         A. peripheral block integration                      ////
+////         B. RTC Integration                                   ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -575,7 +579,7 @@
 //    Global Register Wishbone Interface
 //---------------------------------------------------------------------
 wire                           wbd_glbl_stb_o                         ; // strobe/request
-wire   [9:0]                   wbd_glbl_adr_o                         ; // address
+wire   [10:0]                  wbd_glbl_adr_o                         ; // address
 wire                           wbd_glbl_we_o                          ; // write
 wire   [WB_WIDTH-1:0]          wbd_glbl_dat_o                         ; // data output
 wire   [3:0]                   wbd_glbl_sel_o                         ; // byte enable
@@ -627,14 +631,15 @@
 wire [7:0]                     cfg_glb_ctrl                           ;
 wire [31:0]                    cfg_clk_skew_ctrl1                     ;
 wire [31:0]                    cfg_clk_skew_ctrl2                     ;
-wire [3:0]                     cfg_wcska_wi                            ; // clock skew adjust for wishbone interconnect
-wire [3:0]                     cfg_wcska_wh                            ; // clock skew adjust for web host
+wire [3:0]                     cfg_wcska_wi                           ; // clock skew adjust for wishbone interconnect
+wire [3:0]                     cfg_wcska_wh                           ; // clock skew adjust for web host
+wire [3:0]                     cfg_wcska_peri                         ; // clock skew adjust for peripheral
 
-wire [3:0]                     cfg_wcska_riscv                         ; // clock skew adjust for riscv
-wire [3:0]                     cfg_wcska_uart                          ; // clock skew adjust for uart
-wire [3:0]                     cfg_wcska_qspi                          ; // clock skew adjust for spi
-wire [3:0]                     cfg_wcska_pinmux                        ; // clock skew adjust for pinmux
-wire [3:0]                     cfg_wcska_qspi_co                       ; // clock skew adjust for global reg
+wire [3:0]                     cfg_wcska_riscv                        ; // clock skew adjust for riscv
+wire [3:0]                     cfg_wcska_uart                         ; // clock skew adjust for uart
+wire [3:0]                     cfg_wcska_qspi                         ; // clock skew adjust for spi
+wire [3:0]                     cfg_wcska_pinmux                       ; // clock skew adjust for pinmux
+wire [3:0]                     cfg_wcska_qspi_co                      ; // clock skew adjust for global reg
 
 // Bus Repeater Signals  output from Wishbone Interface
 wire [3:0]                     cfg_wcska_riscv_rp                      ; // clock skew adjust for riscv
@@ -642,6 +647,7 @@
 wire [3:0]                     cfg_wcska_qspi_rp                       ; // clock skew adjust for spi
 wire [3:0]                     cfg_wcska_pinmux_rp                     ; // clock skew adjust for pinmux
 wire [3:0]                     cfg_wcska_qspi_co_rp                    ; // clock skew adjust for global reg
+wire [3:0]                     cfg_wcska_peri_rp                       ; // clock skew adjust for peripheral 
 
 wire [31:0]                    irq_lines_rp                           ; // Repeater
 wire                           soft_irq_rp                            ; // Repeater
@@ -651,6 +657,8 @@
 wire                           wbd_clk_uart_rp                        ;
 wire                           wbd_clk_pinmux_rp                      ;
 wire                           wbd_clk_pinmux_skew                    ;
+wire                           wbd_clk_peri_rp                        ;
+wire                           wbd_clk_peri_skew                      ;
 
 // Progammable Clock Skew inserted signals
 wire                           wbd_clk_wi_skew                        ; // clock for wishbone interconnect with clock skew
@@ -764,6 +772,7 @@
 // AES Integration local decleration
 //------------------------------------------------------------
 wire                           cpu_clk_aes                            ;
+wire                           cpu_clk_aes_skew                       ;
 wire [3:0]                     cfg_ccska_aes                          ;
 wire [3:0]                     cfg_ccska_aes_rp                       ;
 wire                           aes_dmem_req                           ;
@@ -778,7 +787,8 @@
 //------------------------------------------------------------
 // FPU Integration local decleration
 //------------------------------------------------------------
-wire                           cpu_clk_fpu                            ;
+wire                           cpu_clk_fpu                           ;
+wire                           cpu_clk_fpu_skew                       ;
 wire [3:0]                     cfg_ccska_fpu                          ;
 wire [3:0]                     cfg_ccska_fpu_rp                       ;
 wire                           fpu_dmem_req                           ;
@@ -826,6 +836,19 @@
 wire [7:0]                     cfg_dac3_mux_sel                       ;
 
 //---------------------------------------------------------------------
+// Peripheral Reg I/F
+//---------------------------------------------------------------------
+wire                           reg_peri_cs                            ;
+wire                           reg_peri_wr                            ;
+wire [10:0]                    reg_peri_addr                          ;
+wire [31:0]                    reg_peri_wdata                         ;
+wire [3:0]                     reg_peri_be                            ;
+
+wire [31:0]                    reg_peri_rdata                         ;
+wire                           reg_peri_ack                           ;
+
+wire                           rtc_intr                               ; // RTC interrupt
+//---------------------------------------------------------------------
 // Strap
 //---------------------------------------------------------------------
 wire [31:0]                    system_strap                           ;
@@ -863,6 +886,7 @@
 assign cfg_wcska_uart        = cfg_clk_skew_ctrl1[19:16];
 assign cfg_wcska_pinmux      = cfg_clk_skew_ctrl1[23:20];
 assign cfg_wcska_qspi_co     = cfg_clk_skew_ctrl1[27:24];
+assign cfg_wcska_peri        = cfg_clk_skew_ctrl1[31:28];
 
 /////////////////////////////////////////////////////////
 // RISCV Clock skew control
@@ -890,19 +914,21 @@
 //-------------------------------------
 // cpu clock repeater mapping
 //-------------------------------------
-wire [9:0] cpu_clk_rp;
+wire [2:0] cpu_clk_rp;
 
-wire [5:0] cpu_clk_rp_risc   = cpu_clk_rp[5:0];
-wire       cpu_clk_rp_aes    = cpu_clk_rp[6];
-wire       cpu_clk_rp_fpu    = cpu_clk_rp[7];
-wire       cpu_clk_rp_pinmux = cpu_clk_rp[8];
+wire [1:0] cpu_clk_rp_risc   = cpu_clk_rp[1:0];
+wire       cpu_clk_rp_pinmux = cpu_clk_rp[2];
 
 //----------------------------------------------------------
 // Bus Repeater Initiatiation
 //----------------------------------------------------------
 wire  [37:0]                io_in_rp           ;
+wire  [37:0]                io_in_rp1          ;
+wire  [37:0]                io_in_rp2          ;
 wire  [37:0]                io_out_int         ;
 wire  [37:0]                io_oeb_int         ;
+wire  [37:0]                io_out_rp1         ;
+wire  [37:0]                io_oeb_rp1         ;
 wire                        user_clock2_rp     ;
 
 `include "bus_repeater.sv"
@@ -1010,50 +1036,50 @@
 //------------------------------------------------------------------------------
 ycr_top_wb u_riscv_top (
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                      ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                      ),// User area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .wbd_clk_int             (wbd_clk_risc_rp            ), 
-          .cfg_wcska_riscv_intf    (cfg_wcska_riscv_rp         ), 
-          .wbd_clk_skew            (wbd_clk_riscv_skew         ),
+          .wbd_clk_int        (wbd_clk_risc_rp              ), 
+          .cfg_wcska_riscv_intf(cfg_wcska_riscv_rp           ), 
+          .wbd_clk_skew       (wbd_clk_riscv_skew           ),
 
     // Reset
-          .pwrup_rst_n             (wbd_int_rst_n              ),
-          .rst_n                   (wbd_int_rst_n              ),
-          .cpu_intf_rst_n          (cpu_intf_rst_n             ),
-          .cpu_core_rst_n          (cpu_core_rst_n[0]          ),
-          .riscv_debug             (riscv_debug                ),
-	      .cfg_sram_lphase         (cfg_riscv_sram_lphase      ),
-	      .cfg_cache_ctrl          (cfg_riscv_cache_ctrl       ),
-	      .cfg_bypass_icache       (cfg_bypass_icache          ),
-	      .cfg_bypass_dcache       (cfg_bypass_dcache          ),
+          .pwrup_rst_n        (wbd_int_rst_n                ),
+          .rst_n              (wbd_int_rst_n                ),
+          .cpu_intf_rst_n     (cpu_intf_rst_n               ),
+          .cpu_core_rst_n     (cpu_core_rst_n[0]            ),
+          .riscv_debug        (riscv_debug                  ),
+	      .cfg_sram_lphase    (cfg_riscv_sram_lphase        ),
+	      .cfg_cache_ctrl     (cfg_riscv_cache_ctrl         ),
+	      .cfg_bypass_icache  (cfg_bypass_icache            ),
+	      .cfg_bypass_dcache  (cfg_bypass_dcache            ),
 
     // Clock
-          .core_clk_int            (cpu_clk_rp_risc            ),
-          .cfg_ccska_riscv_intf    (cfg_ccska_riscv_intf_rp    ),
-          .cfg_ccska_riscv_icon    (cfg_ccska_riscv_icon_rp    ),
-          .cfg_ccska_riscv_core0   (cfg_ccska_riscv_core0_rp   ),
+          .core_clk_int         (cpu_clk_rp_risc            ),
+          .cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp    ),
+          .cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp    ),
+          .cfg_ccska_riscv_core0(cfg_ccska_riscv_core0_rp   ),
 
-          .rtc_clk                 (rtc_clk                    ),
+          .rtc_clk              (rtc_clk                    ),
 
 
     // IRQ
-          .irq_lines               (irq_lines_rp               ), 
-          .soft_irq                (soft_irq_rp                ), // TODO - Interrupts
+          .irq_lines            (irq_lines_rp               ), 
+          .soft_irq             (soft_irq_rp                ), // TODO - Interrupts
 
     // DFT
-    //    .test_mode               (1'b0                       ), // Moved inside IP
-    //    .test_rst_n              (1'b1                       ), // Moved inside IP
+    //    .test_mode            (1'b0                       ), // Moved inside IP
+    //    .test_rst_n           (1'b1                       ), // Moved inside IP
 
 `ifndef SCR1_TCM_MEM
     // SRAM-0 PORT-0
-          .sram0_clk0             (sram0_clk0                  ),
-          .sram0_csb0             (sram0_csb0                  ),
-          .sram0_web0             (sram0_web0                  ),
-          .sram0_addr0            (sram0_addr0                 ),
-          .sram0_wmask0           (sram0_wmask0                ),
-          .sram0_din0             (sram0_din0                  ),
-          .sram0_dout0            (sram0_dout0                 ),
+          .sram0_clk0           (sram0_clk0                  ),
+          .sram0_csb0           (sram0_csb0                  ),
+          .sram0_web0           (sram0_web0                  ),
+          .sram0_addr0          (sram0_addr0                 ),
+          .sram0_wmask0         (sram0_wmask0                ),
+          .sram0_din0           (sram0_din0                  ),
+          .sram0_dout0          (sram0_dout0                 ),
     
     // SRAM-0 PORT-0
           .sram0_clk1             (sram0_clk1                   ),
@@ -1147,6 +1173,7 @@
           .wbd_dmem_lack_i         (wbd_riscv_dmem_lack_o   ),
           .wbd_dmem_err_i          (wbd_riscv_dmem_err_o    ),
 
+          .cpu_clk_aes             (cpu_clk_aes             ),
           .aes_dmem_req            (aes_dmem_req            ),
           .aes_dmem_cmd            (aes_dmem_cmd            ),
           .aes_dmem_width          (aes_dmem_width          ),
@@ -1156,6 +1183,7 @@
           .aes_dmem_rdata          (aes_dmem_rdata          ),
           .aes_dmem_resp           (aes_dmem_resp           ),
 
+          .cpu_clk_fpu             (cpu_clk_fpu             ),
           .fpu_dmem_req            (fpu_dmem_req            ),
           .fpu_dmem_cmd            (fpu_dmem_cmd            ),
           .fpu_dmem_width          (fpu_dmem_width          ),
@@ -1166,6 +1194,10 @@
           .fpu_dmem_resp           (fpu_dmem_resp           )
 );
 
+//----------------------------------------------
+// TCM
+//----------------------------------------------
+
 `ifndef SCR1_TCM_MEM
 sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb(
 `ifdef USE_POWER_PINS
@@ -1210,6 +1242,9 @@
 ***/
 `endif
 
+//------------------------------------------------
+// icache
+//------------------------------------------------
 
 sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb(
 `ifdef USE_POWER_PINS
@@ -1231,6 +1266,10 @@
           .dout1              (icache_mem_dout1             )
   );
 
+//----------------------------------------------------------
+// dcache
+//----------------------------------------------------------
+
 sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb(
 `ifdef USE_POWER_PINS
           .vccd1              (vccd1                        ),// User area 1 1.8V supply
@@ -1256,25 +1295,25 @@
 *************************************************/
 aes_top u_aes (
 `ifdef USE_POWER_PINS
-    .vccd1                 (vccd1            ),
-    .vssd1                 (vssd1            ),
+          .vccd1              (vccd1                        ),
+          .vssd1              (vssd1                        ),
 `endif
 
-    .mclk                  (cpu_clk_aes      ),
-    .rst_n                 (cpu_intf_rst_n   ),
+          .mclk               (cpu_clk_aes_skew             ),
+          .rst_n              (cpu_intf_rst_n               ),
 
-    .cfg_cska              (cfg_ccska_aes_rp ),
-    .wbd_clk_int           (cpu_clk_rp_aes   ),
-    .wbd_clk_out           (cpu_clk_aes      ),
+          .cfg_cska           (cfg_ccska_aes_rp             ),
+          .wbd_clk_int        (cpu_clk_aes                  ),
+          .wbd_clk_out        (cpu_clk_aes_skew             ),
 
-    .dmem_req              (aes_dmem_req     ),
-    .dmem_cmd              (aes_dmem_cmd     ),
-    .dmem_width            (aes_dmem_width   ),
-    .dmem_addr             (aes_dmem_addr    ),
-    .dmem_wdata            (aes_dmem_wdata   ),
-    .dmem_req_ack          (aes_dmem_req_ack ),
-    .dmem_rdata            (aes_dmem_rdata   ),
-    .dmem_resp             (aes_dmem_resp    )
+          .dmem_req           (aes_dmem_req                 ),
+          .dmem_cmd           (aes_dmem_cmd                 ),
+          .dmem_width         (aes_dmem_width               ),
+          .dmem_addr          (aes_dmem_addr                ),
+          .dmem_wdata         (aes_dmem_wdata               ),
+          .dmem_req_ack       (aes_dmem_req_ack             ),
+          .dmem_rdata         (aes_dmem_rdata               ),
+          .dmem_resp          (aes_dmem_resp                )
 );
 
 /***********************************************
@@ -1282,116 +1321,115 @@
 *************************************************/
 fpu_wrapper u_fpu (
 `ifdef USE_POWER_PINS
-    .vccd1                 (vccd1            ),
-    .vssd1                 (vssd1            ),
+          .vccd1              (vccd1                        ),
+          .vssd1              (vssd1                        ),
 `endif
 
-    .mclk                  (cpu_clk_fpu      ),
-    .rst_n                 (cpu_intf_rst_n   ),
+          .mclk               (cpu_clk_fpu_skew             ),
+          .rst_n              (cpu_intf_rst_n               ),
 
-    .cfg_cska              (cfg_ccska_fpu_rp ),
-    .wbd_clk_int           (cpu_clk_rp_fpu   ),
-    .wbd_clk_out           (cpu_clk_fpu      ),
+          .cfg_cska           (cfg_ccska_fpu_rp             ),
+          .wbd_clk_int        (cpu_clk_rp_fpu               ),
+          .wbd_clk_out        (cpu_clk_fpu_skew             ),
 
-    .dmem_req              (fpu_dmem_req     ),
-    .dmem_cmd              (fpu_dmem_cmd     ),
-    .dmem_width            (fpu_dmem_width   ),
-    .dmem_addr             (fpu_dmem_addr    ),
-    .dmem_wdata            (fpu_dmem_wdata   ),
-    .dmem_req_ack          (fpu_dmem_req_ack ),
-    .dmem_rdata            (fpu_dmem_rdata   ),
-    .dmem_resp             (fpu_dmem_resp    )
+          .dmem_req           (fpu_dmem_req                 ),
+          .dmem_cmd           (fpu_dmem_cmd                 ),
+          .dmem_width         (fpu_dmem_width               ),
+          .dmem_addr          (fpu_dmem_addr                ),
+          .dmem_wdata         (fpu_dmem_wdata               ),
+          .dmem_req_ack       (fpu_dmem_req_ack             ),
+          .dmem_rdata         (fpu_dmem_rdata               ),
+          .dmem_resp          (fpu_dmem_resp                )
 );
 
 /*********************************************************
 * SPI Master
-* This is implementation of an SPI master that is controlled via an AXI bus                                                  . 
+* This is of an SPI master that is controlled via an AXI bus                                                                                                       . 
 * It has FIFOs for transmitting and receiving data. 
 * It supports both the normal SPI mode and QPI mode with 4 data lines.
 * *******************************************************/
 
 qspim_top
-#(
+#                             (
 `ifndef SYNTHESIS
     .WB_WIDTH  (WB_WIDTH                                    )
 `endif
 ) u_qspi_master
 (
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .mclk                    (wbd_clk_spi             ),
-          .rst_n                   (qspim_rst_n             ),
+          .mclk               (wbd_clk_spi                  ),
+          .rst_n              (qspim_rst_n                  ),
 
-          .strap_flash             (strap_qspi_flash        ),
-          .strap_pre_sram          (strap_qspi_pre_sram     ),
-          .strap_sram              (strap_qspi_sram         ),
-          .cfg_init_bypass         (strap_qspi_init_bypass  ),
+          .strap_flash        (strap_qspi_flash             ),
+          .strap_pre_sram     (strap_qspi_pre_sram          ),
+          .strap_sram         (strap_qspi_sram              ),
+          .cfg_init_bypass    (strap_qspi_init_bypass       ),
 
     // Clock Skew Adjust
-          .cfg_cska_sp_co          (cfg_wcska_qspi_co_rp     ),
-          .cfg_cska_spi            (cfg_wcska_qspi_rp        ),
-          .wbd_clk_int             (wbd_clk_qspi_rp         ),
-          .wbd_clk_spi             (wbd_clk_spi             ),
+          .cfg_cska_sp_co     (cfg_wcska_qspi_co_rp         ),
+          .cfg_cska_spi       (cfg_wcska_qspi_rp            ),
+          .wbd_clk_int        (wbd_clk_qspi_rp              ),
+          .wbd_clk_spi        (wbd_clk_spi                  ),
 
-          .wbd_stb_i               (wbd_spim_stb_o          ),
-          .wbd_adr_i               (wbd_spim_adr_o          ),
-          .wbd_we_i                (wbd_spim_we_o           ), 
-          .wbd_dat_i               (wbd_spim_dat_o          ),
-          .wbd_sel_i               (wbd_spim_sel_o          ),
-          .wbd_bl_i                (wbd_spim_bl_o           ),
-          .wbd_bry_i               (wbd_spim_bry_o          ),
-          .wbd_dat_o               (wbd_spim_dat_i          ),
-          .wbd_ack_o               (wbd_spim_ack_i          ),
-          .wbd_lack_o              (wbd_spim_lack_i         ),
-          .wbd_err_o               (wbd_spim_err_i          ),
+          .wbd_stb_i          (wbd_spim_stb_o               ),
+          .wbd_adr_i          (wbd_spim_adr_o               ),
+          .wbd_we_i           (wbd_spim_we_o                ), 
+          .wbd_dat_i          (wbd_spim_dat_o               ),
+          .wbd_sel_i          (wbd_spim_sel_o               ),
+          .wbd_bl_i           (wbd_spim_bl_o                ),
+          .wbd_bry_i          (wbd_spim_bry_o               ),
+          .wbd_dat_o          (wbd_spim_dat_i               ),
+          .wbd_ack_o          (wbd_spim_ack_i               ),
+          .wbd_lack_o         (wbd_spim_lack_i              ),
+          .wbd_err_o          (wbd_spim_err_i               ),
 
-          .spi_debug               (spi_debug               ),
+          .spi_debug          (spi_debug                    ),
 
     // Pad Interface
-          .spi_sdi                 (sflash_di               ),
-          .spi_clk                 (sflash_sck              ),
-          .spi_csn                 (spi_csn                 ),
-          .spi_sdo                 (sflash_do               ),
-          .spi_oen                 (sflash_oen              )
+          .spi_sdi            (sflash_di                    ),
+          .spi_clk            (sflash_sck                   ),
+          .spi_csn            (spi_csn                      ),
+          .spi_sdo            (sflash_do                    ),
+          .spi_oen            (sflash_oen                   )
 
 );
 
 
+//---------------------------------------------------
+// wb_interconnect
+//---------------------------------------------------
 
 wb_interconnect  #(
 	`ifndef SYNTHESIS
-          .CH_CLK_WD           (14                      ),
-	      .CH_DATA_WD          (154                     )
+          .CH_CLK_WD          (8                            ),
+          .CH_DATA_WD         (158                          )
         `endif
 	) u_intercon (
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+       .vccd1              (vccd1                        ),// User area 1 1                                                     .8V supply
+       .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-	  .ch_clk_in               ({
+	  .ch_clk_in              ({
                                      cpu_clk,
                                      cpu_clk,
                                      cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
+                                     wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int}                  ),
-	  .ch_clk_out              ({
+	  .ch_clk_out             ({
                                      cpu_clk_rp,
+                                     wbd_clk_peri_rp, 
                                      wbd_clk_pinmux_rp, 
                                      wbd_clk_uart_rp, 
                                      wbd_clk_qspi_rp, 
                                      wbd_clk_risc_rp}              ),
-	  .ch_data_in              ({
+	  .ch_data_in             ({
+			                      cfg_wcska_peri[3:0],
                                   cfg_ccska_fpu[3:0],
                                   cfg_ccska_aes[3:0],
                                   strap_sticky[31:0],
@@ -1417,7 +1455,8 @@
 		                          cfg_wcska_qspi[3:0],
                                   cfg_wcska_riscv[3:0]
 			             }                             ),
-	  .ch_data_out             ({
+	  .ch_data_out            ({
+		                          cfg_wcska_peri_rp[3:0],
 			                      cfg_ccska_fpu_rp[3:0],
 			                      cfg_ccska_aes_rp[3:0],
                                   strap_sticky_rp[31:0],
@@ -1444,309 +1483,372 @@
                                   cfg_wcska_riscv_rp[3:0]
                                } ),
      // Clock Skew adjust
-	  .wbd_clk_int                 (wbd_clk_int             ), 
-	  .cfg_cska_wi                 (cfg_wcska_wi            ), 
-	  .wbd_clk_wi                  (wbd_clk_wi_skew         ),
+          .wbd_clk_int        (wbd_clk_int                  ), 
+          .cfg_cska_wi        (cfg_wcska_wi                 ), 
+          .wbd_clk_wi         (wbd_clk_wi_skew              ),
 
-          .clk_i                   (wbd_clk_wi_skew         ), 
-          .rst_n                   (wbd_int_rst_n           ),
+          .clk_i              (wbd_clk_wi_skew              ), 
+          .rst_n              (wbd_int_rst_n                ),
 
          // Master 0 Interface
-          .m0_wbd_dat_i            (wbd_int_dat_i           ),
-          .m0_wbd_adr_i            (wbd_int_adr_i           ),
-          .m0_wbd_sel_i            (wbd_int_sel_i           ),
-          .m0_wbd_we_i             (wbd_int_we_i            ),
-          .m0_wbd_cyc_i            (wbd_int_cyc_i           ),
-          .m0_wbd_stb_i            (wbd_int_stb_i           ),
-          .m0_wbd_dat_o            (wbd_int_dat_o           ),
-          .m0_wbd_ack_o            (wbd_int_ack_o           ),
-          .m0_wbd_err_o            (wbd_int_err_o           ),
+          .m0_wbd_dat_i       (wbd_int_dat_i                ),
+          .m0_wbd_adr_i       (wbd_int_adr_i                ),
+          .m0_wbd_sel_i       (wbd_int_sel_i                ),
+          .m0_wbd_we_i        (wbd_int_we_i                 ),
+          .m0_wbd_cyc_i       (wbd_int_cyc_i                ),
+          .m0_wbd_stb_i       (wbd_int_stb_i                ),
+          .m0_wbd_dat_o       (wbd_int_dat_o                ),
+          .m0_wbd_ack_o       (wbd_int_ack_o                ),
+          .m0_wbd_err_o       (wbd_int_err_o                ),
          
          // Master 1 Interface
-          .m1_wbd_dat_i            (wbd_riscv_dmem_dat_i    ),
-          .m1_wbd_adr_i            (wbd_riscv_dmem_adr_i    ),
-          .m1_wbd_sel_i            (wbd_riscv_dmem_sel_i    ),
-          .m1_wbd_bl_i             (wbd_riscv_dmem_bl_i    ),
-          .m1_wbd_bry_i            (wbd_riscv_dmem_bry_i    ),
-          .m1_wbd_we_i             (wbd_riscv_dmem_we_i     ),
-          .m1_wbd_cyc_i            (wbd_riscv_dmem_stb_i    ),
-          .m1_wbd_stb_i            (wbd_riscv_dmem_stb_i    ),
-          .m1_wbd_dat_o            (wbd_riscv_dmem_dat_o    ),
-          .m1_wbd_ack_o            (wbd_riscv_dmem_ack_o    ),
-          .m1_wbd_lack_o           (wbd_riscv_dmem_lack_o   ),
-          .m1_wbd_err_o            (wbd_riscv_dmem_err_o    ),
+          .m1_wbd_dat_i       (wbd_riscv_dmem_dat_i         ),
+          .m1_wbd_adr_i       (wbd_riscv_dmem_adr_i         ),
+          .m1_wbd_sel_i       (wbd_riscv_dmem_sel_i         ),
+          .m1_wbd_bl_i        (wbd_riscv_dmem_bl_i          ),
+          .m1_wbd_bry_i       (wbd_riscv_dmem_bry_i         ),
+          .m1_wbd_we_i        (wbd_riscv_dmem_we_i          ),
+          .m1_wbd_cyc_i       (wbd_riscv_dmem_stb_i         ),
+          .m1_wbd_stb_i       (wbd_riscv_dmem_stb_i         ),
+          .m1_wbd_dat_o       (wbd_riscv_dmem_dat_o         ),
+          .m1_wbd_ack_o       (wbd_riscv_dmem_ack_o         ),
+          .m1_wbd_lack_o      (wbd_riscv_dmem_lack_o        ),
+          .m1_wbd_err_o       (wbd_riscv_dmem_err_o         ),
          
          // Master 2 Interface
-          .m2_wbd_dat_i            (wbd_riscv_dcache_dat_i  ),
-          .m2_wbd_adr_i            (wbd_riscv_dcache_adr_i  ),
-          .m2_wbd_sel_i            (wbd_riscv_dcache_sel_i  ),
-          .m2_wbd_bl_i             (wbd_riscv_dcache_bl_i   ),
-          .m2_wbd_bry_i            (wbd_riscv_dcache_bry_i  ),
-          .m2_wbd_we_i             (wbd_riscv_dcache_we_i   ),
-          .m2_wbd_cyc_i            (wbd_riscv_dcache_stb_i  ),
-          .m2_wbd_stb_i            (wbd_riscv_dcache_stb_i  ),
-          .m2_wbd_dat_o            (wbd_riscv_dcache_dat_o  ),
-          .m2_wbd_ack_o            (wbd_riscv_dcache_ack_o  ),
-          .m2_wbd_lack_o           (wbd_riscv_dcache_lack_o ),
-          .m2_wbd_err_o            (wbd_riscv_dcache_err_o  ),
+          .m2_wbd_dat_i       (wbd_riscv_dcache_dat_i       ),
+          .m2_wbd_adr_i       (wbd_riscv_dcache_adr_i       ),
+          .m2_wbd_sel_i       (wbd_riscv_dcache_sel_i       ),
+          .m2_wbd_bl_i        (wbd_riscv_dcache_bl_i        ),
+          .m2_wbd_bry_i       (wbd_riscv_dcache_bry_i       ),
+          .m2_wbd_we_i        (wbd_riscv_dcache_we_i        ),
+          .m2_wbd_cyc_i       (wbd_riscv_dcache_stb_i       ),
+          .m2_wbd_stb_i       (wbd_riscv_dcache_stb_i       ),
+          .m2_wbd_dat_o       (wbd_riscv_dcache_dat_o       ),
+          .m2_wbd_ack_o       (wbd_riscv_dcache_ack_o       ),
+          .m2_wbd_lack_o      (wbd_riscv_dcache_lack_o      ),
+          .m2_wbd_err_o       (wbd_riscv_dcache_err_o       ),
 
          // Master 3 Interface
-          .m3_wbd_adr_i            (wbd_riscv_icache_adr_i  ),
-          .m3_wbd_sel_i            (wbd_riscv_icache_sel_i  ),
-          .m3_wbd_bl_i             (wbd_riscv_icache_bl_i   ),
-          .m3_wbd_bry_i            (wbd_riscv_icache_bry_i  ),
-          .m3_wbd_we_i             (wbd_riscv_icache_we_i   ),
-          .m3_wbd_cyc_i            (wbd_riscv_icache_stb_i  ),
-          .m3_wbd_stb_i            (wbd_riscv_icache_stb_i  ),
-          .m3_wbd_dat_o            (wbd_riscv_icache_dat_o  ),
-          .m3_wbd_ack_o            (wbd_riscv_icache_ack_o  ),
-          .m3_wbd_lack_o           (wbd_riscv_icache_lack_o ),
-          .m3_wbd_err_o            (wbd_riscv_icache_err_o  ),
+          .m3_wbd_adr_i       (wbd_riscv_icache_adr_i       ),
+          .m3_wbd_sel_i       (wbd_riscv_icache_sel_i       ),
+          .m3_wbd_bl_i        (wbd_riscv_icache_bl_i        ),
+          .m3_wbd_bry_i       (wbd_riscv_icache_bry_i       ),
+          .m3_wbd_we_i        (wbd_riscv_icache_we_i        ),
+          .m3_wbd_cyc_i       (wbd_riscv_icache_stb_i       ),
+          .m3_wbd_stb_i       (wbd_riscv_icache_stb_i       ),
+          .m3_wbd_dat_o       (wbd_riscv_icache_dat_o       ),
+          .m3_wbd_ack_o       (wbd_riscv_icache_ack_o       ),
+          .m3_wbd_lack_o      (wbd_riscv_icache_lack_o      ),
+          .m3_wbd_err_o       (wbd_riscv_icache_err_o       ),
          
          
          // Slave 0 Interface
-       // .s0_wbd_err_i            (1'b0                    ), - Moved inside IP
-          .s0_wbd_dat_i            (wbd_spim_dat_i          ),
-          .s0_wbd_ack_i            (wbd_spim_ack_i          ),
-          .s0_wbd_lack_i           (wbd_spim_lack_i         ),
-          .s0_wbd_dat_o            (wbd_spim_dat_o          ),
-          .s0_wbd_adr_o            (wbd_spim_adr_o          ),
-          .s0_wbd_bry_o            (wbd_spim_bry_o          ),
-          .s0_wbd_bl_o             (wbd_spim_bl_o           ),
-          .s0_wbd_sel_o            (wbd_spim_sel_o          ),
-          .s0_wbd_we_o             (wbd_spim_we_o           ),  
-          .s0_wbd_cyc_o            (wbd_spim_cyc_o          ),
-          .s0_wbd_stb_o            (wbd_spim_stb_o          ),
+       // .s0_wbd_err_i       (1'b0                         ), - Moved inside IP
+          .s0_wbd_dat_i       (wbd_spim_dat_i               ),
+          .s0_wbd_ack_i       (wbd_spim_ack_i               ),
+          .s0_wbd_lack_i      (wbd_spim_lack_i              ),
+          .s0_wbd_dat_o       (wbd_spim_dat_o               ),
+          .s0_wbd_adr_o       (wbd_spim_adr_o               ),
+          .s0_wbd_bry_o       (wbd_spim_bry_o               ),
+          .s0_wbd_bl_o        (wbd_spim_bl_o                ),
+          .s0_wbd_sel_o       (wbd_spim_sel_o               ),
+          .s0_wbd_we_o        (wbd_spim_we_o                ),  
+          .s0_wbd_cyc_o       (wbd_spim_cyc_o               ),
+          .s0_wbd_stb_o       (wbd_spim_stb_o               ),
          
          // Slave 1 Interface
-       // .s1_wbd_err_i            (1'b0                    ), - Moved inside IP
-          .s1_wbd_dat_i            (wbd_uart_dat_i          ),
-          .s1_wbd_ack_i            (wbd_uart_ack_i          ),
-          .s1_wbd_dat_o            (wbd_uart_dat_o          ),
-          .s1_wbd_adr_o            (wbd_uart_adr_o          ),
-          .s1_wbd_sel_o            (wbd_uart_sel_o          ),
-          .s1_wbd_we_o             (wbd_uart_we_o           ),  
-          .s1_wbd_cyc_o            (wbd_uart_cyc_o          ),
-          .s1_wbd_stb_o            (wbd_uart_stb_o          ),
+       // .s1_wbd_err_i       (1'b0                         ), - Moved inside IP
+          .s1_wbd_dat_i       (wbd_uart_dat_i               ),
+          .s1_wbd_ack_i       (wbd_uart_ack_i               ),
+          .s1_wbd_dat_o       (wbd_uart_dat_o               ),
+          .s1_wbd_adr_o       (wbd_uart_adr_o               ),
+          .s1_wbd_sel_o       (wbd_uart_sel_o               ),
+          .s1_wbd_we_o        (wbd_uart_we_o                ),  
+          .s1_wbd_cyc_o       (wbd_uart_cyc_o               ),
+          .s1_wbd_stb_o       (wbd_uart_stb_o               ),
          
          // Slave 2 Interface
-       // .s2_wbd_err_i            (1'b0                    ), - Moved inside IP
-          .s2_wbd_dat_i            (wbd_glbl_dat_i          ),
-          .s2_wbd_ack_i            (wbd_glbl_ack_i          ),
-          .s2_wbd_dat_o            (wbd_glbl_dat_o          ),
-          .s2_wbd_adr_o            (wbd_glbl_adr_o          ),
-          .s2_wbd_sel_o            (wbd_glbl_sel_o          ),
-          .s2_wbd_we_o             (wbd_glbl_we_o           ),  
-          .s2_wbd_cyc_o            (wbd_glbl_cyc_o          ),
-          .s2_wbd_stb_o            (wbd_glbl_stb_o          )
+       // .s2_wbd_err_i       (1'b0                         ), - Moved inside IP
+          .s2_wbd_dat_i       (wbd_glbl_dat_i               ),
+          .s2_wbd_ack_i       (wbd_glbl_ack_i               ),
+          .s2_wbd_dat_o       (wbd_glbl_dat_o               ),
+          .s2_wbd_adr_o       (wbd_glbl_adr_o               ),
+          .s2_wbd_sel_o       (wbd_glbl_sel_o               ),
+          .s2_wbd_we_o        (wbd_glbl_we_o                ),  
+          .s2_wbd_cyc_o       (wbd_glbl_cyc_o               ),
+          .s2_wbd_stb_o       (wbd_glbl_stb_o               )
 
 
 	);
 
+//-----------------------------------------------
+// uart+i2c+usb+spi
+//-----------------------------------------------
 
 uart_i2c_usb_spi_top   u_uart_i2c_usb_spi (
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .wbd_clk_int             (wbd_clk_uart_rp         ), 
-          .cfg_cska_uart           (cfg_wcska_uart_rp        ), 
-          .wbd_clk_uart            (wbd_clk_uart_skew       ),
+          .wbd_clk_int        (wbd_clk_uart_rp              ), 
+          .cfg_cska_uart      (cfg_wcska_uart_rp            ), 
+          .wbd_clk_uart       (wbd_clk_uart_skew            ),
 
-          .uart_rstn               (uart_rst_n              ), // uart reset
-          .i2c_rstn                (i2c_rst_n               ), // i2c reset
-          .usb_rstn                (usb_rst_n               ), // USB reset
-          .spi_rstn                (sspim_rst_n             ), // SPI reset
-          .app_clk                 (wbd_clk_uart_skew       ),
-	      .usb_clk                 (usb_clk                 ),
+          .uart_rstn          (uart_rst_n                   ), // uart reset
+          .i2c_rstn           (i2c_rst_n                    ), // i2c reset
+          .usb_rstn           (usb_rst_n                    ), // USB reset
+          .spi_rstn           (sspim_rst_n                  ), // SPI reset
+          .app_clk            (wbd_clk_uart_skew            ),
+          .usb_clk            (usb_clk                      ),
 
         // Reg Bus Interface Signal
-          .reg_cs                  (wbd_uart_stb_o          ),
-          .reg_wr                  (wbd_uart_we_o           ),
-          .reg_addr                (wbd_uart_adr_o[8:0]     ),
-          .reg_wdata               (wbd_uart_dat_o          ),
-          .reg_be                  (wbd_uart_sel_o          ),
+          .reg_cs             (wbd_uart_stb_o               ),
+          .reg_wr             (wbd_uart_we_o                ),
+          .reg_addr           (wbd_uart_adr_o[8:0]          ),
+          .reg_wdata          (wbd_uart_dat_o               ),
+          .reg_be             (wbd_uart_sel_o               ),
 
        // Outputs
-          .reg_rdata               (wbd_uart_dat_i          ),
-          .reg_ack                 (wbd_uart_ack_i          ),
+          .reg_rdata          (wbd_uart_dat_i               ),
+          .reg_ack            (wbd_uart_ack_i               ),
 
        // Pad interface
-          .scl_pad_i               (i2cm_clk_i              ),
-          .scl_pad_o               (i2cm_clk_o              ),
-          .scl_pad_oen_o           (i2cm_clk_oen            ),
+          .scl_pad_i          (i2cm_clk_i                   ),
+          .scl_pad_o          (i2cm_clk_o                   ),
+          .scl_pad_oen_o      (i2cm_clk_oen                 ),
 
-          .sda_pad_i               (i2cm_data_i             ),
-          .sda_pad_o               (i2cm_data_o             ),
-          .sda_padoen_o            (i2cm_data_oen           ),
+          .sda_pad_i          (i2cm_data_i                  ),
+          .sda_pad_o          (i2cm_data_o                  ),
+          .sda_padoen_o       (i2cm_data_oen                ),
      
-          .i2cm_intr_o             (i2cm_intr_o             ),
+          .i2cm_intr_o        (i2cm_intr_o                  ),
 
-          .uart_rxd                (uart_rxd                ),
-          .uart_txd                (uart_txd                ),
+          .uart_rxd           (uart_rxd                     ),
+          .uart_txd           (uart_txd                     ),
 
-          .usb_in_dp               (usb_dp_i                ),
-          .usb_in_dn               (usb_dn_i                ),
+          .usb_in_dp          (usb_dp_i                     ),
+          .usb_in_dn          (usb_dn_i                     ),
 
-          .usb_out_dp              (usb_dp_o                ),
-          .usb_out_dn              (usb_dn_o                ),
-          .usb_out_tx_oen          (usb_oen                 ),
+          .usb_out_dp         (usb_dp_o                     ),
+          .usb_out_dn         (usb_dn_o                     ),
+          .usb_out_tx_oen     (usb_oen                      ),
        
-          .usb_intr_o              (usb_intr_o              ),
+          .usb_intr_o         (usb_intr_o                   ),
 
       // SPIM Master
-          .sspim_sck               (sspim_sck               ), 
-          .sspim_so                (sspim_so                ),  
-          .sspim_si                (sspim_si                ),  
-          .sspim_ssn               (sspim_ssn               )  
+          .sspim_sck          (sspim_sck                    ), 
+          .sspim_so           (sspim_so                     ),  
+          .sspim_si           (sspim_si                     ),  
+          .sspim_ssn          (sspim_ssn                    )  
 
      );
 
+//---------------------------------------
+// Pinmux
+//---------------------------------------
+
 pinmux_top u_pinmux(
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
         //clk skew adjust
-          .cfg_cska_pinmux         (cfg_wcska_pinmux_rp      ),
-          .wbd_clk_int             (wbd_clk_pinmux_rp       ),
-          .wbd_clk_pinmux          (wbd_clk_pinmux_skew     ),
+          .cfg_cska_pinmux    (cfg_wcska_pinmux_rp          ),
+          .wbd_clk_int        (wbd_clk_pinmux_rp            ),
+          .wbd_clk_pinmux     (wbd_clk_pinmux_skew          ),
 
         // System Signals
         // Inputs
-          .mclk                    (wbd_clk_pinmux_skew     ),
-          .e_reset_n               (e_reset_n_rp            ),
-          .p_reset_n               (p_reset_n_rp            ),
-          .s_reset_n               (wbd_int_rst_n           ),
+          .mclk               (wbd_clk_pinmux_skew          ),
+          .e_reset_n          (e_reset_n_rp                 ),
+          .p_reset_n          (p_reset_n_rp                 ),
+          .s_reset_n          (wbd_int_rst_n                ),
 
-          .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl_rp   ),
-          .system_strap            (system_strap_rp         ),
-          .strap_sticky            (strap_sticky            ),
-	      .strap_uartm             (strap_uartm             ),
+          .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl_rp        ),
+          .system_strap       (system_strap_rp              ),
+          .strap_sticky       (strap_sticky                 ),
+          .strap_uartm        (strap_uartm                  ),
 
-          .user_clock1             (wb_clk_i_rp             ),
-          .user_clock2             (user_clock2_rp          ),
-          .int_pll_clock           (int_pll_clock           ),
-          .xtal_clk                (xtal_clk                ),
-          .cpu_clk                 (cpu_clk_rp_pinmux       ),
+          .user_clock1        (wb_clk_i_rp                  ),
+          .user_clock2        (user_clock2_rp               ),
+          .int_pll_clock      (int_pll_clock                ),
+          .xtal_clk           (xtal_clk                     ),
+          .cpu_clk            (cpu_clk_rp_pinmux            ),
 
 
-          .rtc_clk                 (rtc_clk                 ),
-          .usb_clk                 (usb_clk                 ),
+          .rtc_clk            (rtc_clk                      ),
+          .usb_clk            (usb_clk                      ),
 	// Reset Control
-          .cpu_core_rst_n          (cpu_core_rst_n          ),
-          .cpu_intf_rst_n          (cpu_intf_rst_n          ),
-          .qspim_rst_n             (qspim_rst_n             ),
-          .sspim_rst_n             (sspim_rst_n             ),
-          .uart_rst_n              (uart_rst_n              ),
-          .i2cm_rst_n              (i2c_rst_n               ),
-          .usb_rst_n               (usb_rst_n               ),
+          .cpu_core_rst_n     (cpu_core_rst_n               ),
+          .cpu_intf_rst_n     (cpu_intf_rst_n               ),
+          .qspim_rst_n        (qspim_rst_n                  ),
+          .sspim_rst_n        (sspim_rst_n                  ),
+          .uart_rst_n         (uart_rst_n                   ),
+          .i2cm_rst_n         (i2c_rst_n                    ),
+          .usb_rst_n          (usb_rst_n                    ),
 
-	      .cfg_riscv_ctrl          (cfg_riscv_ctrl          ),
+          .cfg_riscv_ctrl     (cfg_riscv_ctrl               ),
 
         // Reg Bus Interface Signal
-          .reg_cs                  (wbd_glbl_stb_o          ),
-          .reg_wr                  (wbd_glbl_we_o           ),
-          .reg_addr                (wbd_glbl_adr_o          ),
-          .reg_wdata               (wbd_glbl_dat_o          ),
-          .reg_be                  (wbd_glbl_sel_o          ),
+          .reg_cs             (wbd_glbl_stb_o               ),
+          .reg_wr             (wbd_glbl_we_o                ),
+          .reg_addr           (wbd_glbl_adr_o               ),
+          .reg_wdata          (wbd_glbl_dat_o               ),
+          .reg_be             (wbd_glbl_sel_o               ),
 
        // Outputs
-          .reg_rdata               (wbd_glbl_dat_i          ),
-          .reg_ack                 (wbd_glbl_ack_i          ),
+          .reg_rdata          (wbd_glbl_dat_i               ),
+          .reg_ack            (wbd_glbl_ack_i               ),
 
 
        // Risc configuration
-          .irq_lines               (irq_lines               ),
-          .soft_irq                (soft_irq                ),
-          .user_irq                (user_irq                ),
-          .usb_intr                (usb_intr_o              ),
-          .i2cm_intr               (i2cm_intr_o             ),
+          .irq_lines          (irq_lines                    ),
+          .soft_irq           (soft_irq                     ),
+          .user_irq           (user_irq                     ),
+          .usb_intr           (usb_intr_o                   ),
+          .i2cm_intr          (i2cm_intr_o                  ),
 
        // Digital IO
-          .digital_io_out          (io_out_int              ),
-          .digital_io_oen          (io_oeb_int              ),
-          .digital_io_in           (io_in_rp                ),
+          .digital_io_out     (io_out_int                   ),
+          .digital_io_oen     (io_oeb_int                   ),
+          .digital_io_in      (io_in_rp                     ),
 
        // SFLASH I/F
-          .sflash_sck              (sflash_sck              ),
-          .sflash_ss               (spi_csn                 ),
-          .sflash_oen              (sflash_oen              ),
-          .sflash_do               (sflash_do               ),
-          .sflash_di               (sflash_di               ),
+          .sflash_sck         (sflash_sck                   ),
+          .sflash_ss          (spi_csn                      ),
+          .sflash_oen         (sflash_oen                   ),
+          .sflash_do          (sflash_do                    ),
+          .sflash_di          (sflash_di                    ),
 
 
        // USB I/F
-          .usb_dp_o                (usb_dp_o                ),
-          .usb_dn_o                (usb_dn_o                ),
-          .usb_oen                 (usb_oen                 ),
-          .usb_dp_i                (usb_dp_i                ),
-          .usb_dn_i                (usb_dn_i                ),
+          .usb_dp_o           (usb_dp_o                     ),
+          .usb_dn_o           (usb_dn_o                     ),
+          .usb_oen            (usb_oen                      ),
+          .usb_dp_i           (usb_dp_i                     ),
+          .usb_dn_i           (usb_dn_i                     ),
 
        // UART I/F
-          .uart_txd                (uart_txd                ),
-          .uart_rxd                (uart_rxd                ),
+          .uart_txd           (uart_txd                     ),
+          .uart_rxd           (uart_rxd                     ),
 
        // I2CM I/F
-          .i2cm_clk_o              (i2cm_clk_o              ),
-          .i2cm_clk_i              (i2cm_clk_i              ),
-          .i2cm_clk_oen            (i2cm_clk_oen            ),
-          .i2cm_data_oen           (i2cm_data_oen           ),
-          .i2cm_data_o             (i2cm_data_o             ),
-          .i2cm_data_i             (i2cm_data_i             ),
+          .i2cm_clk_o         (i2cm_clk_o                   ),
+          .i2cm_clk_i         (i2cm_clk_i                   ),
+          .i2cm_clk_oen       (i2cm_clk_oen                 ),
+          .i2cm_data_oen      (i2cm_data_oen                ),
+          .i2cm_data_o        (i2cm_data_o                  ),
+          .i2cm_data_i        (i2cm_data_i                  ),
 
        // SPI MASTER
-          .spim_sck                (sspim_sck               ),
-          .spim_ssn                (sspim_ssn               ),
-          .spim_miso               (sspim_so                ),
-          .spim_mosi               (sspim_si                ),
+          .spim_sck           (sspim_sck                    ),
+          .spim_ssn           (sspim_ssn                    ),
+          .spim_miso          (sspim_so                     ),
+          .spim_mosi          (sspim_si                     ),
        
        // SPI SLAVE
-          .spis_sck                (sspis_sck               ),
-          .spis_ssn                (sspis_ssn               ),
-          .spis_miso               (sspis_so                ),
-          .spis_mosi               (sspis_si                ),
+          .spis_sck           (sspis_sck                    ),
+          .spis_ssn           (sspis_ssn                    ),
+          .spis_miso          (sspis_so                     ),
+          .spis_mosi          (sspis_si                     ),
 
       // UART MASTER I/F
-          .uartm_rxd               (uartm_rxd               ),
-          .uartm_txd               (uartm_txd               ),
+          .uartm_rxd          (uartm_rxd                    ),
+          .uartm_txd          (uartm_txd                    ),
 
 
-	  .pulse1m_mclk            (pulse1m_mclk            ),
+          .pulse1m_mclk       (pulse1m_mclk                 ),
+     
+          .pinmux_debug       (pinmux_debug                 ),
+     
+     
+          .cfg_pll_enb        (cfg_pll_enb                  ), 
+          .cfg_pll_fed_div    (cfg_pll_fed_div              ), 
+          .cfg_dco_mode       (cfg_dco_mode                 ), 
+          .cfg_dc_trim        (cfg_dc_trim                  ),
+          .pll_ref_clk        (pll_ref_clk                  ),
+     
+        // Peripheral Reg Bus Interface Signal
+          .reg_peri_cs        (reg_peri_cs                  ),
+          .reg_peri_wr        (reg_peri_wr                  ),
+          .reg_peri_addr      (reg_peri_addr                ),
+          .reg_peri_wdata     (reg_peri_wdata               ),
+          .reg_peri_be        (reg_peri_be                  ),
 
-	  .pinmux_debug            (pinmux_debug            ),
+       // Outputs
+          .reg_peri_rdata     (reg_peri_rdata               ),
+          .reg_peri_ack       (reg_peri_ack                 ),
 
+          .rtc_intr           (rtc_intr                     )
 
-       .cfg_pll_enb            (cfg_pll_enb             ), 
-       .cfg_pll_fed_div        (cfg_pll_fed_div         ), 
-       .cfg_dco_mode           (cfg_dco_mode            ), 
-       .cfg_dc_trim            (cfg_dc_trim             ),
-       .pll_ref_clk            (pll_ref_clk             ),
+   ); 
 
-       .cfg_dac0_mux_sel       (cfg_dac0_mux_sel        ),
-       .cfg_dac1_mux_sel       (cfg_dac1_mux_sel        ),
-       .cfg_dac2_mux_sel       (cfg_dac2_mux_sel        ),
-       .cfg_dac3_mux_sel       (cfg_dac3_mux_sel        )
+//---------------------------------------------------------
+// Peripheral block
+//----------------------------------------------------------
+
+peri_top u_peri(
+`ifdef USE_POWER_PINS
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
+`endif
+        //clk skew adjust
+          .cfg_cska_peri      (cfg_wcska_peri_rp            ),
+          .wbd_clk_int        (wbd_clk_peri_rp              ),
+          .wbd_clk_peri       (wbd_clk_peri_skew            ),
+
+        // System Signals
+        // Inputs
+          .mclk                    (wbd_clk_peri_skew       ),
+          .s_reset_n               (wbd_int_rst_n           ),
+
+        // Peripheral Reg Bus Interface Signal
+          .reg_cs                  (reg_peri_cs             ),
+          .reg_wr                  (reg_peri_wr             ),
+          .reg_addr                (reg_peri_addr           ),
+          .reg_wdata               (reg_peri_wdata          ),
+          .reg_be                  (reg_peri_be             ),
+
+       // Outputs
+          .reg_rdata               (reg_peri_rdata          ),
+          .reg_ack                 (reg_peri_ack            ),
+
+          // RTC clock domain
+          .rtc_clk                 (rtc_clk                 ),
+          .rtc_intr                (rtc_intr                ),
+
+          .inc_time_s              (                        ),
+          .inc_date_d              (                        ),
+
+          .cfg_dac0_mux_sel        (cfg_dac0_mux_sel        ),
+          .cfg_dac1_mux_sel        (cfg_dac1_mux_sel        ),
+          .cfg_dac2_mux_sel        (cfg_dac2_mux_sel        ),
+          .cfg_dac3_mux_sel        (cfg_dac3_mux_sel        )
 
    ); 
 
 
 
+//------------------------------------------
+// 4 x 8 bit DAC
+//------------------------------------------
+
 
 dac_top  u_4x8bit_dac(
 `ifdef USE_POWER_PINS
-    .vccd1                 (vdda1                  ),
-    .vssd1                 (vssa1                  ),
+          .vccd1              (vdda1                        ),
+          .vssd1              (vssa1                        ),
 `endif
-    .Vref (analog_io[23]),
-    .DIn0 (cfg_dac0_mux_sel),
-    .DIn1 (cfg_dac1_mux_sel),
-    .DIn2 (cfg_dac2_mux_sel),
-    .DIn3 (cfg_dac3_mux_sel),
-    .Vout0(analog_io[15]   ),
-    .Vout1(analog_io[16]   ),
-    .Vout2(analog_io[17]   ),
-    .Vout3(analog_io[18]   )
+          .Vref               (analog_io[23]                ),
+          .DIn0               (cfg_dac0_mux_sel             ),
+          .DIn1               (cfg_dac1_mux_sel             ),
+          .DIn2               (cfg_dac2_mux_sel             ),
+          .DIn3               (cfg_dac3_mux_sel             ),
+          .Vout0              (analog_io[15]                ),
+          .Vout1              (analog_io[16]                ),
+          .Vout2              (analog_io[17]                ),
+          .Vout3              (analog_io[18]                )
    );
 
 
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 3c904f9..f2b704a 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -15,7 +15,8 @@
 `define ADDR_SPACE_TIMER   32'h3002_0180
 `define ADDR_SPACE_SEMA    32'h3002_0200
 `define ADDR_SPACE_WS281X  32'h3002_0280
-`define ADDR_SPACE_ANALOG  32'h3002_0300
+`define ADDR_SPACE_ANALOG  32'h3002_0400
+`define ADDR_SPACE_RTC     32'h3002_0480
 `define ADDR_SPACE_WBHOST  32'h3008_0000
 
 //--------------------------------------------------
@@ -166,3 +167,13 @@
 `define UART_RDATA        8'h18  // Reg-6
 `define UART_TFIFO_STAT   8'h1C  // Reg-7
 `define UART_RFIFO_STAT   8'h20  // Reg-8
+
+//--------------------------------------------------------
+// RTC Register Map
+//--------------------------------------------------------
+`define  RTC_CMD          8'h0
+`define  RTC_TIME         8'h4
+`define  RTC_DATE         8'h8
+`define  RTC_ALRM1        8'hC
+`define  RTC_ALRM2        8'h10
+`define  RTC_CTRL         8'h14
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index e595919..ea798b9 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,7 +203,7 @@
          input	logic 	        s2_wbd_ack_i,
          // input	logic 	s2_wbd_err_i, - unused
          output	logic [31:0]	s2_wbd_dat_o,
-         output	logic [9:0]	    s2_wbd_adr_o, // glbl reg need only 9 bits
+         output	logic [10:0]	s2_wbd_adr_o, // glbl reg need only 9 bits
          output	logic [3:0]	    s2_wbd_sel_o,
          output	logic 	        s2_wbd_we_o,
          output	logic 	        s2_wbd_cyc_o,
@@ -677,7 +677,7 @@
  assign  s1_wbd_stb_o =  s1_wb_wr.wbd_stb ;
                       
  assign  s2_wbd_dat_o =  s2_wb_wr.wbd_dat ;
- assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit
+ assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit
  assign  s2_wbd_sel_o =  s2_wb_wr.wbd_sel ;
  assign  s2_wbd_we_o  =  s2_wb_wr.wbd_we  ;
  assign  s2_wbd_cyc_o =  s2_wb_wr.wbd_cyc ;
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index dc5e3f6..86e4308 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit dc5e3f6baba16dad71199777a802fe812982f5a4
+Subproject commit 86e4308350445841634940db1ca5ed634b830a8b