diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..697fc15
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 1e5ace33ca8d8c89b41051dc1acf52d440b7aa0d
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..3e02e1f
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/dineshannayya/riscduino_qcore.git
+Branch: main
+Commit: 7764ef40a007aa7e18c93005922bf01a9b39dba3
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..42a89ef
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,1005 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
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+    Elapsed: 0.150s  Memory: 971.00M
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+DRC section
+BEOL section
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+END: 67/20 (li)
+START: 67/44 (mcon)
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+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 2304.530s  Memory: 7222.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..30912b0
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,817 @@
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
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+"enclosing" in: sky130A_mr.drc:372
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+"output" in: sky130A_mr.drc:372
+    Edge pairs: 0 (flat)  0 (hierarchical)
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+"enclosing" in: sky130A_mr.drc:373
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+"not_interacting" in: sky130A_mr.drc:375
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+"separation" in: sky130A_mr.drc:375
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+"output" in: sky130A_mr.drc:375
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1860.00M
+END: 89/44 (capm)
+START: 97/44 (cap2m)
+"width" in: sky130A_mr.drc:380
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+"output" in: sky130A_mr.drc:380
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+"output" in: sky130A_mr.drc:388
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+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
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+END: 75/20 (hvi)
+START: 125/20 (hvntm)
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+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1860.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 233.980s  Memory: 1828.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..1a943c1
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
+"polygons" in: met_min_ca_density.lydrc:35
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+    Elapsed: 0.440s  Memory: 976.00M
+"polygons" in: met_min_ca_density.lydrc:36
+    Polygons (raw): 10385548 (flat)  364685 (hierarchical)
+    Elapsed: 0.340s  Memory: 985.00M
+"polygons" in: met_min_ca_density.lydrc:38
+    Polygons (raw): 8531508 (flat)  2056622 (hierarchical)
+    Elapsed: 1.370s  Memory: 1044.00M
+"polygons" in: met_min_ca_density.lydrc:39
+    Polygons (raw): 1735124 (flat)  740714 (hierarchical)
+    Elapsed: 0.590s  Memory: 1053.00M
+"polygons" in: met_min_ca_density.lydrc:41
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+    Elapsed: 0.800s  Memory: 1079.00M
+"polygons" in: met_min_ca_density.lydrc:42
+    Polygons (raw): 394801 (flat)  262372 (hierarchical)
+    Elapsed: 0.330s  Memory: 1082.00M
+"polygons" in: met_min_ca_density.lydrc:44
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+    Elapsed: 0.330s  Memory: 1088.00M
+"polygons" in: met_min_ca_density.lydrc:45
+    Polygons (raw): 414888 (flat)  315056 (hierarchical)
+    Elapsed: 0.350s  Memory: 1094.00M
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+    Polygons (raw): 75418 (flat)  34143 (hierarchical)
+    Elapsed: 0.190s  Memory: 1095.00M
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+    Elapsed: 0.010s  Memory: 1095.00M
+"polygons" in: met_min_ca_density.lydrc:49
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+    Elapsed: 0.030s  Memory: 1097.00M
+"polygons" in: met_min_ca_density.lydrc:51
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+    Elapsed: 0.000s  Memory: 1097.00M
+"input" in: met_min_ca_density.lydrc:53
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+    Elapsed: 0.190s  Memory: 1097.00M
+"area" in: met_min_ca_density.lydrc:55
+    Elapsed: 3.730s  Memory: 1114.00M
+"polygons" in: met_min_ca_density.lydrc:59
+    Polygons (raw): 8301559 (flat)  370434 (hierarchical)
+    Elapsed: 0.370s  Memory: 1116.00M
+"area" in: met_min_ca_density.lydrc:59
+    Elapsed: 38.340s  Memory: 1650.00M
+li1_ca_density is 0.6993671376867996
+"polygons" in: met_min_ca_density.lydrc:69
+    Polygons (raw): 8531508 (flat)  2056622 (hierarchical)
+    Elapsed: 1.380s  Memory: 1650.00M
+"area" in: met_min_ca_density.lydrc:69
+    Elapsed: 40.090s  Memory: 1720.00M
+m1_ca_density is 0.8175428347018991
+"polygons" in: met_min_ca_density.lydrc:79
+    Polygons (raw): 3152203 (flat)  999080 (hierarchical)
+    Elapsed: 0.820s  Memory: 1720.00M
+"area" in: met_min_ca_density.lydrc:79
+    Elapsed: 7.750s  Memory: 1729.00M
+m2_ca_density is 0.8984619282183998
+"polygons" in: met_min_ca_density.lydrc:89
+    Polygons (raw): 476920 (flat)  247196 (hierarchical)
+    Elapsed: 0.330s  Memory: 1729.00M
+"area" in: met_min_ca_density.lydrc:89
+    Elapsed: 2.250s  Memory: 1729.00M
+m3_ca_density is 0.9303010181813317
+"polygons" in: met_min_ca_density.lydrc:99
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+    Elapsed: 0.200s  Memory: 1729.00M
+"area" in: met_min_ca_density.lydrc:99
+    Elapsed: 0.630s  Memory: 1729.00M
+m4_ca_density is 0.7814383871711551
+"polygons" in: met_min_ca_density.lydrc:109
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1729.00M
+"area" in: met_min_ca_density.lydrc:109
+    Elapsed: 0.270s  Memory: 1729.00M
+m5_ca_density is 0.7194373163138232
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 107.730s  Memory: 1651.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..412afab
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,765 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:60: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 1668836 (flat)  950 (hierarchical)
+    Elapsed: 0.250s  Memory: 971.00M
+"polygons" in: sky130A_mr.drc:125
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+    Elapsed: 0.180s  Memory: 971.00M
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+    Elapsed: 0.150s  Memory: 971.00M
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+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.690s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 8.250s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.610s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.510s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.060s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.000s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.290s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.370s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.770s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.730s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.390s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.380s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.380s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.390s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.390s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.400s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.390s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.380s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"with_angle" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 3064.00M
+"ongrid" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.370s  Memory: 3064.00M
+"output" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3064.00M
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 273.230s  Memory: 2972.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..db0fc9f
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/riscduino-qcore_q2_3/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/dat
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/EMP     72/5/dat
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 2612308 kB
+VmHWM:	 1373236 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..a626353
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,6 @@
+writing to /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper_no_zero_areas.gds
+0 zero-area shapes
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	 1942432 kB
+VmHWM:	 1555420 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..052ea5e
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,606 @@
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Error parsing "/opt/checks/tech-files/sky130A.magicrc": can't read "::env(PDK_PATH)": no such variable
+Bad local startup file "/opt/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Cell sky130_sram_2kbyte_1rw1r_32x512_8 has technology "sky130A", but current technology is "minimum"
+Loading technology sky130A
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Cell path is now "$CAD_ROOT/magic/sys/current $CAD_ROOT/magic/tutorial /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_io/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_io/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_pr/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_pr/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hd/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hd/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hvl/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hvl/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_ml_xx_hd/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_sram_macros/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_sram_macros/maglef"
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "ycr4_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+Reading "bus_rep_west".
+    5000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 116010538): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 116011242): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 116012202): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116504448): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116508224): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116512416): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116517216): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116519264): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116698706): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116702482): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116706674): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116713138): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116715314): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116955764): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116959540): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116963732): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116970196): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116972372): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning:  cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "peri_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "bus_rep_east".
+    5000 uses
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__dlclkp_2".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "bus_rep_south".
+    5000 uses
+Reading "bus_rep_north".
+    5000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..f65aecb
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 0059588eebfc704681dc2368bd1d33d96281d10f
+SKY130A PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..554d69c
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,80 @@
+2022-12-14 09:29:57 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_qcore.git | Branch: main | Commit: 7764ef40a007aa7e18c93005922bf01a9b39dba3
+2022-12-14 09:29:57 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-qcore_q2_3
+2022-12-14 09:29:59 - [INFO] - {{Project Type Info}} digital
+2022-12-14 09:30:00 - [INFO] - {{Project GDS Info}} user_project_wrapper: 1e5ace33ca8d8c89b41051dc1acf52d440b7aa0d
+2022-12-14 09:30:00 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
+2022-12-14 09:30:00 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+2022-12-14 09:30:00 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs'
+2022-12-14 09:30:00 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-12-14 09:30:00 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
+2022-12-14 09:30:01 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-qcore_q2_3.
+2022-12-14 09:30:01 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-12-14 09:30:02 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-qcore_q2_3.
+2022-12-14 09:30:02 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-12-14 09:30:02 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q2_3/verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
+2022-12-14 09:30:02 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q2_3/verilog/dv/common/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
+2022-12-14 09:30:02 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q2_3/verilog/dv/user_gpio/.user_timer_tb.v.swp): 'utf-8' codec can't decode byte 0xc1 in position 16: invalid start byte
+2022-12-14 09:30:02 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-qcore_q2_3/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
+2022-12-14 09:30:02 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 443 non-compliant file(s) with the SPDX Standard.
+2022-12-14 09:30:02 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-qcore_q2_3/run_regress', 'riscduino-qcore_q2_3/deps/timing-scripts/timing.mk', 'riscduino-qcore_q2_3/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/caravel_spef_mapping.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/common.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/f.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/s.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/env/t.tcl', 'riscduino-qcore_q2_3/deps/timing-scripts/scripts/compare_reports.py', 'riscduino-qcore_q2_3/deps/timing-scripts/scripts/generate_spef_mapping.py', 'riscduino-qcore_q2_3/deps/timing-scripts/scripts/get_macros.py', 'riscduino-qcore_q2_3/deps/timing-scripts/scripts/pdk_helpers.py']
+2022-12-14 09:30:02 - [INFO] - For the full SPDX compliance report check: riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/spdx_compliance_report.log
+2022-12-14 09:30:02 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
+2022-12-14 09:30:02 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-12-14 09:30:02 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
+2022-12-14 09:30:02 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-12-14 09:30:04 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-12-14 09:30:04 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
+2022-12-14 09:30:04 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-12-14 09:30:04 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
+2022-12-14 09:30:12 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-12-14 09:30:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-12-14 09:30:12 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-12-14 09:30:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (21 instances). 
+2022-12-14 09:30:12 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-12-14 09:30:12 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-12-14 09:30:12 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-12-14 09:30:12 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-12-14 09:30:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-12-14 09:30:12 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-12-14 09:30:12 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
+2022-12-14 09:30:12 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'riscduino-qcore_q2_3/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
+2022-12-14 09:30:14 - [INFO] - GPIO-DEFINES report path: riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/gpio_defines.report
+2022-12-14 09:30:14 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
+2022-12-14 09:30:14 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
+2022-12-14 09:33:50 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper.xor.gds
+2022-12-14 09:33:50 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-12-14 09:33:50 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
+2022-12-14 10:16:01 - [INFO] - 0 DRC violations
+2022-12-14 10:16:01 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:16:01 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
+2022-12-14 10:16:01 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-14 10:16:01 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-qcore_q2_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_feol_check.xml -rd feol=true >& riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/klayout_feol_check.log
+2022-12-14 10:19:08 - [INFO] - No DRC Violations found
+2022-12-14 10:19:08 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:19:08 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
+2022-12-14 10:19:08 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-14 10:19:08 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-qcore_q2_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_beol_check.xml -rd beol=true >& riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/klayout_beol_check.log
+2022-12-14 10:42:17 - [INFO] - No DRC Violations found
+2022-12-14 10:42:17 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:42:17 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
+2022-12-14 10:42:17 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-14 10:42:17 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-qcore_q2_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/klayout_offgrid_check.log
+2022-12-14 10:46:52 - [INFO] - No DRC Violations found
+2022-12-14 10:46:52 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:46:52 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
+2022-12-14 10:46:52 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-14 10:46:52 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=riscduino-qcore_q2_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_met_min_ca_density_check.xml >& riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/klayout_met_min_ca_density_check.log
+2022-12-14 10:48:41 - [INFO] - No DRC Violations found
+2022-12-14 10:48:41 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:48:41 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
+2022-12-14 10:48:41 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-14 10:48:41 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=riscduino-qcore_q2_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
+2022-12-14 10:49:21 - [INFO] - No DRC Violations found
+2022-12-14 10:49:21 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:49:21 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
+2022-12-14 10:49:21 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-14 10:49:21 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=riscduino-qcore_q2_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper_no_zero_areas.gds >& riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs/klayout_zeroarea_check.log
+2022-12-14 10:49:42 - [INFO] - No DRC Violations found
+2022-12-14 10:49:42 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-14 10:49:42 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/logs'
+2022-12-14 10:49:42 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..072babf
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,443 @@
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+/root/riscduino-qcore_q2_3/verilog/rtl/qspim/openlane/qspim_top/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/qspim/openlane/qspim_top/interactive.tcl
+/root/riscduino-qcore_q2_3/verilog/rtl/qspim/sdc/qspim_top.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/qspim/tb/run_iverilog
+/root/riscduino-qcore_q2_3/verilog/rtl/rtc/openlane/rtc_top/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/rtc/verilog/dv/user_rtc/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/rtc/verilog/dv/user_rtc/pli_rtc.c
+/root/riscduino-qcore_q2_3/verilog/rtl/rtc/verilog/rtl/lib/ctech_cells.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sar_adc/ACMP.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sar_adc/ACMP_HVL.v
+/root/riscduino-qcore_q2_3/verilog/rtl/sar_adc/DAC_8BIT.v
+/root/riscduino-qcore_q2_3/verilog/rtl/sar_adc/SAR.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sar_adc/sar_adc.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-qcore_q2_3/verilog/rtl/sspim/src/filelist_spi.f
+/root/riscduino-qcore_q2_3/verilog/rtl/sspim/src/sspim_cfg.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sspim/src/sspim_clkgen.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sspim/src/sspim_ctl.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/sspim/src/sspim_if.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/timer/src/timer.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/uart2wb/src/run_verilog
+/root/riscduino-qcore_q2_3/verilog/rtl/uart2wb/src/uart_auto_det.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/uart2wb/src/uart_msg_handler.v
+/root/riscduino-qcore_q2_3/verilog/rtl/usb1_host/src/filelist.f
+/root/riscduino-qcore_q2_3/verilog/rtl/ws281x/src/ws281x_driver.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/run_iverilog
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/openlane/ycr2c/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/drc_exclude.cells
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/pdn_cfg.tcl
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/openlane/ycr_core/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/openlane/ycr_intf/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/iverilog_vpi/system.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/coremark/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/coremark/core_portme.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/coremark/core_portme.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/dhry.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/dhry_1.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/dhry_2.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/hello/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/hello/hello.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/isr_sample/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/isr_sample/isr_sample.S
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/isr_sample/timer.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/aw_test_macros.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/compliance_io.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/compliance_test.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/riscv_test.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/riscv_test_macros.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/test_macros.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/Makefile
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/riscv_test.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/rv32_tests.inc
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/test_macros.h
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/verilator_wrap/ycr_ahb_wrapper.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/verilator_wrap/ycr_axi_wrapper.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/sim/verilator_wrap/ycr_wb_wrapper.c
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/core.files
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/wb_top.files
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/cache/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/cache/src/core/ycr_cache_defs.svh
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/cache/src/model/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/includes/ycr_cache_defs.svh
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/synth/base.sdc
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/synth/scripts/libtrim.pl
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ahb_tb.files
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/axi_tb.files
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/uprj_netlists.v
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/wb_tb.files
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_ahb.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_axi.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_wb.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_ahb.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_axi.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_runtests.sv
+/root/riscduino-qcore_q2_3/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_wb.sv
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..4056146
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.340
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..e5e3fd2
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,753 @@
+Reading file /root/riscduino-qcore_q2_3/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "ycr4_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+Reading "bus_rep_west".
+    5000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 116010538): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 116011242): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 116012202): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116504448): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116508224): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116512416): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116517216): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 116519264): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116698706): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116702482): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116706674): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116713138): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 116715314): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116955764): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116959540): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116963732): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116970196): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 116972372): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "peri_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "bus_rep_east".
+    5000 uses
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__dlclkp_2".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "bus_rep_south".
+    5000 uses
+Reading "bus_rep_north".
+    5000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+Writing layout file: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/mpw_precheck/132729aa-1cc6-495f-8a0a-32315c17d942/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.150s  Memory: 524.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/gpio_defines.report b/mpw_precheck/outputs/reports/gpio_defines.report
new file mode 100644
index 0000000..a5b0eaf
--- /dev/null
+++ b/mpw_precheck/outputs/reports/gpio_defines.report
@@ -0,0 +1,33 @@
+USER_CONFIG_GPIO_5_INIT    13'h1800
+USER_CONFIG_GPIO_6_INIT    13'h1800
+USER_CONFIG_GPIO_7_INIT    13'h1800
+USER_CONFIG_GPIO_8_INIT    13'h1800
+USER_CONFIG_GPIO_9_INIT    13'h1800
+USER_CONFIG_GPIO_10_INIT   13'h1800
+USER_CONFIG_GPIO_11_INIT   13'h1800
+USER_CONFIG_GPIO_12_INIT   13'h1800
+USER_CONFIG_GPIO_13_INIT   13'h1800
+USER_CONFIG_GPIO_14_INIT   13'h1800
+USER_CONFIG_GPIO_15_INIT   13'h1800
+USER_CONFIG_GPIO_16_INIT   13'h1800
+USER_CONFIG_GPIO_17_INIT   13'h1800
+USER_CONFIG_GPIO_18_INIT   13'h1800
+USER_CONFIG_GPIO_19_INIT   13'h1800
+USER_CONFIG_GPIO_20_INIT   13'h1800
+USER_CONFIG_GPIO_21_INIT   13'h1800
+USER_CONFIG_GPIO_22_INIT   13'h1800
+USER_CONFIG_GPIO_23_INIT   13'h1800
+USER_CONFIG_GPIO_24_INIT   13'h1800
+USER_CONFIG_GPIO_25_INIT   13'h1800
+USER_CONFIG_GPIO_26_INIT   13'h1800
+USER_CONFIG_GPIO_27_INIT   13'h1800
+USER_CONFIG_GPIO_28_INIT   13'h1800
+USER_CONFIG_GPIO_29_INIT   13'h1800
+USER_CONFIG_GPIO_30_INIT   13'h1800
+USER_CONFIG_GPIO_31_INIT   13'h1800
+USER_CONFIG_GPIO_32_INIT   13'h1800
+USER_CONFIG_GPIO_33_INIT   13'h1800
+USER_CONFIG_GPIO_34_INIT   13'h1800
+USER_CONFIG_GPIO_35_INIT   13'h1800
+USER_CONFIG_GPIO_36_INIT   13'h1800
+USER_CONFIG_GPIO_37_INIT   13'h1800
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..71b30a8
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..bd9f536
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/riscduino-qcore_q2_3/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..3a6491d
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,11356 @@
+module user_project_wrapper (user_clock2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    vssa2,
+    vdda2,
+    vssa1,
+    vdda1,
+    vssd2,
+    vccd2,
+    vssd1,
+    vccd1,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ input vssa2;
+ input vdda2;
+ input vssa1;
+ input vdda1;
+ input vssd2;
+ input vccd2;
+ input vssd1;
+ input vccd1;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire \buf_out_north[0] ;
+ wire \buf_out_north[10] ;
+ wire \buf_out_north[11] ;
+ wire \buf_out_north[12] ;
+ wire \buf_out_north[13] ;
+ wire \buf_out_north[14] ;
+ wire \buf_out_north[15] ;
+ wire \buf_out_north[16] ;
+ wire \buf_out_north[17] ;
+ wire \buf_out_north[18] ;
+ wire \buf_out_north[19] ;
+ wire \buf_out_north[1] ;
+ wire \buf_out_north[20] ;
+ wire \buf_out_north[21] ;
+ wire \buf_out_north[22] ;
+ wire \buf_out_north[23] ;
+ wire \buf_out_north[24] ;
+ wire \buf_out_north[25] ;
+ wire \buf_out_north[26] ;
+ wire \buf_out_north[27] ;
+ wire \buf_out_north[28] ;
+ wire \buf_out_north[29] ;
+ wire \buf_out_north[2] ;
+ wire \buf_out_north[30] ;
+ wire \buf_out_north[31] ;
+ wire \buf_out_north[32] ;
+ wire \buf_out_north[33] ;
+ wire \buf_out_north[34] ;
+ wire \buf_out_north[35] ;
+ wire \buf_out_north[36] ;
+ wire \buf_out_north[37] ;
+ wire \buf_out_north[38] ;
+ wire \buf_out_north[39] ;
+ wire \buf_out_north[3] ;
+ wire \buf_out_north[40] ;
+ wire \buf_out_north[41] ;
+ wire \buf_out_north[4] ;
+ wire \buf_out_north[5] ;
+ wire \buf_out_north[6] ;
+ wire \buf_out_north[7] ;
+ wire \buf_out_north[8] ;
+ wire \buf_out_north[9] ;
+ wire \cfg_ccska_aes_rp[0] ;
+ wire \cfg_ccska_aes_rp[1] ;
+ wire \cfg_ccska_aes_rp[2] ;
+ wire \cfg_ccska_aes_rp[3] ;
+ wire \cfg_ccska_fpu_rp[0] ;
+ wire \cfg_ccska_fpu_rp[1] ;
+ wire \cfg_ccska_fpu_rp[2] ;
+ wire \cfg_ccska_fpu_rp[3] ;
+ wire \cfg_clk_skew_ctrl1[0] ;
+ wire \cfg_clk_skew_ctrl1[10] ;
+ wire \cfg_clk_skew_ctrl1[11] ;
+ wire \cfg_clk_skew_ctrl1[12] ;
+ wire \cfg_clk_skew_ctrl1[13] ;
+ wire \cfg_clk_skew_ctrl1[14] ;
+ wire \cfg_clk_skew_ctrl1[15] ;
+ wire \cfg_clk_skew_ctrl1[16] ;
+ wire \cfg_clk_skew_ctrl1[17] ;
+ wire \cfg_clk_skew_ctrl1[18] ;
+ wire \cfg_clk_skew_ctrl1[19] ;
+ wire \cfg_clk_skew_ctrl1[1] ;
+ wire \cfg_clk_skew_ctrl1[20] ;
+ wire \cfg_clk_skew_ctrl1[21] ;
+ wire \cfg_clk_skew_ctrl1[22] ;
+ wire \cfg_clk_skew_ctrl1[23] ;
+ wire \cfg_clk_skew_ctrl1[24] ;
+ wire \cfg_clk_skew_ctrl1[25] ;
+ wire \cfg_clk_skew_ctrl1[26] ;
+ wire \cfg_clk_skew_ctrl1[27] ;
+ wire \cfg_clk_skew_ctrl1[28] ;
+ wire \cfg_clk_skew_ctrl1[29] ;
+ wire \cfg_clk_skew_ctrl1[2] ;
+ wire \cfg_clk_skew_ctrl1[30] ;
+ wire \cfg_clk_skew_ctrl1[31] ;
+ wire \cfg_clk_skew_ctrl1[3] ;
+ wire \cfg_clk_skew_ctrl1[4] ;
+ wire \cfg_clk_skew_ctrl1[5] ;
+ wire \cfg_clk_skew_ctrl1[6] ;
+ wire \cfg_clk_skew_ctrl1[7] ;
+ wire \cfg_clk_skew_ctrl1[8] ;
+ wire \cfg_clk_skew_ctrl1[9] ;
+ wire \cfg_clk_skew_ctrl2[0] ;
+ wire \cfg_clk_skew_ctrl2[10] ;
+ wire \cfg_clk_skew_ctrl2[11] ;
+ wire \cfg_clk_skew_ctrl2[12] ;
+ wire \cfg_clk_skew_ctrl2[13] ;
+ wire \cfg_clk_skew_ctrl2[14] ;
+ wire \cfg_clk_skew_ctrl2[15] ;
+ wire \cfg_clk_skew_ctrl2[16] ;
+ wire \cfg_clk_skew_ctrl2[17] ;
+ wire \cfg_clk_skew_ctrl2[18] ;
+ wire \cfg_clk_skew_ctrl2[19] ;
+ wire \cfg_clk_skew_ctrl2[1] ;
+ wire \cfg_clk_skew_ctrl2[20] ;
+ wire \cfg_clk_skew_ctrl2[21] ;
+ wire \cfg_clk_skew_ctrl2[22] ;
+ wire \cfg_clk_skew_ctrl2[23] ;
+ wire \cfg_clk_skew_ctrl2[24] ;
+ wire \cfg_clk_skew_ctrl2[25] ;
+ wire \cfg_clk_skew_ctrl2[26] ;
+ wire \cfg_clk_skew_ctrl2[27] ;
+ wire \cfg_clk_skew_ctrl2[28] ;
+ wire \cfg_clk_skew_ctrl2[29] ;
+ wire \cfg_clk_skew_ctrl2[2] ;
+ wire \cfg_clk_skew_ctrl2[30] ;
+ wire \cfg_clk_skew_ctrl2[31] ;
+ wire \cfg_clk_skew_ctrl2[3] ;
+ wire \cfg_clk_skew_ctrl2[4] ;
+ wire \cfg_clk_skew_ctrl2[5] ;
+ wire \cfg_clk_skew_ctrl2[6] ;
+ wire \cfg_clk_skew_ctrl2[7] ;
+ wire \cfg_clk_skew_ctrl2[8] ;
+ wire \cfg_clk_skew_ctrl2[9] ;
+ wire \cfg_dac0_mux_sel[0] ;
+ wire \cfg_dac0_mux_sel[1] ;
+ wire \cfg_dac0_mux_sel[2] ;
+ wire \cfg_dac0_mux_sel[3] ;
+ wire \cfg_dac0_mux_sel[4] ;
+ wire \cfg_dac0_mux_sel[5] ;
+ wire \cfg_dac0_mux_sel[6] ;
+ wire \cfg_dac0_mux_sel[7] ;
+ wire \cfg_dac1_mux_sel[0] ;
+ wire \cfg_dac1_mux_sel[1] ;
+ wire \cfg_dac1_mux_sel[2] ;
+ wire \cfg_dac1_mux_sel[3] ;
+ wire \cfg_dac1_mux_sel[4] ;
+ wire \cfg_dac1_mux_sel[5] ;
+ wire \cfg_dac1_mux_sel[6] ;
+ wire \cfg_dac1_mux_sel[7] ;
+ wire \cfg_dac2_mux_sel[0] ;
+ wire \cfg_dac2_mux_sel[1] ;
+ wire \cfg_dac2_mux_sel[2] ;
+ wire \cfg_dac2_mux_sel[3] ;
+ wire \cfg_dac2_mux_sel[4] ;
+ wire \cfg_dac2_mux_sel[5] ;
+ wire \cfg_dac2_mux_sel[6] ;
+ wire \cfg_dac2_mux_sel[7] ;
+ wire \cfg_dac3_mux_sel[0] ;
+ wire \cfg_dac3_mux_sel[1] ;
+ wire \cfg_dac3_mux_sel[2] ;
+ wire \cfg_dac3_mux_sel[3] ;
+ wire \cfg_dac3_mux_sel[4] ;
+ wire \cfg_dac3_mux_sel[5] ;
+ wire \cfg_dac3_mux_sel[6] ;
+ wire \cfg_dac3_mux_sel[7] ;
+ wire \cfg_dc_trim[0] ;
+ wire \cfg_dc_trim[10] ;
+ wire \cfg_dc_trim[11] ;
+ wire \cfg_dc_trim[12] ;
+ wire \cfg_dc_trim[13] ;
+ wire \cfg_dc_trim[14] ;
+ wire \cfg_dc_trim[15] ;
+ wire \cfg_dc_trim[16] ;
+ wire \cfg_dc_trim[17] ;
+ wire \cfg_dc_trim[18] ;
+ wire \cfg_dc_trim[19] ;
+ wire \cfg_dc_trim[1] ;
+ wire \cfg_dc_trim[20] ;
+ wire \cfg_dc_trim[21] ;
+ wire \cfg_dc_trim[22] ;
+ wire \cfg_dc_trim[23] ;
+ wire \cfg_dc_trim[24] ;
+ wire \cfg_dc_trim[25] ;
+ wire \cfg_dc_trim[2] ;
+ wire \cfg_dc_trim[3] ;
+ wire \cfg_dc_trim[4] ;
+ wire \cfg_dc_trim[5] ;
+ wire \cfg_dc_trim[6] ;
+ wire \cfg_dc_trim[7] ;
+ wire \cfg_dc_trim[8] ;
+ wire \cfg_dc_trim[9] ;
+ wire cfg_dco_mode;
+ wire cfg_pll_enb;
+ wire \cfg_pll_fed_div[0] ;
+ wire \cfg_pll_fed_div[1] ;
+ wire \cfg_pll_fed_div[2] ;
+ wire \cfg_pll_fed_div[3] ;
+ wire \cfg_pll_fed_div[4] ;
+ wire \cfg_riscv_ctrl[0] ;
+ wire \cfg_riscv_ctrl[10] ;
+ wire \cfg_riscv_ctrl[11] ;
+ wire \cfg_riscv_ctrl[12] ;
+ wire \cfg_riscv_ctrl[13] ;
+ wire \cfg_riscv_ctrl[14] ;
+ wire \cfg_riscv_ctrl[15] ;
+ wire \cfg_riscv_ctrl[1] ;
+ wire \cfg_riscv_ctrl[2] ;
+ wire \cfg_riscv_ctrl[3] ;
+ wire \cfg_riscv_ctrl[4] ;
+ wire \cfg_riscv_ctrl[5] ;
+ wire \cfg_riscv_ctrl[6] ;
+ wire \cfg_riscv_ctrl[7] ;
+ wire \cfg_riscv_ctrl[8] ;
+ wire \cfg_riscv_ctrl[9] ;
+ wire cfg_strap_pad_ctrl;
+ wire cfg_strap_pad_ctrl_rp;
+ wire \cfg_wcska_peri_rp[0] ;
+ wire \cfg_wcska_peri_rp[1] ;
+ wire \cfg_wcska_peri_rp[2] ;
+ wire \cfg_wcska_peri_rp[3] ;
+ wire \cfg_wcska_pinmux_rp[0] ;
+ wire \cfg_wcska_pinmux_rp[1] ;
+ wire \cfg_wcska_pinmux_rp[2] ;
+ wire \cfg_wcska_pinmux_rp[3] ;
+ wire \cfg_wcska_qspi_co_rp[0] ;
+ wire \cfg_wcska_qspi_co_rp[1] ;
+ wire \cfg_wcska_qspi_co_rp[2] ;
+ wire \cfg_wcska_qspi_co_rp[3] ;
+ wire \cfg_wcska_qspi_rp[0] ;
+ wire \cfg_wcska_qspi_rp[1] ;
+ wire \cfg_wcska_qspi_rp[2] ;
+ wire \cfg_wcska_qspi_rp[3] ;
+ wire \cfg_wcska_uart_rp[0] ;
+ wire \cfg_wcska_uart_rp[1] ;
+ wire \cfg_wcska_uart_rp[2] ;
+ wire \cfg_wcska_uart_rp[3] ;
+ wire \ch_out_east[11] ;
+ wire \ch_out_east[14] ;
+ wire \ch_out_east[17] ;
+ wire \ch_out_east[20] ;
+ wire \ch_out_east[23] ;
+ wire \ch_out_east[26] ;
+ wire \ch_out_east[29] ;
+ wire \ch_out_east[2] ;
+ wire \ch_out_east[32] ;
+ wire \ch_out_east[35] ;
+ wire \ch_out_east[38] ;
+ wire \ch_out_east[41] ;
+ wire \ch_out_east[44] ;
+ wire \ch_out_east[5] ;
+ wire \ch_out_east[8] ;
+ wire \ch_out_north[11] ;
+ wire \ch_out_north[14] ;
+ wire \ch_out_north[17] ;
+ wire \ch_out_north[20] ;
+ wire \ch_out_north[23] ;
+ wire \ch_out_north[26] ;
+ wire \ch_out_north[2] ;
+ wire \ch_out_north[5] ;
+ wire \ch_out_north[8] ;
+ wire \ch_out_south[0] ;
+ wire \ch_out_south[100] ;
+ wire \ch_out_south[101] ;
+ wire \ch_out_south[103] ;
+ wire \ch_out_south[104] ;
+ wire \ch_out_south[106] ;
+ wire \ch_out_south[108] ;
+ wire \ch_out_south[10] ;
+ wire \ch_out_south[110] ;
+ wire \ch_out_south[112] ;
+ wire \ch_out_south[114] ;
+ wire \ch_out_south[116] ;
+ wire \ch_out_south[118] ;
+ wire \ch_out_south[11] ;
+ wire \ch_out_south[120] ;
+ wire \ch_out_south[122] ;
+ wire \ch_out_south[124] ;
+ wire \ch_out_south[126] ;
+ wire \ch_out_south[128] ;
+ wire \ch_out_south[130] ;
+ wire \ch_out_south[132] ;
+ wire \ch_out_south[134] ;
+ wire \ch_out_south[136] ;
+ wire \ch_out_south[138] ;
+ wire \ch_out_south[13] ;
+ wire \ch_out_south[140] ;
+ wire \ch_out_south[14] ;
+ wire \ch_out_south[15] ;
+ wire \ch_out_south[17] ;
+ wire \ch_out_south[18] ;
+ wire \ch_out_south[19] ;
+ wire \ch_out_south[1] ;
+ wire \ch_out_south[21] ;
+ wire \ch_out_south[22] ;
+ wire \ch_out_south[23] ;
+ wire \ch_out_south[252] ;
+ wire \ch_out_south[25] ;
+ wire \ch_out_south[26] ;
+ wire \ch_out_south[28] ;
+ wire \ch_out_south[29] ;
+ wire \ch_out_south[31] ;
+ wire \ch_out_south[32] ;
+ wire \ch_out_south[34] ;
+ wire \ch_out_south[35] ;
+ wire \ch_out_south[37] ;
+ wire \ch_out_south[38] ;
+ wire \ch_out_south[3] ;
+ wire \ch_out_south[40] ;
+ wire \ch_out_south[41] ;
+ wire \ch_out_south[43] ;
+ wire \ch_out_south[44] ;
+ wire \ch_out_south[46] ;
+ wire \ch_out_south[47] ;
+ wire \ch_out_south[49] ;
+ wire \ch_out_south[4] ;
+ wire \ch_out_south[50] ;
+ wire \ch_out_south[52] ;
+ wire \ch_out_south[53] ;
+ wire \ch_out_south[55] ;
+ wire \ch_out_south[56] ;
+ wire \ch_out_south[58] ;
+ wire \ch_out_south[59] ;
+ wire \ch_out_south[5] ;
+ wire \ch_out_south[61] ;
+ wire \ch_out_south[62] ;
+ wire \ch_out_south[64] ;
+ wire \ch_out_south[65] ;
+ wire \ch_out_south[67] ;
+ wire \ch_out_south[68] ;
+ wire \ch_out_south[6] ;
+ wire \ch_out_south[70] ;
+ wire \ch_out_south[71] ;
+ wire \ch_out_south[73] ;
+ wire \ch_out_south[74] ;
+ wire \ch_out_south[76] ;
+ wire \ch_out_south[77] ;
+ wire \ch_out_south[79] ;
+ wire \ch_out_south[7] ;
+ wire \ch_out_south[80] ;
+ wire \ch_out_south[82] ;
+ wire \ch_out_south[83] ;
+ wire \ch_out_south[85] ;
+ wire \ch_out_south[86] ;
+ wire \ch_out_south[88] ;
+ wire \ch_out_south[89] ;
+ wire \ch_out_south[91] ;
+ wire \ch_out_south[92] ;
+ wire \ch_out_south[94] ;
+ wire \ch_out_south[95] ;
+ wire \ch_out_south[97] ;
+ wire \ch_out_south[98] ;
+ wire \ch_out_south[9] ;
+ wire \ch_out_west[0] ;
+ wire \ch_out_west[12] ;
+ wire \ch_out_west[15] ;
+ wire \ch_out_west[18] ;
+ wire \ch_out_west[21] ;
+ wire \ch_out_west[24] ;
+ wire \ch_out_west[27] ;
+ wire \ch_out_west[30] ;
+ wire \ch_out_west[33] ;
+ wire \ch_out_west[36] ;
+ wire \ch_out_west[39] ;
+ wire \ch_out_west[3] ;
+ wire \ch_out_west[6] ;
+ wire \ch_out_west[9] ;
+ wire cpu_clk;
+ wire \cpu_clk_rp[2] ;
+ wire e_reset_n;
+ wire e_reset_n_rp;
+ wire i2c_rst_n;
+ wire i2cm_clk_i;
+ wire i2cm_clk_o;
+ wire i2cm_clk_oen;
+ wire i2cm_data_i;
+ wire i2cm_data_o;
+ wire i2cm_data_oen;
+ wire i2cm_intr_o;
+ wire \io_oeb_int[0] ;
+ wire \io_oeb_int[10] ;
+ wire \io_oeb_int[11] ;
+ wire \io_oeb_int[12] ;
+ wire \io_oeb_int[13] ;
+ wire \io_oeb_int[14] ;
+ wire \io_oeb_int[15] ;
+ wire \io_oeb_int[16] ;
+ wire \io_oeb_int[17] ;
+ wire \io_oeb_int[18] ;
+ wire \io_oeb_int[19] ;
+ wire \io_oeb_int[1] ;
+ wire \io_oeb_int[20] ;
+ wire \io_oeb_int[21] ;
+ wire \io_oeb_int[22] ;
+ wire \io_oeb_int[23] ;
+ wire \io_oeb_int[24] ;
+ wire \io_oeb_int[25] ;
+ wire \io_oeb_int[26] ;
+ wire \io_oeb_int[27] ;
+ wire \io_oeb_int[28] ;
+ wire \io_oeb_int[29] ;
+ wire \io_oeb_int[2] ;
+ wire \io_oeb_int[30] ;
+ wire \io_oeb_int[31] ;
+ wire \io_oeb_int[32] ;
+ wire \io_oeb_int[33] ;
+ wire \io_oeb_int[34] ;
+ wire \io_oeb_int[35] ;
+ wire \io_oeb_int[36] ;
+ wire \io_oeb_int[37] ;
+ wire \io_oeb_int[3] ;
+ wire \io_oeb_int[4] ;
+ wire \io_oeb_int[5] ;
+ wire \io_oeb_int[6] ;
+ wire \io_oeb_int[7] ;
+ wire \io_oeb_int[8] ;
+ wire \io_oeb_int[9] ;
+ wire \io_out_int[0] ;
+ wire \io_out_int[10] ;
+ wire \io_out_int[11] ;
+ wire \io_out_int[12] ;
+ wire \io_out_int[13] ;
+ wire \io_out_int[14] ;
+ wire \io_out_int[15] ;
+ wire \io_out_int[16] ;
+ wire \io_out_int[17] ;
+ wire \io_out_int[18] ;
+ wire \io_out_int[19] ;
+ wire \io_out_int[1] ;
+ wire \io_out_int[20] ;
+ wire \io_out_int[21] ;
+ wire \io_out_int[22] ;
+ wire \io_out_int[23] ;
+ wire \io_out_int[24] ;
+ wire \io_out_int[25] ;
+ wire \io_out_int[26] ;
+ wire \io_out_int[27] ;
+ wire \io_out_int[28] ;
+ wire \io_out_int[29] ;
+ wire \io_out_int[2] ;
+ wire \io_out_int[30] ;
+ wire \io_out_int[31] ;
+ wire \io_out_int[32] ;
+ wire \io_out_int[33] ;
+ wire \io_out_int[34] ;
+ wire \io_out_int[35] ;
+ wire \io_out_int[36] ;
+ wire \io_out_int[37] ;
+ wire \io_out_int[3] ;
+ wire \io_out_int[4] ;
+ wire \io_out_int[5] ;
+ wire \io_out_int[6] ;
+ wire \io_out_int[7] ;
+ wire \io_out_int[8] ;
+ wire \io_out_int[9] ;
+ wire ir_intr;
+ wire ir_rx;
+ wire ir_tx;
+ wire \irq_lines[0] ;
+ wire \irq_lines[10] ;
+ wire \irq_lines[11] ;
+ wire \irq_lines[12] ;
+ wire \irq_lines[13] ;
+ wire \irq_lines[14] ;
+ wire \irq_lines[15] ;
+ wire \irq_lines[16] ;
+ wire \irq_lines[17] ;
+ wire \irq_lines[18] ;
+ wire \irq_lines[19] ;
+ wire \irq_lines[1] ;
+ wire \irq_lines[20] ;
+ wire \irq_lines[21] ;
+ wire \irq_lines[22] ;
+ wire \irq_lines[23] ;
+ wire \irq_lines[24] ;
+ wire \irq_lines[25] ;
+ wire \irq_lines[26] ;
+ wire \irq_lines[27] ;
+ wire \irq_lines[28] ;
+ wire \irq_lines[29] ;
+ wire \irq_lines[2] ;
+ wire \irq_lines[30] ;
+ wire \irq_lines[31] ;
+ wire \irq_lines[3] ;
+ wire \irq_lines[4] ;
+ wire \irq_lines[5] ;
+ wire \irq_lines[6] ;
+ wire \irq_lines[7] ;
+ wire \irq_lines[8] ;
+ wire \irq_lines[9] ;
+ wire p_reset_n;
+ wire p_reset_n_rp;
+ wire \pinmux_debug[0] ;
+ wire \pinmux_debug[10] ;
+ wire \pinmux_debug[11] ;
+ wire \pinmux_debug[12] ;
+ wire \pinmux_debug[13] ;
+ wire \pinmux_debug[14] ;
+ wire \pinmux_debug[15] ;
+ wire \pinmux_debug[16] ;
+ wire \pinmux_debug[17] ;
+ wire \pinmux_debug[18] ;
+ wire \pinmux_debug[19] ;
+ wire \pinmux_debug[1] ;
+ wire \pinmux_debug[20] ;
+ wire \pinmux_debug[21] ;
+ wire \pinmux_debug[22] ;
+ wire \pinmux_debug[23] ;
+ wire \pinmux_debug[24] ;
+ wire \pinmux_debug[25] ;
+ wire \pinmux_debug[26] ;
+ wire \pinmux_debug[27] ;
+ wire \pinmux_debug[28] ;
+ wire \pinmux_debug[29] ;
+ wire \pinmux_debug[2] ;
+ wire \pinmux_debug[30] ;
+ wire \pinmux_debug[31] ;
+ wire \pinmux_debug[3] ;
+ wire \pinmux_debug[4] ;
+ wire \pinmux_debug[5] ;
+ wire \pinmux_debug[6] ;
+ wire \pinmux_debug[7] ;
+ wire \pinmux_debug[8] ;
+ wire \pinmux_debug[9] ;
+ wire \pll_clk_out[0] ;
+ wire \pll_clk_out[1] ;
+ wire pll_ref_clk;
+ wire pulse1m_mclk;
+ wire qspim_rst_n;
+ wire reg_peri_ack;
+ wire \reg_peri_addr[0] ;
+ wire \reg_peri_addr[10] ;
+ wire \reg_peri_addr[1] ;
+ wire \reg_peri_addr[2] ;
+ wire \reg_peri_addr[3] ;
+ wire \reg_peri_addr[4] ;
+ wire \reg_peri_addr[5] ;
+ wire \reg_peri_addr[6] ;
+ wire \reg_peri_addr[7] ;
+ wire \reg_peri_addr[8] ;
+ wire \reg_peri_addr[9] ;
+ wire \reg_peri_be[0] ;
+ wire \reg_peri_be[1] ;
+ wire \reg_peri_be[2] ;
+ wire \reg_peri_be[3] ;
+ wire reg_peri_cs;
+ wire \reg_peri_rdata[0] ;
+ wire \reg_peri_rdata[10] ;
+ wire \reg_peri_rdata[11] ;
+ wire \reg_peri_rdata[12] ;
+ wire \reg_peri_rdata[13] ;
+ wire \reg_peri_rdata[14] ;
+ wire \reg_peri_rdata[15] ;
+ wire \reg_peri_rdata[16] ;
+ wire \reg_peri_rdata[17] ;
+ wire \reg_peri_rdata[18] ;
+ wire \reg_peri_rdata[19] ;
+ wire \reg_peri_rdata[1] ;
+ wire \reg_peri_rdata[20] ;
+ wire \reg_peri_rdata[21] ;
+ wire \reg_peri_rdata[22] ;
+ wire \reg_peri_rdata[23] ;
+ wire \reg_peri_rdata[24] ;
+ wire \reg_peri_rdata[25] ;
+ wire \reg_peri_rdata[26] ;
+ wire \reg_peri_rdata[27] ;
+ wire \reg_peri_rdata[28] ;
+ wire \reg_peri_rdata[29] ;
+ wire \reg_peri_rdata[2] ;
+ wire \reg_peri_rdata[30] ;
+ wire \reg_peri_rdata[31] ;
+ wire \reg_peri_rdata[3] ;
+ wire \reg_peri_rdata[4] ;
+ wire \reg_peri_rdata[5] ;
+ wire \reg_peri_rdata[6] ;
+ wire \reg_peri_rdata[7] ;
+ wire \reg_peri_rdata[8] ;
+ wire \reg_peri_rdata[9] ;
+ wire \reg_peri_wdata[0] ;
+ wire \reg_peri_wdata[10] ;
+ wire \reg_peri_wdata[11] ;
+ wire \reg_peri_wdata[12] ;
+ wire \reg_peri_wdata[13] ;
+ wire \reg_peri_wdata[14] ;
+ wire \reg_peri_wdata[15] ;
+ wire \reg_peri_wdata[16] ;
+ wire \reg_peri_wdata[17] ;
+ wire \reg_peri_wdata[18] ;
+ wire \reg_peri_wdata[19] ;
+ wire \reg_peri_wdata[1] ;
+ wire \reg_peri_wdata[20] ;
+ wire \reg_peri_wdata[21] ;
+ wire \reg_peri_wdata[22] ;
+ wire \reg_peri_wdata[23] ;
+ wire \reg_peri_wdata[24] ;
+ wire \reg_peri_wdata[25] ;
+ wire \reg_peri_wdata[26] ;
+ wire \reg_peri_wdata[27] ;
+ wire \reg_peri_wdata[28] ;
+ wire \reg_peri_wdata[29] ;
+ wire \reg_peri_wdata[2] ;
+ wire \reg_peri_wdata[30] ;
+ wire \reg_peri_wdata[31] ;
+ wire \reg_peri_wdata[3] ;
+ wire \reg_peri_wdata[4] ;
+ wire \reg_peri_wdata[5] ;
+ wire \reg_peri_wdata[6] ;
+ wire \reg_peri_wdata[7] ;
+ wire \reg_peri_wdata[8] ;
+ wire \reg_peri_wdata[9] ;
+ wire reg_peri_wr;
+ wire rtc_intr;
+ wire s_reset_n;
+ wire \sflash_di[0] ;
+ wire \sflash_di[1] ;
+ wire \sflash_di[2] ;
+ wire \sflash_di[3] ;
+ wire \sflash_do[0] ;
+ wire \sflash_do[1] ;
+ wire \sflash_do[2] ;
+ wire \sflash_do[3] ;
+ wire \sflash_oen[0] ;
+ wire \sflash_oen[1] ;
+ wire \sflash_oen[2] ;
+ wire \sflash_oen[3] ;
+ wire sflash_sck;
+ wire soft_irq;
+ wire \spi_csn[0] ;
+ wire \spi_csn[1] ;
+ wire \spi_csn[2] ;
+ wire \spi_csn[3] ;
+ wire \spi_debug[0] ;
+ wire \spi_debug[10] ;
+ wire \spi_debug[11] ;
+ wire \spi_debug[12] ;
+ wire \spi_debug[13] ;
+ wire \spi_debug[14] ;
+ wire \spi_debug[15] ;
+ wire \spi_debug[16] ;
+ wire \spi_debug[17] ;
+ wire \spi_debug[18] ;
+ wire \spi_debug[19] ;
+ wire \spi_debug[1] ;
+ wire \spi_debug[20] ;
+ wire \spi_debug[21] ;
+ wire \spi_debug[22] ;
+ wire \spi_debug[23] ;
+ wire \spi_debug[24] ;
+ wire \spi_debug[25] ;
+ wire \spi_debug[26] ;
+ wire \spi_debug[27] ;
+ wire \spi_debug[28] ;
+ wire \spi_debug[29] ;
+ wire \spi_debug[2] ;
+ wire \spi_debug[30] ;
+ wire \spi_debug[31] ;
+ wire \spi_debug[3] ;
+ wire \spi_debug[4] ;
+ wire \spi_debug[5] ;
+ wire \spi_debug[6] ;
+ wire \spi_debug[7] ;
+ wire \spi_debug[8] ;
+ wire \spi_debug[9] ;
+ wire sspim_rst_n;
+ wire sspim_sck;
+ wire sspim_si;
+ wire sspim_so;
+ wire \sspim_ssn[0] ;
+ wire \sspim_ssn[1] ;
+ wire \sspim_ssn[2] ;
+ wire \sspim_ssn[3] ;
+ wire sspis_sck;
+ wire sspis_si;
+ wire sspis_so;
+ wire sspis_ssn;
+ wire \strap_sticky[0] ;
+ wire \strap_sticky[10] ;
+ wire \strap_sticky[11] ;
+ wire \strap_sticky[12] ;
+ wire \strap_sticky[13] ;
+ wire \strap_sticky[14] ;
+ wire \strap_sticky[15] ;
+ wire \strap_sticky[16] ;
+ wire \strap_sticky[17] ;
+ wire \strap_sticky[18] ;
+ wire \strap_sticky[19] ;
+ wire \strap_sticky[1] ;
+ wire \strap_sticky[20] ;
+ wire \strap_sticky[21] ;
+ wire \strap_sticky[22] ;
+ wire \strap_sticky[23] ;
+ wire \strap_sticky[24] ;
+ wire \strap_sticky[25] ;
+ wire \strap_sticky[26] ;
+ wire \strap_sticky[27] ;
+ wire \strap_sticky[28] ;
+ wire \strap_sticky[29] ;
+ wire \strap_sticky[2] ;
+ wire \strap_sticky[30] ;
+ wire \strap_sticky[31] ;
+ wire \strap_sticky[3] ;
+ wire \strap_sticky[4] ;
+ wire \strap_sticky[5] ;
+ wire \strap_sticky[6] ;
+ wire \strap_sticky[7] ;
+ wire \strap_sticky[8] ;
+ wire \strap_sticky[9] ;
+ wire \strap_sticky_rp[0] ;
+ wire \strap_sticky_rp[10] ;
+ wire \strap_sticky_rp[11] ;
+ wire \strap_sticky_rp[12] ;
+ wire \strap_sticky_rp[13] ;
+ wire \strap_sticky_rp[14] ;
+ wire \strap_sticky_rp[15] ;
+ wire \strap_sticky_rp[16] ;
+ wire \strap_sticky_rp[17] ;
+ wire \strap_sticky_rp[18] ;
+ wire \strap_sticky_rp[19] ;
+ wire \strap_sticky_rp[1] ;
+ wire \strap_sticky_rp[20] ;
+ wire \strap_sticky_rp[21] ;
+ wire \strap_sticky_rp[22] ;
+ wire \strap_sticky_rp[23] ;
+ wire \strap_sticky_rp[24] ;
+ wire \strap_sticky_rp[25] ;
+ wire \strap_sticky_rp[26] ;
+ wire \strap_sticky_rp[27] ;
+ wire \strap_sticky_rp[28] ;
+ wire \strap_sticky_rp[29] ;
+ wire \strap_sticky_rp[2] ;
+ wire \strap_sticky_rp[30] ;
+ wire \strap_sticky_rp[31] ;
+ wire \strap_sticky_rp[3] ;
+ wire \strap_sticky_rp[4] ;
+ wire \strap_sticky_rp[5] ;
+ wire \strap_sticky_rp[6] ;
+ wire \strap_sticky_rp[7] ;
+ wire \strap_sticky_rp[8] ;
+ wire \strap_sticky_rp[9] ;
+ wire \strap_uartm[0] ;
+ wire \strap_uartm[1] ;
+ wire \strap_uartm_rp[0] ;
+ wire \strap_uartm_rp[1] ;
+ wire \system_strap[0] ;
+ wire \system_strap[10] ;
+ wire \system_strap[11] ;
+ wire \system_strap[12] ;
+ wire \system_strap[13] ;
+ wire \system_strap[14] ;
+ wire \system_strap[15] ;
+ wire \system_strap[16] ;
+ wire \system_strap[17] ;
+ wire \system_strap[18] ;
+ wire \system_strap[19] ;
+ wire \system_strap[1] ;
+ wire \system_strap[20] ;
+ wire \system_strap[21] ;
+ wire \system_strap[22] ;
+ wire \system_strap[23] ;
+ wire \system_strap[24] ;
+ wire \system_strap[25] ;
+ wire \system_strap[26] ;
+ wire \system_strap[27] ;
+ wire \system_strap[28] ;
+ wire \system_strap[29] ;
+ wire \system_strap[2] ;
+ wire \system_strap[30] ;
+ wire \system_strap[31] ;
+ wire \system_strap[3] ;
+ wire \system_strap[4] ;
+ wire \system_strap[5] ;
+ wire \system_strap[6] ;
+ wire \system_strap[7] ;
+ wire \system_strap[8] ;
+ wire \system_strap[9] ;
+ wire \system_strap_rp[0] ;
+ wire \system_strap_rp[10] ;
+ wire \system_strap_rp[11] ;
+ wire \system_strap_rp[12] ;
+ wire \system_strap_rp[13] ;
+ wire \system_strap_rp[14] ;
+ wire \system_strap_rp[15] ;
+ wire \system_strap_rp[16] ;
+ wire \system_strap_rp[17] ;
+ wire \system_strap_rp[18] ;
+ wire \system_strap_rp[19] ;
+ wire \system_strap_rp[1] ;
+ wire \system_strap_rp[20] ;
+ wire \system_strap_rp[21] ;
+ wire \system_strap_rp[22] ;
+ wire \system_strap_rp[23] ;
+ wire \system_strap_rp[24] ;
+ wire \system_strap_rp[25] ;
+ wire \system_strap_rp[26] ;
+ wire \system_strap_rp[27] ;
+ wire \system_strap_rp[28] ;
+ wire \system_strap_rp[29] ;
+ wire \system_strap_rp[2] ;
+ wire \system_strap_rp[30] ;
+ wire \system_strap_rp[31] ;
+ wire \system_strap_rp[3] ;
+ wire \system_strap_rp[4] ;
+ wire \system_strap_rp[5] ;
+ wire \system_strap_rp[6] ;
+ wire \system_strap_rp[7] ;
+ wire \system_strap_rp[8] ;
+ wire \system_strap_rp[9] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core2[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core3[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[3] ;
+ wire \u_riscv_top.cfg_dcache_force_flush ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[0] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[1] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[2] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[3] ;
+ wire \u_riscv_top.core0_clk ;
+ wire \u_riscv_top.core0_debug[0] ;
+ wire \u_riscv_top.core0_debug[10] ;
+ wire \u_riscv_top.core0_debug[11] ;
+ wire \u_riscv_top.core0_debug[12] ;
+ wire \u_riscv_top.core0_debug[13] ;
+ wire \u_riscv_top.core0_debug[14] ;
+ wire \u_riscv_top.core0_debug[15] ;
+ wire \u_riscv_top.core0_debug[16] ;
+ wire \u_riscv_top.core0_debug[17] ;
+ wire \u_riscv_top.core0_debug[18] ;
+ wire \u_riscv_top.core0_debug[19] ;
+ wire \u_riscv_top.core0_debug[1] ;
+ wire \u_riscv_top.core0_debug[20] ;
+ wire \u_riscv_top.core0_debug[21] ;
+ wire \u_riscv_top.core0_debug[22] ;
+ wire \u_riscv_top.core0_debug[23] ;
+ wire \u_riscv_top.core0_debug[24] ;
+ wire \u_riscv_top.core0_debug[25] ;
+ wire \u_riscv_top.core0_debug[26] ;
+ wire \u_riscv_top.core0_debug[27] ;
+ wire \u_riscv_top.core0_debug[28] ;
+ wire \u_riscv_top.core0_debug[29] ;
+ wire \u_riscv_top.core0_debug[2] ;
+ wire \u_riscv_top.core0_debug[30] ;
+ wire \u_riscv_top.core0_debug[31] ;
+ wire \u_riscv_top.core0_debug[32] ;
+ wire \u_riscv_top.core0_debug[33] ;
+ wire \u_riscv_top.core0_debug[34] ;
+ wire \u_riscv_top.core0_debug[35] ;
+ wire \u_riscv_top.core0_debug[36] ;
+ wire \u_riscv_top.core0_debug[37] ;
+ wire \u_riscv_top.core0_debug[38] ;
+ wire \u_riscv_top.core0_debug[39] ;
+ wire \u_riscv_top.core0_debug[3] ;
+ wire \u_riscv_top.core0_debug[40] ;
+ wire \u_riscv_top.core0_debug[41] ;
+ wire \u_riscv_top.core0_debug[42] ;
+ wire \u_riscv_top.core0_debug[43] ;
+ wire \u_riscv_top.core0_debug[44] ;
+ wire \u_riscv_top.core0_debug[45] ;
+ wire \u_riscv_top.core0_debug[46] ;
+ wire \u_riscv_top.core0_debug[47] ;
+ wire \u_riscv_top.core0_debug[48] ;
+ wire \u_riscv_top.core0_debug[4] ;
+ wire \u_riscv_top.core0_debug[5] ;
+ wire \u_riscv_top.core0_debug[6] ;
+ wire \u_riscv_top.core0_debug[7] ;
+ wire \u_riscv_top.core0_debug[8] ;
+ wire \u_riscv_top.core0_debug[9] ;
+ wire \u_riscv_top.core0_dmem_addr[0] ;
+ wire \u_riscv_top.core0_dmem_addr[10] ;
+ wire \u_riscv_top.core0_dmem_addr[11] ;
+ wire \u_riscv_top.core0_dmem_addr[12] ;
+ wire \u_riscv_top.core0_dmem_addr[13] ;
+ wire \u_riscv_top.core0_dmem_addr[14] ;
+ wire \u_riscv_top.core0_dmem_addr[15] ;
+ wire \u_riscv_top.core0_dmem_addr[16] ;
+ wire \u_riscv_top.core0_dmem_addr[17] ;
+ wire \u_riscv_top.core0_dmem_addr[18] ;
+ wire \u_riscv_top.core0_dmem_addr[19] ;
+ wire \u_riscv_top.core0_dmem_addr[1] ;
+ wire \u_riscv_top.core0_dmem_addr[20] ;
+ wire \u_riscv_top.core0_dmem_addr[21] ;
+ wire \u_riscv_top.core0_dmem_addr[22] ;
+ wire \u_riscv_top.core0_dmem_addr[23] ;
+ wire \u_riscv_top.core0_dmem_addr[24] ;
+ wire \u_riscv_top.core0_dmem_addr[25] ;
+ wire \u_riscv_top.core0_dmem_addr[26] ;
+ wire \u_riscv_top.core0_dmem_addr[27] ;
+ wire \u_riscv_top.core0_dmem_addr[28] ;
+ wire \u_riscv_top.core0_dmem_addr[29] ;
+ wire \u_riscv_top.core0_dmem_addr[2] ;
+ wire \u_riscv_top.core0_dmem_addr[30] ;
+ wire \u_riscv_top.core0_dmem_addr[31] ;
+ wire \u_riscv_top.core0_dmem_addr[3] ;
+ wire \u_riscv_top.core0_dmem_addr[4] ;
+ wire \u_riscv_top.core0_dmem_addr[5] ;
+ wire \u_riscv_top.core0_dmem_addr[6] ;
+ wire \u_riscv_top.core0_dmem_addr[7] ;
+ wire \u_riscv_top.core0_dmem_addr[8] ;
+ wire \u_riscv_top.core0_dmem_addr[9] ;
+ wire \u_riscv_top.core0_dmem_cmd ;
+ wire \u_riscv_top.core0_dmem_rdata[0] ;
+ wire \u_riscv_top.core0_dmem_rdata[10] ;
+ wire \u_riscv_top.core0_dmem_rdata[11] ;
+ wire \u_riscv_top.core0_dmem_rdata[12] ;
+ wire \u_riscv_top.core0_dmem_rdata[13] ;
+ wire \u_riscv_top.core0_dmem_rdata[14] ;
+ wire \u_riscv_top.core0_dmem_rdata[15] ;
+ wire \u_riscv_top.core0_dmem_rdata[16] ;
+ wire \u_riscv_top.core0_dmem_rdata[17] ;
+ wire \u_riscv_top.core0_dmem_rdata[18] ;
+ wire \u_riscv_top.core0_dmem_rdata[19] ;
+ wire \u_riscv_top.core0_dmem_rdata[1] ;
+ wire \u_riscv_top.core0_dmem_rdata[20] ;
+ wire \u_riscv_top.core0_dmem_rdata[21] ;
+ wire \u_riscv_top.core0_dmem_rdata[22] ;
+ wire \u_riscv_top.core0_dmem_rdata[23] ;
+ wire \u_riscv_top.core0_dmem_rdata[24] ;
+ wire \u_riscv_top.core0_dmem_rdata[25] ;
+ wire \u_riscv_top.core0_dmem_rdata[26] ;
+ wire \u_riscv_top.core0_dmem_rdata[27] ;
+ wire \u_riscv_top.core0_dmem_rdata[28] ;
+ wire \u_riscv_top.core0_dmem_rdata[29] ;
+ wire \u_riscv_top.core0_dmem_rdata[2] ;
+ wire \u_riscv_top.core0_dmem_rdata[30] ;
+ wire \u_riscv_top.core0_dmem_rdata[31] ;
+ wire \u_riscv_top.core0_dmem_rdata[3] ;
+ wire \u_riscv_top.core0_dmem_rdata[4] ;
+ wire \u_riscv_top.core0_dmem_rdata[5] ;
+ wire \u_riscv_top.core0_dmem_rdata[6] ;
+ wire \u_riscv_top.core0_dmem_rdata[7] ;
+ wire \u_riscv_top.core0_dmem_rdata[8] ;
+ wire \u_riscv_top.core0_dmem_rdata[9] ;
+ wire \u_riscv_top.core0_dmem_req ;
+ wire \u_riscv_top.core0_dmem_req_ack ;
+ wire \u_riscv_top.core0_dmem_resp[0] ;
+ wire \u_riscv_top.core0_dmem_resp[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[0] ;
+ wire \u_riscv_top.core0_dmem_wdata[10] ;
+ wire \u_riscv_top.core0_dmem_wdata[11] ;
+ wire \u_riscv_top.core0_dmem_wdata[12] ;
+ wire \u_riscv_top.core0_dmem_wdata[13] ;
+ wire \u_riscv_top.core0_dmem_wdata[14] ;
+ wire \u_riscv_top.core0_dmem_wdata[15] ;
+ wire \u_riscv_top.core0_dmem_wdata[16] ;
+ wire \u_riscv_top.core0_dmem_wdata[17] ;
+ wire \u_riscv_top.core0_dmem_wdata[18] ;
+ wire \u_riscv_top.core0_dmem_wdata[19] ;
+ wire \u_riscv_top.core0_dmem_wdata[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[20] ;
+ wire \u_riscv_top.core0_dmem_wdata[21] ;
+ wire \u_riscv_top.core0_dmem_wdata[22] ;
+ wire \u_riscv_top.core0_dmem_wdata[23] ;
+ wire \u_riscv_top.core0_dmem_wdata[24] ;
+ wire \u_riscv_top.core0_dmem_wdata[25] ;
+ wire \u_riscv_top.core0_dmem_wdata[26] ;
+ wire \u_riscv_top.core0_dmem_wdata[27] ;
+ wire \u_riscv_top.core0_dmem_wdata[28] ;
+ wire \u_riscv_top.core0_dmem_wdata[29] ;
+ wire \u_riscv_top.core0_dmem_wdata[2] ;
+ wire \u_riscv_top.core0_dmem_wdata[30] ;
+ wire \u_riscv_top.core0_dmem_wdata[31] ;
+ wire \u_riscv_top.core0_dmem_wdata[3] ;
+ wire \u_riscv_top.core0_dmem_wdata[4] ;
+ wire \u_riscv_top.core0_dmem_wdata[5] ;
+ wire \u_riscv_top.core0_dmem_wdata[6] ;
+ wire \u_riscv_top.core0_dmem_wdata[7] ;
+ wire \u_riscv_top.core0_dmem_wdata[8] ;
+ wire \u_riscv_top.core0_dmem_wdata[9] ;
+ wire \u_riscv_top.core0_dmem_width[0] ;
+ wire \u_riscv_top.core0_dmem_width[1] ;
+ wire \u_riscv_top.core0_imem_addr[0] ;
+ wire \u_riscv_top.core0_imem_addr[10] ;
+ wire \u_riscv_top.core0_imem_addr[11] ;
+ wire \u_riscv_top.core0_imem_addr[12] ;
+ wire \u_riscv_top.core0_imem_addr[13] ;
+ wire \u_riscv_top.core0_imem_addr[14] ;
+ wire \u_riscv_top.core0_imem_addr[15] ;
+ wire \u_riscv_top.core0_imem_addr[16] ;
+ wire \u_riscv_top.core0_imem_addr[17] ;
+ wire \u_riscv_top.core0_imem_addr[18] ;
+ wire \u_riscv_top.core0_imem_addr[19] ;
+ wire \u_riscv_top.core0_imem_addr[1] ;
+ wire \u_riscv_top.core0_imem_addr[20] ;
+ wire \u_riscv_top.core0_imem_addr[21] ;
+ wire \u_riscv_top.core0_imem_addr[22] ;
+ wire \u_riscv_top.core0_imem_addr[23] ;
+ wire \u_riscv_top.core0_imem_addr[24] ;
+ wire \u_riscv_top.core0_imem_addr[25] ;
+ wire \u_riscv_top.core0_imem_addr[26] ;
+ wire \u_riscv_top.core0_imem_addr[27] ;
+ wire \u_riscv_top.core0_imem_addr[28] ;
+ wire \u_riscv_top.core0_imem_addr[29] ;
+ wire \u_riscv_top.core0_imem_addr[2] ;
+ wire \u_riscv_top.core0_imem_addr[30] ;
+ wire \u_riscv_top.core0_imem_addr[31] ;
+ wire \u_riscv_top.core0_imem_addr[3] ;
+ wire \u_riscv_top.core0_imem_addr[4] ;
+ wire \u_riscv_top.core0_imem_addr[5] ;
+ wire \u_riscv_top.core0_imem_addr[6] ;
+ wire \u_riscv_top.core0_imem_addr[7] ;
+ wire \u_riscv_top.core0_imem_addr[8] ;
+ wire \u_riscv_top.core0_imem_addr[9] ;
+ wire \u_riscv_top.core0_imem_bl[0] ;
+ wire \u_riscv_top.core0_imem_bl[1] ;
+ wire \u_riscv_top.core0_imem_bl[2] ;
+ wire \u_riscv_top.core0_imem_cmd ;
+ wire \u_riscv_top.core0_imem_rdata[0] ;
+ wire \u_riscv_top.core0_imem_rdata[10] ;
+ wire \u_riscv_top.core0_imem_rdata[11] ;
+ wire \u_riscv_top.core0_imem_rdata[12] ;
+ wire \u_riscv_top.core0_imem_rdata[13] ;
+ wire \u_riscv_top.core0_imem_rdata[14] ;
+ wire \u_riscv_top.core0_imem_rdata[15] ;
+ wire \u_riscv_top.core0_imem_rdata[16] ;
+ wire \u_riscv_top.core0_imem_rdata[17] ;
+ wire \u_riscv_top.core0_imem_rdata[18] ;
+ wire \u_riscv_top.core0_imem_rdata[19] ;
+ wire \u_riscv_top.core0_imem_rdata[1] ;
+ wire \u_riscv_top.core0_imem_rdata[20] ;
+ wire \u_riscv_top.core0_imem_rdata[21] ;
+ wire \u_riscv_top.core0_imem_rdata[22] ;
+ wire \u_riscv_top.core0_imem_rdata[23] ;
+ wire \u_riscv_top.core0_imem_rdata[24] ;
+ wire \u_riscv_top.core0_imem_rdata[25] ;
+ wire \u_riscv_top.core0_imem_rdata[26] ;
+ wire \u_riscv_top.core0_imem_rdata[27] ;
+ wire \u_riscv_top.core0_imem_rdata[28] ;
+ wire \u_riscv_top.core0_imem_rdata[29] ;
+ wire \u_riscv_top.core0_imem_rdata[2] ;
+ wire \u_riscv_top.core0_imem_rdata[30] ;
+ wire \u_riscv_top.core0_imem_rdata[31] ;
+ wire \u_riscv_top.core0_imem_rdata[3] ;
+ wire \u_riscv_top.core0_imem_rdata[4] ;
+ wire \u_riscv_top.core0_imem_rdata[5] ;
+ wire \u_riscv_top.core0_imem_rdata[6] ;
+ wire \u_riscv_top.core0_imem_rdata[7] ;
+ wire \u_riscv_top.core0_imem_rdata[8] ;
+ wire \u_riscv_top.core0_imem_rdata[9] ;
+ wire \u_riscv_top.core0_imem_req ;
+ wire \u_riscv_top.core0_imem_req_ack ;
+ wire \u_riscv_top.core0_imem_resp[0] ;
+ wire \u_riscv_top.core0_imem_resp[1] ;
+ wire \u_riscv_top.core0_irq_lines[0] ;
+ wire \u_riscv_top.core0_irq_lines[10] ;
+ wire \u_riscv_top.core0_irq_lines[11] ;
+ wire \u_riscv_top.core0_irq_lines[12] ;
+ wire \u_riscv_top.core0_irq_lines[13] ;
+ wire \u_riscv_top.core0_irq_lines[14] ;
+ wire \u_riscv_top.core0_irq_lines[15] ;
+ wire \u_riscv_top.core0_irq_lines[16] ;
+ wire \u_riscv_top.core0_irq_lines[17] ;
+ wire \u_riscv_top.core0_irq_lines[18] ;
+ wire \u_riscv_top.core0_irq_lines[19] ;
+ wire \u_riscv_top.core0_irq_lines[1] ;
+ wire \u_riscv_top.core0_irq_lines[20] ;
+ wire \u_riscv_top.core0_irq_lines[21] ;
+ wire \u_riscv_top.core0_irq_lines[22] ;
+ wire \u_riscv_top.core0_irq_lines[23] ;
+ wire \u_riscv_top.core0_irq_lines[24] ;
+ wire \u_riscv_top.core0_irq_lines[25] ;
+ wire \u_riscv_top.core0_irq_lines[26] ;
+ wire \u_riscv_top.core0_irq_lines[27] ;
+ wire \u_riscv_top.core0_irq_lines[28] ;
+ wire \u_riscv_top.core0_irq_lines[29] ;
+ wire \u_riscv_top.core0_irq_lines[2] ;
+ wire \u_riscv_top.core0_irq_lines[30] ;
+ wire \u_riscv_top.core0_irq_lines[31] ;
+ wire \u_riscv_top.core0_irq_lines[3] ;
+ wire \u_riscv_top.core0_irq_lines[4] ;
+ wire \u_riscv_top.core0_irq_lines[5] ;
+ wire \u_riscv_top.core0_irq_lines[6] ;
+ wire \u_riscv_top.core0_irq_lines[7] ;
+ wire \u_riscv_top.core0_irq_lines[8] ;
+ wire \u_riscv_top.core0_irq_lines[9] ;
+ wire \u_riscv_top.core0_soft_irq ;
+ wire \u_riscv_top.core0_timer_irq ;
+ wire \u_riscv_top.core0_timer_val[0] ;
+ wire \u_riscv_top.core0_timer_val[10] ;
+ wire \u_riscv_top.core0_timer_val[11] ;
+ wire \u_riscv_top.core0_timer_val[12] ;
+ wire \u_riscv_top.core0_timer_val[13] ;
+ wire \u_riscv_top.core0_timer_val[14] ;
+ wire \u_riscv_top.core0_timer_val[15] ;
+ wire \u_riscv_top.core0_timer_val[16] ;
+ wire \u_riscv_top.core0_timer_val[17] ;
+ wire \u_riscv_top.core0_timer_val[18] ;
+ wire \u_riscv_top.core0_timer_val[19] ;
+ wire \u_riscv_top.core0_timer_val[1] ;
+ wire \u_riscv_top.core0_timer_val[20] ;
+ wire \u_riscv_top.core0_timer_val[21] ;
+ wire \u_riscv_top.core0_timer_val[22] ;
+ wire \u_riscv_top.core0_timer_val[23] ;
+ wire \u_riscv_top.core0_timer_val[24] ;
+ wire \u_riscv_top.core0_timer_val[25] ;
+ wire \u_riscv_top.core0_timer_val[26] ;
+ wire \u_riscv_top.core0_timer_val[27] ;
+ wire \u_riscv_top.core0_timer_val[28] ;
+ wire \u_riscv_top.core0_timer_val[29] ;
+ wire \u_riscv_top.core0_timer_val[2] ;
+ wire \u_riscv_top.core0_timer_val[30] ;
+ wire \u_riscv_top.core0_timer_val[31] ;
+ wire \u_riscv_top.core0_timer_val[32] ;
+ wire \u_riscv_top.core0_timer_val[33] ;
+ wire \u_riscv_top.core0_timer_val[34] ;
+ wire \u_riscv_top.core0_timer_val[35] ;
+ wire \u_riscv_top.core0_timer_val[36] ;
+ wire \u_riscv_top.core0_timer_val[37] ;
+ wire \u_riscv_top.core0_timer_val[38] ;
+ wire \u_riscv_top.core0_timer_val[39] ;
+ wire \u_riscv_top.core0_timer_val[3] ;
+ wire \u_riscv_top.core0_timer_val[40] ;
+ wire \u_riscv_top.core0_timer_val[41] ;
+ wire \u_riscv_top.core0_timer_val[42] ;
+ wire \u_riscv_top.core0_timer_val[43] ;
+ wire \u_riscv_top.core0_timer_val[44] ;
+ wire \u_riscv_top.core0_timer_val[45] ;
+ wire \u_riscv_top.core0_timer_val[46] ;
+ wire \u_riscv_top.core0_timer_val[47] ;
+ wire \u_riscv_top.core0_timer_val[48] ;
+ wire \u_riscv_top.core0_timer_val[49] ;
+ wire \u_riscv_top.core0_timer_val[4] ;
+ wire \u_riscv_top.core0_timer_val[50] ;
+ wire \u_riscv_top.core0_timer_val[51] ;
+ wire \u_riscv_top.core0_timer_val[52] ;
+ wire \u_riscv_top.core0_timer_val[53] ;
+ wire \u_riscv_top.core0_timer_val[54] ;
+ wire \u_riscv_top.core0_timer_val[55] ;
+ wire \u_riscv_top.core0_timer_val[56] ;
+ wire \u_riscv_top.core0_timer_val[57] ;
+ wire \u_riscv_top.core0_timer_val[58] ;
+ wire \u_riscv_top.core0_timer_val[59] ;
+ wire \u_riscv_top.core0_timer_val[5] ;
+ wire \u_riscv_top.core0_timer_val[60] ;
+ wire \u_riscv_top.core0_timer_val[61] ;
+ wire \u_riscv_top.core0_timer_val[62] ;
+ wire \u_riscv_top.core0_timer_val[63] ;
+ wire \u_riscv_top.core0_timer_val[6] ;
+ wire \u_riscv_top.core0_timer_val[7] ;
+ wire \u_riscv_top.core0_timer_val[8] ;
+ wire \u_riscv_top.core0_timer_val[9] ;
+ wire \u_riscv_top.core0_uid[0] ;
+ wire \u_riscv_top.core0_uid[1] ;
+ wire \u_riscv_top.core1_clk ;
+ wire \u_riscv_top.core1_debug[0] ;
+ wire \u_riscv_top.core1_debug[10] ;
+ wire \u_riscv_top.core1_debug[11] ;
+ wire \u_riscv_top.core1_debug[12] ;
+ wire \u_riscv_top.core1_debug[13] ;
+ wire \u_riscv_top.core1_debug[14] ;
+ wire \u_riscv_top.core1_debug[15] ;
+ wire \u_riscv_top.core1_debug[16] ;
+ wire \u_riscv_top.core1_debug[17] ;
+ wire \u_riscv_top.core1_debug[18] ;
+ wire \u_riscv_top.core1_debug[19] ;
+ wire \u_riscv_top.core1_debug[1] ;
+ wire \u_riscv_top.core1_debug[20] ;
+ wire \u_riscv_top.core1_debug[21] ;
+ wire \u_riscv_top.core1_debug[22] ;
+ wire \u_riscv_top.core1_debug[23] ;
+ wire \u_riscv_top.core1_debug[24] ;
+ wire \u_riscv_top.core1_debug[25] ;
+ wire \u_riscv_top.core1_debug[26] ;
+ wire \u_riscv_top.core1_debug[27] ;
+ wire \u_riscv_top.core1_debug[28] ;
+ wire \u_riscv_top.core1_debug[29] ;
+ wire \u_riscv_top.core1_debug[2] ;
+ wire \u_riscv_top.core1_debug[30] ;
+ wire \u_riscv_top.core1_debug[31] ;
+ wire \u_riscv_top.core1_debug[32] ;
+ wire \u_riscv_top.core1_debug[33] ;
+ wire \u_riscv_top.core1_debug[34] ;
+ wire \u_riscv_top.core1_debug[35] ;
+ wire \u_riscv_top.core1_debug[36] ;
+ wire \u_riscv_top.core1_debug[37] ;
+ wire \u_riscv_top.core1_debug[38] ;
+ wire \u_riscv_top.core1_debug[39] ;
+ wire \u_riscv_top.core1_debug[3] ;
+ wire \u_riscv_top.core1_debug[40] ;
+ wire \u_riscv_top.core1_debug[41] ;
+ wire \u_riscv_top.core1_debug[42] ;
+ wire \u_riscv_top.core1_debug[43] ;
+ wire \u_riscv_top.core1_debug[44] ;
+ wire \u_riscv_top.core1_debug[45] ;
+ wire \u_riscv_top.core1_debug[46] ;
+ wire \u_riscv_top.core1_debug[47] ;
+ wire \u_riscv_top.core1_debug[48] ;
+ wire \u_riscv_top.core1_debug[4] ;
+ wire \u_riscv_top.core1_debug[5] ;
+ wire \u_riscv_top.core1_debug[6] ;
+ wire \u_riscv_top.core1_debug[7] ;
+ wire \u_riscv_top.core1_debug[8] ;
+ wire \u_riscv_top.core1_debug[9] ;
+ wire \u_riscv_top.core1_dmem_addr[0] ;
+ wire \u_riscv_top.core1_dmem_addr[10] ;
+ wire \u_riscv_top.core1_dmem_addr[11] ;
+ wire \u_riscv_top.core1_dmem_addr[12] ;
+ wire \u_riscv_top.core1_dmem_addr[13] ;
+ wire \u_riscv_top.core1_dmem_addr[14] ;
+ wire \u_riscv_top.core1_dmem_addr[15] ;
+ wire \u_riscv_top.core1_dmem_addr[16] ;
+ wire \u_riscv_top.core1_dmem_addr[17] ;
+ wire \u_riscv_top.core1_dmem_addr[18] ;
+ wire \u_riscv_top.core1_dmem_addr[19] ;
+ wire \u_riscv_top.core1_dmem_addr[1] ;
+ wire \u_riscv_top.core1_dmem_addr[20] ;
+ wire \u_riscv_top.core1_dmem_addr[21] ;
+ wire \u_riscv_top.core1_dmem_addr[22] ;
+ wire \u_riscv_top.core1_dmem_addr[23] ;
+ wire \u_riscv_top.core1_dmem_addr[24] ;
+ wire \u_riscv_top.core1_dmem_addr[25] ;
+ wire \u_riscv_top.core1_dmem_addr[26] ;
+ wire \u_riscv_top.core1_dmem_addr[27] ;
+ wire \u_riscv_top.core1_dmem_addr[28] ;
+ wire \u_riscv_top.core1_dmem_addr[29] ;
+ wire \u_riscv_top.core1_dmem_addr[2] ;
+ wire \u_riscv_top.core1_dmem_addr[30] ;
+ wire \u_riscv_top.core1_dmem_addr[31] ;
+ wire \u_riscv_top.core1_dmem_addr[3] ;
+ wire \u_riscv_top.core1_dmem_addr[4] ;
+ wire \u_riscv_top.core1_dmem_addr[5] ;
+ wire \u_riscv_top.core1_dmem_addr[6] ;
+ wire \u_riscv_top.core1_dmem_addr[7] ;
+ wire \u_riscv_top.core1_dmem_addr[8] ;
+ wire \u_riscv_top.core1_dmem_addr[9] ;
+ wire \u_riscv_top.core1_dmem_cmd ;
+ wire \u_riscv_top.core1_dmem_rdata[0] ;
+ wire \u_riscv_top.core1_dmem_rdata[10] ;
+ wire \u_riscv_top.core1_dmem_rdata[11] ;
+ wire \u_riscv_top.core1_dmem_rdata[12] ;
+ wire \u_riscv_top.core1_dmem_rdata[13] ;
+ wire \u_riscv_top.core1_dmem_rdata[14] ;
+ wire \u_riscv_top.core1_dmem_rdata[15] ;
+ wire \u_riscv_top.core1_dmem_rdata[16] ;
+ wire \u_riscv_top.core1_dmem_rdata[17] ;
+ wire \u_riscv_top.core1_dmem_rdata[18] ;
+ wire \u_riscv_top.core1_dmem_rdata[19] ;
+ wire \u_riscv_top.core1_dmem_rdata[1] ;
+ wire \u_riscv_top.core1_dmem_rdata[20] ;
+ wire \u_riscv_top.core1_dmem_rdata[21] ;
+ wire \u_riscv_top.core1_dmem_rdata[22] ;
+ wire \u_riscv_top.core1_dmem_rdata[23] ;
+ wire \u_riscv_top.core1_dmem_rdata[24] ;
+ wire \u_riscv_top.core1_dmem_rdata[25] ;
+ wire \u_riscv_top.core1_dmem_rdata[26] ;
+ wire \u_riscv_top.core1_dmem_rdata[27] ;
+ wire \u_riscv_top.core1_dmem_rdata[28] ;
+ wire \u_riscv_top.core1_dmem_rdata[29] ;
+ wire \u_riscv_top.core1_dmem_rdata[2] ;
+ wire \u_riscv_top.core1_dmem_rdata[30] ;
+ wire \u_riscv_top.core1_dmem_rdata[31] ;
+ wire \u_riscv_top.core1_dmem_rdata[3] ;
+ wire \u_riscv_top.core1_dmem_rdata[4] ;
+ wire \u_riscv_top.core1_dmem_rdata[5] ;
+ wire \u_riscv_top.core1_dmem_rdata[6] ;
+ wire \u_riscv_top.core1_dmem_rdata[7] ;
+ wire \u_riscv_top.core1_dmem_rdata[8] ;
+ wire \u_riscv_top.core1_dmem_rdata[9] ;
+ wire \u_riscv_top.core1_dmem_req ;
+ wire \u_riscv_top.core1_dmem_req_ack ;
+ wire \u_riscv_top.core1_dmem_resp[0] ;
+ wire \u_riscv_top.core1_dmem_resp[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[0] ;
+ wire \u_riscv_top.core1_dmem_wdata[10] ;
+ wire \u_riscv_top.core1_dmem_wdata[11] ;
+ wire \u_riscv_top.core1_dmem_wdata[12] ;
+ wire \u_riscv_top.core1_dmem_wdata[13] ;
+ wire \u_riscv_top.core1_dmem_wdata[14] ;
+ wire \u_riscv_top.core1_dmem_wdata[15] ;
+ wire \u_riscv_top.core1_dmem_wdata[16] ;
+ wire \u_riscv_top.core1_dmem_wdata[17] ;
+ wire \u_riscv_top.core1_dmem_wdata[18] ;
+ wire \u_riscv_top.core1_dmem_wdata[19] ;
+ wire \u_riscv_top.core1_dmem_wdata[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[20] ;
+ wire \u_riscv_top.core1_dmem_wdata[21] ;
+ wire \u_riscv_top.core1_dmem_wdata[22] ;
+ wire \u_riscv_top.core1_dmem_wdata[23] ;
+ wire \u_riscv_top.core1_dmem_wdata[24] ;
+ wire \u_riscv_top.core1_dmem_wdata[25] ;
+ wire \u_riscv_top.core1_dmem_wdata[26] ;
+ wire \u_riscv_top.core1_dmem_wdata[27] ;
+ wire \u_riscv_top.core1_dmem_wdata[28] ;
+ wire \u_riscv_top.core1_dmem_wdata[29] ;
+ wire \u_riscv_top.core1_dmem_wdata[2] ;
+ wire \u_riscv_top.core1_dmem_wdata[30] ;
+ wire \u_riscv_top.core1_dmem_wdata[31] ;
+ wire \u_riscv_top.core1_dmem_wdata[3] ;
+ wire \u_riscv_top.core1_dmem_wdata[4] ;
+ wire \u_riscv_top.core1_dmem_wdata[5] ;
+ wire \u_riscv_top.core1_dmem_wdata[6] ;
+ wire \u_riscv_top.core1_dmem_wdata[7] ;
+ wire \u_riscv_top.core1_dmem_wdata[8] ;
+ wire \u_riscv_top.core1_dmem_wdata[9] ;
+ wire \u_riscv_top.core1_dmem_width[0] ;
+ wire \u_riscv_top.core1_dmem_width[1] ;
+ wire \u_riscv_top.core1_imem_addr[0] ;
+ wire \u_riscv_top.core1_imem_addr[10] ;
+ wire \u_riscv_top.core1_imem_addr[11] ;
+ wire \u_riscv_top.core1_imem_addr[12] ;
+ wire \u_riscv_top.core1_imem_addr[13] ;
+ wire \u_riscv_top.core1_imem_addr[14] ;
+ wire \u_riscv_top.core1_imem_addr[15] ;
+ wire \u_riscv_top.core1_imem_addr[16] ;
+ wire \u_riscv_top.core1_imem_addr[17] ;
+ wire \u_riscv_top.core1_imem_addr[18] ;
+ wire \u_riscv_top.core1_imem_addr[19] ;
+ wire \u_riscv_top.core1_imem_addr[1] ;
+ wire \u_riscv_top.core1_imem_addr[20] ;
+ wire \u_riscv_top.core1_imem_addr[21] ;
+ wire \u_riscv_top.core1_imem_addr[22] ;
+ wire \u_riscv_top.core1_imem_addr[23] ;
+ wire \u_riscv_top.core1_imem_addr[24] ;
+ wire \u_riscv_top.core1_imem_addr[25] ;
+ wire \u_riscv_top.core1_imem_addr[26] ;
+ wire \u_riscv_top.core1_imem_addr[27] ;
+ wire \u_riscv_top.core1_imem_addr[28] ;
+ wire \u_riscv_top.core1_imem_addr[29] ;
+ wire \u_riscv_top.core1_imem_addr[2] ;
+ wire \u_riscv_top.core1_imem_addr[30] ;
+ wire \u_riscv_top.core1_imem_addr[31] ;
+ wire \u_riscv_top.core1_imem_addr[3] ;
+ wire \u_riscv_top.core1_imem_addr[4] ;
+ wire \u_riscv_top.core1_imem_addr[5] ;
+ wire \u_riscv_top.core1_imem_addr[6] ;
+ wire \u_riscv_top.core1_imem_addr[7] ;
+ wire \u_riscv_top.core1_imem_addr[8] ;
+ wire \u_riscv_top.core1_imem_addr[9] ;
+ wire \u_riscv_top.core1_imem_bl[0] ;
+ wire \u_riscv_top.core1_imem_bl[1] ;
+ wire \u_riscv_top.core1_imem_bl[2] ;
+ wire \u_riscv_top.core1_imem_cmd ;
+ wire \u_riscv_top.core1_imem_rdata[0] ;
+ wire \u_riscv_top.core1_imem_rdata[10] ;
+ wire \u_riscv_top.core1_imem_rdata[11] ;
+ wire \u_riscv_top.core1_imem_rdata[12] ;
+ wire \u_riscv_top.core1_imem_rdata[13] ;
+ wire \u_riscv_top.core1_imem_rdata[14] ;
+ wire \u_riscv_top.core1_imem_rdata[15] ;
+ wire \u_riscv_top.core1_imem_rdata[16] ;
+ wire \u_riscv_top.core1_imem_rdata[17] ;
+ wire \u_riscv_top.core1_imem_rdata[18] ;
+ wire \u_riscv_top.core1_imem_rdata[19] ;
+ wire \u_riscv_top.core1_imem_rdata[1] ;
+ wire \u_riscv_top.core1_imem_rdata[20] ;
+ wire \u_riscv_top.core1_imem_rdata[21] ;
+ wire \u_riscv_top.core1_imem_rdata[22] ;
+ wire \u_riscv_top.core1_imem_rdata[23] ;
+ wire \u_riscv_top.core1_imem_rdata[24] ;
+ wire \u_riscv_top.core1_imem_rdata[25] ;
+ wire \u_riscv_top.core1_imem_rdata[26] ;
+ wire \u_riscv_top.core1_imem_rdata[27] ;
+ wire \u_riscv_top.core1_imem_rdata[28] ;
+ wire \u_riscv_top.core1_imem_rdata[29] ;
+ wire \u_riscv_top.core1_imem_rdata[2] ;
+ wire \u_riscv_top.core1_imem_rdata[30] ;
+ wire \u_riscv_top.core1_imem_rdata[31] ;
+ wire \u_riscv_top.core1_imem_rdata[3] ;
+ wire \u_riscv_top.core1_imem_rdata[4] ;
+ wire \u_riscv_top.core1_imem_rdata[5] ;
+ wire \u_riscv_top.core1_imem_rdata[6] ;
+ wire \u_riscv_top.core1_imem_rdata[7] ;
+ wire \u_riscv_top.core1_imem_rdata[8] ;
+ wire \u_riscv_top.core1_imem_rdata[9] ;
+ wire \u_riscv_top.core1_imem_req ;
+ wire \u_riscv_top.core1_imem_req_ack ;
+ wire \u_riscv_top.core1_imem_resp[0] ;
+ wire \u_riscv_top.core1_imem_resp[1] ;
+ wire \u_riscv_top.core1_irq_lines[0] ;
+ wire \u_riscv_top.core1_irq_lines[10] ;
+ wire \u_riscv_top.core1_irq_lines[11] ;
+ wire \u_riscv_top.core1_irq_lines[12] ;
+ wire \u_riscv_top.core1_irq_lines[13] ;
+ wire \u_riscv_top.core1_irq_lines[14] ;
+ wire \u_riscv_top.core1_irq_lines[15] ;
+ wire \u_riscv_top.core1_irq_lines[16] ;
+ wire \u_riscv_top.core1_irq_lines[17] ;
+ wire \u_riscv_top.core1_irq_lines[18] ;
+ wire \u_riscv_top.core1_irq_lines[19] ;
+ wire \u_riscv_top.core1_irq_lines[1] ;
+ wire \u_riscv_top.core1_irq_lines[20] ;
+ wire \u_riscv_top.core1_irq_lines[21] ;
+ wire \u_riscv_top.core1_irq_lines[22] ;
+ wire \u_riscv_top.core1_irq_lines[23] ;
+ wire \u_riscv_top.core1_irq_lines[24] ;
+ wire \u_riscv_top.core1_irq_lines[25] ;
+ wire \u_riscv_top.core1_irq_lines[26] ;
+ wire \u_riscv_top.core1_irq_lines[27] ;
+ wire \u_riscv_top.core1_irq_lines[28] ;
+ wire \u_riscv_top.core1_irq_lines[29] ;
+ wire \u_riscv_top.core1_irq_lines[2] ;
+ wire \u_riscv_top.core1_irq_lines[30] ;
+ wire \u_riscv_top.core1_irq_lines[31] ;
+ wire \u_riscv_top.core1_irq_lines[3] ;
+ wire \u_riscv_top.core1_irq_lines[4] ;
+ wire \u_riscv_top.core1_irq_lines[5] ;
+ wire \u_riscv_top.core1_irq_lines[6] ;
+ wire \u_riscv_top.core1_irq_lines[7] ;
+ wire \u_riscv_top.core1_irq_lines[8] ;
+ wire \u_riscv_top.core1_irq_lines[9] ;
+ wire \u_riscv_top.core1_soft_irq ;
+ wire \u_riscv_top.core1_timer_irq ;
+ wire \u_riscv_top.core1_timer_val[0] ;
+ wire \u_riscv_top.core1_timer_val[10] ;
+ wire \u_riscv_top.core1_timer_val[11] ;
+ wire \u_riscv_top.core1_timer_val[12] ;
+ wire \u_riscv_top.core1_timer_val[13] ;
+ wire \u_riscv_top.core1_timer_val[14] ;
+ wire \u_riscv_top.core1_timer_val[15] ;
+ wire \u_riscv_top.core1_timer_val[16] ;
+ wire \u_riscv_top.core1_timer_val[17] ;
+ wire \u_riscv_top.core1_timer_val[18] ;
+ wire \u_riscv_top.core1_timer_val[19] ;
+ wire \u_riscv_top.core1_timer_val[1] ;
+ wire \u_riscv_top.core1_timer_val[20] ;
+ wire \u_riscv_top.core1_timer_val[21] ;
+ wire \u_riscv_top.core1_timer_val[22] ;
+ wire \u_riscv_top.core1_timer_val[23] ;
+ wire \u_riscv_top.core1_timer_val[24] ;
+ wire \u_riscv_top.core1_timer_val[25] ;
+ wire \u_riscv_top.core1_timer_val[26] ;
+ wire \u_riscv_top.core1_timer_val[27] ;
+ wire \u_riscv_top.core1_timer_val[28] ;
+ wire \u_riscv_top.core1_timer_val[29] ;
+ wire \u_riscv_top.core1_timer_val[2] ;
+ wire \u_riscv_top.core1_timer_val[30] ;
+ wire \u_riscv_top.core1_timer_val[31] ;
+ wire \u_riscv_top.core1_timer_val[32] ;
+ wire \u_riscv_top.core1_timer_val[33] ;
+ wire \u_riscv_top.core1_timer_val[34] ;
+ wire \u_riscv_top.core1_timer_val[35] ;
+ wire \u_riscv_top.core1_timer_val[36] ;
+ wire \u_riscv_top.core1_timer_val[37] ;
+ wire \u_riscv_top.core1_timer_val[38] ;
+ wire \u_riscv_top.core1_timer_val[39] ;
+ wire \u_riscv_top.core1_timer_val[3] ;
+ wire \u_riscv_top.core1_timer_val[40] ;
+ wire \u_riscv_top.core1_timer_val[41] ;
+ wire \u_riscv_top.core1_timer_val[42] ;
+ wire \u_riscv_top.core1_timer_val[43] ;
+ wire \u_riscv_top.core1_timer_val[44] ;
+ wire \u_riscv_top.core1_timer_val[45] ;
+ wire \u_riscv_top.core1_timer_val[46] ;
+ wire \u_riscv_top.core1_timer_val[47] ;
+ wire \u_riscv_top.core1_timer_val[48] ;
+ wire \u_riscv_top.core1_timer_val[49] ;
+ wire \u_riscv_top.core1_timer_val[4] ;
+ wire \u_riscv_top.core1_timer_val[50] ;
+ wire \u_riscv_top.core1_timer_val[51] ;
+ wire \u_riscv_top.core1_timer_val[52] ;
+ wire \u_riscv_top.core1_timer_val[53] ;
+ wire \u_riscv_top.core1_timer_val[54] ;
+ wire \u_riscv_top.core1_timer_val[55] ;
+ wire \u_riscv_top.core1_timer_val[56] ;
+ wire \u_riscv_top.core1_timer_val[57] ;
+ wire \u_riscv_top.core1_timer_val[58] ;
+ wire \u_riscv_top.core1_timer_val[59] ;
+ wire \u_riscv_top.core1_timer_val[5] ;
+ wire \u_riscv_top.core1_timer_val[60] ;
+ wire \u_riscv_top.core1_timer_val[61] ;
+ wire \u_riscv_top.core1_timer_val[62] ;
+ wire \u_riscv_top.core1_timer_val[63] ;
+ wire \u_riscv_top.core1_timer_val[6] ;
+ wire \u_riscv_top.core1_timer_val[7] ;
+ wire \u_riscv_top.core1_timer_val[8] ;
+ wire \u_riscv_top.core1_timer_val[9] ;
+ wire \u_riscv_top.core1_uid[0] ;
+ wire \u_riscv_top.core1_uid[1] ;
+ wire \u_riscv_top.core2_clk ;
+ wire \u_riscv_top.core2_debug[0] ;
+ wire \u_riscv_top.core2_debug[10] ;
+ wire \u_riscv_top.core2_debug[11] ;
+ wire \u_riscv_top.core2_debug[12] ;
+ wire \u_riscv_top.core2_debug[13] ;
+ wire \u_riscv_top.core2_debug[14] ;
+ wire \u_riscv_top.core2_debug[15] ;
+ wire \u_riscv_top.core2_debug[16] ;
+ wire \u_riscv_top.core2_debug[17] ;
+ wire \u_riscv_top.core2_debug[18] ;
+ wire \u_riscv_top.core2_debug[19] ;
+ wire \u_riscv_top.core2_debug[1] ;
+ wire \u_riscv_top.core2_debug[20] ;
+ wire \u_riscv_top.core2_debug[21] ;
+ wire \u_riscv_top.core2_debug[22] ;
+ wire \u_riscv_top.core2_debug[23] ;
+ wire \u_riscv_top.core2_debug[24] ;
+ wire \u_riscv_top.core2_debug[25] ;
+ wire \u_riscv_top.core2_debug[26] ;
+ wire \u_riscv_top.core2_debug[27] ;
+ wire \u_riscv_top.core2_debug[28] ;
+ wire \u_riscv_top.core2_debug[29] ;
+ wire \u_riscv_top.core2_debug[2] ;
+ wire \u_riscv_top.core2_debug[30] ;
+ wire \u_riscv_top.core2_debug[31] ;
+ wire \u_riscv_top.core2_debug[32] ;
+ wire \u_riscv_top.core2_debug[33] ;
+ wire \u_riscv_top.core2_debug[34] ;
+ wire \u_riscv_top.core2_debug[35] ;
+ wire \u_riscv_top.core2_debug[36] ;
+ wire \u_riscv_top.core2_debug[37] ;
+ wire \u_riscv_top.core2_debug[38] ;
+ wire \u_riscv_top.core2_debug[39] ;
+ wire \u_riscv_top.core2_debug[3] ;
+ wire \u_riscv_top.core2_debug[40] ;
+ wire \u_riscv_top.core2_debug[41] ;
+ wire \u_riscv_top.core2_debug[42] ;
+ wire \u_riscv_top.core2_debug[43] ;
+ wire \u_riscv_top.core2_debug[44] ;
+ wire \u_riscv_top.core2_debug[45] ;
+ wire \u_riscv_top.core2_debug[46] ;
+ wire \u_riscv_top.core2_debug[47] ;
+ wire \u_riscv_top.core2_debug[48] ;
+ wire \u_riscv_top.core2_debug[4] ;
+ wire \u_riscv_top.core2_debug[5] ;
+ wire \u_riscv_top.core2_debug[6] ;
+ wire \u_riscv_top.core2_debug[7] ;
+ wire \u_riscv_top.core2_debug[8] ;
+ wire \u_riscv_top.core2_debug[9] ;
+ wire \u_riscv_top.core2_dmem_addr[0] ;
+ wire \u_riscv_top.core2_dmem_addr[10] ;
+ wire \u_riscv_top.core2_dmem_addr[11] ;
+ wire \u_riscv_top.core2_dmem_addr[12] ;
+ wire \u_riscv_top.core2_dmem_addr[13] ;
+ wire \u_riscv_top.core2_dmem_addr[14] ;
+ wire \u_riscv_top.core2_dmem_addr[15] ;
+ wire \u_riscv_top.core2_dmem_addr[16] ;
+ wire \u_riscv_top.core2_dmem_addr[17] ;
+ wire \u_riscv_top.core2_dmem_addr[18] ;
+ wire \u_riscv_top.core2_dmem_addr[19] ;
+ wire \u_riscv_top.core2_dmem_addr[1] ;
+ wire \u_riscv_top.core2_dmem_addr[20] ;
+ wire \u_riscv_top.core2_dmem_addr[21] ;
+ wire \u_riscv_top.core2_dmem_addr[22] ;
+ wire \u_riscv_top.core2_dmem_addr[23] ;
+ wire \u_riscv_top.core2_dmem_addr[24] ;
+ wire \u_riscv_top.core2_dmem_addr[25] ;
+ wire \u_riscv_top.core2_dmem_addr[26] ;
+ wire \u_riscv_top.core2_dmem_addr[27] ;
+ wire \u_riscv_top.core2_dmem_addr[28] ;
+ wire \u_riscv_top.core2_dmem_addr[29] ;
+ wire \u_riscv_top.core2_dmem_addr[2] ;
+ wire \u_riscv_top.core2_dmem_addr[30] ;
+ wire \u_riscv_top.core2_dmem_addr[31] ;
+ wire \u_riscv_top.core2_dmem_addr[3] ;
+ wire \u_riscv_top.core2_dmem_addr[4] ;
+ wire \u_riscv_top.core2_dmem_addr[5] ;
+ wire \u_riscv_top.core2_dmem_addr[6] ;
+ wire \u_riscv_top.core2_dmem_addr[7] ;
+ wire \u_riscv_top.core2_dmem_addr[8] ;
+ wire \u_riscv_top.core2_dmem_addr[9] ;
+ wire \u_riscv_top.core2_dmem_cmd ;
+ wire \u_riscv_top.core2_dmem_rdata[0] ;
+ wire \u_riscv_top.core2_dmem_rdata[10] ;
+ wire \u_riscv_top.core2_dmem_rdata[11] ;
+ wire \u_riscv_top.core2_dmem_rdata[12] ;
+ wire \u_riscv_top.core2_dmem_rdata[13] ;
+ wire \u_riscv_top.core2_dmem_rdata[14] ;
+ wire \u_riscv_top.core2_dmem_rdata[15] ;
+ wire \u_riscv_top.core2_dmem_rdata[16] ;
+ wire \u_riscv_top.core2_dmem_rdata[17] ;
+ wire \u_riscv_top.core2_dmem_rdata[18] ;
+ wire \u_riscv_top.core2_dmem_rdata[19] ;
+ wire \u_riscv_top.core2_dmem_rdata[1] ;
+ wire \u_riscv_top.core2_dmem_rdata[20] ;
+ wire \u_riscv_top.core2_dmem_rdata[21] ;
+ wire \u_riscv_top.core2_dmem_rdata[22] ;
+ wire \u_riscv_top.core2_dmem_rdata[23] ;
+ wire \u_riscv_top.core2_dmem_rdata[24] ;
+ wire \u_riscv_top.core2_dmem_rdata[25] ;
+ wire \u_riscv_top.core2_dmem_rdata[26] ;
+ wire \u_riscv_top.core2_dmem_rdata[27] ;
+ wire \u_riscv_top.core2_dmem_rdata[28] ;
+ wire \u_riscv_top.core2_dmem_rdata[29] ;
+ wire \u_riscv_top.core2_dmem_rdata[2] ;
+ wire \u_riscv_top.core2_dmem_rdata[30] ;
+ wire \u_riscv_top.core2_dmem_rdata[31] ;
+ wire \u_riscv_top.core2_dmem_rdata[3] ;
+ wire \u_riscv_top.core2_dmem_rdata[4] ;
+ wire \u_riscv_top.core2_dmem_rdata[5] ;
+ wire \u_riscv_top.core2_dmem_rdata[6] ;
+ wire \u_riscv_top.core2_dmem_rdata[7] ;
+ wire \u_riscv_top.core2_dmem_rdata[8] ;
+ wire \u_riscv_top.core2_dmem_rdata[9] ;
+ wire \u_riscv_top.core2_dmem_req ;
+ wire \u_riscv_top.core2_dmem_req_ack ;
+ wire \u_riscv_top.core2_dmem_resp[0] ;
+ wire \u_riscv_top.core2_dmem_resp[1] ;
+ wire \u_riscv_top.core2_dmem_wdata[0] ;
+ wire \u_riscv_top.core2_dmem_wdata[10] ;
+ wire \u_riscv_top.core2_dmem_wdata[11] ;
+ wire \u_riscv_top.core2_dmem_wdata[12] ;
+ wire \u_riscv_top.core2_dmem_wdata[13] ;
+ wire \u_riscv_top.core2_dmem_wdata[14] ;
+ wire \u_riscv_top.core2_dmem_wdata[15] ;
+ wire \u_riscv_top.core2_dmem_wdata[16] ;
+ wire \u_riscv_top.core2_dmem_wdata[17] ;
+ wire \u_riscv_top.core2_dmem_wdata[18] ;
+ wire \u_riscv_top.core2_dmem_wdata[19] ;
+ wire \u_riscv_top.core2_dmem_wdata[1] ;
+ wire \u_riscv_top.core2_dmem_wdata[20] ;
+ wire \u_riscv_top.core2_dmem_wdata[21] ;
+ wire \u_riscv_top.core2_dmem_wdata[22] ;
+ wire \u_riscv_top.core2_dmem_wdata[23] ;
+ wire \u_riscv_top.core2_dmem_wdata[24] ;
+ wire \u_riscv_top.core2_dmem_wdata[25] ;
+ wire \u_riscv_top.core2_dmem_wdata[26] ;
+ wire \u_riscv_top.core2_dmem_wdata[27] ;
+ wire \u_riscv_top.core2_dmem_wdata[28] ;
+ wire \u_riscv_top.core2_dmem_wdata[29] ;
+ wire \u_riscv_top.core2_dmem_wdata[2] ;
+ wire \u_riscv_top.core2_dmem_wdata[30] ;
+ wire \u_riscv_top.core2_dmem_wdata[31] ;
+ wire \u_riscv_top.core2_dmem_wdata[3] ;
+ wire \u_riscv_top.core2_dmem_wdata[4] ;
+ wire \u_riscv_top.core2_dmem_wdata[5] ;
+ wire \u_riscv_top.core2_dmem_wdata[6] ;
+ wire \u_riscv_top.core2_dmem_wdata[7] ;
+ wire \u_riscv_top.core2_dmem_wdata[8] ;
+ wire \u_riscv_top.core2_dmem_wdata[9] ;
+ wire \u_riscv_top.core2_dmem_width[0] ;
+ wire \u_riscv_top.core2_dmem_width[1] ;
+ wire \u_riscv_top.core2_imem_addr[0] ;
+ wire \u_riscv_top.core2_imem_addr[10] ;
+ wire \u_riscv_top.core2_imem_addr[11] ;
+ wire \u_riscv_top.core2_imem_addr[12] ;
+ wire \u_riscv_top.core2_imem_addr[13] ;
+ wire \u_riscv_top.core2_imem_addr[14] ;
+ wire \u_riscv_top.core2_imem_addr[15] ;
+ wire \u_riscv_top.core2_imem_addr[16] ;
+ wire \u_riscv_top.core2_imem_addr[17] ;
+ wire \u_riscv_top.core2_imem_addr[18] ;
+ wire \u_riscv_top.core2_imem_addr[19] ;
+ wire \u_riscv_top.core2_imem_addr[1] ;
+ wire \u_riscv_top.core2_imem_addr[20] ;
+ wire \u_riscv_top.core2_imem_addr[21] ;
+ wire \u_riscv_top.core2_imem_addr[22] ;
+ wire \u_riscv_top.core2_imem_addr[23] ;
+ wire \u_riscv_top.core2_imem_addr[24] ;
+ wire \u_riscv_top.core2_imem_addr[25] ;
+ wire \u_riscv_top.core2_imem_addr[26] ;
+ wire \u_riscv_top.core2_imem_addr[27] ;
+ wire \u_riscv_top.core2_imem_addr[28] ;
+ wire \u_riscv_top.core2_imem_addr[29] ;
+ wire \u_riscv_top.core2_imem_addr[2] ;
+ wire \u_riscv_top.core2_imem_addr[30] ;
+ wire \u_riscv_top.core2_imem_addr[31] ;
+ wire \u_riscv_top.core2_imem_addr[3] ;
+ wire \u_riscv_top.core2_imem_addr[4] ;
+ wire \u_riscv_top.core2_imem_addr[5] ;
+ wire \u_riscv_top.core2_imem_addr[6] ;
+ wire \u_riscv_top.core2_imem_addr[7] ;
+ wire \u_riscv_top.core2_imem_addr[8] ;
+ wire \u_riscv_top.core2_imem_addr[9] ;
+ wire \u_riscv_top.core2_imem_bl[0] ;
+ wire \u_riscv_top.core2_imem_bl[1] ;
+ wire \u_riscv_top.core2_imem_bl[2] ;
+ wire \u_riscv_top.core2_imem_cmd ;
+ wire \u_riscv_top.core2_imem_rdata[0] ;
+ wire \u_riscv_top.core2_imem_rdata[10] ;
+ wire \u_riscv_top.core2_imem_rdata[11] ;
+ wire \u_riscv_top.core2_imem_rdata[12] ;
+ wire \u_riscv_top.core2_imem_rdata[13] ;
+ wire \u_riscv_top.core2_imem_rdata[14] ;
+ wire \u_riscv_top.core2_imem_rdata[15] ;
+ wire \u_riscv_top.core2_imem_rdata[16] ;
+ wire \u_riscv_top.core2_imem_rdata[17] ;
+ wire \u_riscv_top.core2_imem_rdata[18] ;
+ wire \u_riscv_top.core2_imem_rdata[19] ;
+ wire \u_riscv_top.core2_imem_rdata[1] ;
+ wire \u_riscv_top.core2_imem_rdata[20] ;
+ wire \u_riscv_top.core2_imem_rdata[21] ;
+ wire \u_riscv_top.core2_imem_rdata[22] ;
+ wire \u_riscv_top.core2_imem_rdata[23] ;
+ wire \u_riscv_top.core2_imem_rdata[24] ;
+ wire \u_riscv_top.core2_imem_rdata[25] ;
+ wire \u_riscv_top.core2_imem_rdata[26] ;
+ wire \u_riscv_top.core2_imem_rdata[27] ;
+ wire \u_riscv_top.core2_imem_rdata[28] ;
+ wire \u_riscv_top.core2_imem_rdata[29] ;
+ wire \u_riscv_top.core2_imem_rdata[2] ;
+ wire \u_riscv_top.core2_imem_rdata[30] ;
+ wire \u_riscv_top.core2_imem_rdata[31] ;
+ wire \u_riscv_top.core2_imem_rdata[3] ;
+ wire \u_riscv_top.core2_imem_rdata[4] ;
+ wire \u_riscv_top.core2_imem_rdata[5] ;
+ wire \u_riscv_top.core2_imem_rdata[6] ;
+ wire \u_riscv_top.core2_imem_rdata[7] ;
+ wire \u_riscv_top.core2_imem_rdata[8] ;
+ wire \u_riscv_top.core2_imem_rdata[9] ;
+ wire \u_riscv_top.core2_imem_req ;
+ wire \u_riscv_top.core2_imem_req_ack ;
+ wire \u_riscv_top.core2_imem_resp[0] ;
+ wire \u_riscv_top.core2_imem_resp[1] ;
+ wire \u_riscv_top.core2_irq_lines[0] ;
+ wire \u_riscv_top.core2_irq_lines[10] ;
+ wire \u_riscv_top.core2_irq_lines[11] ;
+ wire \u_riscv_top.core2_irq_lines[12] ;
+ wire \u_riscv_top.core2_irq_lines[13] ;
+ wire \u_riscv_top.core2_irq_lines[14] ;
+ wire \u_riscv_top.core2_irq_lines[15] ;
+ wire \u_riscv_top.core2_irq_lines[16] ;
+ wire \u_riscv_top.core2_irq_lines[17] ;
+ wire \u_riscv_top.core2_irq_lines[18] ;
+ wire \u_riscv_top.core2_irq_lines[19] ;
+ wire \u_riscv_top.core2_irq_lines[1] ;
+ wire \u_riscv_top.core2_irq_lines[20] ;
+ wire \u_riscv_top.core2_irq_lines[21] ;
+ wire \u_riscv_top.core2_irq_lines[22] ;
+ wire \u_riscv_top.core2_irq_lines[23] ;
+ wire \u_riscv_top.core2_irq_lines[24] ;
+ wire \u_riscv_top.core2_irq_lines[25] ;
+ wire \u_riscv_top.core2_irq_lines[26] ;
+ wire \u_riscv_top.core2_irq_lines[27] ;
+ wire \u_riscv_top.core2_irq_lines[28] ;
+ wire \u_riscv_top.core2_irq_lines[29] ;
+ wire \u_riscv_top.core2_irq_lines[2] ;
+ wire \u_riscv_top.core2_irq_lines[30] ;
+ wire \u_riscv_top.core2_irq_lines[31] ;
+ wire \u_riscv_top.core2_irq_lines[3] ;
+ wire \u_riscv_top.core2_irq_lines[4] ;
+ wire \u_riscv_top.core2_irq_lines[5] ;
+ wire \u_riscv_top.core2_irq_lines[6] ;
+ wire \u_riscv_top.core2_irq_lines[7] ;
+ wire \u_riscv_top.core2_irq_lines[8] ;
+ wire \u_riscv_top.core2_irq_lines[9] ;
+ wire \u_riscv_top.core2_soft_irq ;
+ wire \u_riscv_top.core2_timer_irq ;
+ wire \u_riscv_top.core2_timer_val[0] ;
+ wire \u_riscv_top.core2_timer_val[10] ;
+ wire \u_riscv_top.core2_timer_val[11] ;
+ wire \u_riscv_top.core2_timer_val[12] ;
+ wire \u_riscv_top.core2_timer_val[13] ;
+ wire \u_riscv_top.core2_timer_val[14] ;
+ wire \u_riscv_top.core2_timer_val[15] ;
+ wire \u_riscv_top.core2_timer_val[16] ;
+ wire \u_riscv_top.core2_timer_val[17] ;
+ wire \u_riscv_top.core2_timer_val[18] ;
+ wire \u_riscv_top.core2_timer_val[19] ;
+ wire \u_riscv_top.core2_timer_val[1] ;
+ wire \u_riscv_top.core2_timer_val[20] ;
+ wire \u_riscv_top.core2_timer_val[21] ;
+ wire \u_riscv_top.core2_timer_val[22] ;
+ wire \u_riscv_top.core2_timer_val[23] ;
+ wire \u_riscv_top.core2_timer_val[24] ;
+ wire \u_riscv_top.core2_timer_val[25] ;
+ wire \u_riscv_top.core2_timer_val[26] ;
+ wire \u_riscv_top.core2_timer_val[27] ;
+ wire \u_riscv_top.core2_timer_val[28] ;
+ wire \u_riscv_top.core2_timer_val[29] ;
+ wire \u_riscv_top.core2_timer_val[2] ;
+ wire \u_riscv_top.core2_timer_val[30] ;
+ wire \u_riscv_top.core2_timer_val[31] ;
+ wire \u_riscv_top.core2_timer_val[32] ;
+ wire \u_riscv_top.core2_timer_val[33] ;
+ wire \u_riscv_top.core2_timer_val[34] ;
+ wire \u_riscv_top.core2_timer_val[35] ;
+ wire \u_riscv_top.core2_timer_val[36] ;
+ wire \u_riscv_top.core2_timer_val[37] ;
+ wire \u_riscv_top.core2_timer_val[38] ;
+ wire \u_riscv_top.core2_timer_val[39] ;
+ wire \u_riscv_top.core2_timer_val[3] ;
+ wire \u_riscv_top.core2_timer_val[40] ;
+ wire \u_riscv_top.core2_timer_val[41] ;
+ wire \u_riscv_top.core2_timer_val[42] ;
+ wire \u_riscv_top.core2_timer_val[43] ;
+ wire \u_riscv_top.core2_timer_val[44] ;
+ wire \u_riscv_top.core2_timer_val[45] ;
+ wire \u_riscv_top.core2_timer_val[46] ;
+ wire \u_riscv_top.core2_timer_val[47] ;
+ wire \u_riscv_top.core2_timer_val[48] ;
+ wire \u_riscv_top.core2_timer_val[49] ;
+ wire \u_riscv_top.core2_timer_val[4] ;
+ wire \u_riscv_top.core2_timer_val[50] ;
+ wire \u_riscv_top.core2_timer_val[51] ;
+ wire \u_riscv_top.core2_timer_val[52] ;
+ wire \u_riscv_top.core2_timer_val[53] ;
+ wire \u_riscv_top.core2_timer_val[54] ;
+ wire \u_riscv_top.core2_timer_val[55] ;
+ wire \u_riscv_top.core2_timer_val[56] ;
+ wire \u_riscv_top.core2_timer_val[57] ;
+ wire \u_riscv_top.core2_timer_val[58] ;
+ wire \u_riscv_top.core2_timer_val[59] ;
+ wire \u_riscv_top.core2_timer_val[5] ;
+ wire \u_riscv_top.core2_timer_val[60] ;
+ wire \u_riscv_top.core2_timer_val[61] ;
+ wire \u_riscv_top.core2_timer_val[62] ;
+ wire \u_riscv_top.core2_timer_val[63] ;
+ wire \u_riscv_top.core2_timer_val[6] ;
+ wire \u_riscv_top.core2_timer_val[7] ;
+ wire \u_riscv_top.core2_timer_val[8] ;
+ wire \u_riscv_top.core2_timer_val[9] ;
+ wire \u_riscv_top.core2_uid[0] ;
+ wire \u_riscv_top.core2_uid[1] ;
+ wire \u_riscv_top.core3_clk ;
+ wire \u_riscv_top.core3_debug[0] ;
+ wire \u_riscv_top.core3_debug[10] ;
+ wire \u_riscv_top.core3_debug[11] ;
+ wire \u_riscv_top.core3_debug[12] ;
+ wire \u_riscv_top.core3_debug[13] ;
+ wire \u_riscv_top.core3_debug[14] ;
+ wire \u_riscv_top.core3_debug[15] ;
+ wire \u_riscv_top.core3_debug[16] ;
+ wire \u_riscv_top.core3_debug[17] ;
+ wire \u_riscv_top.core3_debug[18] ;
+ wire \u_riscv_top.core3_debug[19] ;
+ wire \u_riscv_top.core3_debug[1] ;
+ wire \u_riscv_top.core3_debug[20] ;
+ wire \u_riscv_top.core3_debug[21] ;
+ wire \u_riscv_top.core3_debug[22] ;
+ wire \u_riscv_top.core3_debug[23] ;
+ wire \u_riscv_top.core3_debug[24] ;
+ wire \u_riscv_top.core3_debug[25] ;
+ wire \u_riscv_top.core3_debug[26] ;
+ wire \u_riscv_top.core3_debug[27] ;
+ wire \u_riscv_top.core3_debug[28] ;
+ wire \u_riscv_top.core3_debug[29] ;
+ wire \u_riscv_top.core3_debug[2] ;
+ wire \u_riscv_top.core3_debug[30] ;
+ wire \u_riscv_top.core3_debug[31] ;
+ wire \u_riscv_top.core3_debug[32] ;
+ wire \u_riscv_top.core3_debug[33] ;
+ wire \u_riscv_top.core3_debug[34] ;
+ wire \u_riscv_top.core3_debug[35] ;
+ wire \u_riscv_top.core3_debug[36] ;
+ wire \u_riscv_top.core3_debug[37] ;
+ wire \u_riscv_top.core3_debug[38] ;
+ wire \u_riscv_top.core3_debug[39] ;
+ wire \u_riscv_top.core3_debug[3] ;
+ wire \u_riscv_top.core3_debug[40] ;
+ wire \u_riscv_top.core3_debug[41] ;
+ wire \u_riscv_top.core3_debug[42] ;
+ wire \u_riscv_top.core3_debug[43] ;
+ wire \u_riscv_top.core3_debug[44] ;
+ wire \u_riscv_top.core3_debug[45] ;
+ wire \u_riscv_top.core3_debug[46] ;
+ wire \u_riscv_top.core3_debug[47] ;
+ wire \u_riscv_top.core3_debug[48] ;
+ wire \u_riscv_top.core3_debug[4] ;
+ wire \u_riscv_top.core3_debug[5] ;
+ wire \u_riscv_top.core3_debug[6] ;
+ wire \u_riscv_top.core3_debug[7] ;
+ wire \u_riscv_top.core3_debug[8] ;
+ wire \u_riscv_top.core3_debug[9] ;
+ wire \u_riscv_top.core3_dmem_addr[0] ;
+ wire \u_riscv_top.core3_dmem_addr[10] ;
+ wire \u_riscv_top.core3_dmem_addr[11] ;
+ wire \u_riscv_top.core3_dmem_addr[12] ;
+ wire \u_riscv_top.core3_dmem_addr[13] ;
+ wire \u_riscv_top.core3_dmem_addr[14] ;
+ wire \u_riscv_top.core3_dmem_addr[15] ;
+ wire \u_riscv_top.core3_dmem_addr[16] ;
+ wire \u_riscv_top.core3_dmem_addr[17] ;
+ wire \u_riscv_top.core3_dmem_addr[18] ;
+ wire \u_riscv_top.core3_dmem_addr[19] ;
+ wire \u_riscv_top.core3_dmem_addr[1] ;
+ wire \u_riscv_top.core3_dmem_addr[20] ;
+ wire \u_riscv_top.core3_dmem_addr[21] ;
+ wire \u_riscv_top.core3_dmem_addr[22] ;
+ wire \u_riscv_top.core3_dmem_addr[23] ;
+ wire \u_riscv_top.core3_dmem_addr[24] ;
+ wire \u_riscv_top.core3_dmem_addr[25] ;
+ wire \u_riscv_top.core3_dmem_addr[26] ;
+ wire \u_riscv_top.core3_dmem_addr[27] ;
+ wire \u_riscv_top.core3_dmem_addr[28] ;
+ wire \u_riscv_top.core3_dmem_addr[29] ;
+ wire \u_riscv_top.core3_dmem_addr[2] ;
+ wire \u_riscv_top.core3_dmem_addr[30] ;
+ wire \u_riscv_top.core3_dmem_addr[31] ;
+ wire \u_riscv_top.core3_dmem_addr[3] ;
+ wire \u_riscv_top.core3_dmem_addr[4] ;
+ wire \u_riscv_top.core3_dmem_addr[5] ;
+ wire \u_riscv_top.core3_dmem_addr[6] ;
+ wire \u_riscv_top.core3_dmem_addr[7] ;
+ wire \u_riscv_top.core3_dmem_addr[8] ;
+ wire \u_riscv_top.core3_dmem_addr[9] ;
+ wire \u_riscv_top.core3_dmem_cmd ;
+ wire \u_riscv_top.core3_dmem_rdata[0] ;
+ wire \u_riscv_top.core3_dmem_rdata[10] ;
+ wire \u_riscv_top.core3_dmem_rdata[11] ;
+ wire \u_riscv_top.core3_dmem_rdata[12] ;
+ wire \u_riscv_top.core3_dmem_rdata[13] ;
+ wire \u_riscv_top.core3_dmem_rdata[14] ;
+ wire \u_riscv_top.core3_dmem_rdata[15] ;
+ wire \u_riscv_top.core3_dmem_rdata[16] ;
+ wire \u_riscv_top.core3_dmem_rdata[17] ;
+ wire \u_riscv_top.core3_dmem_rdata[18] ;
+ wire \u_riscv_top.core3_dmem_rdata[19] ;
+ wire \u_riscv_top.core3_dmem_rdata[1] ;
+ wire \u_riscv_top.core3_dmem_rdata[20] ;
+ wire \u_riscv_top.core3_dmem_rdata[21] ;
+ wire \u_riscv_top.core3_dmem_rdata[22] ;
+ wire \u_riscv_top.core3_dmem_rdata[23] ;
+ wire \u_riscv_top.core3_dmem_rdata[24] ;
+ wire \u_riscv_top.core3_dmem_rdata[25] ;
+ wire \u_riscv_top.core3_dmem_rdata[26] ;
+ wire \u_riscv_top.core3_dmem_rdata[27] ;
+ wire \u_riscv_top.core3_dmem_rdata[28] ;
+ wire \u_riscv_top.core3_dmem_rdata[29] ;
+ wire \u_riscv_top.core3_dmem_rdata[2] ;
+ wire \u_riscv_top.core3_dmem_rdata[30] ;
+ wire \u_riscv_top.core3_dmem_rdata[31] ;
+ wire \u_riscv_top.core3_dmem_rdata[3] ;
+ wire \u_riscv_top.core3_dmem_rdata[4] ;
+ wire \u_riscv_top.core3_dmem_rdata[5] ;
+ wire \u_riscv_top.core3_dmem_rdata[6] ;
+ wire \u_riscv_top.core3_dmem_rdata[7] ;
+ wire \u_riscv_top.core3_dmem_rdata[8] ;
+ wire \u_riscv_top.core3_dmem_rdata[9] ;
+ wire \u_riscv_top.core3_dmem_req ;
+ wire \u_riscv_top.core3_dmem_req_ack ;
+ wire \u_riscv_top.core3_dmem_resp[0] ;
+ wire \u_riscv_top.core3_dmem_resp[1] ;
+ wire \u_riscv_top.core3_dmem_wdata[0] ;
+ wire \u_riscv_top.core3_dmem_wdata[10] ;
+ wire \u_riscv_top.core3_dmem_wdata[11] ;
+ wire \u_riscv_top.core3_dmem_wdata[12] ;
+ wire \u_riscv_top.core3_dmem_wdata[13] ;
+ wire \u_riscv_top.core3_dmem_wdata[14] ;
+ wire \u_riscv_top.core3_dmem_wdata[15] ;
+ wire \u_riscv_top.core3_dmem_wdata[16] ;
+ wire \u_riscv_top.core3_dmem_wdata[17] ;
+ wire \u_riscv_top.core3_dmem_wdata[18] ;
+ wire \u_riscv_top.core3_dmem_wdata[19] ;
+ wire \u_riscv_top.core3_dmem_wdata[1] ;
+ wire \u_riscv_top.core3_dmem_wdata[20] ;
+ wire \u_riscv_top.core3_dmem_wdata[21] ;
+ wire \u_riscv_top.core3_dmem_wdata[22] ;
+ wire \u_riscv_top.core3_dmem_wdata[23] ;
+ wire \u_riscv_top.core3_dmem_wdata[24] ;
+ wire \u_riscv_top.core3_dmem_wdata[25] ;
+ wire \u_riscv_top.core3_dmem_wdata[26] ;
+ wire \u_riscv_top.core3_dmem_wdata[27] ;
+ wire \u_riscv_top.core3_dmem_wdata[28] ;
+ wire \u_riscv_top.core3_dmem_wdata[29] ;
+ wire \u_riscv_top.core3_dmem_wdata[2] ;
+ wire \u_riscv_top.core3_dmem_wdata[30] ;
+ wire \u_riscv_top.core3_dmem_wdata[31] ;
+ wire \u_riscv_top.core3_dmem_wdata[3] ;
+ wire \u_riscv_top.core3_dmem_wdata[4] ;
+ wire \u_riscv_top.core3_dmem_wdata[5] ;
+ wire \u_riscv_top.core3_dmem_wdata[6] ;
+ wire \u_riscv_top.core3_dmem_wdata[7] ;
+ wire \u_riscv_top.core3_dmem_wdata[8] ;
+ wire \u_riscv_top.core3_dmem_wdata[9] ;
+ wire \u_riscv_top.core3_dmem_width[0] ;
+ wire \u_riscv_top.core3_dmem_width[1] ;
+ wire \u_riscv_top.core3_imem_addr[0] ;
+ wire \u_riscv_top.core3_imem_addr[10] ;
+ wire \u_riscv_top.core3_imem_addr[11] ;
+ wire \u_riscv_top.core3_imem_addr[12] ;
+ wire \u_riscv_top.core3_imem_addr[13] ;
+ wire \u_riscv_top.core3_imem_addr[14] ;
+ wire \u_riscv_top.core3_imem_addr[15] ;
+ wire \u_riscv_top.core3_imem_addr[16] ;
+ wire \u_riscv_top.core3_imem_addr[17] ;
+ wire \u_riscv_top.core3_imem_addr[18] ;
+ wire \u_riscv_top.core3_imem_addr[19] ;
+ wire \u_riscv_top.core3_imem_addr[1] ;
+ wire \u_riscv_top.core3_imem_addr[20] ;
+ wire \u_riscv_top.core3_imem_addr[21] ;
+ wire \u_riscv_top.core3_imem_addr[22] ;
+ wire \u_riscv_top.core3_imem_addr[23] ;
+ wire \u_riscv_top.core3_imem_addr[24] ;
+ wire \u_riscv_top.core3_imem_addr[25] ;
+ wire \u_riscv_top.core3_imem_addr[26] ;
+ wire \u_riscv_top.core3_imem_addr[27] ;
+ wire \u_riscv_top.core3_imem_addr[28] ;
+ wire \u_riscv_top.core3_imem_addr[29] ;
+ wire \u_riscv_top.core3_imem_addr[2] ;
+ wire \u_riscv_top.core3_imem_addr[30] ;
+ wire \u_riscv_top.core3_imem_addr[31] ;
+ wire \u_riscv_top.core3_imem_addr[3] ;
+ wire \u_riscv_top.core3_imem_addr[4] ;
+ wire \u_riscv_top.core3_imem_addr[5] ;
+ wire \u_riscv_top.core3_imem_addr[6] ;
+ wire \u_riscv_top.core3_imem_addr[7] ;
+ wire \u_riscv_top.core3_imem_addr[8] ;
+ wire \u_riscv_top.core3_imem_addr[9] ;
+ wire \u_riscv_top.core3_imem_bl[0] ;
+ wire \u_riscv_top.core3_imem_bl[1] ;
+ wire \u_riscv_top.core3_imem_bl[2] ;
+ wire \u_riscv_top.core3_imem_cmd ;
+ wire \u_riscv_top.core3_imem_rdata[0] ;
+ wire \u_riscv_top.core3_imem_rdata[10] ;
+ wire \u_riscv_top.core3_imem_rdata[11] ;
+ wire \u_riscv_top.core3_imem_rdata[12] ;
+ wire \u_riscv_top.core3_imem_rdata[13] ;
+ wire \u_riscv_top.core3_imem_rdata[14] ;
+ wire \u_riscv_top.core3_imem_rdata[15] ;
+ wire \u_riscv_top.core3_imem_rdata[16] ;
+ wire \u_riscv_top.core3_imem_rdata[17] ;
+ wire \u_riscv_top.core3_imem_rdata[18] ;
+ wire \u_riscv_top.core3_imem_rdata[19] ;
+ wire \u_riscv_top.core3_imem_rdata[1] ;
+ wire \u_riscv_top.core3_imem_rdata[20] ;
+ wire \u_riscv_top.core3_imem_rdata[21] ;
+ wire \u_riscv_top.core3_imem_rdata[22] ;
+ wire \u_riscv_top.core3_imem_rdata[23] ;
+ wire \u_riscv_top.core3_imem_rdata[24] ;
+ wire \u_riscv_top.core3_imem_rdata[25] ;
+ wire \u_riscv_top.core3_imem_rdata[26] ;
+ wire \u_riscv_top.core3_imem_rdata[27] ;
+ wire \u_riscv_top.core3_imem_rdata[28] ;
+ wire \u_riscv_top.core3_imem_rdata[29] ;
+ wire \u_riscv_top.core3_imem_rdata[2] ;
+ wire \u_riscv_top.core3_imem_rdata[30] ;
+ wire \u_riscv_top.core3_imem_rdata[31] ;
+ wire \u_riscv_top.core3_imem_rdata[3] ;
+ wire \u_riscv_top.core3_imem_rdata[4] ;
+ wire \u_riscv_top.core3_imem_rdata[5] ;
+ wire \u_riscv_top.core3_imem_rdata[6] ;
+ wire \u_riscv_top.core3_imem_rdata[7] ;
+ wire \u_riscv_top.core3_imem_rdata[8] ;
+ wire \u_riscv_top.core3_imem_rdata[9] ;
+ wire \u_riscv_top.core3_imem_req ;
+ wire \u_riscv_top.core3_imem_req_ack ;
+ wire \u_riscv_top.core3_imem_resp[0] ;
+ wire \u_riscv_top.core3_imem_resp[1] ;
+ wire \u_riscv_top.core3_irq_lines[0] ;
+ wire \u_riscv_top.core3_irq_lines[10] ;
+ wire \u_riscv_top.core3_irq_lines[11] ;
+ wire \u_riscv_top.core3_irq_lines[12] ;
+ wire \u_riscv_top.core3_irq_lines[13] ;
+ wire \u_riscv_top.core3_irq_lines[14] ;
+ wire \u_riscv_top.core3_irq_lines[15] ;
+ wire \u_riscv_top.core3_irq_lines[16] ;
+ wire \u_riscv_top.core3_irq_lines[17] ;
+ wire \u_riscv_top.core3_irq_lines[18] ;
+ wire \u_riscv_top.core3_irq_lines[19] ;
+ wire \u_riscv_top.core3_irq_lines[1] ;
+ wire \u_riscv_top.core3_irq_lines[20] ;
+ wire \u_riscv_top.core3_irq_lines[21] ;
+ wire \u_riscv_top.core3_irq_lines[22] ;
+ wire \u_riscv_top.core3_irq_lines[23] ;
+ wire \u_riscv_top.core3_irq_lines[24] ;
+ wire \u_riscv_top.core3_irq_lines[25] ;
+ wire \u_riscv_top.core3_irq_lines[26] ;
+ wire \u_riscv_top.core3_irq_lines[27] ;
+ wire \u_riscv_top.core3_irq_lines[28] ;
+ wire \u_riscv_top.core3_irq_lines[29] ;
+ wire \u_riscv_top.core3_irq_lines[2] ;
+ wire \u_riscv_top.core3_irq_lines[30] ;
+ wire \u_riscv_top.core3_irq_lines[31] ;
+ wire \u_riscv_top.core3_irq_lines[3] ;
+ wire \u_riscv_top.core3_irq_lines[4] ;
+ wire \u_riscv_top.core3_irq_lines[5] ;
+ wire \u_riscv_top.core3_irq_lines[6] ;
+ wire \u_riscv_top.core3_irq_lines[7] ;
+ wire \u_riscv_top.core3_irq_lines[8] ;
+ wire \u_riscv_top.core3_irq_lines[9] ;
+ wire \u_riscv_top.core3_soft_irq ;
+ wire \u_riscv_top.core3_timer_irq ;
+ wire \u_riscv_top.core3_timer_val[0] ;
+ wire \u_riscv_top.core3_timer_val[10] ;
+ wire \u_riscv_top.core3_timer_val[11] ;
+ wire \u_riscv_top.core3_timer_val[12] ;
+ wire \u_riscv_top.core3_timer_val[13] ;
+ wire \u_riscv_top.core3_timer_val[14] ;
+ wire \u_riscv_top.core3_timer_val[15] ;
+ wire \u_riscv_top.core3_timer_val[16] ;
+ wire \u_riscv_top.core3_timer_val[17] ;
+ wire \u_riscv_top.core3_timer_val[18] ;
+ wire \u_riscv_top.core3_timer_val[19] ;
+ wire \u_riscv_top.core3_timer_val[1] ;
+ wire \u_riscv_top.core3_timer_val[20] ;
+ wire \u_riscv_top.core3_timer_val[21] ;
+ wire \u_riscv_top.core3_timer_val[22] ;
+ wire \u_riscv_top.core3_timer_val[23] ;
+ wire \u_riscv_top.core3_timer_val[24] ;
+ wire \u_riscv_top.core3_timer_val[25] ;
+ wire \u_riscv_top.core3_timer_val[26] ;
+ wire \u_riscv_top.core3_timer_val[27] ;
+ wire \u_riscv_top.core3_timer_val[28] ;
+ wire \u_riscv_top.core3_timer_val[29] ;
+ wire \u_riscv_top.core3_timer_val[2] ;
+ wire \u_riscv_top.core3_timer_val[30] ;
+ wire \u_riscv_top.core3_timer_val[31] ;
+ wire \u_riscv_top.core3_timer_val[32] ;
+ wire \u_riscv_top.core3_timer_val[33] ;
+ wire \u_riscv_top.core3_timer_val[34] ;
+ wire \u_riscv_top.core3_timer_val[35] ;
+ wire \u_riscv_top.core3_timer_val[36] ;
+ wire \u_riscv_top.core3_timer_val[37] ;
+ wire \u_riscv_top.core3_timer_val[38] ;
+ wire \u_riscv_top.core3_timer_val[39] ;
+ wire \u_riscv_top.core3_timer_val[3] ;
+ wire \u_riscv_top.core3_timer_val[40] ;
+ wire \u_riscv_top.core3_timer_val[41] ;
+ wire \u_riscv_top.core3_timer_val[42] ;
+ wire \u_riscv_top.core3_timer_val[43] ;
+ wire \u_riscv_top.core3_timer_val[44] ;
+ wire \u_riscv_top.core3_timer_val[45] ;
+ wire \u_riscv_top.core3_timer_val[46] ;
+ wire \u_riscv_top.core3_timer_val[47] ;
+ wire \u_riscv_top.core3_timer_val[48] ;
+ wire \u_riscv_top.core3_timer_val[49] ;
+ wire \u_riscv_top.core3_timer_val[4] ;
+ wire \u_riscv_top.core3_timer_val[50] ;
+ wire \u_riscv_top.core3_timer_val[51] ;
+ wire \u_riscv_top.core3_timer_val[52] ;
+ wire \u_riscv_top.core3_timer_val[53] ;
+ wire \u_riscv_top.core3_timer_val[54] ;
+ wire \u_riscv_top.core3_timer_val[55] ;
+ wire \u_riscv_top.core3_timer_val[56] ;
+ wire \u_riscv_top.core3_timer_val[57] ;
+ wire \u_riscv_top.core3_timer_val[58] ;
+ wire \u_riscv_top.core3_timer_val[59] ;
+ wire \u_riscv_top.core3_timer_val[5] ;
+ wire \u_riscv_top.core3_timer_val[60] ;
+ wire \u_riscv_top.core3_timer_val[61] ;
+ wire \u_riscv_top.core3_timer_val[62] ;
+ wire \u_riscv_top.core3_timer_val[63] ;
+ wire \u_riscv_top.core3_timer_val[6] ;
+ wire \u_riscv_top.core3_timer_val[7] ;
+ wire \u_riscv_top.core3_timer_val[8] ;
+ wire \u_riscv_top.core3_timer_val[9] ;
+ wire \u_riscv_top.core3_uid[0] ;
+ wire \u_riscv_top.core3_uid[1] ;
+ wire \u_riscv_top.core_clk_core0_skew ;
+ wire \u_riscv_top.core_clk_core1_skew ;
+ wire \u_riscv_top.core_clk_core2_skew ;
+ wire \u_riscv_top.core_clk_core3_skew ;
+ wire \u_riscv_top.core_clk_icon_skew ;
+ wire \u_riscv_top.core_clk_int[0] ;
+ wire \u_riscv_top.core_clk_int[1] ;
+ wire \u_riscv_top.core_clk_intf_skew ;
+ wire \u_riscv_top.core_clk_out[0] ;
+ wire \u_riscv_top.core_clk_out[1] ;
+ wire \u_riscv_top.core_clk_out[2] ;
+ wire \u_riscv_top.core_clk_out[3] ;
+ wire \u_riscv_top.core_dcache_addr[0] ;
+ wire \u_riscv_top.core_dcache_addr[10] ;
+ wire \u_riscv_top.core_dcache_addr[11] ;
+ wire \u_riscv_top.core_dcache_addr[12] ;
+ wire \u_riscv_top.core_dcache_addr[13] ;
+ wire \u_riscv_top.core_dcache_addr[14] ;
+ wire \u_riscv_top.core_dcache_addr[15] ;
+ wire \u_riscv_top.core_dcache_addr[16] ;
+ wire \u_riscv_top.core_dcache_addr[17] ;
+ wire \u_riscv_top.core_dcache_addr[18] ;
+ wire \u_riscv_top.core_dcache_addr[19] ;
+ wire \u_riscv_top.core_dcache_addr[1] ;
+ wire \u_riscv_top.core_dcache_addr[20] ;
+ wire \u_riscv_top.core_dcache_addr[21] ;
+ wire \u_riscv_top.core_dcache_addr[22] ;
+ wire \u_riscv_top.core_dcache_addr[23] ;
+ wire \u_riscv_top.core_dcache_addr[24] ;
+ wire \u_riscv_top.core_dcache_addr[25] ;
+ wire \u_riscv_top.core_dcache_addr[26] ;
+ wire \u_riscv_top.core_dcache_addr[27] ;
+ wire \u_riscv_top.core_dcache_addr[28] ;
+ wire \u_riscv_top.core_dcache_addr[29] ;
+ wire \u_riscv_top.core_dcache_addr[2] ;
+ wire \u_riscv_top.core_dcache_addr[30] ;
+ wire \u_riscv_top.core_dcache_addr[31] ;
+ wire \u_riscv_top.core_dcache_addr[3] ;
+ wire \u_riscv_top.core_dcache_addr[4] ;
+ wire \u_riscv_top.core_dcache_addr[5] ;
+ wire \u_riscv_top.core_dcache_addr[6] ;
+ wire \u_riscv_top.core_dcache_addr[7] ;
+ wire \u_riscv_top.core_dcache_addr[8] ;
+ wire \u_riscv_top.core_dcache_addr[9] ;
+ wire \u_riscv_top.core_dcache_cmd ;
+ wire \u_riscv_top.core_dcache_rdata[0] ;
+ wire \u_riscv_top.core_dcache_rdata[10] ;
+ wire \u_riscv_top.core_dcache_rdata[11] ;
+ wire \u_riscv_top.core_dcache_rdata[12] ;
+ wire \u_riscv_top.core_dcache_rdata[13] ;
+ wire \u_riscv_top.core_dcache_rdata[14] ;
+ wire \u_riscv_top.core_dcache_rdata[15] ;
+ wire \u_riscv_top.core_dcache_rdata[16] ;
+ wire \u_riscv_top.core_dcache_rdata[17] ;
+ wire \u_riscv_top.core_dcache_rdata[18] ;
+ wire \u_riscv_top.core_dcache_rdata[19] ;
+ wire \u_riscv_top.core_dcache_rdata[1] ;
+ wire \u_riscv_top.core_dcache_rdata[20] ;
+ wire \u_riscv_top.core_dcache_rdata[21] ;
+ wire \u_riscv_top.core_dcache_rdata[22] ;
+ wire \u_riscv_top.core_dcache_rdata[23] ;
+ wire \u_riscv_top.core_dcache_rdata[24] ;
+ wire \u_riscv_top.core_dcache_rdata[25] ;
+ wire \u_riscv_top.core_dcache_rdata[26] ;
+ wire \u_riscv_top.core_dcache_rdata[27] ;
+ wire \u_riscv_top.core_dcache_rdata[28] ;
+ wire \u_riscv_top.core_dcache_rdata[29] ;
+ wire \u_riscv_top.core_dcache_rdata[2] ;
+ wire \u_riscv_top.core_dcache_rdata[30] ;
+ wire \u_riscv_top.core_dcache_rdata[31] ;
+ wire \u_riscv_top.core_dcache_rdata[3] ;
+ wire \u_riscv_top.core_dcache_rdata[4] ;
+ wire \u_riscv_top.core_dcache_rdata[5] ;
+ wire \u_riscv_top.core_dcache_rdata[6] ;
+ wire \u_riscv_top.core_dcache_rdata[7] ;
+ wire \u_riscv_top.core_dcache_rdata[8] ;
+ wire \u_riscv_top.core_dcache_rdata[9] ;
+ wire \u_riscv_top.core_dcache_req ;
+ wire \u_riscv_top.core_dcache_req_ack ;
+ wire \u_riscv_top.core_dcache_resp[0] ;
+ wire \u_riscv_top.core_dcache_resp[1] ;
+ wire \u_riscv_top.core_dcache_wdata[0] ;
+ wire \u_riscv_top.core_dcache_wdata[10] ;
+ wire \u_riscv_top.core_dcache_wdata[11] ;
+ wire \u_riscv_top.core_dcache_wdata[12] ;
+ wire \u_riscv_top.core_dcache_wdata[13] ;
+ wire \u_riscv_top.core_dcache_wdata[14] ;
+ wire \u_riscv_top.core_dcache_wdata[15] ;
+ wire \u_riscv_top.core_dcache_wdata[16] ;
+ wire \u_riscv_top.core_dcache_wdata[17] ;
+ wire \u_riscv_top.core_dcache_wdata[18] ;
+ wire \u_riscv_top.core_dcache_wdata[19] ;
+ wire \u_riscv_top.core_dcache_wdata[1] ;
+ wire \u_riscv_top.core_dcache_wdata[20] ;
+ wire \u_riscv_top.core_dcache_wdata[21] ;
+ wire \u_riscv_top.core_dcache_wdata[22] ;
+ wire \u_riscv_top.core_dcache_wdata[23] ;
+ wire \u_riscv_top.core_dcache_wdata[24] ;
+ wire \u_riscv_top.core_dcache_wdata[25] ;
+ wire \u_riscv_top.core_dcache_wdata[26] ;
+ wire \u_riscv_top.core_dcache_wdata[27] ;
+ wire \u_riscv_top.core_dcache_wdata[28] ;
+ wire \u_riscv_top.core_dcache_wdata[29] ;
+ wire \u_riscv_top.core_dcache_wdata[2] ;
+ wire \u_riscv_top.core_dcache_wdata[30] ;
+ wire \u_riscv_top.core_dcache_wdata[31] ;
+ wire \u_riscv_top.core_dcache_wdata[3] ;
+ wire \u_riscv_top.core_dcache_wdata[4] ;
+ wire \u_riscv_top.core_dcache_wdata[5] ;
+ wire \u_riscv_top.core_dcache_wdata[6] ;
+ wire \u_riscv_top.core_dcache_wdata[7] ;
+ wire \u_riscv_top.core_dcache_wdata[8] ;
+ wire \u_riscv_top.core_dcache_wdata[9] ;
+ wire \u_riscv_top.core_dcache_width[0] ;
+ wire \u_riscv_top.core_dcache_width[1] ;
+ wire \u_riscv_top.core_dmem_addr[0] ;
+ wire \u_riscv_top.core_dmem_addr[10] ;
+ wire \u_riscv_top.core_dmem_addr[11] ;
+ wire \u_riscv_top.core_dmem_addr[12] ;
+ wire \u_riscv_top.core_dmem_addr[13] ;
+ wire \u_riscv_top.core_dmem_addr[14] ;
+ wire \u_riscv_top.core_dmem_addr[15] ;
+ wire \u_riscv_top.core_dmem_addr[16] ;
+ wire \u_riscv_top.core_dmem_addr[17] ;
+ wire \u_riscv_top.core_dmem_addr[18] ;
+ wire \u_riscv_top.core_dmem_addr[19] ;
+ wire \u_riscv_top.core_dmem_addr[1] ;
+ wire \u_riscv_top.core_dmem_addr[20] ;
+ wire \u_riscv_top.core_dmem_addr[21] ;
+ wire \u_riscv_top.core_dmem_addr[22] ;
+ wire \u_riscv_top.core_dmem_addr[23] ;
+ wire \u_riscv_top.core_dmem_addr[24] ;
+ wire \u_riscv_top.core_dmem_addr[25] ;
+ wire \u_riscv_top.core_dmem_addr[26] ;
+ wire \u_riscv_top.core_dmem_addr[27] ;
+ wire \u_riscv_top.core_dmem_addr[28] ;
+ wire \u_riscv_top.core_dmem_addr[29] ;
+ wire \u_riscv_top.core_dmem_addr[2] ;
+ wire \u_riscv_top.core_dmem_addr[30] ;
+ wire \u_riscv_top.core_dmem_addr[31] ;
+ wire \u_riscv_top.core_dmem_addr[3] ;
+ wire \u_riscv_top.core_dmem_addr[4] ;
+ wire \u_riscv_top.core_dmem_addr[5] ;
+ wire \u_riscv_top.core_dmem_addr[6] ;
+ wire \u_riscv_top.core_dmem_addr[7] ;
+ wire \u_riscv_top.core_dmem_addr[8] ;
+ wire \u_riscv_top.core_dmem_addr[9] ;
+ wire \u_riscv_top.core_dmem_bl[0] ;
+ wire \u_riscv_top.core_dmem_bl[1] ;
+ wire \u_riscv_top.core_dmem_bl[2] ;
+ wire \u_riscv_top.core_dmem_cmd ;
+ wire \u_riscv_top.core_dmem_rdata[0] ;
+ wire \u_riscv_top.core_dmem_rdata[10] ;
+ wire \u_riscv_top.core_dmem_rdata[11] ;
+ wire \u_riscv_top.core_dmem_rdata[12] ;
+ wire \u_riscv_top.core_dmem_rdata[13] ;
+ wire \u_riscv_top.core_dmem_rdata[14] ;
+ wire \u_riscv_top.core_dmem_rdata[15] ;
+ wire \u_riscv_top.core_dmem_rdata[16] ;
+ wire \u_riscv_top.core_dmem_rdata[17] ;
+ wire \u_riscv_top.core_dmem_rdata[18] ;
+ wire \u_riscv_top.core_dmem_rdata[19] ;
+ wire \u_riscv_top.core_dmem_rdata[1] ;
+ wire \u_riscv_top.core_dmem_rdata[20] ;
+ wire \u_riscv_top.core_dmem_rdata[21] ;
+ wire \u_riscv_top.core_dmem_rdata[22] ;
+ wire \u_riscv_top.core_dmem_rdata[23] ;
+ wire \u_riscv_top.core_dmem_rdata[24] ;
+ wire \u_riscv_top.core_dmem_rdata[25] ;
+ wire \u_riscv_top.core_dmem_rdata[26] ;
+ wire \u_riscv_top.core_dmem_rdata[27] ;
+ wire \u_riscv_top.core_dmem_rdata[28] ;
+ wire \u_riscv_top.core_dmem_rdata[29] ;
+ wire \u_riscv_top.core_dmem_rdata[2] ;
+ wire \u_riscv_top.core_dmem_rdata[30] ;
+ wire \u_riscv_top.core_dmem_rdata[31] ;
+ wire \u_riscv_top.core_dmem_rdata[3] ;
+ wire \u_riscv_top.core_dmem_rdata[4] ;
+ wire \u_riscv_top.core_dmem_rdata[5] ;
+ wire \u_riscv_top.core_dmem_rdata[6] ;
+ wire \u_riscv_top.core_dmem_rdata[7] ;
+ wire \u_riscv_top.core_dmem_rdata[8] ;
+ wire \u_riscv_top.core_dmem_rdata[9] ;
+ wire \u_riscv_top.core_dmem_req ;
+ wire \u_riscv_top.core_dmem_req_ack ;
+ wire \u_riscv_top.core_dmem_resp[0] ;
+ wire \u_riscv_top.core_dmem_resp[1] ;
+ wire \u_riscv_top.core_dmem_wdata[0] ;
+ wire \u_riscv_top.core_dmem_wdata[10] ;
+ wire \u_riscv_top.core_dmem_wdata[11] ;
+ wire \u_riscv_top.core_dmem_wdata[12] ;
+ wire \u_riscv_top.core_dmem_wdata[13] ;
+ wire \u_riscv_top.core_dmem_wdata[14] ;
+ wire \u_riscv_top.core_dmem_wdata[15] ;
+ wire \u_riscv_top.core_dmem_wdata[16] ;
+ wire \u_riscv_top.core_dmem_wdata[17] ;
+ wire \u_riscv_top.core_dmem_wdata[18] ;
+ wire \u_riscv_top.core_dmem_wdata[19] ;
+ wire \u_riscv_top.core_dmem_wdata[1] ;
+ wire \u_riscv_top.core_dmem_wdata[20] ;
+ wire \u_riscv_top.core_dmem_wdata[21] ;
+ wire \u_riscv_top.core_dmem_wdata[22] ;
+ wire \u_riscv_top.core_dmem_wdata[23] ;
+ wire \u_riscv_top.core_dmem_wdata[24] ;
+ wire \u_riscv_top.core_dmem_wdata[25] ;
+ wire \u_riscv_top.core_dmem_wdata[26] ;
+ wire \u_riscv_top.core_dmem_wdata[27] ;
+ wire \u_riscv_top.core_dmem_wdata[28] ;
+ wire \u_riscv_top.core_dmem_wdata[29] ;
+ wire \u_riscv_top.core_dmem_wdata[2] ;
+ wire \u_riscv_top.core_dmem_wdata[30] ;
+ wire \u_riscv_top.core_dmem_wdata[31] ;
+ wire \u_riscv_top.core_dmem_wdata[3] ;
+ wire \u_riscv_top.core_dmem_wdata[4] ;
+ wire \u_riscv_top.core_dmem_wdata[5] ;
+ wire \u_riscv_top.core_dmem_wdata[6] ;
+ wire \u_riscv_top.core_dmem_wdata[7] ;
+ wire \u_riscv_top.core_dmem_wdata[8] ;
+ wire \u_riscv_top.core_dmem_wdata[9] ;
+ wire \u_riscv_top.core_dmem_width[0] ;
+ wire \u_riscv_top.core_dmem_width[1] ;
+ wire \u_riscv_top.core_icache_addr[0] ;
+ wire \u_riscv_top.core_icache_addr[10] ;
+ wire \u_riscv_top.core_icache_addr[11] ;
+ wire \u_riscv_top.core_icache_addr[12] ;
+ wire \u_riscv_top.core_icache_addr[13] ;
+ wire \u_riscv_top.core_icache_addr[14] ;
+ wire \u_riscv_top.core_icache_addr[15] ;
+ wire \u_riscv_top.core_icache_addr[16] ;
+ wire \u_riscv_top.core_icache_addr[17] ;
+ wire \u_riscv_top.core_icache_addr[18] ;
+ wire \u_riscv_top.core_icache_addr[19] ;
+ wire \u_riscv_top.core_icache_addr[1] ;
+ wire \u_riscv_top.core_icache_addr[20] ;
+ wire \u_riscv_top.core_icache_addr[21] ;
+ wire \u_riscv_top.core_icache_addr[22] ;
+ wire \u_riscv_top.core_icache_addr[23] ;
+ wire \u_riscv_top.core_icache_addr[24] ;
+ wire \u_riscv_top.core_icache_addr[25] ;
+ wire \u_riscv_top.core_icache_addr[26] ;
+ wire \u_riscv_top.core_icache_addr[27] ;
+ wire \u_riscv_top.core_icache_addr[28] ;
+ wire \u_riscv_top.core_icache_addr[29] ;
+ wire \u_riscv_top.core_icache_addr[2] ;
+ wire \u_riscv_top.core_icache_addr[30] ;
+ wire \u_riscv_top.core_icache_addr[31] ;
+ wire \u_riscv_top.core_icache_addr[3] ;
+ wire \u_riscv_top.core_icache_addr[4] ;
+ wire \u_riscv_top.core_icache_addr[5] ;
+ wire \u_riscv_top.core_icache_addr[6] ;
+ wire \u_riscv_top.core_icache_addr[7] ;
+ wire \u_riscv_top.core_icache_addr[8] ;
+ wire \u_riscv_top.core_icache_addr[9] ;
+ wire \u_riscv_top.core_icache_bl[0] ;
+ wire \u_riscv_top.core_icache_bl[1] ;
+ wire \u_riscv_top.core_icache_bl[2] ;
+ wire \u_riscv_top.core_icache_cmd ;
+ wire \u_riscv_top.core_icache_rdata[0] ;
+ wire \u_riscv_top.core_icache_rdata[10] ;
+ wire \u_riscv_top.core_icache_rdata[11] ;
+ wire \u_riscv_top.core_icache_rdata[12] ;
+ wire \u_riscv_top.core_icache_rdata[13] ;
+ wire \u_riscv_top.core_icache_rdata[14] ;
+ wire \u_riscv_top.core_icache_rdata[15] ;
+ wire \u_riscv_top.core_icache_rdata[16] ;
+ wire \u_riscv_top.core_icache_rdata[17] ;
+ wire \u_riscv_top.core_icache_rdata[18] ;
+ wire \u_riscv_top.core_icache_rdata[19] ;
+ wire \u_riscv_top.core_icache_rdata[1] ;
+ wire \u_riscv_top.core_icache_rdata[20] ;
+ wire \u_riscv_top.core_icache_rdata[21] ;
+ wire \u_riscv_top.core_icache_rdata[22] ;
+ wire \u_riscv_top.core_icache_rdata[23] ;
+ wire \u_riscv_top.core_icache_rdata[24] ;
+ wire \u_riscv_top.core_icache_rdata[25] ;
+ wire \u_riscv_top.core_icache_rdata[26] ;
+ wire \u_riscv_top.core_icache_rdata[27] ;
+ wire \u_riscv_top.core_icache_rdata[28] ;
+ wire \u_riscv_top.core_icache_rdata[29] ;
+ wire \u_riscv_top.core_icache_rdata[2] ;
+ wire \u_riscv_top.core_icache_rdata[30] ;
+ wire \u_riscv_top.core_icache_rdata[31] ;
+ wire \u_riscv_top.core_icache_rdata[3] ;
+ wire \u_riscv_top.core_icache_rdata[4] ;
+ wire \u_riscv_top.core_icache_rdata[5] ;
+ wire \u_riscv_top.core_icache_rdata[6] ;
+ wire \u_riscv_top.core_icache_rdata[7] ;
+ wire \u_riscv_top.core_icache_rdata[8] ;
+ wire \u_riscv_top.core_icache_rdata[9] ;
+ wire \u_riscv_top.core_icache_req ;
+ wire \u_riscv_top.core_icache_req_ack ;
+ wire \u_riscv_top.core_icache_resp[0] ;
+ wire \u_riscv_top.core_icache_resp[1] ;
+ wire \u_riscv_top.core_icache_width[0] ;
+ wire \u_riscv_top.core_icache_width[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[0] ;
+ wire \u_riscv_top.cpu_core_rst_n[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[2] ;
+ wire \u_riscv_top.cpu_core_rst_n[3] ;
+ wire \u_riscv_top.cpu_intf_rst_n ;
+ wire \u_riscv_top.dcache_mem_addr0[0] ;
+ wire \u_riscv_top.dcache_mem_addr0[1] ;
+ wire \u_riscv_top.dcache_mem_addr0[2] ;
+ wire \u_riscv_top.dcache_mem_addr0[3] ;
+ wire \u_riscv_top.dcache_mem_addr0[4] ;
+ wire \u_riscv_top.dcache_mem_addr0[5] ;
+ wire \u_riscv_top.dcache_mem_addr0[6] ;
+ wire \u_riscv_top.dcache_mem_addr0[7] ;
+ wire \u_riscv_top.dcache_mem_addr0[8] ;
+ wire \u_riscv_top.dcache_mem_addr1[0] ;
+ wire \u_riscv_top.dcache_mem_addr1[1] ;
+ wire \u_riscv_top.dcache_mem_addr1[2] ;
+ wire \u_riscv_top.dcache_mem_addr1[3] ;
+ wire \u_riscv_top.dcache_mem_addr1[4] ;
+ wire \u_riscv_top.dcache_mem_addr1[5] ;
+ wire \u_riscv_top.dcache_mem_addr1[6] ;
+ wire \u_riscv_top.dcache_mem_addr1[7] ;
+ wire \u_riscv_top.dcache_mem_addr1[8] ;
+ wire \u_riscv_top.dcache_mem_clk0 ;
+ wire \u_riscv_top.dcache_mem_clk1 ;
+ wire \u_riscv_top.dcache_mem_csb0 ;
+ wire \u_riscv_top.dcache_mem_csb1 ;
+ wire \u_riscv_top.dcache_mem_din0[0] ;
+ wire \u_riscv_top.dcache_mem_din0[10] ;
+ wire \u_riscv_top.dcache_mem_din0[11] ;
+ wire \u_riscv_top.dcache_mem_din0[12] ;
+ wire \u_riscv_top.dcache_mem_din0[13] ;
+ wire \u_riscv_top.dcache_mem_din0[14] ;
+ wire \u_riscv_top.dcache_mem_din0[15] ;
+ wire \u_riscv_top.dcache_mem_din0[16] ;
+ wire \u_riscv_top.dcache_mem_din0[17] ;
+ wire \u_riscv_top.dcache_mem_din0[18] ;
+ wire \u_riscv_top.dcache_mem_din0[19] ;
+ wire \u_riscv_top.dcache_mem_din0[1] ;
+ wire \u_riscv_top.dcache_mem_din0[20] ;
+ wire \u_riscv_top.dcache_mem_din0[21] ;
+ wire \u_riscv_top.dcache_mem_din0[22] ;
+ wire \u_riscv_top.dcache_mem_din0[23] ;
+ wire \u_riscv_top.dcache_mem_din0[24] ;
+ wire \u_riscv_top.dcache_mem_din0[25] ;
+ wire \u_riscv_top.dcache_mem_din0[26] ;
+ wire \u_riscv_top.dcache_mem_din0[27] ;
+ wire \u_riscv_top.dcache_mem_din0[28] ;
+ wire \u_riscv_top.dcache_mem_din0[29] ;
+ wire \u_riscv_top.dcache_mem_din0[2] ;
+ wire \u_riscv_top.dcache_mem_din0[30] ;
+ wire \u_riscv_top.dcache_mem_din0[31] ;
+ wire \u_riscv_top.dcache_mem_din0[3] ;
+ wire \u_riscv_top.dcache_mem_din0[4] ;
+ wire \u_riscv_top.dcache_mem_din0[5] ;
+ wire \u_riscv_top.dcache_mem_din0[6] ;
+ wire \u_riscv_top.dcache_mem_din0[7] ;
+ wire \u_riscv_top.dcache_mem_din0[8] ;
+ wire \u_riscv_top.dcache_mem_din0[9] ;
+ wire \u_riscv_top.dcache_mem_dout0[0] ;
+ wire \u_riscv_top.dcache_mem_dout0[10] ;
+ wire \u_riscv_top.dcache_mem_dout0[11] ;
+ wire \u_riscv_top.dcache_mem_dout0[12] ;
+ wire \u_riscv_top.dcache_mem_dout0[13] ;
+ wire \u_riscv_top.dcache_mem_dout0[14] ;
+ wire \u_riscv_top.dcache_mem_dout0[15] ;
+ wire \u_riscv_top.dcache_mem_dout0[16] ;
+ wire \u_riscv_top.dcache_mem_dout0[17] ;
+ wire \u_riscv_top.dcache_mem_dout0[18] ;
+ wire \u_riscv_top.dcache_mem_dout0[19] ;
+ wire \u_riscv_top.dcache_mem_dout0[1] ;
+ wire \u_riscv_top.dcache_mem_dout0[20] ;
+ wire \u_riscv_top.dcache_mem_dout0[21] ;
+ wire \u_riscv_top.dcache_mem_dout0[22] ;
+ wire \u_riscv_top.dcache_mem_dout0[23] ;
+ wire \u_riscv_top.dcache_mem_dout0[24] ;
+ wire \u_riscv_top.dcache_mem_dout0[25] ;
+ wire \u_riscv_top.dcache_mem_dout0[26] ;
+ wire \u_riscv_top.dcache_mem_dout0[27] ;
+ wire \u_riscv_top.dcache_mem_dout0[28] ;
+ wire \u_riscv_top.dcache_mem_dout0[29] ;
+ wire \u_riscv_top.dcache_mem_dout0[2] ;
+ wire \u_riscv_top.dcache_mem_dout0[30] ;
+ wire \u_riscv_top.dcache_mem_dout0[31] ;
+ wire \u_riscv_top.dcache_mem_dout0[3] ;
+ wire \u_riscv_top.dcache_mem_dout0[4] ;
+ wire \u_riscv_top.dcache_mem_dout0[5] ;
+ wire \u_riscv_top.dcache_mem_dout0[6] ;
+ wire \u_riscv_top.dcache_mem_dout0[7] ;
+ wire \u_riscv_top.dcache_mem_dout0[8] ;
+ wire \u_riscv_top.dcache_mem_dout0[9] ;
+ wire \u_riscv_top.dcache_mem_dout1[0] ;
+ wire \u_riscv_top.dcache_mem_dout1[10] ;
+ wire \u_riscv_top.dcache_mem_dout1[11] ;
+ wire \u_riscv_top.dcache_mem_dout1[12] ;
+ wire \u_riscv_top.dcache_mem_dout1[13] ;
+ wire \u_riscv_top.dcache_mem_dout1[14] ;
+ wire \u_riscv_top.dcache_mem_dout1[15] ;
+ wire \u_riscv_top.dcache_mem_dout1[16] ;
+ wire \u_riscv_top.dcache_mem_dout1[17] ;
+ wire \u_riscv_top.dcache_mem_dout1[18] ;
+ wire \u_riscv_top.dcache_mem_dout1[19] ;
+ wire \u_riscv_top.dcache_mem_dout1[1] ;
+ wire \u_riscv_top.dcache_mem_dout1[20] ;
+ wire \u_riscv_top.dcache_mem_dout1[21] ;
+ wire \u_riscv_top.dcache_mem_dout1[22] ;
+ wire \u_riscv_top.dcache_mem_dout1[23] ;
+ wire \u_riscv_top.dcache_mem_dout1[24] ;
+ wire \u_riscv_top.dcache_mem_dout1[25] ;
+ wire \u_riscv_top.dcache_mem_dout1[26] ;
+ wire \u_riscv_top.dcache_mem_dout1[27] ;
+ wire \u_riscv_top.dcache_mem_dout1[28] ;
+ wire \u_riscv_top.dcache_mem_dout1[29] ;
+ wire \u_riscv_top.dcache_mem_dout1[2] ;
+ wire \u_riscv_top.dcache_mem_dout1[30] ;
+ wire \u_riscv_top.dcache_mem_dout1[31] ;
+ wire \u_riscv_top.dcache_mem_dout1[3] ;
+ wire \u_riscv_top.dcache_mem_dout1[4] ;
+ wire \u_riscv_top.dcache_mem_dout1[5] ;
+ wire \u_riscv_top.dcache_mem_dout1[6] ;
+ wire \u_riscv_top.dcache_mem_dout1[7] ;
+ wire \u_riscv_top.dcache_mem_dout1[8] ;
+ wire \u_riscv_top.dcache_mem_dout1[9] ;
+ wire \u_riscv_top.dcache_mem_web0 ;
+ wire \u_riscv_top.dcache_mem_wmask0[0] ;
+ wire \u_riscv_top.dcache_mem_wmask0[1] ;
+ wire \u_riscv_top.dcache_mem_wmask0[2] ;
+ wire \u_riscv_top.dcache_mem_wmask0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[0] ;
+ wire \u_riscv_top.icache_mem_addr0[1] ;
+ wire \u_riscv_top.icache_mem_addr0[2] ;
+ wire \u_riscv_top.icache_mem_addr0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[4] ;
+ wire \u_riscv_top.icache_mem_addr0[5] ;
+ wire \u_riscv_top.icache_mem_addr0[6] ;
+ wire \u_riscv_top.icache_mem_addr0[7] ;
+ wire \u_riscv_top.icache_mem_addr0[8] ;
+ wire \u_riscv_top.icache_mem_addr1[0] ;
+ wire \u_riscv_top.icache_mem_addr1[1] ;
+ wire \u_riscv_top.icache_mem_addr1[2] ;
+ wire \u_riscv_top.icache_mem_addr1[3] ;
+ wire \u_riscv_top.icache_mem_addr1[4] ;
+ wire \u_riscv_top.icache_mem_addr1[5] ;
+ wire \u_riscv_top.icache_mem_addr1[6] ;
+ wire \u_riscv_top.icache_mem_addr1[7] ;
+ wire \u_riscv_top.icache_mem_addr1[8] ;
+ wire \u_riscv_top.icache_mem_clk0 ;
+ wire \u_riscv_top.icache_mem_clk1 ;
+ wire \u_riscv_top.icache_mem_csb0 ;
+ wire \u_riscv_top.icache_mem_csb1 ;
+ wire \u_riscv_top.icache_mem_din0[0] ;
+ wire \u_riscv_top.icache_mem_din0[10] ;
+ wire \u_riscv_top.icache_mem_din0[11] ;
+ wire \u_riscv_top.icache_mem_din0[12] ;
+ wire \u_riscv_top.icache_mem_din0[13] ;
+ wire \u_riscv_top.icache_mem_din0[14] ;
+ wire \u_riscv_top.icache_mem_din0[15] ;
+ wire \u_riscv_top.icache_mem_din0[16] ;
+ wire \u_riscv_top.icache_mem_din0[17] ;
+ wire \u_riscv_top.icache_mem_din0[18] ;
+ wire \u_riscv_top.icache_mem_din0[19] ;
+ wire \u_riscv_top.icache_mem_din0[1] ;
+ wire \u_riscv_top.icache_mem_din0[20] ;
+ wire \u_riscv_top.icache_mem_din0[21] ;
+ wire \u_riscv_top.icache_mem_din0[22] ;
+ wire \u_riscv_top.icache_mem_din0[23] ;
+ wire \u_riscv_top.icache_mem_din0[24] ;
+ wire \u_riscv_top.icache_mem_din0[25] ;
+ wire \u_riscv_top.icache_mem_din0[26] ;
+ wire \u_riscv_top.icache_mem_din0[27] ;
+ wire \u_riscv_top.icache_mem_din0[28] ;
+ wire \u_riscv_top.icache_mem_din0[29] ;
+ wire \u_riscv_top.icache_mem_din0[2] ;
+ wire \u_riscv_top.icache_mem_din0[30] ;
+ wire \u_riscv_top.icache_mem_din0[31] ;
+ wire \u_riscv_top.icache_mem_din0[3] ;
+ wire \u_riscv_top.icache_mem_din0[4] ;
+ wire \u_riscv_top.icache_mem_din0[5] ;
+ wire \u_riscv_top.icache_mem_din0[6] ;
+ wire \u_riscv_top.icache_mem_din0[7] ;
+ wire \u_riscv_top.icache_mem_din0[8] ;
+ wire \u_riscv_top.icache_mem_din0[9] ;
+ wire \u_riscv_top.icache_mem_dout1[0] ;
+ wire \u_riscv_top.icache_mem_dout1[10] ;
+ wire \u_riscv_top.icache_mem_dout1[11] ;
+ wire \u_riscv_top.icache_mem_dout1[12] ;
+ wire \u_riscv_top.icache_mem_dout1[13] ;
+ wire \u_riscv_top.icache_mem_dout1[14] ;
+ wire \u_riscv_top.icache_mem_dout1[15] ;
+ wire \u_riscv_top.icache_mem_dout1[16] ;
+ wire \u_riscv_top.icache_mem_dout1[17] ;
+ wire \u_riscv_top.icache_mem_dout1[18] ;
+ wire \u_riscv_top.icache_mem_dout1[19] ;
+ wire \u_riscv_top.icache_mem_dout1[1] ;
+ wire \u_riscv_top.icache_mem_dout1[20] ;
+ wire \u_riscv_top.icache_mem_dout1[21] ;
+ wire \u_riscv_top.icache_mem_dout1[22] ;
+ wire \u_riscv_top.icache_mem_dout1[23] ;
+ wire \u_riscv_top.icache_mem_dout1[24] ;
+ wire \u_riscv_top.icache_mem_dout1[25] ;
+ wire \u_riscv_top.icache_mem_dout1[26] ;
+ wire \u_riscv_top.icache_mem_dout1[27] ;
+ wire \u_riscv_top.icache_mem_dout1[28] ;
+ wire \u_riscv_top.icache_mem_dout1[29] ;
+ wire \u_riscv_top.icache_mem_dout1[2] ;
+ wire \u_riscv_top.icache_mem_dout1[30] ;
+ wire \u_riscv_top.icache_mem_dout1[31] ;
+ wire \u_riscv_top.icache_mem_dout1[3] ;
+ wire \u_riscv_top.icache_mem_dout1[4] ;
+ wire \u_riscv_top.icache_mem_dout1[5] ;
+ wire \u_riscv_top.icache_mem_dout1[6] ;
+ wire \u_riscv_top.icache_mem_dout1[7] ;
+ wire \u_riscv_top.icache_mem_dout1[8] ;
+ wire \u_riscv_top.icache_mem_dout1[9] ;
+ wire \u_riscv_top.icache_mem_web0 ;
+ wire \u_riscv_top.icache_mem_wmask0[0] ;
+ wire \u_riscv_top.icache_mem_wmask0[1] ;
+ wire \u_riscv_top.icache_mem_wmask0[2] ;
+ wire \u_riscv_top.icache_mem_wmask0[3] ;
+ wire \u_riscv_top.irq_lines[0] ;
+ wire \u_riscv_top.irq_lines[10] ;
+ wire \u_riscv_top.irq_lines[11] ;
+ wire \u_riscv_top.irq_lines[12] ;
+ wire \u_riscv_top.irq_lines[13] ;
+ wire \u_riscv_top.irq_lines[14] ;
+ wire \u_riscv_top.irq_lines[15] ;
+ wire \u_riscv_top.irq_lines[16] ;
+ wire \u_riscv_top.irq_lines[17] ;
+ wire \u_riscv_top.irq_lines[18] ;
+ wire \u_riscv_top.irq_lines[19] ;
+ wire \u_riscv_top.irq_lines[1] ;
+ wire \u_riscv_top.irq_lines[20] ;
+ wire \u_riscv_top.irq_lines[21] ;
+ wire \u_riscv_top.irq_lines[22] ;
+ wire \u_riscv_top.irq_lines[23] ;
+ wire \u_riscv_top.irq_lines[24] ;
+ wire \u_riscv_top.irq_lines[25] ;
+ wire \u_riscv_top.irq_lines[26] ;
+ wire \u_riscv_top.irq_lines[27] ;
+ wire \u_riscv_top.irq_lines[28] ;
+ wire \u_riscv_top.irq_lines[29] ;
+ wire \u_riscv_top.irq_lines[2] ;
+ wire \u_riscv_top.irq_lines[30] ;
+ wire \u_riscv_top.irq_lines[31] ;
+ wire \u_riscv_top.irq_lines[3] ;
+ wire \u_riscv_top.irq_lines[4] ;
+ wire \u_riscv_top.irq_lines[5] ;
+ wire \u_riscv_top.irq_lines[6] ;
+ wire \u_riscv_top.irq_lines[7] ;
+ wire \u_riscv_top.irq_lines[8] ;
+ wire \u_riscv_top.irq_lines[9] ;
+ wire \u_riscv_top.pwrup_rst_n ;
+ wire \u_riscv_top.riscv_debug[0] ;
+ wire \u_riscv_top.riscv_debug[10] ;
+ wire \u_riscv_top.riscv_debug[11] ;
+ wire \u_riscv_top.riscv_debug[12] ;
+ wire \u_riscv_top.riscv_debug[13] ;
+ wire \u_riscv_top.riscv_debug[14] ;
+ wire \u_riscv_top.riscv_debug[15] ;
+ wire \u_riscv_top.riscv_debug[16] ;
+ wire \u_riscv_top.riscv_debug[17] ;
+ wire \u_riscv_top.riscv_debug[18] ;
+ wire \u_riscv_top.riscv_debug[19] ;
+ wire \u_riscv_top.riscv_debug[1] ;
+ wire \u_riscv_top.riscv_debug[20] ;
+ wire \u_riscv_top.riscv_debug[21] ;
+ wire \u_riscv_top.riscv_debug[22] ;
+ wire \u_riscv_top.riscv_debug[23] ;
+ wire \u_riscv_top.riscv_debug[24] ;
+ wire \u_riscv_top.riscv_debug[25] ;
+ wire \u_riscv_top.riscv_debug[26] ;
+ wire \u_riscv_top.riscv_debug[27] ;
+ wire \u_riscv_top.riscv_debug[28] ;
+ wire \u_riscv_top.riscv_debug[29] ;
+ wire \u_riscv_top.riscv_debug[2] ;
+ wire \u_riscv_top.riscv_debug[30] ;
+ wire \u_riscv_top.riscv_debug[31] ;
+ wire \u_riscv_top.riscv_debug[32] ;
+ wire \u_riscv_top.riscv_debug[33] ;
+ wire \u_riscv_top.riscv_debug[34] ;
+ wire \u_riscv_top.riscv_debug[35] ;
+ wire \u_riscv_top.riscv_debug[36] ;
+ wire \u_riscv_top.riscv_debug[37] ;
+ wire \u_riscv_top.riscv_debug[38] ;
+ wire \u_riscv_top.riscv_debug[39] ;
+ wire \u_riscv_top.riscv_debug[3] ;
+ wire \u_riscv_top.riscv_debug[40] ;
+ wire \u_riscv_top.riscv_debug[41] ;
+ wire \u_riscv_top.riscv_debug[42] ;
+ wire \u_riscv_top.riscv_debug[43] ;
+ wire \u_riscv_top.riscv_debug[44] ;
+ wire \u_riscv_top.riscv_debug[45] ;
+ wire \u_riscv_top.riscv_debug[46] ;
+ wire \u_riscv_top.riscv_debug[47] ;
+ wire \u_riscv_top.riscv_debug[48] ;
+ wire \u_riscv_top.riscv_debug[49] ;
+ wire \u_riscv_top.riscv_debug[4] ;
+ wire \u_riscv_top.riscv_debug[50] ;
+ wire \u_riscv_top.riscv_debug[51] ;
+ wire \u_riscv_top.riscv_debug[52] ;
+ wire \u_riscv_top.riscv_debug[53] ;
+ wire \u_riscv_top.riscv_debug[54] ;
+ wire \u_riscv_top.riscv_debug[55] ;
+ wire \u_riscv_top.riscv_debug[56] ;
+ wire \u_riscv_top.riscv_debug[57] ;
+ wire \u_riscv_top.riscv_debug[58] ;
+ wire \u_riscv_top.riscv_debug[59] ;
+ wire \u_riscv_top.riscv_debug[5] ;
+ wire \u_riscv_top.riscv_debug[60] ;
+ wire \u_riscv_top.riscv_debug[61] ;
+ wire \u_riscv_top.riscv_debug[62] ;
+ wire \u_riscv_top.riscv_debug[63] ;
+ wire \u_riscv_top.riscv_debug[6] ;
+ wire \u_riscv_top.riscv_debug[7] ;
+ wire \u_riscv_top.riscv_debug[8] ;
+ wire \u_riscv_top.riscv_debug[9] ;
+ wire \u_riscv_top.rtc_clk ;
+ wire \u_riscv_top.soft_irq ;
+ wire \u_riscv_top.sram0_addr0[0] ;
+ wire \u_riscv_top.sram0_addr0[1] ;
+ wire \u_riscv_top.sram0_addr0[2] ;
+ wire \u_riscv_top.sram0_addr0[3] ;
+ wire \u_riscv_top.sram0_addr0[4] ;
+ wire \u_riscv_top.sram0_addr0[5] ;
+ wire \u_riscv_top.sram0_addr0[6] ;
+ wire \u_riscv_top.sram0_addr0[7] ;
+ wire \u_riscv_top.sram0_addr0[8] ;
+ wire \u_riscv_top.sram0_addr1[0] ;
+ wire \u_riscv_top.sram0_addr1[1] ;
+ wire \u_riscv_top.sram0_addr1[2] ;
+ wire \u_riscv_top.sram0_addr1[3] ;
+ wire \u_riscv_top.sram0_addr1[4] ;
+ wire \u_riscv_top.sram0_addr1[5] ;
+ wire \u_riscv_top.sram0_addr1[6] ;
+ wire \u_riscv_top.sram0_addr1[7] ;
+ wire \u_riscv_top.sram0_addr1[8] ;
+ wire \u_riscv_top.sram0_clk0 ;
+ wire \u_riscv_top.sram0_clk1 ;
+ wire \u_riscv_top.sram0_csb0 ;
+ wire \u_riscv_top.sram0_csb1 ;
+ wire \u_riscv_top.sram0_din0[0] ;
+ wire \u_riscv_top.sram0_din0[10] ;
+ wire \u_riscv_top.sram0_din0[11] ;
+ wire \u_riscv_top.sram0_din0[12] ;
+ wire \u_riscv_top.sram0_din0[13] ;
+ wire \u_riscv_top.sram0_din0[14] ;
+ wire \u_riscv_top.sram0_din0[15] ;
+ wire \u_riscv_top.sram0_din0[16] ;
+ wire \u_riscv_top.sram0_din0[17] ;
+ wire \u_riscv_top.sram0_din0[18] ;
+ wire \u_riscv_top.sram0_din0[19] ;
+ wire \u_riscv_top.sram0_din0[1] ;
+ wire \u_riscv_top.sram0_din0[20] ;
+ wire \u_riscv_top.sram0_din0[21] ;
+ wire \u_riscv_top.sram0_din0[22] ;
+ wire \u_riscv_top.sram0_din0[23] ;
+ wire \u_riscv_top.sram0_din0[24] ;
+ wire \u_riscv_top.sram0_din0[25] ;
+ wire \u_riscv_top.sram0_din0[26] ;
+ wire \u_riscv_top.sram0_din0[27] ;
+ wire \u_riscv_top.sram0_din0[28] ;
+ wire \u_riscv_top.sram0_din0[29] ;
+ wire \u_riscv_top.sram0_din0[2] ;
+ wire \u_riscv_top.sram0_din0[30] ;
+ wire \u_riscv_top.sram0_din0[31] ;
+ wire \u_riscv_top.sram0_din0[3] ;
+ wire \u_riscv_top.sram0_din0[4] ;
+ wire \u_riscv_top.sram0_din0[5] ;
+ wire \u_riscv_top.sram0_din0[6] ;
+ wire \u_riscv_top.sram0_din0[7] ;
+ wire \u_riscv_top.sram0_din0[8] ;
+ wire \u_riscv_top.sram0_din0[9] ;
+ wire \u_riscv_top.sram0_dout0[0] ;
+ wire \u_riscv_top.sram0_dout0[10] ;
+ wire \u_riscv_top.sram0_dout0[11] ;
+ wire \u_riscv_top.sram0_dout0[12] ;
+ wire \u_riscv_top.sram0_dout0[13] ;
+ wire \u_riscv_top.sram0_dout0[14] ;
+ wire \u_riscv_top.sram0_dout0[15] ;
+ wire \u_riscv_top.sram0_dout0[16] ;
+ wire \u_riscv_top.sram0_dout0[17] ;
+ wire \u_riscv_top.sram0_dout0[18] ;
+ wire \u_riscv_top.sram0_dout0[19] ;
+ wire \u_riscv_top.sram0_dout0[1] ;
+ wire \u_riscv_top.sram0_dout0[20] ;
+ wire \u_riscv_top.sram0_dout0[21] ;
+ wire \u_riscv_top.sram0_dout0[22] ;
+ wire \u_riscv_top.sram0_dout0[23] ;
+ wire \u_riscv_top.sram0_dout0[24] ;
+ wire \u_riscv_top.sram0_dout0[25] ;
+ wire \u_riscv_top.sram0_dout0[26] ;
+ wire \u_riscv_top.sram0_dout0[27] ;
+ wire \u_riscv_top.sram0_dout0[28] ;
+ wire \u_riscv_top.sram0_dout0[29] ;
+ wire \u_riscv_top.sram0_dout0[2] ;
+ wire \u_riscv_top.sram0_dout0[30] ;
+ wire \u_riscv_top.sram0_dout0[31] ;
+ wire \u_riscv_top.sram0_dout0[3] ;
+ wire \u_riscv_top.sram0_dout0[4] ;
+ wire \u_riscv_top.sram0_dout0[5] ;
+ wire \u_riscv_top.sram0_dout0[6] ;
+ wire \u_riscv_top.sram0_dout0[7] ;
+ wire \u_riscv_top.sram0_dout0[8] ;
+ wire \u_riscv_top.sram0_dout0[9] ;
+ wire \u_riscv_top.sram0_dout1[0] ;
+ wire \u_riscv_top.sram0_dout1[10] ;
+ wire \u_riscv_top.sram0_dout1[11] ;
+ wire \u_riscv_top.sram0_dout1[12] ;
+ wire \u_riscv_top.sram0_dout1[13] ;
+ wire \u_riscv_top.sram0_dout1[14] ;
+ wire \u_riscv_top.sram0_dout1[15] ;
+ wire \u_riscv_top.sram0_dout1[16] ;
+ wire \u_riscv_top.sram0_dout1[17] ;
+ wire \u_riscv_top.sram0_dout1[18] ;
+ wire \u_riscv_top.sram0_dout1[19] ;
+ wire \u_riscv_top.sram0_dout1[1] ;
+ wire \u_riscv_top.sram0_dout1[20] ;
+ wire \u_riscv_top.sram0_dout1[21] ;
+ wire \u_riscv_top.sram0_dout1[22] ;
+ wire \u_riscv_top.sram0_dout1[23] ;
+ wire \u_riscv_top.sram0_dout1[24] ;
+ wire \u_riscv_top.sram0_dout1[25] ;
+ wire \u_riscv_top.sram0_dout1[26] ;
+ wire \u_riscv_top.sram0_dout1[27] ;
+ wire \u_riscv_top.sram0_dout1[28] ;
+ wire \u_riscv_top.sram0_dout1[29] ;
+ wire \u_riscv_top.sram0_dout1[2] ;
+ wire \u_riscv_top.sram0_dout1[30] ;
+ wire \u_riscv_top.sram0_dout1[31] ;
+ wire \u_riscv_top.sram0_dout1[3] ;
+ wire \u_riscv_top.sram0_dout1[4] ;
+ wire \u_riscv_top.sram0_dout1[5] ;
+ wire \u_riscv_top.sram0_dout1[6] ;
+ wire \u_riscv_top.sram0_dout1[7] ;
+ wire \u_riscv_top.sram0_dout1[8] ;
+ wire \u_riscv_top.sram0_dout1[9] ;
+ wire \u_riscv_top.sram0_web0 ;
+ wire \u_riscv_top.sram0_wmask0[0] ;
+ wire \u_riscv_top.sram0_wmask0[1] ;
+ wire \u_riscv_top.sram0_wmask0[2] ;
+ wire \u_riscv_top.sram0_wmask0[3] ;
+ wire \u_riscv_top.wb_clk ;
+ wire \u_riscv_top.wb_dcache_ack_i ;
+ wire \u_riscv_top.wb_dcache_adr_o[0] ;
+ wire \u_riscv_top.wb_dcache_adr_o[10] ;
+ wire \u_riscv_top.wb_dcache_adr_o[11] ;
+ wire \u_riscv_top.wb_dcache_adr_o[12] ;
+ wire \u_riscv_top.wb_dcache_adr_o[13] ;
+ wire \u_riscv_top.wb_dcache_adr_o[14] ;
+ wire \u_riscv_top.wb_dcache_adr_o[15] ;
+ wire \u_riscv_top.wb_dcache_adr_o[16] ;
+ wire \u_riscv_top.wb_dcache_adr_o[17] ;
+ wire \u_riscv_top.wb_dcache_adr_o[18] ;
+ wire \u_riscv_top.wb_dcache_adr_o[19] ;
+ wire \u_riscv_top.wb_dcache_adr_o[1] ;
+ wire \u_riscv_top.wb_dcache_adr_o[20] ;
+ wire \u_riscv_top.wb_dcache_adr_o[21] ;
+ wire \u_riscv_top.wb_dcache_adr_o[22] ;
+ wire \u_riscv_top.wb_dcache_adr_o[23] ;
+ wire \u_riscv_top.wb_dcache_adr_o[24] ;
+ wire \u_riscv_top.wb_dcache_adr_o[25] ;
+ wire \u_riscv_top.wb_dcache_adr_o[26] ;
+ wire \u_riscv_top.wb_dcache_adr_o[27] ;
+ wire \u_riscv_top.wb_dcache_adr_o[28] ;
+ wire \u_riscv_top.wb_dcache_adr_o[29] ;
+ wire \u_riscv_top.wb_dcache_adr_o[2] ;
+ wire \u_riscv_top.wb_dcache_adr_o[30] ;
+ wire \u_riscv_top.wb_dcache_adr_o[31] ;
+ wire \u_riscv_top.wb_dcache_adr_o[3] ;
+ wire \u_riscv_top.wb_dcache_adr_o[4] ;
+ wire \u_riscv_top.wb_dcache_adr_o[5] ;
+ wire \u_riscv_top.wb_dcache_adr_o[6] ;
+ wire \u_riscv_top.wb_dcache_adr_o[7] ;
+ wire \u_riscv_top.wb_dcache_adr_o[8] ;
+ wire \u_riscv_top.wb_dcache_adr_o[9] ;
+ wire \u_riscv_top.wb_dcache_bl_o[0] ;
+ wire \u_riscv_top.wb_dcache_bl_o[1] ;
+ wire \u_riscv_top.wb_dcache_bl_o[2] ;
+ wire \u_riscv_top.wb_dcache_bl_o[3] ;
+ wire \u_riscv_top.wb_dcache_bl_o[4] ;
+ wire \u_riscv_top.wb_dcache_bl_o[5] ;
+ wire \u_riscv_top.wb_dcache_bl_o[6] ;
+ wire \u_riscv_top.wb_dcache_bl_o[7] ;
+ wire \u_riscv_top.wb_dcache_bl_o[8] ;
+ wire \u_riscv_top.wb_dcache_bl_o[9] ;
+ wire \u_riscv_top.wb_dcache_bry_o ;
+ wire \u_riscv_top.wb_dcache_cyc_o ;
+ wire \u_riscv_top.wb_dcache_dat_i[0] ;
+ wire \u_riscv_top.wb_dcache_dat_i[10] ;
+ wire \u_riscv_top.wb_dcache_dat_i[11] ;
+ wire \u_riscv_top.wb_dcache_dat_i[12] ;
+ wire \u_riscv_top.wb_dcache_dat_i[13] ;
+ wire \u_riscv_top.wb_dcache_dat_i[14] ;
+ wire \u_riscv_top.wb_dcache_dat_i[15] ;
+ wire \u_riscv_top.wb_dcache_dat_i[16] ;
+ wire \u_riscv_top.wb_dcache_dat_i[17] ;
+ wire \u_riscv_top.wb_dcache_dat_i[18] ;
+ wire \u_riscv_top.wb_dcache_dat_i[19] ;
+ wire \u_riscv_top.wb_dcache_dat_i[1] ;
+ wire \u_riscv_top.wb_dcache_dat_i[20] ;
+ wire \u_riscv_top.wb_dcache_dat_i[21] ;
+ wire \u_riscv_top.wb_dcache_dat_i[22] ;
+ wire \u_riscv_top.wb_dcache_dat_i[23] ;
+ wire \u_riscv_top.wb_dcache_dat_i[24] ;
+ wire \u_riscv_top.wb_dcache_dat_i[25] ;
+ wire \u_riscv_top.wb_dcache_dat_i[26] ;
+ wire \u_riscv_top.wb_dcache_dat_i[27] ;
+ wire \u_riscv_top.wb_dcache_dat_i[28] ;
+ wire \u_riscv_top.wb_dcache_dat_i[29] ;
+ wire \u_riscv_top.wb_dcache_dat_i[2] ;
+ wire \u_riscv_top.wb_dcache_dat_i[30] ;
+ wire \u_riscv_top.wb_dcache_dat_i[31] ;
+ wire \u_riscv_top.wb_dcache_dat_i[3] ;
+ wire \u_riscv_top.wb_dcache_dat_i[4] ;
+ wire \u_riscv_top.wb_dcache_dat_i[5] ;
+ wire \u_riscv_top.wb_dcache_dat_i[6] ;
+ wire \u_riscv_top.wb_dcache_dat_i[7] ;
+ wire \u_riscv_top.wb_dcache_dat_i[8] ;
+ wire \u_riscv_top.wb_dcache_dat_i[9] ;
+ wire \u_riscv_top.wb_dcache_dat_o[0] ;
+ wire \u_riscv_top.wb_dcache_dat_o[10] ;
+ wire \u_riscv_top.wb_dcache_dat_o[11] ;
+ wire \u_riscv_top.wb_dcache_dat_o[12] ;
+ wire \u_riscv_top.wb_dcache_dat_o[13] ;
+ wire \u_riscv_top.wb_dcache_dat_o[14] ;
+ wire \u_riscv_top.wb_dcache_dat_o[15] ;
+ wire \u_riscv_top.wb_dcache_dat_o[16] ;
+ wire \u_riscv_top.wb_dcache_dat_o[17] ;
+ wire \u_riscv_top.wb_dcache_dat_o[18] ;
+ wire \u_riscv_top.wb_dcache_dat_o[19] ;
+ wire \u_riscv_top.wb_dcache_dat_o[1] ;
+ wire \u_riscv_top.wb_dcache_dat_o[20] ;
+ wire \u_riscv_top.wb_dcache_dat_o[21] ;
+ wire \u_riscv_top.wb_dcache_dat_o[22] ;
+ wire \u_riscv_top.wb_dcache_dat_o[23] ;
+ wire \u_riscv_top.wb_dcache_dat_o[24] ;
+ wire \u_riscv_top.wb_dcache_dat_o[25] ;
+ wire \u_riscv_top.wb_dcache_dat_o[26] ;
+ wire \u_riscv_top.wb_dcache_dat_o[27] ;
+ wire \u_riscv_top.wb_dcache_dat_o[28] ;
+ wire \u_riscv_top.wb_dcache_dat_o[29] ;
+ wire \u_riscv_top.wb_dcache_dat_o[2] ;
+ wire \u_riscv_top.wb_dcache_dat_o[30] ;
+ wire \u_riscv_top.wb_dcache_dat_o[31] ;
+ wire \u_riscv_top.wb_dcache_dat_o[3] ;
+ wire \u_riscv_top.wb_dcache_dat_o[4] ;
+ wire \u_riscv_top.wb_dcache_dat_o[5] ;
+ wire \u_riscv_top.wb_dcache_dat_o[6] ;
+ wire \u_riscv_top.wb_dcache_dat_o[7] ;
+ wire \u_riscv_top.wb_dcache_dat_o[8] ;
+ wire \u_riscv_top.wb_dcache_dat_o[9] ;
+ wire \u_riscv_top.wb_dcache_err_i ;
+ wire \u_riscv_top.wb_dcache_lack_i ;
+ wire \u_riscv_top.wb_dcache_sel_o[0] ;
+ wire \u_riscv_top.wb_dcache_sel_o[1] ;
+ wire \u_riscv_top.wb_dcache_sel_o[2] ;
+ wire \u_riscv_top.wb_dcache_sel_o[3] ;
+ wire \u_riscv_top.wb_dcache_stb_o ;
+ wire \u_riscv_top.wb_dcache_we_o ;
+ wire \u_riscv_top.wb_icache_ack_i ;
+ wire \u_riscv_top.wb_icache_adr_o[0] ;
+ wire \u_riscv_top.wb_icache_adr_o[10] ;
+ wire \u_riscv_top.wb_icache_adr_o[11] ;
+ wire \u_riscv_top.wb_icache_adr_o[12] ;
+ wire \u_riscv_top.wb_icache_adr_o[13] ;
+ wire \u_riscv_top.wb_icache_adr_o[14] ;
+ wire \u_riscv_top.wb_icache_adr_o[15] ;
+ wire \u_riscv_top.wb_icache_adr_o[16] ;
+ wire \u_riscv_top.wb_icache_adr_o[17] ;
+ wire \u_riscv_top.wb_icache_adr_o[18] ;
+ wire \u_riscv_top.wb_icache_adr_o[19] ;
+ wire \u_riscv_top.wb_icache_adr_o[1] ;
+ wire \u_riscv_top.wb_icache_adr_o[20] ;
+ wire \u_riscv_top.wb_icache_adr_o[21] ;
+ wire \u_riscv_top.wb_icache_adr_o[22] ;
+ wire \u_riscv_top.wb_icache_adr_o[23] ;
+ wire \u_riscv_top.wb_icache_adr_o[24] ;
+ wire \u_riscv_top.wb_icache_adr_o[25] ;
+ wire \u_riscv_top.wb_icache_adr_o[26] ;
+ wire \u_riscv_top.wb_icache_adr_o[27] ;
+ wire \u_riscv_top.wb_icache_adr_o[28] ;
+ wire \u_riscv_top.wb_icache_adr_o[29] ;
+ wire \u_riscv_top.wb_icache_adr_o[2] ;
+ wire \u_riscv_top.wb_icache_adr_o[30] ;
+ wire \u_riscv_top.wb_icache_adr_o[31] ;
+ wire \u_riscv_top.wb_icache_adr_o[3] ;
+ wire \u_riscv_top.wb_icache_adr_o[4] ;
+ wire \u_riscv_top.wb_icache_adr_o[5] ;
+ wire \u_riscv_top.wb_icache_adr_o[6] ;
+ wire \u_riscv_top.wb_icache_adr_o[7] ;
+ wire \u_riscv_top.wb_icache_adr_o[8] ;
+ wire \u_riscv_top.wb_icache_adr_o[9] ;
+ wire \u_riscv_top.wb_icache_bl_o[0] ;
+ wire \u_riscv_top.wb_icache_bl_o[1] ;
+ wire \u_riscv_top.wb_icache_bl_o[2] ;
+ wire \u_riscv_top.wb_icache_bl_o[3] ;
+ wire \u_riscv_top.wb_icache_bl_o[4] ;
+ wire \u_riscv_top.wb_icache_bl_o[5] ;
+ wire \u_riscv_top.wb_icache_bl_o[6] ;
+ wire \u_riscv_top.wb_icache_bl_o[7] ;
+ wire \u_riscv_top.wb_icache_bl_o[8] ;
+ wire \u_riscv_top.wb_icache_bl_o[9] ;
+ wire \u_riscv_top.wb_icache_bry_o ;
+ wire \u_riscv_top.wb_icache_cyc_o ;
+ wire \u_riscv_top.wb_icache_dat_i[0] ;
+ wire \u_riscv_top.wb_icache_dat_i[10] ;
+ wire \u_riscv_top.wb_icache_dat_i[11] ;
+ wire \u_riscv_top.wb_icache_dat_i[12] ;
+ wire \u_riscv_top.wb_icache_dat_i[13] ;
+ wire \u_riscv_top.wb_icache_dat_i[14] ;
+ wire \u_riscv_top.wb_icache_dat_i[15] ;
+ wire \u_riscv_top.wb_icache_dat_i[16] ;
+ wire \u_riscv_top.wb_icache_dat_i[17] ;
+ wire \u_riscv_top.wb_icache_dat_i[18] ;
+ wire \u_riscv_top.wb_icache_dat_i[19] ;
+ wire \u_riscv_top.wb_icache_dat_i[1] ;
+ wire \u_riscv_top.wb_icache_dat_i[20] ;
+ wire \u_riscv_top.wb_icache_dat_i[21] ;
+ wire \u_riscv_top.wb_icache_dat_i[22] ;
+ wire \u_riscv_top.wb_icache_dat_i[23] ;
+ wire \u_riscv_top.wb_icache_dat_i[24] ;
+ wire \u_riscv_top.wb_icache_dat_i[25] ;
+ wire \u_riscv_top.wb_icache_dat_i[26] ;
+ wire \u_riscv_top.wb_icache_dat_i[27] ;
+ wire \u_riscv_top.wb_icache_dat_i[28] ;
+ wire \u_riscv_top.wb_icache_dat_i[29] ;
+ wire \u_riscv_top.wb_icache_dat_i[2] ;
+ wire \u_riscv_top.wb_icache_dat_i[30] ;
+ wire \u_riscv_top.wb_icache_dat_i[31] ;
+ wire \u_riscv_top.wb_icache_dat_i[3] ;
+ wire \u_riscv_top.wb_icache_dat_i[4] ;
+ wire \u_riscv_top.wb_icache_dat_i[5] ;
+ wire \u_riscv_top.wb_icache_dat_i[6] ;
+ wire \u_riscv_top.wb_icache_dat_i[7] ;
+ wire \u_riscv_top.wb_icache_dat_i[8] ;
+ wire \u_riscv_top.wb_icache_dat_i[9] ;
+ wire \u_riscv_top.wb_icache_err_i ;
+ wire \u_riscv_top.wb_icache_lack_i ;
+ wire \u_riscv_top.wb_icache_sel_o[0] ;
+ wire \u_riscv_top.wb_icache_sel_o[1] ;
+ wire \u_riscv_top.wb_icache_sel_o[2] ;
+ wire \u_riscv_top.wb_icache_sel_o[3] ;
+ wire \u_riscv_top.wb_icache_stb_o ;
+ wire \u_riscv_top.wb_icache_we_o ;
+ wire \u_riscv_top.wbd_clk_int ;
+ wire \u_riscv_top.wbd_dmem_ack_i ;
+ wire \u_riscv_top.wbd_dmem_adr_o[0] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[10] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[11] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[12] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[13] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[14] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[15] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[16] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[17] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[18] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[19] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[1] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[20] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[21] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[22] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[23] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[24] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[25] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[26] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[27] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[28] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[29] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[2] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[30] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[31] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[3] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[4] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[5] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[6] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[7] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[8] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[9] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[0] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[1] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[2] ;
+ wire \u_riscv_top.wbd_dmem_bry_o ;
+ wire \u_riscv_top.wbd_dmem_dat_i[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[9] ;
+ wire \u_riscv_top.wbd_dmem_err_i ;
+ wire \u_riscv_top.wbd_dmem_lack_i ;
+ wire \u_riscv_top.wbd_dmem_sel_o[0] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[1] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[2] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[3] ;
+ wire \u_riscv_top.wbd_dmem_stb_o ;
+ wire \u_riscv_top.wbd_dmem_we_o ;
+ wire \uart_rst_n[0] ;
+ wire \uart_rst_n[1] ;
+ wire \uart_rxd[0] ;
+ wire \uart_rxd[1] ;
+ wire \uart_txd[0] ;
+ wire \uart_txd[1] ;
+ wire uartm_rxd;
+ wire uartm_txd;
+ wire usb_clk;
+ wire usb_dn_i;
+ wire usb_dn_o;
+ wire usb_dp_i;
+ wire usb_dp_o;
+ wire usb_intr_o;
+ wire usb_oen;
+ wire usb_rst_n;
+ wire wbd_clk_int;
+ wire wbd_clk_peri_rp;
+ wire wbd_clk_peri_skew;
+ wire wbd_clk_pinmux_rp;
+ wire wbd_clk_pinmux_skew;
+ wire wbd_clk_qspi_rp;
+ wire wbd_clk_spi;
+ wire wbd_clk_uart_rp;
+ wire wbd_clk_uart_skew;
+ wire wbd_clk_wh;
+ wire wbd_clk_wi_skew;
+ wire wbd_glbl_ack_i;
+ wire \wbd_glbl_adr_o[0] ;
+ wire \wbd_glbl_adr_o[10] ;
+ wire \wbd_glbl_adr_o[1] ;
+ wire \wbd_glbl_adr_o[2] ;
+ wire \wbd_glbl_adr_o[3] ;
+ wire \wbd_glbl_adr_o[4] ;
+ wire \wbd_glbl_adr_o[5] ;
+ wire \wbd_glbl_adr_o[6] ;
+ wire \wbd_glbl_adr_o[7] ;
+ wire \wbd_glbl_adr_o[8] ;
+ wire \wbd_glbl_adr_o[9] ;
+ wire wbd_glbl_cyc_o;
+ wire \wbd_glbl_dat_i[0] ;
+ wire \wbd_glbl_dat_i[10] ;
+ wire \wbd_glbl_dat_i[11] ;
+ wire \wbd_glbl_dat_i[12] ;
+ wire \wbd_glbl_dat_i[13] ;
+ wire \wbd_glbl_dat_i[14] ;
+ wire \wbd_glbl_dat_i[15] ;
+ wire \wbd_glbl_dat_i[16] ;
+ wire \wbd_glbl_dat_i[17] ;
+ wire \wbd_glbl_dat_i[18] ;
+ wire \wbd_glbl_dat_i[19] ;
+ wire \wbd_glbl_dat_i[1] ;
+ wire \wbd_glbl_dat_i[20] ;
+ wire \wbd_glbl_dat_i[21] ;
+ wire \wbd_glbl_dat_i[22] ;
+ wire \wbd_glbl_dat_i[23] ;
+ wire \wbd_glbl_dat_i[24] ;
+ wire \wbd_glbl_dat_i[25] ;
+ wire \wbd_glbl_dat_i[26] ;
+ wire \wbd_glbl_dat_i[27] ;
+ wire \wbd_glbl_dat_i[28] ;
+ wire \wbd_glbl_dat_i[29] ;
+ wire \wbd_glbl_dat_i[2] ;
+ wire \wbd_glbl_dat_i[30] ;
+ wire \wbd_glbl_dat_i[31] ;
+ wire \wbd_glbl_dat_i[3] ;
+ wire \wbd_glbl_dat_i[4] ;
+ wire \wbd_glbl_dat_i[5] ;
+ wire \wbd_glbl_dat_i[6] ;
+ wire \wbd_glbl_dat_i[7] ;
+ wire \wbd_glbl_dat_i[8] ;
+ wire \wbd_glbl_dat_i[9] ;
+ wire \wbd_glbl_dat_o[0] ;
+ wire \wbd_glbl_dat_o[10] ;
+ wire \wbd_glbl_dat_o[11] ;
+ wire \wbd_glbl_dat_o[12] ;
+ wire \wbd_glbl_dat_o[13] ;
+ wire \wbd_glbl_dat_o[14] ;
+ wire \wbd_glbl_dat_o[15] ;
+ wire \wbd_glbl_dat_o[16] ;
+ wire \wbd_glbl_dat_o[17] ;
+ wire \wbd_glbl_dat_o[18] ;
+ wire \wbd_glbl_dat_o[19] ;
+ wire \wbd_glbl_dat_o[1] ;
+ wire \wbd_glbl_dat_o[20] ;
+ wire \wbd_glbl_dat_o[21] ;
+ wire \wbd_glbl_dat_o[22] ;
+ wire \wbd_glbl_dat_o[23] ;
+ wire \wbd_glbl_dat_o[24] ;
+ wire \wbd_glbl_dat_o[25] ;
+ wire \wbd_glbl_dat_o[26] ;
+ wire \wbd_glbl_dat_o[27] ;
+ wire \wbd_glbl_dat_o[28] ;
+ wire \wbd_glbl_dat_o[29] ;
+ wire \wbd_glbl_dat_o[2] ;
+ wire \wbd_glbl_dat_o[30] ;
+ wire \wbd_glbl_dat_o[31] ;
+ wire \wbd_glbl_dat_o[3] ;
+ wire \wbd_glbl_dat_o[4] ;
+ wire \wbd_glbl_dat_o[5] ;
+ wire \wbd_glbl_dat_o[6] ;
+ wire \wbd_glbl_dat_o[7] ;
+ wire \wbd_glbl_dat_o[8] ;
+ wire \wbd_glbl_dat_o[9] ;
+ wire \wbd_glbl_sel_o[0] ;
+ wire \wbd_glbl_sel_o[1] ;
+ wire \wbd_glbl_sel_o[2] ;
+ wire \wbd_glbl_sel_o[3] ;
+ wire wbd_glbl_stb_o;
+ wire wbd_glbl_we_o;
+ wire wbd_int_ack_o;
+ wire \wbd_int_adr_i[0] ;
+ wire \wbd_int_adr_i[10] ;
+ wire \wbd_int_adr_i[11] ;
+ wire \wbd_int_adr_i[12] ;
+ wire \wbd_int_adr_i[13] ;
+ wire \wbd_int_adr_i[14] ;
+ wire \wbd_int_adr_i[15] ;
+ wire \wbd_int_adr_i[16] ;
+ wire \wbd_int_adr_i[17] ;
+ wire \wbd_int_adr_i[18] ;
+ wire \wbd_int_adr_i[19] ;
+ wire \wbd_int_adr_i[1] ;
+ wire \wbd_int_adr_i[20] ;
+ wire \wbd_int_adr_i[21] ;
+ wire \wbd_int_adr_i[22] ;
+ wire \wbd_int_adr_i[23] ;
+ wire \wbd_int_adr_i[24] ;
+ wire \wbd_int_adr_i[25] ;
+ wire \wbd_int_adr_i[26] ;
+ wire \wbd_int_adr_i[27] ;
+ wire \wbd_int_adr_i[28] ;
+ wire \wbd_int_adr_i[29] ;
+ wire \wbd_int_adr_i[2] ;
+ wire \wbd_int_adr_i[30] ;
+ wire \wbd_int_adr_i[31] ;
+ wire \wbd_int_adr_i[3] ;
+ wire \wbd_int_adr_i[4] ;
+ wire \wbd_int_adr_i[5] ;
+ wire \wbd_int_adr_i[6] ;
+ wire \wbd_int_adr_i[7] ;
+ wire \wbd_int_adr_i[8] ;
+ wire \wbd_int_adr_i[9] ;
+ wire wbd_int_cyc_i;
+ wire \wbd_int_dat_i[0] ;
+ wire \wbd_int_dat_i[10] ;
+ wire \wbd_int_dat_i[11] ;
+ wire \wbd_int_dat_i[12] ;
+ wire \wbd_int_dat_i[13] ;
+ wire \wbd_int_dat_i[14] ;
+ wire \wbd_int_dat_i[15] ;
+ wire \wbd_int_dat_i[16] ;
+ wire \wbd_int_dat_i[17] ;
+ wire \wbd_int_dat_i[18] ;
+ wire \wbd_int_dat_i[19] ;
+ wire \wbd_int_dat_i[1] ;
+ wire \wbd_int_dat_i[20] ;
+ wire \wbd_int_dat_i[21] ;
+ wire \wbd_int_dat_i[22] ;
+ wire \wbd_int_dat_i[23] ;
+ wire \wbd_int_dat_i[24] ;
+ wire \wbd_int_dat_i[25] ;
+ wire \wbd_int_dat_i[26] ;
+ wire \wbd_int_dat_i[27] ;
+ wire \wbd_int_dat_i[28] ;
+ wire \wbd_int_dat_i[29] ;
+ wire \wbd_int_dat_i[2] ;
+ wire \wbd_int_dat_i[30] ;
+ wire \wbd_int_dat_i[31] ;
+ wire \wbd_int_dat_i[3] ;
+ wire \wbd_int_dat_i[4] ;
+ wire \wbd_int_dat_i[5] ;
+ wire \wbd_int_dat_i[6] ;
+ wire \wbd_int_dat_i[7] ;
+ wire \wbd_int_dat_i[8] ;
+ wire \wbd_int_dat_i[9] ;
+ wire \wbd_int_dat_o[0] ;
+ wire \wbd_int_dat_o[10] ;
+ wire \wbd_int_dat_o[11] ;
+ wire \wbd_int_dat_o[12] ;
+ wire \wbd_int_dat_o[13] ;
+ wire \wbd_int_dat_o[14] ;
+ wire \wbd_int_dat_o[15] ;
+ wire \wbd_int_dat_o[16] ;
+ wire \wbd_int_dat_o[17] ;
+ wire \wbd_int_dat_o[18] ;
+ wire \wbd_int_dat_o[19] ;
+ wire \wbd_int_dat_o[1] ;
+ wire \wbd_int_dat_o[20] ;
+ wire \wbd_int_dat_o[21] ;
+ wire \wbd_int_dat_o[22] ;
+ wire \wbd_int_dat_o[23] ;
+ wire \wbd_int_dat_o[24] ;
+ wire \wbd_int_dat_o[25] ;
+ wire \wbd_int_dat_o[26] ;
+ wire \wbd_int_dat_o[27] ;
+ wire \wbd_int_dat_o[28] ;
+ wire \wbd_int_dat_o[29] ;
+ wire \wbd_int_dat_o[2] ;
+ wire \wbd_int_dat_o[30] ;
+ wire \wbd_int_dat_o[31] ;
+ wire \wbd_int_dat_o[3] ;
+ wire \wbd_int_dat_o[4] ;
+ wire \wbd_int_dat_o[5] ;
+ wire \wbd_int_dat_o[6] ;
+ wire \wbd_int_dat_o[7] ;
+ wire \wbd_int_dat_o[8] ;
+ wire \wbd_int_dat_o[9] ;
+ wire wbd_int_err_o;
+ wire \wbd_int_sel_i[0] ;
+ wire \wbd_int_sel_i[1] ;
+ wire \wbd_int_sel_i[2] ;
+ wire \wbd_int_sel_i[3] ;
+ wire wbd_int_stb_i;
+ wire wbd_int_we_i;
+ wire wbd_pll_rst_n;
+ wire wbd_spim_ack_i;
+ wire \wbd_spim_adr_o[0] ;
+ wire \wbd_spim_adr_o[10] ;
+ wire \wbd_spim_adr_o[11] ;
+ wire \wbd_spim_adr_o[12] ;
+ wire \wbd_spim_adr_o[13] ;
+ wire \wbd_spim_adr_o[14] ;
+ wire \wbd_spim_adr_o[15] ;
+ wire \wbd_spim_adr_o[16] ;
+ wire \wbd_spim_adr_o[17] ;
+ wire \wbd_spim_adr_o[18] ;
+ wire \wbd_spim_adr_o[19] ;
+ wire \wbd_spim_adr_o[1] ;
+ wire \wbd_spim_adr_o[20] ;
+ wire \wbd_spim_adr_o[21] ;
+ wire \wbd_spim_adr_o[22] ;
+ wire \wbd_spim_adr_o[23] ;
+ wire \wbd_spim_adr_o[24] ;
+ wire \wbd_spim_adr_o[25] ;
+ wire \wbd_spim_adr_o[26] ;
+ wire \wbd_spim_adr_o[27] ;
+ wire \wbd_spim_adr_o[28] ;
+ wire \wbd_spim_adr_o[29] ;
+ wire \wbd_spim_adr_o[2] ;
+ wire \wbd_spim_adr_o[30] ;
+ wire \wbd_spim_adr_o[31] ;
+ wire \wbd_spim_adr_o[3] ;
+ wire \wbd_spim_adr_o[4] ;
+ wire \wbd_spim_adr_o[5] ;
+ wire \wbd_spim_adr_o[6] ;
+ wire \wbd_spim_adr_o[7] ;
+ wire \wbd_spim_adr_o[8] ;
+ wire \wbd_spim_adr_o[9] ;
+ wire \wbd_spim_bl_o[0] ;
+ wire \wbd_spim_bl_o[1] ;
+ wire \wbd_spim_bl_o[2] ;
+ wire \wbd_spim_bl_o[3] ;
+ wire \wbd_spim_bl_o[4] ;
+ wire \wbd_spim_bl_o[5] ;
+ wire \wbd_spim_bl_o[6] ;
+ wire \wbd_spim_bl_o[7] ;
+ wire \wbd_spim_bl_o[8] ;
+ wire \wbd_spim_bl_o[9] ;
+ wire wbd_spim_bry_o;
+ wire wbd_spim_cyc_o;
+ wire \wbd_spim_dat_i[0] ;
+ wire \wbd_spim_dat_i[10] ;
+ wire \wbd_spim_dat_i[11] ;
+ wire \wbd_spim_dat_i[12] ;
+ wire \wbd_spim_dat_i[13] ;
+ wire \wbd_spim_dat_i[14] ;
+ wire \wbd_spim_dat_i[15] ;
+ wire \wbd_spim_dat_i[16] ;
+ wire \wbd_spim_dat_i[17] ;
+ wire \wbd_spim_dat_i[18] ;
+ wire \wbd_spim_dat_i[19] ;
+ wire \wbd_spim_dat_i[1] ;
+ wire \wbd_spim_dat_i[20] ;
+ wire \wbd_spim_dat_i[21] ;
+ wire \wbd_spim_dat_i[22] ;
+ wire \wbd_spim_dat_i[23] ;
+ wire \wbd_spim_dat_i[24] ;
+ wire \wbd_spim_dat_i[25] ;
+ wire \wbd_spim_dat_i[26] ;
+ wire \wbd_spim_dat_i[27] ;
+ wire \wbd_spim_dat_i[28] ;
+ wire \wbd_spim_dat_i[29] ;
+ wire \wbd_spim_dat_i[2] ;
+ wire \wbd_spim_dat_i[30] ;
+ wire \wbd_spim_dat_i[31] ;
+ wire \wbd_spim_dat_i[3] ;
+ wire \wbd_spim_dat_i[4] ;
+ wire \wbd_spim_dat_i[5] ;
+ wire \wbd_spim_dat_i[6] ;
+ wire \wbd_spim_dat_i[7] ;
+ wire \wbd_spim_dat_i[8] ;
+ wire \wbd_spim_dat_i[9] ;
+ wire \wbd_spim_dat_o[0] ;
+ wire \wbd_spim_dat_o[10] ;
+ wire \wbd_spim_dat_o[11] ;
+ wire \wbd_spim_dat_o[12] ;
+ wire \wbd_spim_dat_o[13] ;
+ wire \wbd_spim_dat_o[14] ;
+ wire \wbd_spim_dat_o[15] ;
+ wire \wbd_spim_dat_o[16] ;
+ wire \wbd_spim_dat_o[17] ;
+ wire \wbd_spim_dat_o[18] ;
+ wire \wbd_spim_dat_o[19] ;
+ wire \wbd_spim_dat_o[1] ;
+ wire \wbd_spim_dat_o[20] ;
+ wire \wbd_spim_dat_o[21] ;
+ wire \wbd_spim_dat_o[22] ;
+ wire \wbd_spim_dat_o[23] ;
+ wire \wbd_spim_dat_o[24] ;
+ wire \wbd_spim_dat_o[25] ;
+ wire \wbd_spim_dat_o[26] ;
+ wire \wbd_spim_dat_o[27] ;
+ wire \wbd_spim_dat_o[28] ;
+ wire \wbd_spim_dat_o[29] ;
+ wire \wbd_spim_dat_o[2] ;
+ wire \wbd_spim_dat_o[30] ;
+ wire \wbd_spim_dat_o[31] ;
+ wire \wbd_spim_dat_o[3] ;
+ wire \wbd_spim_dat_o[4] ;
+ wire \wbd_spim_dat_o[5] ;
+ wire \wbd_spim_dat_o[6] ;
+ wire \wbd_spim_dat_o[7] ;
+ wire \wbd_spim_dat_o[8] ;
+ wire \wbd_spim_dat_o[9] ;
+ wire wbd_spim_err_i;
+ wire wbd_spim_lack_i;
+ wire \wbd_spim_sel_o[0] ;
+ wire \wbd_spim_sel_o[1] ;
+ wire \wbd_spim_sel_o[2] ;
+ wire \wbd_spim_sel_o[3] ;
+ wire wbd_spim_stb_o;
+ wire wbd_spim_we_o;
+ wire wbd_uart_ack_i;
+ wire \wbd_uart_adr_o[0] ;
+ wire \wbd_uart_adr_o[1] ;
+ wire \wbd_uart_adr_o[2] ;
+ wire \wbd_uart_adr_o[3] ;
+ wire \wbd_uart_adr_o[4] ;
+ wire \wbd_uart_adr_o[5] ;
+ wire \wbd_uart_adr_o[6] ;
+ wire \wbd_uart_adr_o[7] ;
+ wire \wbd_uart_adr_o[8] ;
+ wire wbd_uart_cyc_o;
+ wire \wbd_uart_dat_i[0] ;
+ wire \wbd_uart_dat_i[10] ;
+ wire \wbd_uart_dat_i[11] ;
+ wire \wbd_uart_dat_i[12] ;
+ wire \wbd_uart_dat_i[13] ;
+ wire \wbd_uart_dat_i[14] ;
+ wire \wbd_uart_dat_i[15] ;
+ wire \wbd_uart_dat_i[16] ;
+ wire \wbd_uart_dat_i[17] ;
+ wire \wbd_uart_dat_i[18] ;
+ wire \wbd_uart_dat_i[19] ;
+ wire \wbd_uart_dat_i[1] ;
+ wire \wbd_uart_dat_i[20] ;
+ wire \wbd_uart_dat_i[21] ;
+ wire \wbd_uart_dat_i[22] ;
+ wire \wbd_uart_dat_i[23] ;
+ wire \wbd_uart_dat_i[24] ;
+ wire \wbd_uart_dat_i[25] ;
+ wire \wbd_uart_dat_i[26] ;
+ wire \wbd_uart_dat_i[27] ;
+ wire \wbd_uart_dat_i[28] ;
+ wire \wbd_uart_dat_i[29] ;
+ wire \wbd_uart_dat_i[2] ;
+ wire \wbd_uart_dat_i[30] ;
+ wire \wbd_uart_dat_i[31] ;
+ wire \wbd_uart_dat_i[3] ;
+ wire \wbd_uart_dat_i[4] ;
+ wire \wbd_uart_dat_i[5] ;
+ wire \wbd_uart_dat_i[6] ;
+ wire \wbd_uart_dat_i[7] ;
+ wire \wbd_uart_dat_i[8] ;
+ wire \wbd_uart_dat_i[9] ;
+ wire \wbd_uart_dat_o[0] ;
+ wire \wbd_uart_dat_o[10] ;
+ wire \wbd_uart_dat_o[11] ;
+ wire \wbd_uart_dat_o[12] ;
+ wire \wbd_uart_dat_o[13] ;
+ wire \wbd_uart_dat_o[14] ;
+ wire \wbd_uart_dat_o[15] ;
+ wire \wbd_uart_dat_o[16] ;
+ wire \wbd_uart_dat_o[17] ;
+ wire \wbd_uart_dat_o[18] ;
+ wire \wbd_uart_dat_o[19] ;
+ wire \wbd_uart_dat_o[1] ;
+ wire \wbd_uart_dat_o[20] ;
+ wire \wbd_uart_dat_o[21] ;
+ wire \wbd_uart_dat_o[22] ;
+ wire \wbd_uart_dat_o[23] ;
+ wire \wbd_uart_dat_o[24] ;
+ wire \wbd_uart_dat_o[25] ;
+ wire \wbd_uart_dat_o[26] ;
+ wire \wbd_uart_dat_o[27] ;
+ wire \wbd_uart_dat_o[28] ;
+ wire \wbd_uart_dat_o[29] ;
+ wire \wbd_uart_dat_o[2] ;
+ wire \wbd_uart_dat_o[30] ;
+ wire \wbd_uart_dat_o[31] ;
+ wire \wbd_uart_dat_o[3] ;
+ wire \wbd_uart_dat_o[4] ;
+ wire \wbd_uart_dat_o[5] ;
+ wire \wbd_uart_dat_o[6] ;
+ wire \wbd_uart_dat_o[7] ;
+ wire \wbd_uart_dat_o[8] ;
+ wire \wbd_uart_dat_o[9] ;
+ wire \wbd_uart_sel_o[0] ;
+ wire \wbd_uart_sel_o[1] ;
+ wire \wbd_uart_sel_o[2] ;
+ wire \wbd_uart_sel_o[3] ;
+ wire wbd_uart_stb_o;
+ wire wbd_uart_we_o;
+ wire wbs_ack_int_o;
+ wire \wbs_dat_int_o[0] ;
+ wire \wbs_dat_int_o[10] ;
+ wire \wbs_dat_int_o[11] ;
+ wire \wbs_dat_int_o[12] ;
+ wire \wbs_dat_int_o[13] ;
+ wire \wbs_dat_int_o[14] ;
+ wire \wbs_dat_int_o[15] ;
+ wire \wbs_dat_int_o[16] ;
+ wire \wbs_dat_int_o[17] ;
+ wire \wbs_dat_int_o[18] ;
+ wire \wbs_dat_int_o[19] ;
+ wire \wbs_dat_int_o[1] ;
+ wire \wbs_dat_int_o[20] ;
+ wire \wbs_dat_int_o[21] ;
+ wire \wbs_dat_int_o[22] ;
+ wire \wbs_dat_int_o[23] ;
+ wire \wbs_dat_int_o[24] ;
+ wire \wbs_dat_int_o[25] ;
+ wire \wbs_dat_int_o[26] ;
+ wire \wbs_dat_int_o[27] ;
+ wire \wbs_dat_int_o[28] ;
+ wire \wbs_dat_int_o[29] ;
+ wire \wbs_dat_int_o[2] ;
+ wire \wbs_dat_int_o[30] ;
+ wire \wbs_dat_int_o[31] ;
+ wire \wbs_dat_int_o[3] ;
+ wire \wbs_dat_int_o[4] ;
+ wire \wbs_dat_int_o[5] ;
+ wire \wbs_dat_int_o[6] ;
+ wire \wbs_dat_int_o[7] ;
+ wire \wbs_dat_int_o[8] ;
+ wire \wbs_dat_int_o[9] ;
+ wire xtal_clk;
+
+ dac_top u_4x8bit_dac (.Vout0(analog_io[15]),
+    .Vout1(analog_io[16]),
+    .Vout2(analog_io[17]),
+    .Vout3(analog_io[18]),
+    .Vref(analog_io[23]),
+    .vccd1(vdda1),
+    .vssd1(vssa1),
+    .DIn0({\cfg_dac0_mux_sel[7] ,
+    \cfg_dac0_mux_sel[6] ,
+    \cfg_dac0_mux_sel[5] ,
+    \cfg_dac0_mux_sel[4] ,
+    \cfg_dac0_mux_sel[3] ,
+    \cfg_dac0_mux_sel[2] ,
+    \cfg_dac0_mux_sel[1] ,
+    \cfg_dac0_mux_sel[0] }),
+    .DIn1({\cfg_dac1_mux_sel[7] ,
+    \cfg_dac1_mux_sel[6] ,
+    \cfg_dac1_mux_sel[5] ,
+    \cfg_dac1_mux_sel[4] ,
+    \cfg_dac1_mux_sel[3] ,
+    \cfg_dac1_mux_sel[2] ,
+    \cfg_dac1_mux_sel[1] ,
+    \cfg_dac1_mux_sel[0] }),
+    .DIn2({\cfg_dac2_mux_sel[7] ,
+    \cfg_dac2_mux_sel[6] ,
+    \cfg_dac2_mux_sel[5] ,
+    \cfg_dac2_mux_sel[4] ,
+    \cfg_dac2_mux_sel[3] ,
+    \cfg_dac2_mux_sel[2] ,
+    \cfg_dac2_mux_sel[1] ,
+    \cfg_dac2_mux_sel[0] }),
+    .DIn3({\cfg_dac3_mux_sel[7] ,
+    \cfg_dac3_mux_sel[6] ,
+    \cfg_dac3_mux_sel[5] ,
+    \cfg_dac3_mux_sel[4] ,
+    \cfg_dac3_mux_sel[3] ,
+    \cfg_dac3_mux_sel[2] ,
+    \cfg_dac3_mux_sel[1] ,
+    \cfg_dac3_mux_sel[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb (.csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .web0(\u_riscv_top.dcache_mem_web0 ),
+    .clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb (.csb0(\u_riscv_top.icache_mem_csb0 ),
+    .csb1(\u_riscv_top.icache_mem_csb1 ),
+    .web0(\u_riscv_top.icache_mem_web0 ),
+    .clk0(\u_riscv_top.icache_mem_clk0 ),
+    .clk1(\u_riscv_top.icache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .dout0({_NC1,
+    _NC2,
+    _NC3,
+    _NC4,
+    _NC5,
+    _NC6,
+    _NC7,
+    _NC8,
+    _NC9,
+    _NC10,
+    _NC11,
+    _NC12,
+    _NC13,
+    _NC14,
+    _NC15,
+    _NC16,
+    _NC17,
+    _NC18,
+    _NC19,
+    _NC20,
+    _NC21,
+    _NC22,
+    _NC23,
+    _NC24,
+    _NC25,
+    _NC26,
+    _NC27,
+    _NC28,
+    _NC29,
+    _NC30,
+    _NC31,
+    _NC32}),
+    .dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }));
+ wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
+    .m0_wbd_ack_o(wbd_int_ack_o),
+    .m0_wbd_cyc_i(wbd_int_cyc_i),
+    .m0_wbd_err_o(wbd_int_err_o),
+    .m0_wbd_stb_i(wbd_int_stb_i),
+    .m0_wbd_we_i(wbd_int_we_i),
+    .m1_wbd_ack_o(\u_riscv_top.wbd_dmem_ack_i ),
+    .m1_wbd_bry_i(\u_riscv_top.wbd_dmem_bry_o ),
+    .m1_wbd_cyc_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_err_o(\u_riscv_top.wbd_dmem_err_i ),
+    .m1_wbd_lack_o(\u_riscv_top.wbd_dmem_lack_i ),
+    .m1_wbd_stb_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_we_i(\u_riscv_top.wbd_dmem_we_o ),
+    .m2_wbd_ack_o(\u_riscv_top.wb_dcache_ack_i ),
+    .m2_wbd_bry_i(\u_riscv_top.wb_dcache_bry_o ),
+    .m2_wbd_cyc_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_err_o(\u_riscv_top.wb_dcache_err_i ),
+    .m2_wbd_lack_o(\u_riscv_top.wb_dcache_lack_i ),
+    .m2_wbd_stb_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_we_i(\u_riscv_top.wb_dcache_we_o ),
+    .m3_wbd_ack_o(\u_riscv_top.wb_icache_ack_i ),
+    .m3_wbd_bry_i(\u_riscv_top.wb_icache_bry_o ),
+    .m3_wbd_cyc_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_err_o(\u_riscv_top.wb_icache_err_i ),
+    .m3_wbd_lack_o(\u_riscv_top.wb_icache_lack_i ),
+    .m3_wbd_stb_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_we_i(\u_riscv_top.wb_icache_we_o ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .s0_wbd_ack_i(wbd_spim_ack_i),
+    .s0_wbd_bry_o(wbd_spim_bry_o),
+    .s0_wbd_cyc_o(wbd_spim_cyc_o),
+    .s0_wbd_lack_i(wbd_spim_lack_i),
+    .s0_wbd_stb_o(wbd_spim_stb_o),
+    .s0_wbd_we_o(wbd_spim_we_o),
+    .s1_wbd_ack_i(wbd_uart_ack_i),
+    .s1_wbd_cyc_o(wbd_uart_cyc_o),
+    .s1_wbd_stb_o(wbd_uart_stb_o),
+    .s1_wbd_we_o(wbd_uart_we_o),
+    .s2_wbd_ack_i(wbd_glbl_ack_i),
+    .s2_wbd_cyc_o(wbd_glbl_cyc_o),
+    .s2_wbd_stb_o(wbd_glbl_stb_o),
+    .s2_wbd_we_o(wbd_glbl_we_o),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wi(wbd_clk_wi_skew),
+    .cfg_cska_wi({\cfg_clk_skew_ctrl1[3] ,
+    \cfg_clk_skew_ctrl1[2] ,
+    \cfg_clk_skew_ctrl1[1] ,
+    \cfg_clk_skew_ctrl1[0] }),
+    .ch_clk_in({cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int}),
+    .ch_clk_out({\cpu_clk_rp[2] ,
+    \u_riscv_top.core_clk_int[1] ,
+    \u_riscv_top.core_clk_int[0] ,
+    wbd_clk_peri_rp,
+    wbd_clk_pinmux_rp,
+    wbd_clk_uart_rp,
+    wbd_clk_qspi_rp,
+    \u_riscv_top.wbd_clk_int }),
+    .ch_data_in({\cfg_clk_skew_ctrl1[31] ,
+    \cfg_clk_skew_ctrl1[30] ,
+    \cfg_clk_skew_ctrl1[29] ,
+    \cfg_clk_skew_ctrl1[28] ,
+    \cfg_clk_skew_ctrl2[31] ,
+    \cfg_clk_skew_ctrl2[30] ,
+    \cfg_clk_skew_ctrl2[29] ,
+    \cfg_clk_skew_ctrl2[28] ,
+    \cfg_clk_skew_ctrl2[27] ,
+    \cfg_clk_skew_ctrl2[26] ,
+    \cfg_clk_skew_ctrl2[25] ,
+    \cfg_clk_skew_ctrl2[24] ,
+    \strap_sticky[31] ,
+    \strap_sticky[30] ,
+    \strap_sticky[29] ,
+    \strap_sticky[28] ,
+    \strap_sticky[27] ,
+    \strap_sticky[26] ,
+    \strap_sticky[25] ,
+    \strap_sticky[24] ,
+    \strap_sticky[23] ,
+    \strap_sticky[22] ,
+    \strap_sticky[21] ,
+    \strap_sticky[20] ,
+    \strap_sticky[19] ,
+    \strap_sticky[18] ,
+    \strap_sticky[17] ,
+    \strap_sticky[16] ,
+    \strap_sticky[15] ,
+    \strap_sticky[14] ,
+    \strap_sticky[13] ,
+    \strap_sticky[12] ,
+    \strap_sticky[11] ,
+    \strap_sticky[10] ,
+    \strap_sticky[9] ,
+    \strap_sticky[8] ,
+    \strap_sticky[7] ,
+    \strap_sticky[6] ,
+    \strap_sticky[5] ,
+    \strap_sticky[4] ,
+    \strap_sticky[3] ,
+    \strap_sticky[2] ,
+    \strap_sticky[1] ,
+    \strap_sticky[0] ,
+    \strap_uartm[1] ,
+    \strap_uartm[0] ,
+    \system_strap[31] ,
+    \system_strap[30] ,
+    \system_strap[29] ,
+    \system_strap[28] ,
+    \system_strap[27] ,
+    \system_strap[26] ,
+    \system_strap[25] ,
+    \system_strap[24] ,
+    \system_strap[23] ,
+    \system_strap[22] ,
+    \system_strap[21] ,
+    \system_strap[20] ,
+    \system_strap[19] ,
+    \system_strap[18] ,
+    \system_strap[17] ,
+    \system_strap[16] ,
+    \system_strap[15] ,
+    \system_strap[14] ,
+    \system_strap[13] ,
+    \system_strap[12] ,
+    \system_strap[11] ,
+    \system_strap[10] ,
+    \system_strap[9] ,
+    \system_strap[8] ,
+    \system_strap[7] ,
+    \system_strap[6] ,
+    \system_strap[5] ,
+    \system_strap[4] ,
+    \system_strap[3] ,
+    \system_strap[2] ,
+    \system_strap[1] ,
+    \system_strap[0] ,
+    p_reset_n,
+    e_reset_n,
+    cfg_strap_pad_ctrl,
+    soft_irq,
+    \irq_lines[31] ,
+    \irq_lines[30] ,
+    \irq_lines[29] ,
+    \irq_lines[28] ,
+    \irq_lines[27] ,
+    \irq_lines[26] ,
+    \irq_lines[25] ,
+    \irq_lines[24] ,
+    \irq_lines[23] ,
+    \irq_lines[22] ,
+    \irq_lines[21] ,
+    \irq_lines[20] ,
+    \irq_lines[19] ,
+    \irq_lines[18] ,
+    \irq_lines[17] ,
+    \irq_lines[16] ,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] ,
+    \cfg_clk_skew_ctrl2[23] ,
+    \cfg_clk_skew_ctrl2[22] ,
+    \cfg_clk_skew_ctrl2[21] ,
+    \cfg_clk_skew_ctrl2[20] ,
+    \cfg_clk_skew_ctrl2[19] ,
+    \cfg_clk_skew_ctrl2[18] ,
+    \cfg_clk_skew_ctrl2[17] ,
+    \cfg_clk_skew_ctrl2[16] ,
+    \cfg_clk_skew_ctrl2[15] ,
+    \cfg_clk_skew_ctrl2[14] ,
+    \cfg_clk_skew_ctrl2[13] ,
+    \cfg_clk_skew_ctrl2[12] ,
+    \cfg_clk_skew_ctrl2[11] ,
+    \cfg_clk_skew_ctrl2[10] ,
+    \cfg_clk_skew_ctrl2[9] ,
+    \cfg_clk_skew_ctrl2[8] ,
+    \cfg_clk_skew_ctrl2[7] ,
+    \cfg_clk_skew_ctrl2[6] ,
+    \cfg_clk_skew_ctrl2[5] ,
+    \cfg_clk_skew_ctrl2[4] ,
+    \cfg_clk_skew_ctrl2[3] ,
+    \cfg_clk_skew_ctrl2[2] ,
+    \cfg_clk_skew_ctrl2[1] ,
+    \cfg_clk_skew_ctrl2[0] ,
+    \cfg_clk_skew_ctrl1[27] ,
+    \cfg_clk_skew_ctrl1[26] ,
+    \cfg_clk_skew_ctrl1[25] ,
+    \cfg_clk_skew_ctrl1[24] ,
+    \cfg_clk_skew_ctrl1[23] ,
+    \cfg_clk_skew_ctrl1[22] ,
+    \cfg_clk_skew_ctrl1[21] ,
+    \cfg_clk_skew_ctrl1[20] ,
+    \cfg_clk_skew_ctrl1[19] ,
+    \cfg_clk_skew_ctrl1[18] ,
+    \cfg_clk_skew_ctrl1[17] ,
+    \cfg_clk_skew_ctrl1[16] ,
+    \cfg_clk_skew_ctrl1[15] ,
+    \cfg_clk_skew_ctrl1[14] ,
+    \cfg_clk_skew_ctrl1[13] ,
+    \cfg_clk_skew_ctrl1[12] ,
+    \cfg_clk_skew_ctrl1[11] ,
+    \cfg_clk_skew_ctrl1[10] ,
+    \cfg_clk_skew_ctrl1[9] ,
+    \cfg_clk_skew_ctrl1[8] }),
+    .ch_data_out({\cfg_wcska_peri_rp[3] ,
+    \cfg_wcska_peri_rp[2] ,
+    \cfg_wcska_peri_rp[1] ,
+    \cfg_wcska_peri_rp[0] ,
+    \cfg_ccska_fpu_rp[3] ,
+    \cfg_ccska_fpu_rp[2] ,
+    \cfg_ccska_fpu_rp[1] ,
+    \cfg_ccska_fpu_rp[0] ,
+    \cfg_ccska_aes_rp[3] ,
+    \cfg_ccska_aes_rp[2] ,
+    \cfg_ccska_aes_rp[1] ,
+    \cfg_ccska_aes_rp[0] ,
+    \strap_sticky_rp[31] ,
+    \strap_sticky_rp[30] ,
+    \strap_sticky_rp[29] ,
+    \strap_sticky_rp[28] ,
+    \strap_sticky_rp[27] ,
+    \strap_sticky_rp[26] ,
+    \strap_sticky_rp[25] ,
+    \strap_sticky_rp[24] ,
+    \strap_sticky_rp[23] ,
+    \strap_sticky_rp[22] ,
+    \strap_sticky_rp[21] ,
+    \strap_sticky_rp[20] ,
+    \strap_sticky_rp[19] ,
+    \strap_sticky_rp[18] ,
+    \strap_sticky_rp[17] ,
+    \strap_sticky_rp[16] ,
+    \strap_sticky_rp[15] ,
+    \strap_sticky_rp[14] ,
+    \strap_sticky_rp[13] ,
+    \strap_sticky_rp[12] ,
+    \strap_sticky_rp[11] ,
+    \strap_sticky_rp[10] ,
+    \strap_sticky_rp[9] ,
+    \strap_sticky_rp[8] ,
+    \strap_sticky_rp[7] ,
+    \strap_sticky_rp[6] ,
+    \strap_sticky_rp[5] ,
+    \strap_sticky_rp[4] ,
+    \strap_sticky_rp[3] ,
+    \strap_sticky_rp[2] ,
+    \strap_sticky_rp[1] ,
+    \strap_sticky_rp[0] ,
+    \strap_uartm_rp[1] ,
+    \strap_uartm_rp[0] ,
+    \system_strap_rp[31] ,
+    \system_strap_rp[30] ,
+    \system_strap_rp[29] ,
+    \system_strap_rp[28] ,
+    \system_strap_rp[27] ,
+    \system_strap_rp[26] ,
+    \system_strap_rp[25] ,
+    \system_strap_rp[24] ,
+    \system_strap_rp[23] ,
+    \system_strap_rp[22] ,
+    \system_strap_rp[21] ,
+    \system_strap_rp[20] ,
+    \system_strap_rp[19] ,
+    \system_strap_rp[18] ,
+    \system_strap_rp[17] ,
+    \system_strap_rp[16] ,
+    \system_strap_rp[15] ,
+    \system_strap_rp[14] ,
+    \system_strap_rp[13] ,
+    \system_strap_rp[12] ,
+    \system_strap_rp[11] ,
+    \system_strap_rp[10] ,
+    \system_strap_rp[9] ,
+    \system_strap_rp[8] ,
+    \system_strap_rp[7] ,
+    \system_strap_rp[6] ,
+    \system_strap_rp[5] ,
+    \system_strap_rp[4] ,
+    \system_strap_rp[3] ,
+    \system_strap_rp[2] ,
+    \system_strap_rp[1] ,
+    \system_strap_rp[0] ,
+    p_reset_n_rp,
+    e_reset_n_rp,
+    cfg_strap_pad_ctrl_rp,
+    \u_riscv_top.soft_irq ,
+    \u_riscv_top.irq_lines[31] ,
+    \u_riscv_top.irq_lines[30] ,
+    \u_riscv_top.irq_lines[29] ,
+    \u_riscv_top.irq_lines[28] ,
+    \u_riscv_top.irq_lines[27] ,
+    \u_riscv_top.irq_lines[26] ,
+    \u_riscv_top.irq_lines[25] ,
+    \u_riscv_top.irq_lines[24] ,
+    \u_riscv_top.irq_lines[23] ,
+    \u_riscv_top.irq_lines[22] ,
+    \u_riscv_top.irq_lines[21] ,
+    \u_riscv_top.irq_lines[20] ,
+    \u_riscv_top.irq_lines[19] ,
+    \u_riscv_top.irq_lines[18] ,
+    \u_riscv_top.irq_lines[17] ,
+    \u_riscv_top.irq_lines[16] ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[0] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[3] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[2] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[1] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[0] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[3] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[2] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[1] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[0] ,
+    \cfg_wcska_qspi_co_rp[3] ,
+    \cfg_wcska_qspi_co_rp[2] ,
+    \cfg_wcska_qspi_co_rp[1] ,
+    \cfg_wcska_qspi_co_rp[0] ,
+    \cfg_wcska_pinmux_rp[3] ,
+    \cfg_wcska_pinmux_rp[2] ,
+    \cfg_wcska_pinmux_rp[1] ,
+    \cfg_wcska_pinmux_rp[0] ,
+    \cfg_wcska_uart_rp[3] ,
+    \cfg_wcska_uart_rp[2] ,
+    \cfg_wcska_uart_rp[1] ,
+    \cfg_wcska_uart_rp[0] ,
+    \cfg_wcska_qspi_rp[3] ,
+    \cfg_wcska_qspi_rp[2] ,
+    \cfg_wcska_qspi_rp[1] ,
+    \cfg_wcska_qspi_rp[0] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[3] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[2] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[1] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[0] }),
+    .m0_wbd_adr_i({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .m0_wbd_dat_i({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .m0_wbd_dat_o({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .m0_wbd_sel_i({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }),
+    .m1_wbd_adr_i({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .m1_wbd_bl_i({\u_riscv_top.wbd_dmem_bl_o[2] ,
+    \u_riscv_top.wbd_dmem_bl_o[1] ,
+    \u_riscv_top.wbd_dmem_bl_o[0] }),
+    .m1_wbd_dat_i({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .m1_wbd_dat_o({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .m1_wbd_sel_i({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }),
+    .m2_wbd_adr_i({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .m2_wbd_bl_i({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .m2_wbd_dat_i({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .m2_wbd_dat_o({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .m2_wbd_sel_i({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .m3_wbd_adr_i({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .m3_wbd_bl_i({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .m3_wbd_dat_o({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .m3_wbd_sel_i({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .s0_wbd_bl_o({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }),
+    .s1_wbd_adr_o({\wbd_uart_adr_o[8] ,
+    \wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .s1_wbd_dat_i({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .s1_wbd_dat_o({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .s1_wbd_sel_o({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .s2_wbd_adr_o({\wbd_glbl_adr_o[10] ,
+    \wbd_glbl_adr_o[9] ,
+    \wbd_glbl_adr_o[8] ,
+    \wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }));
+ peri_top u_peri (.ir_intr(ir_intr),
+    .ir_rx(ir_rx),
+    .ir_tx(ir_tx),
+    .mclk(wbd_clk_peri_skew),
+    .reg_ack(reg_peri_ack),
+    .reg_cs(reg_peri_cs),
+    .reg_wr(reg_peri_wr),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .rtc_intr(rtc_intr),
+    .s_reset_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_peri_rp),
+    .wbd_clk_peri(wbd_clk_peri_skew),
+    .cfg_cska_peri({\cfg_wcska_peri_rp[3] ,
+    \cfg_wcska_peri_rp[2] ,
+    \cfg_wcska_peri_rp[1] ,
+    \cfg_wcska_peri_rp[0] }),
+    .cfg_dac0_mux_sel({\cfg_dac0_mux_sel[7] ,
+    \cfg_dac0_mux_sel[6] ,
+    \cfg_dac0_mux_sel[5] ,
+    \cfg_dac0_mux_sel[4] ,
+    \cfg_dac0_mux_sel[3] ,
+    \cfg_dac0_mux_sel[2] ,
+    \cfg_dac0_mux_sel[1] ,
+    \cfg_dac0_mux_sel[0] }),
+    .cfg_dac1_mux_sel({\cfg_dac1_mux_sel[7] ,
+    \cfg_dac1_mux_sel[6] ,
+    \cfg_dac1_mux_sel[5] ,
+    \cfg_dac1_mux_sel[4] ,
+    \cfg_dac1_mux_sel[3] ,
+    \cfg_dac1_mux_sel[2] ,
+    \cfg_dac1_mux_sel[1] ,
+    \cfg_dac1_mux_sel[0] }),
+    .cfg_dac2_mux_sel({\cfg_dac2_mux_sel[7] ,
+    \cfg_dac2_mux_sel[6] ,
+    \cfg_dac2_mux_sel[5] ,
+    \cfg_dac2_mux_sel[4] ,
+    \cfg_dac2_mux_sel[3] ,
+    \cfg_dac2_mux_sel[2] ,
+    \cfg_dac2_mux_sel[1] ,
+    \cfg_dac2_mux_sel[0] }),
+    .cfg_dac3_mux_sel({\cfg_dac3_mux_sel[7] ,
+    \cfg_dac3_mux_sel[6] ,
+    \cfg_dac3_mux_sel[5] ,
+    \cfg_dac3_mux_sel[4] ,
+    \cfg_dac3_mux_sel[3] ,
+    \cfg_dac3_mux_sel[2] ,
+    \cfg_dac3_mux_sel[1] ,
+    \cfg_dac3_mux_sel[0] }),
+    .reg_addr({\reg_peri_addr[10] ,
+    \reg_peri_addr[9] ,
+    \reg_peri_addr[8] ,
+    \reg_peri_addr[7] ,
+    \reg_peri_addr[6] ,
+    \reg_peri_addr[5] ,
+    \reg_peri_addr[4] ,
+    \reg_peri_addr[3] ,
+    \reg_peri_addr[2] ,
+    \reg_peri_addr[1] ,
+    \reg_peri_addr[0] }),
+    .reg_be({\reg_peri_be[3] ,
+    \reg_peri_be[2] ,
+    \reg_peri_be[1] ,
+    \reg_peri_be[0] }),
+    .reg_rdata({\reg_peri_rdata[31] ,
+    \reg_peri_rdata[30] ,
+    \reg_peri_rdata[29] ,
+    \reg_peri_rdata[28] ,
+    \reg_peri_rdata[27] ,
+    \reg_peri_rdata[26] ,
+    \reg_peri_rdata[25] ,
+    \reg_peri_rdata[24] ,
+    \reg_peri_rdata[23] ,
+    \reg_peri_rdata[22] ,
+    \reg_peri_rdata[21] ,
+    \reg_peri_rdata[20] ,
+    \reg_peri_rdata[19] ,
+    \reg_peri_rdata[18] ,
+    \reg_peri_rdata[17] ,
+    \reg_peri_rdata[16] ,
+    \reg_peri_rdata[15] ,
+    \reg_peri_rdata[14] ,
+    \reg_peri_rdata[13] ,
+    \reg_peri_rdata[12] ,
+    \reg_peri_rdata[11] ,
+    \reg_peri_rdata[10] ,
+    \reg_peri_rdata[9] ,
+    \reg_peri_rdata[8] ,
+    \reg_peri_rdata[7] ,
+    \reg_peri_rdata[6] ,
+    \reg_peri_rdata[5] ,
+    \reg_peri_rdata[4] ,
+    \reg_peri_rdata[3] ,
+    \reg_peri_rdata[2] ,
+    \reg_peri_rdata[1] ,
+    \reg_peri_rdata[0] }),
+    .reg_wdata({\reg_peri_wdata[31] ,
+    \reg_peri_wdata[30] ,
+    \reg_peri_wdata[29] ,
+    \reg_peri_wdata[28] ,
+    \reg_peri_wdata[27] ,
+    \reg_peri_wdata[26] ,
+    \reg_peri_wdata[25] ,
+    \reg_peri_wdata[24] ,
+    \reg_peri_wdata[23] ,
+    \reg_peri_wdata[22] ,
+    \reg_peri_wdata[21] ,
+    \reg_peri_wdata[20] ,
+    \reg_peri_wdata[19] ,
+    \reg_peri_wdata[18] ,
+    \reg_peri_wdata[17] ,
+    \reg_peri_wdata[16] ,
+    \reg_peri_wdata[15] ,
+    \reg_peri_wdata[14] ,
+    \reg_peri_wdata[13] ,
+    \reg_peri_wdata[12] ,
+    \reg_peri_wdata[11] ,
+    \reg_peri_wdata[10] ,
+    \reg_peri_wdata[9] ,
+    \reg_peri_wdata[8] ,
+    \reg_peri_wdata[7] ,
+    \reg_peri_wdata[6] ,
+    \reg_peri_wdata[5] ,
+    \reg_peri_wdata[4] ,
+    \reg_peri_wdata[3] ,
+    \reg_peri_wdata[2] ,
+    \reg_peri_wdata[1] ,
+    \reg_peri_wdata[0] }));
+ pinmux_top u_pinmux (.cfg_dco_mode(cfg_dco_mode),
+    .cfg_pll_enb(cfg_pll_enb),
+    .cfg_strap_pad_ctrl(cfg_strap_pad_ctrl_rp),
+    .cpu_clk(\cpu_clk_rp[2] ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .e_reset_n(e_reset_n_rp),
+    .i2cm_clk_i(i2cm_clk_i),
+    .i2cm_clk_o(i2cm_clk_o),
+    .i2cm_clk_oen(i2cm_clk_oen),
+    .i2cm_data_i(i2cm_data_i),
+    .i2cm_data_o(i2cm_data_o),
+    .i2cm_data_oen(i2cm_data_oen),
+    .i2cm_intr(i2cm_intr_o),
+    .i2cm_rst_n(i2c_rst_n),
+    .int_pll_clock(\pll_clk_out[0] ),
+    .ir_intr(ir_intr),
+    .ir_rx(ir_rx),
+    .ir_tx(ir_tx),
+    .mclk(wbd_clk_pinmux_skew),
+    .p_reset_n(p_reset_n_rp),
+    .pll_ref_clk(pll_ref_clk),
+    .pulse1m_mclk(pulse1m_mclk),
+    .qspim_rst_n(qspim_rst_n),
+    .reg_ack(wbd_glbl_ack_i),
+    .reg_cs(wbd_glbl_stb_o),
+    .reg_peri_ack(reg_peri_ack),
+    .reg_peri_cs(reg_peri_cs),
+    .reg_peri_wr(reg_peri_wr),
+    .reg_wr(wbd_glbl_we_o),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .rtc_intr(rtc_intr),
+    .s_reset_n(\u_riscv_top.pwrup_rst_n ),
+    .sflash_sck(sflash_sck),
+    .soft_irq(soft_irq),
+    .spim_miso(sspim_so),
+    .spim_mosi(sspim_si),
+    .spim_sck(sspim_sck),
+    .spis_miso(sspis_so),
+    .spis_mosi(sspis_si),
+    .spis_sck(sspis_sck),
+    .spis_ssn(sspis_ssn),
+    .sspim_rst_n(sspim_rst_n),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .usb_clk(usb_clk),
+    .usb_dn_i(usb_dn_i),
+    .usb_dn_o(usb_dn_o),
+    .usb_dp_i(usb_dp_i),
+    .usb_dp_o(usb_dp_o),
+    .usb_intr(usb_intr_o),
+    .usb_oen(usb_oen),
+    .usb_rst_n(usb_rst_n),
+    .user_clock1(\ch_out_south[0] ),
+    .user_clock2(\ch_out_south[252] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_pinmux_rp),
+    .wbd_clk_pinmux(wbd_clk_pinmux_skew),
+    .xtal_clk(xtal_clk),
+    .cfg_cska_pinmux({\cfg_wcska_pinmux_rp[3] ,
+    \cfg_wcska_pinmux_rp[2] ,
+    \cfg_wcska_pinmux_rp[1] ,
+    \cfg_wcska_pinmux_rp[0] }),
+    .cfg_dc_trim({\cfg_dc_trim[25] ,
+    \cfg_dc_trim[24] ,
+    \cfg_dc_trim[23] ,
+    \cfg_dc_trim[22] ,
+    \cfg_dc_trim[21] ,
+    \cfg_dc_trim[20] ,
+    \cfg_dc_trim[19] ,
+    \cfg_dc_trim[18] ,
+    \cfg_dc_trim[17] ,
+    \cfg_dc_trim[16] ,
+    \cfg_dc_trim[15] ,
+    \cfg_dc_trim[14] ,
+    \cfg_dc_trim[13] ,
+    \cfg_dc_trim[12] ,
+    \cfg_dc_trim[11] ,
+    \cfg_dc_trim[10] ,
+    \cfg_dc_trim[9] ,
+    \cfg_dc_trim[8] ,
+    \cfg_dc_trim[7] ,
+    \cfg_dc_trim[6] ,
+    \cfg_dc_trim[5] ,
+    \cfg_dc_trim[4] ,
+    \cfg_dc_trim[3] ,
+    \cfg_dc_trim[2] ,
+    \cfg_dc_trim[1] ,
+    \cfg_dc_trim[0] }),
+    .cfg_pll_fed_div({\cfg_pll_fed_div[4] ,
+    \cfg_pll_fed_div[3] ,
+    \cfg_pll_fed_div[2] ,
+    \cfg_pll_fed_div[1] ,
+    \cfg_pll_fed_div[0] }),
+    .cfg_riscv_ctrl({\cfg_riscv_ctrl[15] ,
+    \cfg_riscv_ctrl[14] ,
+    \cfg_riscv_ctrl[13] ,
+    \cfg_riscv_ctrl[12] ,
+    \cfg_riscv_ctrl[11] ,
+    \cfg_riscv_ctrl[10] ,
+    \cfg_riscv_ctrl[9] ,
+    \cfg_riscv_ctrl[8] ,
+    \cfg_riscv_ctrl[7] ,
+    \cfg_riscv_ctrl[6] ,
+    \cfg_riscv_ctrl[5] ,
+    \cfg_riscv_ctrl[4] ,
+    \cfg_riscv_ctrl[3] ,
+    \cfg_riscv_ctrl[2] ,
+    \cfg_riscv_ctrl[1] ,
+    \cfg_riscv_ctrl[0] }),
+    .cpu_core_rst_n({\u_riscv_top.cpu_core_rst_n[3] ,
+    \u_riscv_top.cpu_core_rst_n[2] ,
+    \u_riscv_top.cpu_core_rst_n[1] ,
+    \u_riscv_top.cpu_core_rst_n[0] }),
+    .digital_io_in({\buf_out_north[39] ,
+    \buf_out_north[36] ,
+    \buf_out_north[33] ,
+    \buf_out_north[30] ,
+    \buf_out_north[27] ,
+    \buf_out_north[24] ,
+    \buf_out_north[21] ,
+    \buf_out_north[18] ,
+    \buf_out_north[15] ,
+    \buf_out_north[12] ,
+    \buf_out_north[9] ,
+    \buf_out_north[6] ,
+    \buf_out_north[3] ,
+    \buf_out_north[0] ,
+    \ch_out_north[2] ,
+    \ch_out_north[5] ,
+    \ch_out_north[8] ,
+    \ch_out_north[11] ,
+    \ch_out_north[14] ,
+    \ch_out_north[17] ,
+    \ch_out_north[20] ,
+    \ch_out_north[23] ,
+    \ch_out_north[26] ,
+    \ch_out_east[2] ,
+    \ch_out_east[5] ,
+    \ch_out_east[8] ,
+    \ch_out_east[11] ,
+    \ch_out_east[14] ,
+    \ch_out_east[17] ,
+    \ch_out_east[20] ,
+    \ch_out_east[23] ,
+    \ch_out_east[26] ,
+    \ch_out_east[29] ,
+    \ch_out_east[32] ,
+    \ch_out_east[35] ,
+    \ch_out_east[38] ,
+    \ch_out_east[41] ,
+    \ch_out_east[44] }),
+    .digital_io_oen({\io_oeb_int[37] ,
+    \io_oeb_int[36] ,
+    \io_oeb_int[35] ,
+    \io_oeb_int[34] ,
+    \io_oeb_int[33] ,
+    \io_oeb_int[32] ,
+    \io_oeb_int[31] ,
+    \io_oeb_int[30] ,
+    \io_oeb_int[29] ,
+    \io_oeb_int[28] ,
+    \io_oeb_int[27] ,
+    \io_oeb_int[26] ,
+    \io_oeb_int[25] ,
+    \io_oeb_int[24] ,
+    \io_oeb_int[23] ,
+    \io_oeb_int[22] ,
+    \io_oeb_int[21] ,
+    \io_oeb_int[20] ,
+    \io_oeb_int[19] ,
+    \io_oeb_int[18] ,
+    \io_oeb_int[17] ,
+    \io_oeb_int[16] ,
+    \io_oeb_int[15] ,
+    \io_oeb_int[14] ,
+    \io_oeb_int[13] ,
+    \io_oeb_int[12] ,
+    \io_oeb_int[11] ,
+    \io_oeb_int[10] ,
+    \io_oeb_int[9] ,
+    \io_oeb_int[8] ,
+    \io_oeb_int[7] ,
+    \io_oeb_int[6] ,
+    \io_oeb_int[5] ,
+    \io_oeb_int[4] ,
+    \io_oeb_int[3] ,
+    \io_oeb_int[2] ,
+    \io_oeb_int[1] ,
+    \io_oeb_int[0] }),
+    .digital_io_out({\io_out_int[37] ,
+    \io_out_int[36] ,
+    \io_out_int[35] ,
+    \io_out_int[34] ,
+    \io_out_int[33] ,
+    \io_out_int[32] ,
+    \io_out_int[31] ,
+    \io_out_int[30] ,
+    \io_out_int[29] ,
+    \io_out_int[28] ,
+    \io_out_int[27] ,
+    \io_out_int[26] ,
+    \io_out_int[25] ,
+    \io_out_int[24] ,
+    \io_out_int[23] ,
+    \io_out_int[22] ,
+    \io_out_int[21] ,
+    \io_out_int[20] ,
+    \io_out_int[19] ,
+    \io_out_int[18] ,
+    \io_out_int[17] ,
+    \io_out_int[16] ,
+    \io_out_int[15] ,
+    \io_out_int[14] ,
+    \io_out_int[13] ,
+    \io_out_int[12] ,
+    \io_out_int[11] ,
+    \io_out_int[10] ,
+    \io_out_int[9] ,
+    \io_out_int[8] ,
+    \io_out_int[7] ,
+    \io_out_int[6] ,
+    \io_out_int[5] ,
+    \io_out_int[4] ,
+    \io_out_int[3] ,
+    \io_out_int[2] ,
+    \io_out_int[1] ,
+    \io_out_int[0] }),
+    .irq_lines({\irq_lines[31] ,
+    \irq_lines[30] ,
+    \irq_lines[29] ,
+    \irq_lines[28] ,
+    \irq_lines[27] ,
+    \irq_lines[26] ,
+    \irq_lines[25] ,
+    \irq_lines[24] ,
+    \irq_lines[23] ,
+    \irq_lines[22] ,
+    \irq_lines[21] ,
+    \irq_lines[20] ,
+    \irq_lines[19] ,
+    \irq_lines[18] ,
+    \irq_lines[17] ,
+    \irq_lines[16] ,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] }),
+    .pinmux_debug({\pinmux_debug[31] ,
+    \pinmux_debug[30] ,
+    \pinmux_debug[29] ,
+    \pinmux_debug[28] ,
+    \pinmux_debug[27] ,
+    \pinmux_debug[26] ,
+    \pinmux_debug[25] ,
+    \pinmux_debug[24] ,
+    \pinmux_debug[23] ,
+    \pinmux_debug[22] ,
+    \pinmux_debug[21] ,
+    \pinmux_debug[20] ,
+    \pinmux_debug[19] ,
+    \pinmux_debug[18] ,
+    \pinmux_debug[17] ,
+    \pinmux_debug[16] ,
+    \pinmux_debug[15] ,
+    \pinmux_debug[14] ,
+    \pinmux_debug[13] ,
+    \pinmux_debug[12] ,
+    \pinmux_debug[11] ,
+    \pinmux_debug[10] ,
+    \pinmux_debug[9] ,
+    \pinmux_debug[8] ,
+    \pinmux_debug[7] ,
+    \pinmux_debug[6] ,
+    \pinmux_debug[5] ,
+    \pinmux_debug[4] ,
+    \pinmux_debug[3] ,
+    \pinmux_debug[2] ,
+    \pinmux_debug[1] ,
+    \pinmux_debug[0] }),
+    .reg_addr({\wbd_glbl_adr_o[10] ,
+    \wbd_glbl_adr_o[9] ,
+    \wbd_glbl_adr_o[8] ,
+    \wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .reg_be({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }),
+    .reg_peri_addr({\reg_peri_addr[10] ,
+    \reg_peri_addr[9] ,
+    \reg_peri_addr[8] ,
+    \reg_peri_addr[7] ,
+    \reg_peri_addr[6] ,
+    \reg_peri_addr[5] ,
+    \reg_peri_addr[4] ,
+    \reg_peri_addr[3] ,
+    \reg_peri_addr[2] ,
+    \reg_peri_addr[1] ,
+    \reg_peri_addr[0] }),
+    .reg_peri_be({\reg_peri_be[3] ,
+    \reg_peri_be[2] ,
+    \reg_peri_be[1] ,
+    \reg_peri_be[0] }),
+    .reg_peri_rdata({\reg_peri_rdata[31] ,
+    \reg_peri_rdata[30] ,
+    \reg_peri_rdata[29] ,
+    \reg_peri_rdata[28] ,
+    \reg_peri_rdata[27] ,
+    \reg_peri_rdata[26] ,
+    \reg_peri_rdata[25] ,
+    \reg_peri_rdata[24] ,
+    \reg_peri_rdata[23] ,
+    \reg_peri_rdata[22] ,
+    \reg_peri_rdata[21] ,
+    \reg_peri_rdata[20] ,
+    \reg_peri_rdata[19] ,
+    \reg_peri_rdata[18] ,
+    \reg_peri_rdata[17] ,
+    \reg_peri_rdata[16] ,
+    \reg_peri_rdata[15] ,
+    \reg_peri_rdata[14] ,
+    \reg_peri_rdata[13] ,
+    \reg_peri_rdata[12] ,
+    \reg_peri_rdata[11] ,
+    \reg_peri_rdata[10] ,
+    \reg_peri_rdata[9] ,
+    \reg_peri_rdata[8] ,
+    \reg_peri_rdata[7] ,
+    \reg_peri_rdata[6] ,
+    \reg_peri_rdata[5] ,
+    \reg_peri_rdata[4] ,
+    \reg_peri_rdata[3] ,
+    \reg_peri_rdata[2] ,
+    \reg_peri_rdata[1] ,
+    \reg_peri_rdata[0] }),
+    .reg_peri_wdata({\reg_peri_wdata[31] ,
+    \reg_peri_wdata[30] ,
+    \reg_peri_wdata[29] ,
+    \reg_peri_wdata[28] ,
+    \reg_peri_wdata[27] ,
+    \reg_peri_wdata[26] ,
+    \reg_peri_wdata[25] ,
+    \reg_peri_wdata[24] ,
+    \reg_peri_wdata[23] ,
+    \reg_peri_wdata[22] ,
+    \reg_peri_wdata[21] ,
+    \reg_peri_wdata[20] ,
+    \reg_peri_wdata[19] ,
+    \reg_peri_wdata[18] ,
+    \reg_peri_wdata[17] ,
+    \reg_peri_wdata[16] ,
+    \reg_peri_wdata[15] ,
+    \reg_peri_wdata[14] ,
+    \reg_peri_wdata[13] ,
+    \reg_peri_wdata[12] ,
+    \reg_peri_wdata[11] ,
+    \reg_peri_wdata[10] ,
+    \reg_peri_wdata[9] ,
+    \reg_peri_wdata[8] ,
+    \reg_peri_wdata[7] ,
+    \reg_peri_wdata[6] ,
+    \reg_peri_wdata[5] ,
+    \reg_peri_wdata[4] ,
+    \reg_peri_wdata[3] ,
+    \reg_peri_wdata[2] ,
+    \reg_peri_wdata[1] ,
+    \reg_peri_wdata[0] }),
+    .reg_rdata({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .reg_wdata({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .sflash_di({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .sflash_do({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .sflash_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .sflash_ss({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spim_ssn({\sspim_ssn[3] ,
+    \sspim_ssn[2] ,
+    \sspim_ssn[1] ,
+    \sspim_ssn[0] }),
+    .strap_sticky({\strap_sticky[31] ,
+    \strap_sticky[30] ,
+    \strap_sticky[29] ,
+    \strap_sticky[28] ,
+    \strap_sticky[27] ,
+    \strap_sticky[26] ,
+    \strap_sticky[25] ,
+    \strap_sticky[24] ,
+    \strap_sticky[23] ,
+    \strap_sticky[22] ,
+    \strap_sticky[21] ,
+    \strap_sticky[20] ,
+    \strap_sticky[19] ,
+    \strap_sticky[18] ,
+    \strap_sticky[17] ,
+    \strap_sticky[16] ,
+    \strap_sticky[15] ,
+    \strap_sticky[14] ,
+    \strap_sticky[13] ,
+    \strap_sticky[12] ,
+    \strap_sticky[11] ,
+    \strap_sticky[10] ,
+    \strap_sticky[9] ,
+    \strap_sticky[8] ,
+    \strap_sticky[7] ,
+    \strap_sticky[6] ,
+    \strap_sticky[5] ,
+    \strap_sticky[4] ,
+    \strap_sticky[3] ,
+    \strap_sticky[2] ,
+    \strap_sticky[1] ,
+    \strap_sticky[0] }),
+    .strap_uartm({\strap_uartm[1] ,
+    \strap_uartm[0] }),
+    .system_strap({\system_strap_rp[31] ,
+    \system_strap_rp[30] ,
+    \system_strap_rp[29] ,
+    \system_strap_rp[28] ,
+    \system_strap_rp[27] ,
+    \system_strap_rp[26] ,
+    \system_strap_rp[25] ,
+    \system_strap_rp[24] ,
+    \system_strap_rp[23] ,
+    \system_strap_rp[22] ,
+    \system_strap_rp[21] ,
+    \system_strap_rp[20] ,
+    \system_strap_rp[19] ,
+    \system_strap_rp[18] ,
+    \system_strap_rp[17] ,
+    \system_strap_rp[16] ,
+    \system_strap_rp[15] ,
+    \system_strap_rp[14] ,
+    \system_strap_rp[13] ,
+    \system_strap_rp[12] ,
+    \system_strap_rp[11] ,
+    \system_strap_rp[10] ,
+    \system_strap_rp[9] ,
+    \system_strap_rp[8] ,
+    \system_strap_rp[7] ,
+    \system_strap_rp[6] ,
+    \system_strap_rp[5] ,
+    \system_strap_rp[4] ,
+    \system_strap_rp[3] ,
+    \system_strap_rp[2] ,
+    \system_strap_rp[1] ,
+    \system_strap_rp[0] }),
+    .uart_rst_n({\uart_rst_n[1] ,
+    \uart_rst_n[0] }),
+    .uart_rxd({\uart_rxd[1] ,
+    \uart_rxd[0] }),
+    .uart_txd({\uart_txd[1] ,
+    \uart_txd[0] }),
+    .user_irq({user_irq[2],
+    user_irq[1],
+    user_irq[0]}));
+ dg_pll u_pll (.VGND(vssd1),
+    .VPWR(vccd1),
+    .dco(cfg_dco_mode),
+    .enable(cfg_pll_enb),
+    .osc(pll_ref_clk),
+    .resetb(wbd_pll_rst_n),
+    .clockp({\pll_clk_out[1] ,
+    \pll_clk_out[0] }),
+    .div({\cfg_pll_fed_div[4] ,
+    \cfg_pll_fed_div[3] ,
+    \cfg_pll_fed_div[2] ,
+    \cfg_pll_fed_div[1] ,
+    \cfg_pll_fed_div[0] }),
+    .ext_trim({\cfg_dc_trim[25] ,
+    \cfg_dc_trim[24] ,
+    \cfg_dc_trim[23] ,
+    \cfg_dc_trim[22] ,
+    \cfg_dc_trim[21] ,
+    \cfg_dc_trim[20] ,
+    \cfg_dc_trim[19] ,
+    \cfg_dc_trim[18] ,
+    \cfg_dc_trim[17] ,
+    \cfg_dc_trim[16] ,
+    \cfg_dc_trim[15] ,
+    \cfg_dc_trim[14] ,
+    \cfg_dc_trim[13] ,
+    \cfg_dc_trim[12] ,
+    \cfg_dc_trim[11] ,
+    \cfg_dc_trim[10] ,
+    \cfg_dc_trim[9] ,
+    \cfg_dc_trim[8] ,
+    \cfg_dc_trim[7] ,
+    \cfg_dc_trim[6] ,
+    \cfg_dc_trim[5] ,
+    \cfg_dc_trim[4] ,
+    \cfg_dc_trim[3] ,
+    \cfg_dc_trim[2] ,
+    \cfg_dc_trim[1] ,
+    \cfg_dc_trim[0] }));
+ qspim_top u_qspi_master (.cfg_init_bypass(\system_strap[30] ),
+    .mclk(wbd_clk_spi),
+    .rst_n(qspim_rst_n),
+    .spi_clk(sflash_sck),
+    .strap_pre_sram(\system_strap[15] ),
+    .strap_sram(\system_strap[9] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_ack_o(wbd_spim_ack_i),
+    .wbd_bry_i(wbd_spim_bry_o),
+    .wbd_clk_int(wbd_clk_qspi_rp),
+    .wbd_clk_spi(wbd_clk_spi),
+    .wbd_err_o(wbd_spim_err_i),
+    .wbd_lack_o(wbd_spim_lack_i),
+    .wbd_stb_i(wbd_spim_stb_o),
+    .wbd_we_i(wbd_spim_we_o),
+    .cfg_cska_sp_co({\cfg_wcska_qspi_co_rp[3] ,
+    \cfg_wcska_qspi_co_rp[2] ,
+    \cfg_wcska_qspi_co_rp[1] ,
+    \cfg_wcska_qspi_co_rp[0] }),
+    .cfg_cska_spi({\cfg_wcska_qspi_rp[3] ,
+    \cfg_wcska_qspi_rp[2] ,
+    \cfg_wcska_qspi_rp[1] ,
+    \cfg_wcska_qspi_rp[0] }),
+    .spi_csn({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spi_debug({\spi_debug[31] ,
+    \spi_debug[30] ,
+    \spi_debug[29] ,
+    \spi_debug[28] ,
+    \spi_debug[27] ,
+    \spi_debug[26] ,
+    \spi_debug[25] ,
+    \spi_debug[24] ,
+    \spi_debug[23] ,
+    \spi_debug[22] ,
+    \spi_debug[21] ,
+    \spi_debug[20] ,
+    \spi_debug[19] ,
+    \spi_debug[18] ,
+    \spi_debug[17] ,
+    \spi_debug[16] ,
+    \spi_debug[15] ,
+    \spi_debug[14] ,
+    \spi_debug[13] ,
+    \spi_debug[12] ,
+    \spi_debug[11] ,
+    \spi_debug[10] ,
+    \spi_debug[9] ,
+    \spi_debug[8] ,
+    \spi_debug[7] ,
+    \spi_debug[6] ,
+    \spi_debug[5] ,
+    \spi_debug[4] ,
+    \spi_debug[3] ,
+    \spi_debug[2] ,
+    \spi_debug[1] ,
+    \spi_debug[0] }),
+    .spi_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .spi_sdi({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .spi_sdo({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .strap_flash({\system_strap[11] ,
+    \system_strap[10] }),
+    .wbd_adr_i({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .wbd_bl_i({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .wbd_dat_i({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .wbd_dat_o({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .wbd_sel_i({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_0  (.clk(\u_riscv_top.core_clk_core0_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[0] ),
+    .core2dmem_cmd_o(\u_riscv_top.core0_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core0_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core0_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core0_imem_req ),
+    .core_clk_int(\u_riscv_top.core0_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core0_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core0_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core0_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[0] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core0_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core0_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core0[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core0_irq_lines[31] ,
+    \u_riscv_top.core0_irq_lines[30] ,
+    \u_riscv_top.core0_irq_lines[29] ,
+    \u_riscv_top.core0_irq_lines[28] ,
+    \u_riscv_top.core0_irq_lines[27] ,
+    \u_riscv_top.core0_irq_lines[26] ,
+    \u_riscv_top.core0_irq_lines[25] ,
+    \u_riscv_top.core0_irq_lines[24] ,
+    \u_riscv_top.core0_irq_lines[23] ,
+    \u_riscv_top.core0_irq_lines[22] ,
+    \u_riscv_top.core0_irq_lines[21] ,
+    \u_riscv_top.core0_irq_lines[20] ,
+    \u_riscv_top.core0_irq_lines[19] ,
+    \u_riscv_top.core0_irq_lines[18] ,
+    \u_riscv_top.core0_irq_lines[17] ,
+    \u_riscv_top.core0_irq_lines[16] ,
+    \u_riscv_top.core0_irq_lines[15] ,
+    \u_riscv_top.core0_irq_lines[14] ,
+    \u_riscv_top.core0_irq_lines[13] ,
+    \u_riscv_top.core0_irq_lines[12] ,
+    \u_riscv_top.core0_irq_lines[11] ,
+    \u_riscv_top.core0_irq_lines[10] ,
+    \u_riscv_top.core0_irq_lines[9] ,
+    \u_riscv_top.core0_irq_lines[8] ,
+    \u_riscv_top.core0_irq_lines[7] ,
+    \u_riscv_top.core0_irq_lines[6] ,
+    \u_riscv_top.core0_irq_lines[5] ,
+    \u_riscv_top.core0_irq_lines[4] ,
+    \u_riscv_top.core0_irq_lines[3] ,
+    \u_riscv_top.core0_irq_lines[2] ,
+    \u_riscv_top.core0_irq_lines[1] ,
+    \u_riscv_top.core0_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core0_timer_val[63] ,
+    \u_riscv_top.core0_timer_val[62] ,
+    \u_riscv_top.core0_timer_val[61] ,
+    \u_riscv_top.core0_timer_val[60] ,
+    \u_riscv_top.core0_timer_val[59] ,
+    \u_riscv_top.core0_timer_val[58] ,
+    \u_riscv_top.core0_timer_val[57] ,
+    \u_riscv_top.core0_timer_val[56] ,
+    \u_riscv_top.core0_timer_val[55] ,
+    \u_riscv_top.core0_timer_val[54] ,
+    \u_riscv_top.core0_timer_val[53] ,
+    \u_riscv_top.core0_timer_val[52] ,
+    \u_riscv_top.core0_timer_val[51] ,
+    \u_riscv_top.core0_timer_val[50] ,
+    \u_riscv_top.core0_timer_val[49] ,
+    \u_riscv_top.core0_timer_val[48] ,
+    \u_riscv_top.core0_timer_val[47] ,
+    \u_riscv_top.core0_timer_val[46] ,
+    \u_riscv_top.core0_timer_val[45] ,
+    \u_riscv_top.core0_timer_val[44] ,
+    \u_riscv_top.core0_timer_val[43] ,
+    \u_riscv_top.core0_timer_val[42] ,
+    \u_riscv_top.core0_timer_val[41] ,
+    \u_riscv_top.core0_timer_val[40] ,
+    \u_riscv_top.core0_timer_val[39] ,
+    \u_riscv_top.core0_timer_val[38] ,
+    \u_riscv_top.core0_timer_val[37] ,
+    \u_riscv_top.core0_timer_val[36] ,
+    \u_riscv_top.core0_timer_val[35] ,
+    \u_riscv_top.core0_timer_val[34] ,
+    \u_riscv_top.core0_timer_val[33] ,
+    \u_riscv_top.core0_timer_val[32] ,
+    \u_riscv_top.core0_timer_val[31] ,
+    \u_riscv_top.core0_timer_val[30] ,
+    \u_riscv_top.core0_timer_val[29] ,
+    \u_riscv_top.core0_timer_val[28] ,
+    \u_riscv_top.core0_timer_val[27] ,
+    \u_riscv_top.core0_timer_val[26] ,
+    \u_riscv_top.core0_timer_val[25] ,
+    \u_riscv_top.core0_timer_val[24] ,
+    \u_riscv_top.core0_timer_val[23] ,
+    \u_riscv_top.core0_timer_val[22] ,
+    \u_riscv_top.core0_timer_val[21] ,
+    \u_riscv_top.core0_timer_val[20] ,
+    \u_riscv_top.core0_timer_val[19] ,
+    \u_riscv_top.core0_timer_val[18] ,
+    \u_riscv_top.core0_timer_val[17] ,
+    \u_riscv_top.core0_timer_val[16] ,
+    \u_riscv_top.core0_timer_val[15] ,
+    \u_riscv_top.core0_timer_val[14] ,
+    \u_riscv_top.core0_timer_val[13] ,
+    \u_riscv_top.core0_timer_val[12] ,
+    \u_riscv_top.core0_timer_val[11] ,
+    \u_riscv_top.core0_timer_val[10] ,
+    \u_riscv_top.core0_timer_val[9] ,
+    \u_riscv_top.core0_timer_val[8] ,
+    \u_riscv_top.core0_timer_val[7] ,
+    \u_riscv_top.core0_timer_val[6] ,
+    \u_riscv_top.core0_timer_val[5] ,
+    \u_riscv_top.core0_timer_val[4] ,
+    \u_riscv_top.core0_timer_val[3] ,
+    \u_riscv_top.core0_timer_val[2] ,
+    \u_riscv_top.core0_timer_val[1] ,
+    \u_riscv_top.core0_timer_val[0] }),
+    .core_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_1  (.clk(\u_riscv_top.core_clk_core1_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[1] ),
+    .core2dmem_cmd_o(\u_riscv_top.core1_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core1_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core1_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core1_imem_req ),
+    .core_clk_int(\u_riscv_top.core1_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core1_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core1_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core1_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[1] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core1_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core1_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core1[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core1_irq_lines[31] ,
+    \u_riscv_top.core1_irq_lines[30] ,
+    \u_riscv_top.core1_irq_lines[29] ,
+    \u_riscv_top.core1_irq_lines[28] ,
+    \u_riscv_top.core1_irq_lines[27] ,
+    \u_riscv_top.core1_irq_lines[26] ,
+    \u_riscv_top.core1_irq_lines[25] ,
+    \u_riscv_top.core1_irq_lines[24] ,
+    \u_riscv_top.core1_irq_lines[23] ,
+    \u_riscv_top.core1_irq_lines[22] ,
+    \u_riscv_top.core1_irq_lines[21] ,
+    \u_riscv_top.core1_irq_lines[20] ,
+    \u_riscv_top.core1_irq_lines[19] ,
+    \u_riscv_top.core1_irq_lines[18] ,
+    \u_riscv_top.core1_irq_lines[17] ,
+    \u_riscv_top.core1_irq_lines[16] ,
+    \u_riscv_top.core1_irq_lines[15] ,
+    \u_riscv_top.core1_irq_lines[14] ,
+    \u_riscv_top.core1_irq_lines[13] ,
+    \u_riscv_top.core1_irq_lines[12] ,
+    \u_riscv_top.core1_irq_lines[11] ,
+    \u_riscv_top.core1_irq_lines[10] ,
+    \u_riscv_top.core1_irq_lines[9] ,
+    \u_riscv_top.core1_irq_lines[8] ,
+    \u_riscv_top.core1_irq_lines[7] ,
+    \u_riscv_top.core1_irq_lines[6] ,
+    \u_riscv_top.core1_irq_lines[5] ,
+    \u_riscv_top.core1_irq_lines[4] ,
+    \u_riscv_top.core1_irq_lines[3] ,
+    \u_riscv_top.core1_irq_lines[2] ,
+    \u_riscv_top.core1_irq_lines[1] ,
+    \u_riscv_top.core1_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core1_timer_val[63] ,
+    \u_riscv_top.core1_timer_val[62] ,
+    \u_riscv_top.core1_timer_val[61] ,
+    \u_riscv_top.core1_timer_val[60] ,
+    \u_riscv_top.core1_timer_val[59] ,
+    \u_riscv_top.core1_timer_val[58] ,
+    \u_riscv_top.core1_timer_val[57] ,
+    \u_riscv_top.core1_timer_val[56] ,
+    \u_riscv_top.core1_timer_val[55] ,
+    \u_riscv_top.core1_timer_val[54] ,
+    \u_riscv_top.core1_timer_val[53] ,
+    \u_riscv_top.core1_timer_val[52] ,
+    \u_riscv_top.core1_timer_val[51] ,
+    \u_riscv_top.core1_timer_val[50] ,
+    \u_riscv_top.core1_timer_val[49] ,
+    \u_riscv_top.core1_timer_val[48] ,
+    \u_riscv_top.core1_timer_val[47] ,
+    \u_riscv_top.core1_timer_val[46] ,
+    \u_riscv_top.core1_timer_val[45] ,
+    \u_riscv_top.core1_timer_val[44] ,
+    \u_riscv_top.core1_timer_val[43] ,
+    \u_riscv_top.core1_timer_val[42] ,
+    \u_riscv_top.core1_timer_val[41] ,
+    \u_riscv_top.core1_timer_val[40] ,
+    \u_riscv_top.core1_timer_val[39] ,
+    \u_riscv_top.core1_timer_val[38] ,
+    \u_riscv_top.core1_timer_val[37] ,
+    \u_riscv_top.core1_timer_val[36] ,
+    \u_riscv_top.core1_timer_val[35] ,
+    \u_riscv_top.core1_timer_val[34] ,
+    \u_riscv_top.core1_timer_val[33] ,
+    \u_riscv_top.core1_timer_val[32] ,
+    \u_riscv_top.core1_timer_val[31] ,
+    \u_riscv_top.core1_timer_val[30] ,
+    \u_riscv_top.core1_timer_val[29] ,
+    \u_riscv_top.core1_timer_val[28] ,
+    \u_riscv_top.core1_timer_val[27] ,
+    \u_riscv_top.core1_timer_val[26] ,
+    \u_riscv_top.core1_timer_val[25] ,
+    \u_riscv_top.core1_timer_val[24] ,
+    \u_riscv_top.core1_timer_val[23] ,
+    \u_riscv_top.core1_timer_val[22] ,
+    \u_riscv_top.core1_timer_val[21] ,
+    \u_riscv_top.core1_timer_val[20] ,
+    \u_riscv_top.core1_timer_val[19] ,
+    \u_riscv_top.core1_timer_val[18] ,
+    \u_riscv_top.core1_timer_val[17] ,
+    \u_riscv_top.core1_timer_val[16] ,
+    \u_riscv_top.core1_timer_val[15] ,
+    \u_riscv_top.core1_timer_val[14] ,
+    \u_riscv_top.core1_timer_val[13] ,
+    \u_riscv_top.core1_timer_val[12] ,
+    \u_riscv_top.core1_timer_val[11] ,
+    \u_riscv_top.core1_timer_val[10] ,
+    \u_riscv_top.core1_timer_val[9] ,
+    \u_riscv_top.core1_timer_val[8] ,
+    \u_riscv_top.core1_timer_val[7] ,
+    \u_riscv_top.core1_timer_val[6] ,
+    \u_riscv_top.core1_timer_val[5] ,
+    \u_riscv_top.core1_timer_val[4] ,
+    \u_riscv_top.core1_timer_val[3] ,
+    \u_riscv_top.core1_timer_val[2] ,
+    \u_riscv_top.core1_timer_val[1] ,
+    \u_riscv_top.core1_timer_val[0] }),
+    .core_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_2  (.clk(\u_riscv_top.core_clk_core2_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[2] ),
+    .core2dmem_cmd_o(\u_riscv_top.core2_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core2_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core2_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core2_imem_req ),
+    .core_clk_int(\u_riscv_top.core2_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core2_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core2_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core2_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[2] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core2_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core2_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core2[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core2[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core2_dmem_addr[31] ,
+    \u_riscv_top.core2_dmem_addr[30] ,
+    \u_riscv_top.core2_dmem_addr[29] ,
+    \u_riscv_top.core2_dmem_addr[28] ,
+    \u_riscv_top.core2_dmem_addr[27] ,
+    \u_riscv_top.core2_dmem_addr[26] ,
+    \u_riscv_top.core2_dmem_addr[25] ,
+    \u_riscv_top.core2_dmem_addr[24] ,
+    \u_riscv_top.core2_dmem_addr[23] ,
+    \u_riscv_top.core2_dmem_addr[22] ,
+    \u_riscv_top.core2_dmem_addr[21] ,
+    \u_riscv_top.core2_dmem_addr[20] ,
+    \u_riscv_top.core2_dmem_addr[19] ,
+    \u_riscv_top.core2_dmem_addr[18] ,
+    \u_riscv_top.core2_dmem_addr[17] ,
+    \u_riscv_top.core2_dmem_addr[16] ,
+    \u_riscv_top.core2_dmem_addr[15] ,
+    \u_riscv_top.core2_dmem_addr[14] ,
+    \u_riscv_top.core2_dmem_addr[13] ,
+    \u_riscv_top.core2_dmem_addr[12] ,
+    \u_riscv_top.core2_dmem_addr[11] ,
+    \u_riscv_top.core2_dmem_addr[10] ,
+    \u_riscv_top.core2_dmem_addr[9] ,
+    \u_riscv_top.core2_dmem_addr[8] ,
+    \u_riscv_top.core2_dmem_addr[7] ,
+    \u_riscv_top.core2_dmem_addr[6] ,
+    \u_riscv_top.core2_dmem_addr[5] ,
+    \u_riscv_top.core2_dmem_addr[4] ,
+    \u_riscv_top.core2_dmem_addr[3] ,
+    \u_riscv_top.core2_dmem_addr[2] ,
+    \u_riscv_top.core2_dmem_addr[1] ,
+    \u_riscv_top.core2_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core2_dmem_wdata[31] ,
+    \u_riscv_top.core2_dmem_wdata[30] ,
+    \u_riscv_top.core2_dmem_wdata[29] ,
+    \u_riscv_top.core2_dmem_wdata[28] ,
+    \u_riscv_top.core2_dmem_wdata[27] ,
+    \u_riscv_top.core2_dmem_wdata[26] ,
+    \u_riscv_top.core2_dmem_wdata[25] ,
+    \u_riscv_top.core2_dmem_wdata[24] ,
+    \u_riscv_top.core2_dmem_wdata[23] ,
+    \u_riscv_top.core2_dmem_wdata[22] ,
+    \u_riscv_top.core2_dmem_wdata[21] ,
+    \u_riscv_top.core2_dmem_wdata[20] ,
+    \u_riscv_top.core2_dmem_wdata[19] ,
+    \u_riscv_top.core2_dmem_wdata[18] ,
+    \u_riscv_top.core2_dmem_wdata[17] ,
+    \u_riscv_top.core2_dmem_wdata[16] ,
+    \u_riscv_top.core2_dmem_wdata[15] ,
+    \u_riscv_top.core2_dmem_wdata[14] ,
+    \u_riscv_top.core2_dmem_wdata[13] ,
+    \u_riscv_top.core2_dmem_wdata[12] ,
+    \u_riscv_top.core2_dmem_wdata[11] ,
+    \u_riscv_top.core2_dmem_wdata[10] ,
+    \u_riscv_top.core2_dmem_wdata[9] ,
+    \u_riscv_top.core2_dmem_wdata[8] ,
+    \u_riscv_top.core2_dmem_wdata[7] ,
+    \u_riscv_top.core2_dmem_wdata[6] ,
+    \u_riscv_top.core2_dmem_wdata[5] ,
+    \u_riscv_top.core2_dmem_wdata[4] ,
+    \u_riscv_top.core2_dmem_wdata[3] ,
+    \u_riscv_top.core2_dmem_wdata[2] ,
+    \u_riscv_top.core2_dmem_wdata[1] ,
+    \u_riscv_top.core2_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core2_dmem_width[1] ,
+    \u_riscv_top.core2_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core2_imem_addr[31] ,
+    \u_riscv_top.core2_imem_addr[30] ,
+    \u_riscv_top.core2_imem_addr[29] ,
+    \u_riscv_top.core2_imem_addr[28] ,
+    \u_riscv_top.core2_imem_addr[27] ,
+    \u_riscv_top.core2_imem_addr[26] ,
+    \u_riscv_top.core2_imem_addr[25] ,
+    \u_riscv_top.core2_imem_addr[24] ,
+    \u_riscv_top.core2_imem_addr[23] ,
+    \u_riscv_top.core2_imem_addr[22] ,
+    \u_riscv_top.core2_imem_addr[21] ,
+    \u_riscv_top.core2_imem_addr[20] ,
+    \u_riscv_top.core2_imem_addr[19] ,
+    \u_riscv_top.core2_imem_addr[18] ,
+    \u_riscv_top.core2_imem_addr[17] ,
+    \u_riscv_top.core2_imem_addr[16] ,
+    \u_riscv_top.core2_imem_addr[15] ,
+    \u_riscv_top.core2_imem_addr[14] ,
+    \u_riscv_top.core2_imem_addr[13] ,
+    \u_riscv_top.core2_imem_addr[12] ,
+    \u_riscv_top.core2_imem_addr[11] ,
+    \u_riscv_top.core2_imem_addr[10] ,
+    \u_riscv_top.core2_imem_addr[9] ,
+    \u_riscv_top.core2_imem_addr[8] ,
+    \u_riscv_top.core2_imem_addr[7] ,
+    \u_riscv_top.core2_imem_addr[6] ,
+    \u_riscv_top.core2_imem_addr[5] ,
+    \u_riscv_top.core2_imem_addr[4] ,
+    \u_riscv_top.core2_imem_addr[3] ,
+    \u_riscv_top.core2_imem_addr[2] ,
+    \u_riscv_top.core2_imem_addr[1] ,
+    \u_riscv_top.core2_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core2_imem_bl[2] ,
+    \u_riscv_top.core2_imem_bl[1] ,
+    \u_riscv_top.core2_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core2_debug[48] ,
+    \u_riscv_top.core2_debug[47] ,
+    \u_riscv_top.core2_debug[46] ,
+    \u_riscv_top.core2_debug[45] ,
+    \u_riscv_top.core2_debug[44] ,
+    \u_riscv_top.core2_debug[43] ,
+    \u_riscv_top.core2_debug[42] ,
+    \u_riscv_top.core2_debug[41] ,
+    \u_riscv_top.core2_debug[40] ,
+    \u_riscv_top.core2_debug[39] ,
+    \u_riscv_top.core2_debug[38] ,
+    \u_riscv_top.core2_debug[37] ,
+    \u_riscv_top.core2_debug[36] ,
+    \u_riscv_top.core2_debug[35] ,
+    \u_riscv_top.core2_debug[34] ,
+    \u_riscv_top.core2_debug[33] ,
+    \u_riscv_top.core2_debug[32] ,
+    \u_riscv_top.core2_debug[31] ,
+    \u_riscv_top.core2_debug[30] ,
+    \u_riscv_top.core2_debug[29] ,
+    \u_riscv_top.core2_debug[28] ,
+    \u_riscv_top.core2_debug[27] ,
+    \u_riscv_top.core2_debug[26] ,
+    \u_riscv_top.core2_debug[25] ,
+    \u_riscv_top.core2_debug[24] ,
+    \u_riscv_top.core2_debug[23] ,
+    \u_riscv_top.core2_debug[22] ,
+    \u_riscv_top.core2_debug[21] ,
+    \u_riscv_top.core2_debug[20] ,
+    \u_riscv_top.core2_debug[19] ,
+    \u_riscv_top.core2_debug[18] ,
+    \u_riscv_top.core2_debug[17] ,
+    \u_riscv_top.core2_debug[16] ,
+    \u_riscv_top.core2_debug[15] ,
+    \u_riscv_top.core2_debug[14] ,
+    \u_riscv_top.core2_debug[13] ,
+    \u_riscv_top.core2_debug[12] ,
+    \u_riscv_top.core2_debug[11] ,
+    \u_riscv_top.core2_debug[10] ,
+    \u_riscv_top.core2_debug[9] ,
+    \u_riscv_top.core2_debug[8] ,
+    \u_riscv_top.core2_debug[7] ,
+    \u_riscv_top.core2_debug[6] ,
+    \u_riscv_top.core2_debug[5] ,
+    \u_riscv_top.core2_debug[4] ,
+    \u_riscv_top.core2_debug[3] ,
+    \u_riscv_top.core2_debug[2] ,
+    \u_riscv_top.core2_debug[1] ,
+    \u_riscv_top.core2_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core2_irq_lines[31] ,
+    \u_riscv_top.core2_irq_lines[30] ,
+    \u_riscv_top.core2_irq_lines[29] ,
+    \u_riscv_top.core2_irq_lines[28] ,
+    \u_riscv_top.core2_irq_lines[27] ,
+    \u_riscv_top.core2_irq_lines[26] ,
+    \u_riscv_top.core2_irq_lines[25] ,
+    \u_riscv_top.core2_irq_lines[24] ,
+    \u_riscv_top.core2_irq_lines[23] ,
+    \u_riscv_top.core2_irq_lines[22] ,
+    \u_riscv_top.core2_irq_lines[21] ,
+    \u_riscv_top.core2_irq_lines[20] ,
+    \u_riscv_top.core2_irq_lines[19] ,
+    \u_riscv_top.core2_irq_lines[18] ,
+    \u_riscv_top.core2_irq_lines[17] ,
+    \u_riscv_top.core2_irq_lines[16] ,
+    \u_riscv_top.core2_irq_lines[15] ,
+    \u_riscv_top.core2_irq_lines[14] ,
+    \u_riscv_top.core2_irq_lines[13] ,
+    \u_riscv_top.core2_irq_lines[12] ,
+    \u_riscv_top.core2_irq_lines[11] ,
+    \u_riscv_top.core2_irq_lines[10] ,
+    \u_riscv_top.core2_irq_lines[9] ,
+    \u_riscv_top.core2_irq_lines[8] ,
+    \u_riscv_top.core2_irq_lines[7] ,
+    \u_riscv_top.core2_irq_lines[6] ,
+    \u_riscv_top.core2_irq_lines[5] ,
+    \u_riscv_top.core2_irq_lines[4] ,
+    \u_riscv_top.core2_irq_lines[3] ,
+    \u_riscv_top.core2_irq_lines[2] ,
+    \u_riscv_top.core2_irq_lines[1] ,
+    \u_riscv_top.core2_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core2_timer_val[63] ,
+    \u_riscv_top.core2_timer_val[62] ,
+    \u_riscv_top.core2_timer_val[61] ,
+    \u_riscv_top.core2_timer_val[60] ,
+    \u_riscv_top.core2_timer_val[59] ,
+    \u_riscv_top.core2_timer_val[58] ,
+    \u_riscv_top.core2_timer_val[57] ,
+    \u_riscv_top.core2_timer_val[56] ,
+    \u_riscv_top.core2_timer_val[55] ,
+    \u_riscv_top.core2_timer_val[54] ,
+    \u_riscv_top.core2_timer_val[53] ,
+    \u_riscv_top.core2_timer_val[52] ,
+    \u_riscv_top.core2_timer_val[51] ,
+    \u_riscv_top.core2_timer_val[50] ,
+    \u_riscv_top.core2_timer_val[49] ,
+    \u_riscv_top.core2_timer_val[48] ,
+    \u_riscv_top.core2_timer_val[47] ,
+    \u_riscv_top.core2_timer_val[46] ,
+    \u_riscv_top.core2_timer_val[45] ,
+    \u_riscv_top.core2_timer_val[44] ,
+    \u_riscv_top.core2_timer_val[43] ,
+    \u_riscv_top.core2_timer_val[42] ,
+    \u_riscv_top.core2_timer_val[41] ,
+    \u_riscv_top.core2_timer_val[40] ,
+    \u_riscv_top.core2_timer_val[39] ,
+    \u_riscv_top.core2_timer_val[38] ,
+    \u_riscv_top.core2_timer_val[37] ,
+    \u_riscv_top.core2_timer_val[36] ,
+    \u_riscv_top.core2_timer_val[35] ,
+    \u_riscv_top.core2_timer_val[34] ,
+    \u_riscv_top.core2_timer_val[33] ,
+    \u_riscv_top.core2_timer_val[32] ,
+    \u_riscv_top.core2_timer_val[31] ,
+    \u_riscv_top.core2_timer_val[30] ,
+    \u_riscv_top.core2_timer_val[29] ,
+    \u_riscv_top.core2_timer_val[28] ,
+    \u_riscv_top.core2_timer_val[27] ,
+    \u_riscv_top.core2_timer_val[26] ,
+    \u_riscv_top.core2_timer_val[25] ,
+    \u_riscv_top.core2_timer_val[24] ,
+    \u_riscv_top.core2_timer_val[23] ,
+    \u_riscv_top.core2_timer_val[22] ,
+    \u_riscv_top.core2_timer_val[21] ,
+    \u_riscv_top.core2_timer_val[20] ,
+    \u_riscv_top.core2_timer_val[19] ,
+    \u_riscv_top.core2_timer_val[18] ,
+    \u_riscv_top.core2_timer_val[17] ,
+    \u_riscv_top.core2_timer_val[16] ,
+    \u_riscv_top.core2_timer_val[15] ,
+    \u_riscv_top.core2_timer_val[14] ,
+    \u_riscv_top.core2_timer_val[13] ,
+    \u_riscv_top.core2_timer_val[12] ,
+    \u_riscv_top.core2_timer_val[11] ,
+    \u_riscv_top.core2_timer_val[10] ,
+    \u_riscv_top.core2_timer_val[9] ,
+    \u_riscv_top.core2_timer_val[8] ,
+    \u_riscv_top.core2_timer_val[7] ,
+    \u_riscv_top.core2_timer_val[6] ,
+    \u_riscv_top.core2_timer_val[5] ,
+    \u_riscv_top.core2_timer_val[4] ,
+    \u_riscv_top.core2_timer_val[3] ,
+    \u_riscv_top.core2_timer_val[2] ,
+    \u_riscv_top.core2_timer_val[1] ,
+    \u_riscv_top.core2_timer_val[0] }),
+    .core_uid({\u_riscv_top.core2_uid[1] ,
+    \u_riscv_top.core2_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core2_dmem_rdata[31] ,
+    \u_riscv_top.core2_dmem_rdata[30] ,
+    \u_riscv_top.core2_dmem_rdata[29] ,
+    \u_riscv_top.core2_dmem_rdata[28] ,
+    \u_riscv_top.core2_dmem_rdata[27] ,
+    \u_riscv_top.core2_dmem_rdata[26] ,
+    \u_riscv_top.core2_dmem_rdata[25] ,
+    \u_riscv_top.core2_dmem_rdata[24] ,
+    \u_riscv_top.core2_dmem_rdata[23] ,
+    \u_riscv_top.core2_dmem_rdata[22] ,
+    \u_riscv_top.core2_dmem_rdata[21] ,
+    \u_riscv_top.core2_dmem_rdata[20] ,
+    \u_riscv_top.core2_dmem_rdata[19] ,
+    \u_riscv_top.core2_dmem_rdata[18] ,
+    \u_riscv_top.core2_dmem_rdata[17] ,
+    \u_riscv_top.core2_dmem_rdata[16] ,
+    \u_riscv_top.core2_dmem_rdata[15] ,
+    \u_riscv_top.core2_dmem_rdata[14] ,
+    \u_riscv_top.core2_dmem_rdata[13] ,
+    \u_riscv_top.core2_dmem_rdata[12] ,
+    \u_riscv_top.core2_dmem_rdata[11] ,
+    \u_riscv_top.core2_dmem_rdata[10] ,
+    \u_riscv_top.core2_dmem_rdata[9] ,
+    \u_riscv_top.core2_dmem_rdata[8] ,
+    \u_riscv_top.core2_dmem_rdata[7] ,
+    \u_riscv_top.core2_dmem_rdata[6] ,
+    \u_riscv_top.core2_dmem_rdata[5] ,
+    \u_riscv_top.core2_dmem_rdata[4] ,
+    \u_riscv_top.core2_dmem_rdata[3] ,
+    \u_riscv_top.core2_dmem_rdata[2] ,
+    \u_riscv_top.core2_dmem_rdata[1] ,
+    \u_riscv_top.core2_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core2_dmem_resp[1] ,
+    \u_riscv_top.core2_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core2_imem_rdata[31] ,
+    \u_riscv_top.core2_imem_rdata[30] ,
+    \u_riscv_top.core2_imem_rdata[29] ,
+    \u_riscv_top.core2_imem_rdata[28] ,
+    \u_riscv_top.core2_imem_rdata[27] ,
+    \u_riscv_top.core2_imem_rdata[26] ,
+    \u_riscv_top.core2_imem_rdata[25] ,
+    \u_riscv_top.core2_imem_rdata[24] ,
+    \u_riscv_top.core2_imem_rdata[23] ,
+    \u_riscv_top.core2_imem_rdata[22] ,
+    \u_riscv_top.core2_imem_rdata[21] ,
+    \u_riscv_top.core2_imem_rdata[20] ,
+    \u_riscv_top.core2_imem_rdata[19] ,
+    \u_riscv_top.core2_imem_rdata[18] ,
+    \u_riscv_top.core2_imem_rdata[17] ,
+    \u_riscv_top.core2_imem_rdata[16] ,
+    \u_riscv_top.core2_imem_rdata[15] ,
+    \u_riscv_top.core2_imem_rdata[14] ,
+    \u_riscv_top.core2_imem_rdata[13] ,
+    \u_riscv_top.core2_imem_rdata[12] ,
+    \u_riscv_top.core2_imem_rdata[11] ,
+    \u_riscv_top.core2_imem_rdata[10] ,
+    \u_riscv_top.core2_imem_rdata[9] ,
+    \u_riscv_top.core2_imem_rdata[8] ,
+    \u_riscv_top.core2_imem_rdata[7] ,
+    \u_riscv_top.core2_imem_rdata[6] ,
+    \u_riscv_top.core2_imem_rdata[5] ,
+    \u_riscv_top.core2_imem_rdata[4] ,
+    \u_riscv_top.core2_imem_rdata[3] ,
+    \u_riscv_top.core2_imem_rdata[2] ,
+    \u_riscv_top.core2_imem_rdata[1] ,
+    \u_riscv_top.core2_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core2_imem_resp[1] ,
+    \u_riscv_top.core2_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_3  (.clk(\u_riscv_top.core_clk_core3_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[3] ),
+    .core2dmem_cmd_o(\u_riscv_top.core3_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core3_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core3_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core3_imem_req ),
+    .core_clk_int(\u_riscv_top.core3_clk ),
+    .core_clk_skew(\u_riscv_top.core_clk_core3_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core3_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core3_soft_irq ),
+    .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[3] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core3_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core3_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core3[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core3[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core3_dmem_addr[31] ,
+    \u_riscv_top.core3_dmem_addr[30] ,
+    \u_riscv_top.core3_dmem_addr[29] ,
+    \u_riscv_top.core3_dmem_addr[28] ,
+    \u_riscv_top.core3_dmem_addr[27] ,
+    \u_riscv_top.core3_dmem_addr[26] ,
+    \u_riscv_top.core3_dmem_addr[25] ,
+    \u_riscv_top.core3_dmem_addr[24] ,
+    \u_riscv_top.core3_dmem_addr[23] ,
+    \u_riscv_top.core3_dmem_addr[22] ,
+    \u_riscv_top.core3_dmem_addr[21] ,
+    \u_riscv_top.core3_dmem_addr[20] ,
+    \u_riscv_top.core3_dmem_addr[19] ,
+    \u_riscv_top.core3_dmem_addr[18] ,
+    \u_riscv_top.core3_dmem_addr[17] ,
+    \u_riscv_top.core3_dmem_addr[16] ,
+    \u_riscv_top.core3_dmem_addr[15] ,
+    \u_riscv_top.core3_dmem_addr[14] ,
+    \u_riscv_top.core3_dmem_addr[13] ,
+    \u_riscv_top.core3_dmem_addr[12] ,
+    \u_riscv_top.core3_dmem_addr[11] ,
+    \u_riscv_top.core3_dmem_addr[10] ,
+    \u_riscv_top.core3_dmem_addr[9] ,
+    \u_riscv_top.core3_dmem_addr[8] ,
+    \u_riscv_top.core3_dmem_addr[7] ,
+    \u_riscv_top.core3_dmem_addr[6] ,
+    \u_riscv_top.core3_dmem_addr[5] ,
+    \u_riscv_top.core3_dmem_addr[4] ,
+    \u_riscv_top.core3_dmem_addr[3] ,
+    \u_riscv_top.core3_dmem_addr[2] ,
+    \u_riscv_top.core3_dmem_addr[1] ,
+    \u_riscv_top.core3_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core3_dmem_wdata[31] ,
+    \u_riscv_top.core3_dmem_wdata[30] ,
+    \u_riscv_top.core3_dmem_wdata[29] ,
+    \u_riscv_top.core3_dmem_wdata[28] ,
+    \u_riscv_top.core3_dmem_wdata[27] ,
+    \u_riscv_top.core3_dmem_wdata[26] ,
+    \u_riscv_top.core3_dmem_wdata[25] ,
+    \u_riscv_top.core3_dmem_wdata[24] ,
+    \u_riscv_top.core3_dmem_wdata[23] ,
+    \u_riscv_top.core3_dmem_wdata[22] ,
+    \u_riscv_top.core3_dmem_wdata[21] ,
+    \u_riscv_top.core3_dmem_wdata[20] ,
+    \u_riscv_top.core3_dmem_wdata[19] ,
+    \u_riscv_top.core3_dmem_wdata[18] ,
+    \u_riscv_top.core3_dmem_wdata[17] ,
+    \u_riscv_top.core3_dmem_wdata[16] ,
+    \u_riscv_top.core3_dmem_wdata[15] ,
+    \u_riscv_top.core3_dmem_wdata[14] ,
+    \u_riscv_top.core3_dmem_wdata[13] ,
+    \u_riscv_top.core3_dmem_wdata[12] ,
+    \u_riscv_top.core3_dmem_wdata[11] ,
+    \u_riscv_top.core3_dmem_wdata[10] ,
+    \u_riscv_top.core3_dmem_wdata[9] ,
+    \u_riscv_top.core3_dmem_wdata[8] ,
+    \u_riscv_top.core3_dmem_wdata[7] ,
+    \u_riscv_top.core3_dmem_wdata[6] ,
+    \u_riscv_top.core3_dmem_wdata[5] ,
+    \u_riscv_top.core3_dmem_wdata[4] ,
+    \u_riscv_top.core3_dmem_wdata[3] ,
+    \u_riscv_top.core3_dmem_wdata[2] ,
+    \u_riscv_top.core3_dmem_wdata[1] ,
+    \u_riscv_top.core3_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core3_dmem_width[1] ,
+    \u_riscv_top.core3_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core3_imem_addr[31] ,
+    \u_riscv_top.core3_imem_addr[30] ,
+    \u_riscv_top.core3_imem_addr[29] ,
+    \u_riscv_top.core3_imem_addr[28] ,
+    \u_riscv_top.core3_imem_addr[27] ,
+    \u_riscv_top.core3_imem_addr[26] ,
+    \u_riscv_top.core3_imem_addr[25] ,
+    \u_riscv_top.core3_imem_addr[24] ,
+    \u_riscv_top.core3_imem_addr[23] ,
+    \u_riscv_top.core3_imem_addr[22] ,
+    \u_riscv_top.core3_imem_addr[21] ,
+    \u_riscv_top.core3_imem_addr[20] ,
+    \u_riscv_top.core3_imem_addr[19] ,
+    \u_riscv_top.core3_imem_addr[18] ,
+    \u_riscv_top.core3_imem_addr[17] ,
+    \u_riscv_top.core3_imem_addr[16] ,
+    \u_riscv_top.core3_imem_addr[15] ,
+    \u_riscv_top.core3_imem_addr[14] ,
+    \u_riscv_top.core3_imem_addr[13] ,
+    \u_riscv_top.core3_imem_addr[12] ,
+    \u_riscv_top.core3_imem_addr[11] ,
+    \u_riscv_top.core3_imem_addr[10] ,
+    \u_riscv_top.core3_imem_addr[9] ,
+    \u_riscv_top.core3_imem_addr[8] ,
+    \u_riscv_top.core3_imem_addr[7] ,
+    \u_riscv_top.core3_imem_addr[6] ,
+    \u_riscv_top.core3_imem_addr[5] ,
+    \u_riscv_top.core3_imem_addr[4] ,
+    \u_riscv_top.core3_imem_addr[3] ,
+    \u_riscv_top.core3_imem_addr[2] ,
+    \u_riscv_top.core3_imem_addr[1] ,
+    \u_riscv_top.core3_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core3_imem_bl[2] ,
+    \u_riscv_top.core3_imem_bl[1] ,
+    \u_riscv_top.core3_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core3_debug[48] ,
+    \u_riscv_top.core3_debug[47] ,
+    \u_riscv_top.core3_debug[46] ,
+    \u_riscv_top.core3_debug[45] ,
+    \u_riscv_top.core3_debug[44] ,
+    \u_riscv_top.core3_debug[43] ,
+    \u_riscv_top.core3_debug[42] ,
+    \u_riscv_top.core3_debug[41] ,
+    \u_riscv_top.core3_debug[40] ,
+    \u_riscv_top.core3_debug[39] ,
+    \u_riscv_top.core3_debug[38] ,
+    \u_riscv_top.core3_debug[37] ,
+    \u_riscv_top.core3_debug[36] ,
+    \u_riscv_top.core3_debug[35] ,
+    \u_riscv_top.core3_debug[34] ,
+    \u_riscv_top.core3_debug[33] ,
+    \u_riscv_top.core3_debug[32] ,
+    \u_riscv_top.core3_debug[31] ,
+    \u_riscv_top.core3_debug[30] ,
+    \u_riscv_top.core3_debug[29] ,
+    \u_riscv_top.core3_debug[28] ,
+    \u_riscv_top.core3_debug[27] ,
+    \u_riscv_top.core3_debug[26] ,
+    \u_riscv_top.core3_debug[25] ,
+    \u_riscv_top.core3_debug[24] ,
+    \u_riscv_top.core3_debug[23] ,
+    \u_riscv_top.core3_debug[22] ,
+    \u_riscv_top.core3_debug[21] ,
+    \u_riscv_top.core3_debug[20] ,
+    \u_riscv_top.core3_debug[19] ,
+    \u_riscv_top.core3_debug[18] ,
+    \u_riscv_top.core3_debug[17] ,
+    \u_riscv_top.core3_debug[16] ,
+    \u_riscv_top.core3_debug[15] ,
+    \u_riscv_top.core3_debug[14] ,
+    \u_riscv_top.core3_debug[13] ,
+    \u_riscv_top.core3_debug[12] ,
+    \u_riscv_top.core3_debug[11] ,
+    \u_riscv_top.core3_debug[10] ,
+    \u_riscv_top.core3_debug[9] ,
+    \u_riscv_top.core3_debug[8] ,
+    \u_riscv_top.core3_debug[7] ,
+    \u_riscv_top.core3_debug[6] ,
+    \u_riscv_top.core3_debug[5] ,
+    \u_riscv_top.core3_debug[4] ,
+    \u_riscv_top.core3_debug[3] ,
+    \u_riscv_top.core3_debug[2] ,
+    \u_riscv_top.core3_debug[1] ,
+    \u_riscv_top.core3_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core3_irq_lines[31] ,
+    \u_riscv_top.core3_irq_lines[30] ,
+    \u_riscv_top.core3_irq_lines[29] ,
+    \u_riscv_top.core3_irq_lines[28] ,
+    \u_riscv_top.core3_irq_lines[27] ,
+    \u_riscv_top.core3_irq_lines[26] ,
+    \u_riscv_top.core3_irq_lines[25] ,
+    \u_riscv_top.core3_irq_lines[24] ,
+    \u_riscv_top.core3_irq_lines[23] ,
+    \u_riscv_top.core3_irq_lines[22] ,
+    \u_riscv_top.core3_irq_lines[21] ,
+    \u_riscv_top.core3_irq_lines[20] ,
+    \u_riscv_top.core3_irq_lines[19] ,
+    \u_riscv_top.core3_irq_lines[18] ,
+    \u_riscv_top.core3_irq_lines[17] ,
+    \u_riscv_top.core3_irq_lines[16] ,
+    \u_riscv_top.core3_irq_lines[15] ,
+    \u_riscv_top.core3_irq_lines[14] ,
+    \u_riscv_top.core3_irq_lines[13] ,
+    \u_riscv_top.core3_irq_lines[12] ,
+    \u_riscv_top.core3_irq_lines[11] ,
+    \u_riscv_top.core3_irq_lines[10] ,
+    \u_riscv_top.core3_irq_lines[9] ,
+    \u_riscv_top.core3_irq_lines[8] ,
+    \u_riscv_top.core3_irq_lines[7] ,
+    \u_riscv_top.core3_irq_lines[6] ,
+    \u_riscv_top.core3_irq_lines[5] ,
+    \u_riscv_top.core3_irq_lines[4] ,
+    \u_riscv_top.core3_irq_lines[3] ,
+    \u_riscv_top.core3_irq_lines[2] ,
+    \u_riscv_top.core3_irq_lines[1] ,
+    \u_riscv_top.core3_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core3_timer_val[63] ,
+    \u_riscv_top.core3_timer_val[62] ,
+    \u_riscv_top.core3_timer_val[61] ,
+    \u_riscv_top.core3_timer_val[60] ,
+    \u_riscv_top.core3_timer_val[59] ,
+    \u_riscv_top.core3_timer_val[58] ,
+    \u_riscv_top.core3_timer_val[57] ,
+    \u_riscv_top.core3_timer_val[56] ,
+    \u_riscv_top.core3_timer_val[55] ,
+    \u_riscv_top.core3_timer_val[54] ,
+    \u_riscv_top.core3_timer_val[53] ,
+    \u_riscv_top.core3_timer_val[52] ,
+    \u_riscv_top.core3_timer_val[51] ,
+    \u_riscv_top.core3_timer_val[50] ,
+    \u_riscv_top.core3_timer_val[49] ,
+    \u_riscv_top.core3_timer_val[48] ,
+    \u_riscv_top.core3_timer_val[47] ,
+    \u_riscv_top.core3_timer_val[46] ,
+    \u_riscv_top.core3_timer_val[45] ,
+    \u_riscv_top.core3_timer_val[44] ,
+    \u_riscv_top.core3_timer_val[43] ,
+    \u_riscv_top.core3_timer_val[42] ,
+    \u_riscv_top.core3_timer_val[41] ,
+    \u_riscv_top.core3_timer_val[40] ,
+    \u_riscv_top.core3_timer_val[39] ,
+    \u_riscv_top.core3_timer_val[38] ,
+    \u_riscv_top.core3_timer_val[37] ,
+    \u_riscv_top.core3_timer_val[36] ,
+    \u_riscv_top.core3_timer_val[35] ,
+    \u_riscv_top.core3_timer_val[34] ,
+    \u_riscv_top.core3_timer_val[33] ,
+    \u_riscv_top.core3_timer_val[32] ,
+    \u_riscv_top.core3_timer_val[31] ,
+    \u_riscv_top.core3_timer_val[30] ,
+    \u_riscv_top.core3_timer_val[29] ,
+    \u_riscv_top.core3_timer_val[28] ,
+    \u_riscv_top.core3_timer_val[27] ,
+    \u_riscv_top.core3_timer_val[26] ,
+    \u_riscv_top.core3_timer_val[25] ,
+    \u_riscv_top.core3_timer_val[24] ,
+    \u_riscv_top.core3_timer_val[23] ,
+    \u_riscv_top.core3_timer_val[22] ,
+    \u_riscv_top.core3_timer_val[21] ,
+    \u_riscv_top.core3_timer_val[20] ,
+    \u_riscv_top.core3_timer_val[19] ,
+    \u_riscv_top.core3_timer_val[18] ,
+    \u_riscv_top.core3_timer_val[17] ,
+    \u_riscv_top.core3_timer_val[16] ,
+    \u_riscv_top.core3_timer_val[15] ,
+    \u_riscv_top.core3_timer_val[14] ,
+    \u_riscv_top.core3_timer_val[13] ,
+    \u_riscv_top.core3_timer_val[12] ,
+    \u_riscv_top.core3_timer_val[11] ,
+    \u_riscv_top.core3_timer_val[10] ,
+    \u_riscv_top.core3_timer_val[9] ,
+    \u_riscv_top.core3_timer_val[8] ,
+    \u_riscv_top.core3_timer_val[7] ,
+    \u_riscv_top.core3_timer_val[6] ,
+    \u_riscv_top.core3_timer_val[5] ,
+    \u_riscv_top.core3_timer_val[4] ,
+    \u_riscv_top.core3_timer_val[3] ,
+    \u_riscv_top.core3_timer_val[2] ,
+    \u_riscv_top.core3_timer_val[1] ,
+    \u_riscv_top.core3_timer_val[0] }),
+    .core_uid({\u_riscv_top.core3_uid[1] ,
+    \u_riscv_top.core3_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core3_dmem_rdata[31] ,
+    \u_riscv_top.core3_dmem_rdata[30] ,
+    \u_riscv_top.core3_dmem_rdata[29] ,
+    \u_riscv_top.core3_dmem_rdata[28] ,
+    \u_riscv_top.core3_dmem_rdata[27] ,
+    \u_riscv_top.core3_dmem_rdata[26] ,
+    \u_riscv_top.core3_dmem_rdata[25] ,
+    \u_riscv_top.core3_dmem_rdata[24] ,
+    \u_riscv_top.core3_dmem_rdata[23] ,
+    \u_riscv_top.core3_dmem_rdata[22] ,
+    \u_riscv_top.core3_dmem_rdata[21] ,
+    \u_riscv_top.core3_dmem_rdata[20] ,
+    \u_riscv_top.core3_dmem_rdata[19] ,
+    \u_riscv_top.core3_dmem_rdata[18] ,
+    \u_riscv_top.core3_dmem_rdata[17] ,
+    \u_riscv_top.core3_dmem_rdata[16] ,
+    \u_riscv_top.core3_dmem_rdata[15] ,
+    \u_riscv_top.core3_dmem_rdata[14] ,
+    \u_riscv_top.core3_dmem_rdata[13] ,
+    \u_riscv_top.core3_dmem_rdata[12] ,
+    \u_riscv_top.core3_dmem_rdata[11] ,
+    \u_riscv_top.core3_dmem_rdata[10] ,
+    \u_riscv_top.core3_dmem_rdata[9] ,
+    \u_riscv_top.core3_dmem_rdata[8] ,
+    \u_riscv_top.core3_dmem_rdata[7] ,
+    \u_riscv_top.core3_dmem_rdata[6] ,
+    \u_riscv_top.core3_dmem_rdata[5] ,
+    \u_riscv_top.core3_dmem_rdata[4] ,
+    \u_riscv_top.core3_dmem_rdata[3] ,
+    \u_riscv_top.core3_dmem_rdata[2] ,
+    \u_riscv_top.core3_dmem_rdata[1] ,
+    \u_riscv_top.core3_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core3_dmem_resp[1] ,
+    \u_riscv_top.core3_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core3_imem_rdata[31] ,
+    \u_riscv_top.core3_imem_rdata[30] ,
+    \u_riscv_top.core3_imem_rdata[29] ,
+    \u_riscv_top.core3_imem_rdata[28] ,
+    \u_riscv_top.core3_imem_rdata[27] ,
+    \u_riscv_top.core3_imem_rdata[26] ,
+    \u_riscv_top.core3_imem_rdata[25] ,
+    \u_riscv_top.core3_imem_rdata[24] ,
+    \u_riscv_top.core3_imem_rdata[23] ,
+    \u_riscv_top.core3_imem_rdata[22] ,
+    \u_riscv_top.core3_imem_rdata[21] ,
+    \u_riscv_top.core3_imem_rdata[20] ,
+    \u_riscv_top.core3_imem_rdata[19] ,
+    \u_riscv_top.core3_imem_rdata[18] ,
+    \u_riscv_top.core3_imem_rdata[17] ,
+    \u_riscv_top.core3_imem_rdata[16] ,
+    \u_riscv_top.core3_imem_rdata[15] ,
+    \u_riscv_top.core3_imem_rdata[14] ,
+    \u_riscv_top.core3_imem_rdata[13] ,
+    \u_riscv_top.core3_imem_rdata[12] ,
+    \u_riscv_top.core3_imem_rdata[11] ,
+    \u_riscv_top.core3_imem_rdata[10] ,
+    \u_riscv_top.core3_imem_rdata[9] ,
+    \u_riscv_top.core3_imem_rdata[8] ,
+    \u_riscv_top.core3_imem_rdata[7] ,
+    \u_riscv_top.core3_imem_rdata[6] ,
+    \u_riscv_top.core3_imem_rdata[5] ,
+    \u_riscv_top.core3_imem_rdata[4] ,
+    \u_riscv_top.core3_imem_rdata[3] ,
+    \u_riscv_top.core3_imem_rdata[2] ,
+    \u_riscv_top.core3_imem_rdata[1] ,
+    \u_riscv_top.core3_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core3_imem_resp[1] ,
+    \u_riscv_top.core3_imem_resp[0] }));
+ ycr4_iconnect \u_riscv_top.u_connect  (.VGND(vssd1),
+    .VPWR(vccd1),
+    .cfg_bypass_dcache(\cfg_riscv_ctrl[11] ),
+    .cfg_bypass_icache(\cfg_riscv_ctrl[10] ),
+    .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+    .core0_clk(\u_riscv_top.core0_clk ),
+    .core0_dmem_cmd(\u_riscv_top.core0_dmem_cmd ),
+    .core0_dmem_req(\u_riscv_top.core0_dmem_req ),
+    .core0_dmem_req_ack(\u_riscv_top.core0_dmem_req_ack ),
+    .core0_imem_cmd(\u_riscv_top.core0_imem_cmd ),
+    .core0_imem_req(\u_riscv_top.core0_imem_req ),
+    .core0_imem_req_ack(\u_riscv_top.core0_imem_req_ack ),
+    .core0_irq_soft(\u_riscv_top.core0_soft_irq ),
+    .core0_timer_irq(\u_riscv_top.core0_timer_irq ),
+    .core1_clk(\u_riscv_top.core1_clk ),
+    .core1_dmem_cmd(\u_riscv_top.core1_dmem_cmd ),
+    .core1_dmem_req(\u_riscv_top.core1_dmem_req ),
+    .core1_dmem_req_ack(\u_riscv_top.core1_dmem_req_ack ),
+    .core1_imem_cmd(\u_riscv_top.core1_imem_cmd ),
+    .core1_imem_req(\u_riscv_top.core1_imem_req ),
+    .core1_imem_req_ack(\u_riscv_top.core1_imem_req_ack ),
+    .core1_irq_soft(\u_riscv_top.core1_soft_irq ),
+    .core1_timer_irq(\u_riscv_top.core1_timer_irq ),
+    .core2_clk(\u_riscv_top.core2_clk ),
+    .core2_dmem_cmd(\u_riscv_top.core2_dmem_cmd ),
+    .core2_dmem_req(\u_riscv_top.core2_dmem_req ),
+    .core2_dmem_req_ack(\u_riscv_top.core2_dmem_req_ack ),
+    .core2_imem_cmd(\u_riscv_top.core2_imem_cmd ),
+    .core2_imem_req(\u_riscv_top.core2_imem_req ),
+    .core2_imem_req_ack(\u_riscv_top.core2_imem_req_ack ),
+    .core2_irq_soft(\u_riscv_top.core2_soft_irq ),
+    .core2_timer_irq(\u_riscv_top.core2_timer_irq ),
+    .core3_clk(\u_riscv_top.core3_clk ),
+    .core3_dmem_cmd(\u_riscv_top.core3_dmem_cmd ),
+    .core3_dmem_req(\u_riscv_top.core3_dmem_req ),
+    .core3_dmem_req_ack(\u_riscv_top.core3_dmem_req_ack ),
+    .core3_imem_cmd(\u_riscv_top.core3_imem_cmd ),
+    .core3_imem_req(\u_riscv_top.core3_imem_req ),
+    .core3_imem_req_ack(\u_riscv_top.core3_imem_req_ack ),
+    .core3_irq_soft(\u_riscv_top.core3_soft_irq ),
+    .core3_timer_irq(\u_riscv_top.core3_timer_irq ),
+    .core_clk(\u_riscv_top.core_clk_icon_skew ),
+    .core_clk_int(\u_riscv_top.core_clk_int[1] ),
+    .core_clk_skew(\u_riscv_top.core_clk_icon_skew ),
+    .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+    .core_dcache_req(\u_riscv_top.core_dcache_req ),
+    .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+    .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+    .core_dmem_req(\u_riscv_top.core_dmem_req ),
+    .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+    .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+    .core_icache_req(\u_riscv_top.core_icache_req ),
+    .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+    .core_irq_soft_i(\u_riscv_top.soft_irq ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .sram0_clk0(\u_riscv_top.sram0_clk0 ),
+    .sram0_clk1(\u_riscv_top.sram0_clk1 ),
+    .sram0_csb0(\u_riscv_top.sram0_csb0 ),
+    .sram0_csb1(\u_riscv_top.sram0_csb1 ),
+    .sram0_web0(\u_riscv_top.sram0_web0 ),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_icon[3] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[2] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[1] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[0] }),
+    .cfg_sram_lphase({\cfg_riscv_ctrl[3] ,
+    \cfg_riscv_ctrl[2] }),
+    .core0_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core0_dmem_addr({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core0_dmem_rdata({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .core0_dmem_resp({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .core0_dmem_wdata({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core0_dmem_width({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core0_imem_addr({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core0_imem_bl({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core0_imem_rdata({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .core0_imem_resp({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }),
+    .core0_irq_lines({\u_riscv_top.core0_irq_lines[31] ,
+    \u_riscv_top.core0_irq_lines[30] ,
+    \u_riscv_top.core0_irq_lines[29] ,
+    \u_riscv_top.core0_irq_lines[28] ,
+    \u_riscv_top.core0_irq_lines[27] ,
+    \u_riscv_top.core0_irq_lines[26] ,
+    \u_riscv_top.core0_irq_lines[25] ,
+    \u_riscv_top.core0_irq_lines[24] ,
+    \u_riscv_top.core0_irq_lines[23] ,
+    \u_riscv_top.core0_irq_lines[22] ,
+    \u_riscv_top.core0_irq_lines[21] ,
+    \u_riscv_top.core0_irq_lines[20] ,
+    \u_riscv_top.core0_irq_lines[19] ,
+    \u_riscv_top.core0_irq_lines[18] ,
+    \u_riscv_top.core0_irq_lines[17] ,
+    \u_riscv_top.core0_irq_lines[16] ,
+    \u_riscv_top.core0_irq_lines[15] ,
+    \u_riscv_top.core0_irq_lines[14] ,
+    \u_riscv_top.core0_irq_lines[13] ,
+    \u_riscv_top.core0_irq_lines[12] ,
+    \u_riscv_top.core0_irq_lines[11] ,
+    \u_riscv_top.core0_irq_lines[10] ,
+    \u_riscv_top.core0_irq_lines[9] ,
+    \u_riscv_top.core0_irq_lines[8] ,
+    \u_riscv_top.core0_irq_lines[7] ,
+    \u_riscv_top.core0_irq_lines[6] ,
+    \u_riscv_top.core0_irq_lines[5] ,
+    \u_riscv_top.core0_irq_lines[4] ,
+    \u_riscv_top.core0_irq_lines[3] ,
+    \u_riscv_top.core0_irq_lines[2] ,
+    \u_riscv_top.core0_irq_lines[1] ,
+    \u_riscv_top.core0_irq_lines[0] }),
+    .core0_timer_val({\u_riscv_top.core0_timer_val[63] ,
+    \u_riscv_top.core0_timer_val[62] ,
+    \u_riscv_top.core0_timer_val[61] ,
+    \u_riscv_top.core0_timer_val[60] ,
+    \u_riscv_top.core0_timer_val[59] ,
+    \u_riscv_top.core0_timer_val[58] ,
+    \u_riscv_top.core0_timer_val[57] ,
+    \u_riscv_top.core0_timer_val[56] ,
+    \u_riscv_top.core0_timer_val[55] ,
+    \u_riscv_top.core0_timer_val[54] ,
+    \u_riscv_top.core0_timer_val[53] ,
+    \u_riscv_top.core0_timer_val[52] ,
+    \u_riscv_top.core0_timer_val[51] ,
+    \u_riscv_top.core0_timer_val[50] ,
+    \u_riscv_top.core0_timer_val[49] ,
+    \u_riscv_top.core0_timer_val[48] ,
+    \u_riscv_top.core0_timer_val[47] ,
+    \u_riscv_top.core0_timer_val[46] ,
+    \u_riscv_top.core0_timer_val[45] ,
+    \u_riscv_top.core0_timer_val[44] ,
+    \u_riscv_top.core0_timer_val[43] ,
+    \u_riscv_top.core0_timer_val[42] ,
+    \u_riscv_top.core0_timer_val[41] ,
+    \u_riscv_top.core0_timer_val[40] ,
+    \u_riscv_top.core0_timer_val[39] ,
+    \u_riscv_top.core0_timer_val[38] ,
+    \u_riscv_top.core0_timer_val[37] ,
+    \u_riscv_top.core0_timer_val[36] ,
+    \u_riscv_top.core0_timer_val[35] ,
+    \u_riscv_top.core0_timer_val[34] ,
+    \u_riscv_top.core0_timer_val[33] ,
+    \u_riscv_top.core0_timer_val[32] ,
+    \u_riscv_top.core0_timer_val[31] ,
+    \u_riscv_top.core0_timer_val[30] ,
+    \u_riscv_top.core0_timer_val[29] ,
+    \u_riscv_top.core0_timer_val[28] ,
+    \u_riscv_top.core0_timer_val[27] ,
+    \u_riscv_top.core0_timer_val[26] ,
+    \u_riscv_top.core0_timer_val[25] ,
+    \u_riscv_top.core0_timer_val[24] ,
+    \u_riscv_top.core0_timer_val[23] ,
+    \u_riscv_top.core0_timer_val[22] ,
+    \u_riscv_top.core0_timer_val[21] ,
+    \u_riscv_top.core0_timer_val[20] ,
+    \u_riscv_top.core0_timer_val[19] ,
+    \u_riscv_top.core0_timer_val[18] ,
+    \u_riscv_top.core0_timer_val[17] ,
+    \u_riscv_top.core0_timer_val[16] ,
+    \u_riscv_top.core0_timer_val[15] ,
+    \u_riscv_top.core0_timer_val[14] ,
+    \u_riscv_top.core0_timer_val[13] ,
+    \u_riscv_top.core0_timer_val[12] ,
+    \u_riscv_top.core0_timer_val[11] ,
+    \u_riscv_top.core0_timer_val[10] ,
+    \u_riscv_top.core0_timer_val[9] ,
+    \u_riscv_top.core0_timer_val[8] ,
+    \u_riscv_top.core0_timer_val[7] ,
+    \u_riscv_top.core0_timer_val[6] ,
+    \u_riscv_top.core0_timer_val[5] ,
+    \u_riscv_top.core0_timer_val[4] ,
+    \u_riscv_top.core0_timer_val[3] ,
+    \u_riscv_top.core0_timer_val[2] ,
+    \u_riscv_top.core0_timer_val[1] ,
+    \u_riscv_top.core0_timer_val[0] }),
+    .core0_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .core1_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core1_dmem_addr({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core1_dmem_rdata({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .core1_dmem_resp({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .core1_dmem_wdata({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core1_dmem_width({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core1_imem_addr({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core1_imem_bl({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core1_imem_rdata({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .core1_imem_resp({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }),
+    .core1_irq_lines({\u_riscv_top.core1_irq_lines[31] ,
+    \u_riscv_top.core1_irq_lines[30] ,
+    \u_riscv_top.core1_irq_lines[29] ,
+    \u_riscv_top.core1_irq_lines[28] ,
+    \u_riscv_top.core1_irq_lines[27] ,
+    \u_riscv_top.core1_irq_lines[26] ,
+    \u_riscv_top.core1_irq_lines[25] ,
+    \u_riscv_top.core1_irq_lines[24] ,
+    \u_riscv_top.core1_irq_lines[23] ,
+    \u_riscv_top.core1_irq_lines[22] ,
+    \u_riscv_top.core1_irq_lines[21] ,
+    \u_riscv_top.core1_irq_lines[20] ,
+    \u_riscv_top.core1_irq_lines[19] ,
+    \u_riscv_top.core1_irq_lines[18] ,
+    \u_riscv_top.core1_irq_lines[17] ,
+    \u_riscv_top.core1_irq_lines[16] ,
+    \u_riscv_top.core1_irq_lines[15] ,
+    \u_riscv_top.core1_irq_lines[14] ,
+    \u_riscv_top.core1_irq_lines[13] ,
+    \u_riscv_top.core1_irq_lines[12] ,
+    \u_riscv_top.core1_irq_lines[11] ,
+    \u_riscv_top.core1_irq_lines[10] ,
+    \u_riscv_top.core1_irq_lines[9] ,
+    \u_riscv_top.core1_irq_lines[8] ,
+    \u_riscv_top.core1_irq_lines[7] ,
+    \u_riscv_top.core1_irq_lines[6] ,
+    \u_riscv_top.core1_irq_lines[5] ,
+    \u_riscv_top.core1_irq_lines[4] ,
+    \u_riscv_top.core1_irq_lines[3] ,
+    \u_riscv_top.core1_irq_lines[2] ,
+    \u_riscv_top.core1_irq_lines[1] ,
+    \u_riscv_top.core1_irq_lines[0] }),
+    .core1_timer_val({\u_riscv_top.core1_timer_val[63] ,
+    \u_riscv_top.core1_timer_val[62] ,
+    \u_riscv_top.core1_timer_val[61] ,
+    \u_riscv_top.core1_timer_val[60] ,
+    \u_riscv_top.core1_timer_val[59] ,
+    \u_riscv_top.core1_timer_val[58] ,
+    \u_riscv_top.core1_timer_val[57] ,
+    \u_riscv_top.core1_timer_val[56] ,
+    \u_riscv_top.core1_timer_val[55] ,
+    \u_riscv_top.core1_timer_val[54] ,
+    \u_riscv_top.core1_timer_val[53] ,
+    \u_riscv_top.core1_timer_val[52] ,
+    \u_riscv_top.core1_timer_val[51] ,
+    \u_riscv_top.core1_timer_val[50] ,
+    \u_riscv_top.core1_timer_val[49] ,
+    \u_riscv_top.core1_timer_val[48] ,
+    \u_riscv_top.core1_timer_val[47] ,
+    \u_riscv_top.core1_timer_val[46] ,
+    \u_riscv_top.core1_timer_val[45] ,
+    \u_riscv_top.core1_timer_val[44] ,
+    \u_riscv_top.core1_timer_val[43] ,
+    \u_riscv_top.core1_timer_val[42] ,
+    \u_riscv_top.core1_timer_val[41] ,
+    \u_riscv_top.core1_timer_val[40] ,
+    \u_riscv_top.core1_timer_val[39] ,
+    \u_riscv_top.core1_timer_val[38] ,
+    \u_riscv_top.core1_timer_val[37] ,
+    \u_riscv_top.core1_timer_val[36] ,
+    \u_riscv_top.core1_timer_val[35] ,
+    \u_riscv_top.core1_timer_val[34] ,
+    \u_riscv_top.core1_timer_val[33] ,
+    \u_riscv_top.core1_timer_val[32] ,
+    \u_riscv_top.core1_timer_val[31] ,
+    \u_riscv_top.core1_timer_val[30] ,
+    \u_riscv_top.core1_timer_val[29] ,
+    \u_riscv_top.core1_timer_val[28] ,
+    \u_riscv_top.core1_timer_val[27] ,
+    \u_riscv_top.core1_timer_val[26] ,
+    \u_riscv_top.core1_timer_val[25] ,
+    \u_riscv_top.core1_timer_val[24] ,
+    \u_riscv_top.core1_timer_val[23] ,
+    \u_riscv_top.core1_timer_val[22] ,
+    \u_riscv_top.core1_timer_val[21] ,
+    \u_riscv_top.core1_timer_val[20] ,
+    \u_riscv_top.core1_timer_val[19] ,
+    \u_riscv_top.core1_timer_val[18] ,
+    \u_riscv_top.core1_timer_val[17] ,
+    \u_riscv_top.core1_timer_val[16] ,
+    \u_riscv_top.core1_timer_val[15] ,
+    \u_riscv_top.core1_timer_val[14] ,
+    \u_riscv_top.core1_timer_val[13] ,
+    \u_riscv_top.core1_timer_val[12] ,
+    \u_riscv_top.core1_timer_val[11] ,
+    \u_riscv_top.core1_timer_val[10] ,
+    \u_riscv_top.core1_timer_val[9] ,
+    \u_riscv_top.core1_timer_val[8] ,
+    \u_riscv_top.core1_timer_val[7] ,
+    \u_riscv_top.core1_timer_val[6] ,
+    \u_riscv_top.core1_timer_val[5] ,
+    \u_riscv_top.core1_timer_val[4] ,
+    \u_riscv_top.core1_timer_val[3] ,
+    \u_riscv_top.core1_timer_val[2] ,
+    \u_riscv_top.core1_timer_val[1] ,
+    \u_riscv_top.core1_timer_val[0] }),
+    .core1_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .core2_debug({\u_riscv_top.core2_debug[48] ,
+    \u_riscv_top.core2_debug[47] ,
+    \u_riscv_top.core2_debug[46] ,
+    \u_riscv_top.core2_debug[45] ,
+    \u_riscv_top.core2_debug[44] ,
+    \u_riscv_top.core2_debug[43] ,
+    \u_riscv_top.core2_debug[42] ,
+    \u_riscv_top.core2_debug[41] ,
+    \u_riscv_top.core2_debug[40] ,
+    \u_riscv_top.core2_debug[39] ,
+    \u_riscv_top.core2_debug[38] ,
+    \u_riscv_top.core2_debug[37] ,
+    \u_riscv_top.core2_debug[36] ,
+    \u_riscv_top.core2_debug[35] ,
+    \u_riscv_top.core2_debug[34] ,
+    \u_riscv_top.core2_debug[33] ,
+    \u_riscv_top.core2_debug[32] ,
+    \u_riscv_top.core2_debug[31] ,
+    \u_riscv_top.core2_debug[30] ,
+    \u_riscv_top.core2_debug[29] ,
+    \u_riscv_top.core2_debug[28] ,
+    \u_riscv_top.core2_debug[27] ,
+    \u_riscv_top.core2_debug[26] ,
+    \u_riscv_top.core2_debug[25] ,
+    \u_riscv_top.core2_debug[24] ,
+    \u_riscv_top.core2_debug[23] ,
+    \u_riscv_top.core2_debug[22] ,
+    \u_riscv_top.core2_debug[21] ,
+    \u_riscv_top.core2_debug[20] ,
+    \u_riscv_top.core2_debug[19] ,
+    \u_riscv_top.core2_debug[18] ,
+    \u_riscv_top.core2_debug[17] ,
+    \u_riscv_top.core2_debug[16] ,
+    \u_riscv_top.core2_debug[15] ,
+    \u_riscv_top.core2_debug[14] ,
+    \u_riscv_top.core2_debug[13] ,
+    \u_riscv_top.core2_debug[12] ,
+    \u_riscv_top.core2_debug[11] ,
+    \u_riscv_top.core2_debug[10] ,
+    \u_riscv_top.core2_debug[9] ,
+    \u_riscv_top.core2_debug[8] ,
+    \u_riscv_top.core2_debug[7] ,
+    \u_riscv_top.core2_debug[6] ,
+    \u_riscv_top.core2_debug[5] ,
+    \u_riscv_top.core2_debug[4] ,
+    \u_riscv_top.core2_debug[3] ,
+    \u_riscv_top.core2_debug[2] ,
+    \u_riscv_top.core2_debug[1] ,
+    \u_riscv_top.core2_debug[0] }),
+    .core2_dmem_addr({\u_riscv_top.core2_dmem_addr[31] ,
+    \u_riscv_top.core2_dmem_addr[30] ,
+    \u_riscv_top.core2_dmem_addr[29] ,
+    \u_riscv_top.core2_dmem_addr[28] ,
+    \u_riscv_top.core2_dmem_addr[27] ,
+    \u_riscv_top.core2_dmem_addr[26] ,
+    \u_riscv_top.core2_dmem_addr[25] ,
+    \u_riscv_top.core2_dmem_addr[24] ,
+    \u_riscv_top.core2_dmem_addr[23] ,
+    \u_riscv_top.core2_dmem_addr[22] ,
+    \u_riscv_top.core2_dmem_addr[21] ,
+    \u_riscv_top.core2_dmem_addr[20] ,
+    \u_riscv_top.core2_dmem_addr[19] ,
+    \u_riscv_top.core2_dmem_addr[18] ,
+    \u_riscv_top.core2_dmem_addr[17] ,
+    \u_riscv_top.core2_dmem_addr[16] ,
+    \u_riscv_top.core2_dmem_addr[15] ,
+    \u_riscv_top.core2_dmem_addr[14] ,
+    \u_riscv_top.core2_dmem_addr[13] ,
+    \u_riscv_top.core2_dmem_addr[12] ,
+    \u_riscv_top.core2_dmem_addr[11] ,
+    \u_riscv_top.core2_dmem_addr[10] ,
+    \u_riscv_top.core2_dmem_addr[9] ,
+    \u_riscv_top.core2_dmem_addr[8] ,
+    \u_riscv_top.core2_dmem_addr[7] ,
+    \u_riscv_top.core2_dmem_addr[6] ,
+    \u_riscv_top.core2_dmem_addr[5] ,
+    \u_riscv_top.core2_dmem_addr[4] ,
+    \u_riscv_top.core2_dmem_addr[3] ,
+    \u_riscv_top.core2_dmem_addr[2] ,
+    \u_riscv_top.core2_dmem_addr[1] ,
+    \u_riscv_top.core2_dmem_addr[0] }),
+    .core2_dmem_rdata({\u_riscv_top.core2_dmem_rdata[31] ,
+    \u_riscv_top.core2_dmem_rdata[30] ,
+    \u_riscv_top.core2_dmem_rdata[29] ,
+    \u_riscv_top.core2_dmem_rdata[28] ,
+    \u_riscv_top.core2_dmem_rdata[27] ,
+    \u_riscv_top.core2_dmem_rdata[26] ,
+    \u_riscv_top.core2_dmem_rdata[25] ,
+    \u_riscv_top.core2_dmem_rdata[24] ,
+    \u_riscv_top.core2_dmem_rdata[23] ,
+    \u_riscv_top.core2_dmem_rdata[22] ,
+    \u_riscv_top.core2_dmem_rdata[21] ,
+    \u_riscv_top.core2_dmem_rdata[20] ,
+    \u_riscv_top.core2_dmem_rdata[19] ,
+    \u_riscv_top.core2_dmem_rdata[18] ,
+    \u_riscv_top.core2_dmem_rdata[17] ,
+    \u_riscv_top.core2_dmem_rdata[16] ,
+    \u_riscv_top.core2_dmem_rdata[15] ,
+    \u_riscv_top.core2_dmem_rdata[14] ,
+    \u_riscv_top.core2_dmem_rdata[13] ,
+    \u_riscv_top.core2_dmem_rdata[12] ,
+    \u_riscv_top.core2_dmem_rdata[11] ,
+    \u_riscv_top.core2_dmem_rdata[10] ,
+    \u_riscv_top.core2_dmem_rdata[9] ,
+    \u_riscv_top.core2_dmem_rdata[8] ,
+    \u_riscv_top.core2_dmem_rdata[7] ,
+    \u_riscv_top.core2_dmem_rdata[6] ,
+    \u_riscv_top.core2_dmem_rdata[5] ,
+    \u_riscv_top.core2_dmem_rdata[4] ,
+    \u_riscv_top.core2_dmem_rdata[3] ,
+    \u_riscv_top.core2_dmem_rdata[2] ,
+    \u_riscv_top.core2_dmem_rdata[1] ,
+    \u_riscv_top.core2_dmem_rdata[0] }),
+    .core2_dmem_resp({\u_riscv_top.core2_dmem_resp[1] ,
+    \u_riscv_top.core2_dmem_resp[0] }),
+    .core2_dmem_wdata({\u_riscv_top.core2_dmem_wdata[31] ,
+    \u_riscv_top.core2_dmem_wdata[30] ,
+    \u_riscv_top.core2_dmem_wdata[29] ,
+    \u_riscv_top.core2_dmem_wdata[28] ,
+    \u_riscv_top.core2_dmem_wdata[27] ,
+    \u_riscv_top.core2_dmem_wdata[26] ,
+    \u_riscv_top.core2_dmem_wdata[25] ,
+    \u_riscv_top.core2_dmem_wdata[24] ,
+    \u_riscv_top.core2_dmem_wdata[23] ,
+    \u_riscv_top.core2_dmem_wdata[22] ,
+    \u_riscv_top.core2_dmem_wdata[21] ,
+    \u_riscv_top.core2_dmem_wdata[20] ,
+    \u_riscv_top.core2_dmem_wdata[19] ,
+    \u_riscv_top.core2_dmem_wdata[18] ,
+    \u_riscv_top.core2_dmem_wdata[17] ,
+    \u_riscv_top.core2_dmem_wdata[16] ,
+    \u_riscv_top.core2_dmem_wdata[15] ,
+    \u_riscv_top.core2_dmem_wdata[14] ,
+    \u_riscv_top.core2_dmem_wdata[13] ,
+    \u_riscv_top.core2_dmem_wdata[12] ,
+    \u_riscv_top.core2_dmem_wdata[11] ,
+    \u_riscv_top.core2_dmem_wdata[10] ,
+    \u_riscv_top.core2_dmem_wdata[9] ,
+    \u_riscv_top.core2_dmem_wdata[8] ,
+    \u_riscv_top.core2_dmem_wdata[7] ,
+    \u_riscv_top.core2_dmem_wdata[6] ,
+    \u_riscv_top.core2_dmem_wdata[5] ,
+    \u_riscv_top.core2_dmem_wdata[4] ,
+    \u_riscv_top.core2_dmem_wdata[3] ,
+    \u_riscv_top.core2_dmem_wdata[2] ,
+    \u_riscv_top.core2_dmem_wdata[1] ,
+    \u_riscv_top.core2_dmem_wdata[0] }),
+    .core2_dmem_width({\u_riscv_top.core2_dmem_width[1] ,
+    \u_riscv_top.core2_dmem_width[0] }),
+    .core2_imem_addr({\u_riscv_top.core2_imem_addr[31] ,
+    \u_riscv_top.core2_imem_addr[30] ,
+    \u_riscv_top.core2_imem_addr[29] ,
+    \u_riscv_top.core2_imem_addr[28] ,
+    \u_riscv_top.core2_imem_addr[27] ,
+    \u_riscv_top.core2_imem_addr[26] ,
+    \u_riscv_top.core2_imem_addr[25] ,
+    \u_riscv_top.core2_imem_addr[24] ,
+    \u_riscv_top.core2_imem_addr[23] ,
+    \u_riscv_top.core2_imem_addr[22] ,
+    \u_riscv_top.core2_imem_addr[21] ,
+    \u_riscv_top.core2_imem_addr[20] ,
+    \u_riscv_top.core2_imem_addr[19] ,
+    \u_riscv_top.core2_imem_addr[18] ,
+    \u_riscv_top.core2_imem_addr[17] ,
+    \u_riscv_top.core2_imem_addr[16] ,
+    \u_riscv_top.core2_imem_addr[15] ,
+    \u_riscv_top.core2_imem_addr[14] ,
+    \u_riscv_top.core2_imem_addr[13] ,
+    \u_riscv_top.core2_imem_addr[12] ,
+    \u_riscv_top.core2_imem_addr[11] ,
+    \u_riscv_top.core2_imem_addr[10] ,
+    \u_riscv_top.core2_imem_addr[9] ,
+    \u_riscv_top.core2_imem_addr[8] ,
+    \u_riscv_top.core2_imem_addr[7] ,
+    \u_riscv_top.core2_imem_addr[6] ,
+    \u_riscv_top.core2_imem_addr[5] ,
+    \u_riscv_top.core2_imem_addr[4] ,
+    \u_riscv_top.core2_imem_addr[3] ,
+    \u_riscv_top.core2_imem_addr[2] ,
+    \u_riscv_top.core2_imem_addr[1] ,
+    \u_riscv_top.core2_imem_addr[0] }),
+    .core2_imem_bl({\u_riscv_top.core2_imem_bl[2] ,
+    \u_riscv_top.core2_imem_bl[1] ,
+    \u_riscv_top.core2_imem_bl[0] }),
+    .core2_imem_rdata({\u_riscv_top.core2_imem_rdata[31] ,
+    \u_riscv_top.core2_imem_rdata[30] ,
+    \u_riscv_top.core2_imem_rdata[29] ,
+    \u_riscv_top.core2_imem_rdata[28] ,
+    \u_riscv_top.core2_imem_rdata[27] ,
+    \u_riscv_top.core2_imem_rdata[26] ,
+    \u_riscv_top.core2_imem_rdata[25] ,
+    \u_riscv_top.core2_imem_rdata[24] ,
+    \u_riscv_top.core2_imem_rdata[23] ,
+    \u_riscv_top.core2_imem_rdata[22] ,
+    \u_riscv_top.core2_imem_rdata[21] ,
+    \u_riscv_top.core2_imem_rdata[20] ,
+    \u_riscv_top.core2_imem_rdata[19] ,
+    \u_riscv_top.core2_imem_rdata[18] ,
+    \u_riscv_top.core2_imem_rdata[17] ,
+    \u_riscv_top.core2_imem_rdata[16] ,
+    \u_riscv_top.core2_imem_rdata[15] ,
+    \u_riscv_top.core2_imem_rdata[14] ,
+    \u_riscv_top.core2_imem_rdata[13] ,
+    \u_riscv_top.core2_imem_rdata[12] ,
+    \u_riscv_top.core2_imem_rdata[11] ,
+    \u_riscv_top.core2_imem_rdata[10] ,
+    \u_riscv_top.core2_imem_rdata[9] ,
+    \u_riscv_top.core2_imem_rdata[8] ,
+    \u_riscv_top.core2_imem_rdata[7] ,
+    \u_riscv_top.core2_imem_rdata[6] ,
+    \u_riscv_top.core2_imem_rdata[5] ,
+    \u_riscv_top.core2_imem_rdata[4] ,
+    \u_riscv_top.core2_imem_rdata[3] ,
+    \u_riscv_top.core2_imem_rdata[2] ,
+    \u_riscv_top.core2_imem_rdata[1] ,
+    \u_riscv_top.core2_imem_rdata[0] }),
+    .core2_imem_resp({\u_riscv_top.core2_imem_resp[1] ,
+    \u_riscv_top.core2_imem_resp[0] }),
+    .core2_irq_lines({\u_riscv_top.core2_irq_lines[31] ,
+    \u_riscv_top.core2_irq_lines[30] ,
+    \u_riscv_top.core2_irq_lines[29] ,
+    \u_riscv_top.core2_irq_lines[28] ,
+    \u_riscv_top.core2_irq_lines[27] ,
+    \u_riscv_top.core2_irq_lines[26] ,
+    \u_riscv_top.core2_irq_lines[25] ,
+    \u_riscv_top.core2_irq_lines[24] ,
+    \u_riscv_top.core2_irq_lines[23] ,
+    \u_riscv_top.core2_irq_lines[22] ,
+    \u_riscv_top.core2_irq_lines[21] ,
+    \u_riscv_top.core2_irq_lines[20] ,
+    \u_riscv_top.core2_irq_lines[19] ,
+    \u_riscv_top.core2_irq_lines[18] ,
+    \u_riscv_top.core2_irq_lines[17] ,
+    \u_riscv_top.core2_irq_lines[16] ,
+    \u_riscv_top.core2_irq_lines[15] ,
+    \u_riscv_top.core2_irq_lines[14] ,
+    \u_riscv_top.core2_irq_lines[13] ,
+    \u_riscv_top.core2_irq_lines[12] ,
+    \u_riscv_top.core2_irq_lines[11] ,
+    \u_riscv_top.core2_irq_lines[10] ,
+    \u_riscv_top.core2_irq_lines[9] ,
+    \u_riscv_top.core2_irq_lines[8] ,
+    \u_riscv_top.core2_irq_lines[7] ,
+    \u_riscv_top.core2_irq_lines[6] ,
+    \u_riscv_top.core2_irq_lines[5] ,
+    \u_riscv_top.core2_irq_lines[4] ,
+    \u_riscv_top.core2_irq_lines[3] ,
+    \u_riscv_top.core2_irq_lines[2] ,
+    \u_riscv_top.core2_irq_lines[1] ,
+    \u_riscv_top.core2_irq_lines[0] }),
+    .core2_timer_val({\u_riscv_top.core2_timer_val[63] ,
+    \u_riscv_top.core2_timer_val[62] ,
+    \u_riscv_top.core2_timer_val[61] ,
+    \u_riscv_top.core2_timer_val[60] ,
+    \u_riscv_top.core2_timer_val[59] ,
+    \u_riscv_top.core2_timer_val[58] ,
+    \u_riscv_top.core2_timer_val[57] ,
+    \u_riscv_top.core2_timer_val[56] ,
+    \u_riscv_top.core2_timer_val[55] ,
+    \u_riscv_top.core2_timer_val[54] ,
+    \u_riscv_top.core2_timer_val[53] ,
+    \u_riscv_top.core2_timer_val[52] ,
+    \u_riscv_top.core2_timer_val[51] ,
+    \u_riscv_top.core2_timer_val[50] ,
+    \u_riscv_top.core2_timer_val[49] ,
+    \u_riscv_top.core2_timer_val[48] ,
+    \u_riscv_top.core2_timer_val[47] ,
+    \u_riscv_top.core2_timer_val[46] ,
+    \u_riscv_top.core2_timer_val[45] ,
+    \u_riscv_top.core2_timer_val[44] ,
+    \u_riscv_top.core2_timer_val[43] ,
+    \u_riscv_top.core2_timer_val[42] ,
+    \u_riscv_top.core2_timer_val[41] ,
+    \u_riscv_top.core2_timer_val[40] ,
+    \u_riscv_top.core2_timer_val[39] ,
+    \u_riscv_top.core2_timer_val[38] ,
+    \u_riscv_top.core2_timer_val[37] ,
+    \u_riscv_top.core2_timer_val[36] ,
+    \u_riscv_top.core2_timer_val[35] ,
+    \u_riscv_top.core2_timer_val[34] ,
+    \u_riscv_top.core2_timer_val[33] ,
+    \u_riscv_top.core2_timer_val[32] ,
+    \u_riscv_top.core2_timer_val[31] ,
+    \u_riscv_top.core2_timer_val[30] ,
+    \u_riscv_top.core2_timer_val[29] ,
+    \u_riscv_top.core2_timer_val[28] ,
+    \u_riscv_top.core2_timer_val[27] ,
+    \u_riscv_top.core2_timer_val[26] ,
+    \u_riscv_top.core2_timer_val[25] ,
+    \u_riscv_top.core2_timer_val[24] ,
+    \u_riscv_top.core2_timer_val[23] ,
+    \u_riscv_top.core2_timer_val[22] ,
+    \u_riscv_top.core2_timer_val[21] ,
+    \u_riscv_top.core2_timer_val[20] ,
+    \u_riscv_top.core2_timer_val[19] ,
+    \u_riscv_top.core2_timer_val[18] ,
+    \u_riscv_top.core2_timer_val[17] ,
+    \u_riscv_top.core2_timer_val[16] ,
+    \u_riscv_top.core2_timer_val[15] ,
+    \u_riscv_top.core2_timer_val[14] ,
+    \u_riscv_top.core2_timer_val[13] ,
+    \u_riscv_top.core2_timer_val[12] ,
+    \u_riscv_top.core2_timer_val[11] ,
+    \u_riscv_top.core2_timer_val[10] ,
+    \u_riscv_top.core2_timer_val[9] ,
+    \u_riscv_top.core2_timer_val[8] ,
+    \u_riscv_top.core2_timer_val[7] ,
+    \u_riscv_top.core2_timer_val[6] ,
+    \u_riscv_top.core2_timer_val[5] ,
+    \u_riscv_top.core2_timer_val[4] ,
+    \u_riscv_top.core2_timer_val[3] ,
+    \u_riscv_top.core2_timer_val[2] ,
+    \u_riscv_top.core2_timer_val[1] ,
+    \u_riscv_top.core2_timer_val[0] }),
+    .core2_uid({\u_riscv_top.core2_uid[1] ,
+    \u_riscv_top.core2_uid[0] }),
+    .core3_debug({\u_riscv_top.core3_debug[48] ,
+    \u_riscv_top.core3_debug[47] ,
+    \u_riscv_top.core3_debug[46] ,
+    \u_riscv_top.core3_debug[45] ,
+    \u_riscv_top.core3_debug[44] ,
+    \u_riscv_top.core3_debug[43] ,
+    \u_riscv_top.core3_debug[42] ,
+    \u_riscv_top.core3_debug[41] ,
+    \u_riscv_top.core3_debug[40] ,
+    \u_riscv_top.core3_debug[39] ,
+    \u_riscv_top.core3_debug[38] ,
+    \u_riscv_top.core3_debug[37] ,
+    \u_riscv_top.core3_debug[36] ,
+    \u_riscv_top.core3_debug[35] ,
+    \u_riscv_top.core3_debug[34] ,
+    \u_riscv_top.core3_debug[33] ,
+    \u_riscv_top.core3_debug[32] ,
+    \u_riscv_top.core3_debug[31] ,
+    \u_riscv_top.core3_debug[30] ,
+    \u_riscv_top.core3_debug[29] ,
+    \u_riscv_top.core3_debug[28] ,
+    \u_riscv_top.core3_debug[27] ,
+    \u_riscv_top.core3_debug[26] ,
+    \u_riscv_top.core3_debug[25] ,
+    \u_riscv_top.core3_debug[24] ,
+    \u_riscv_top.core3_debug[23] ,
+    \u_riscv_top.core3_debug[22] ,
+    \u_riscv_top.core3_debug[21] ,
+    \u_riscv_top.core3_debug[20] ,
+    \u_riscv_top.core3_debug[19] ,
+    \u_riscv_top.core3_debug[18] ,
+    \u_riscv_top.core3_debug[17] ,
+    \u_riscv_top.core3_debug[16] ,
+    \u_riscv_top.core3_debug[15] ,
+    \u_riscv_top.core3_debug[14] ,
+    \u_riscv_top.core3_debug[13] ,
+    \u_riscv_top.core3_debug[12] ,
+    \u_riscv_top.core3_debug[11] ,
+    \u_riscv_top.core3_debug[10] ,
+    \u_riscv_top.core3_debug[9] ,
+    \u_riscv_top.core3_debug[8] ,
+    \u_riscv_top.core3_debug[7] ,
+    \u_riscv_top.core3_debug[6] ,
+    \u_riscv_top.core3_debug[5] ,
+    \u_riscv_top.core3_debug[4] ,
+    \u_riscv_top.core3_debug[3] ,
+    \u_riscv_top.core3_debug[2] ,
+    \u_riscv_top.core3_debug[1] ,
+    \u_riscv_top.core3_debug[0] }),
+    .core3_dmem_addr({\u_riscv_top.core3_dmem_addr[31] ,
+    \u_riscv_top.core3_dmem_addr[30] ,
+    \u_riscv_top.core3_dmem_addr[29] ,
+    \u_riscv_top.core3_dmem_addr[28] ,
+    \u_riscv_top.core3_dmem_addr[27] ,
+    \u_riscv_top.core3_dmem_addr[26] ,
+    \u_riscv_top.core3_dmem_addr[25] ,
+    \u_riscv_top.core3_dmem_addr[24] ,
+    \u_riscv_top.core3_dmem_addr[23] ,
+    \u_riscv_top.core3_dmem_addr[22] ,
+    \u_riscv_top.core3_dmem_addr[21] ,
+    \u_riscv_top.core3_dmem_addr[20] ,
+    \u_riscv_top.core3_dmem_addr[19] ,
+    \u_riscv_top.core3_dmem_addr[18] ,
+    \u_riscv_top.core3_dmem_addr[17] ,
+    \u_riscv_top.core3_dmem_addr[16] ,
+    \u_riscv_top.core3_dmem_addr[15] ,
+    \u_riscv_top.core3_dmem_addr[14] ,
+    \u_riscv_top.core3_dmem_addr[13] ,
+    \u_riscv_top.core3_dmem_addr[12] ,
+    \u_riscv_top.core3_dmem_addr[11] ,
+    \u_riscv_top.core3_dmem_addr[10] ,
+    \u_riscv_top.core3_dmem_addr[9] ,
+    \u_riscv_top.core3_dmem_addr[8] ,
+    \u_riscv_top.core3_dmem_addr[7] ,
+    \u_riscv_top.core3_dmem_addr[6] ,
+    \u_riscv_top.core3_dmem_addr[5] ,
+    \u_riscv_top.core3_dmem_addr[4] ,
+    \u_riscv_top.core3_dmem_addr[3] ,
+    \u_riscv_top.core3_dmem_addr[2] ,
+    \u_riscv_top.core3_dmem_addr[1] ,
+    \u_riscv_top.core3_dmem_addr[0] }),
+    .core3_dmem_rdata({\u_riscv_top.core3_dmem_rdata[31] ,
+    \u_riscv_top.core3_dmem_rdata[30] ,
+    \u_riscv_top.core3_dmem_rdata[29] ,
+    \u_riscv_top.core3_dmem_rdata[28] ,
+    \u_riscv_top.core3_dmem_rdata[27] ,
+    \u_riscv_top.core3_dmem_rdata[26] ,
+    \u_riscv_top.core3_dmem_rdata[25] ,
+    \u_riscv_top.core3_dmem_rdata[24] ,
+    \u_riscv_top.core3_dmem_rdata[23] ,
+    \u_riscv_top.core3_dmem_rdata[22] ,
+    \u_riscv_top.core3_dmem_rdata[21] ,
+    \u_riscv_top.core3_dmem_rdata[20] ,
+    \u_riscv_top.core3_dmem_rdata[19] ,
+    \u_riscv_top.core3_dmem_rdata[18] ,
+    \u_riscv_top.core3_dmem_rdata[17] ,
+    \u_riscv_top.core3_dmem_rdata[16] ,
+    \u_riscv_top.core3_dmem_rdata[15] ,
+    \u_riscv_top.core3_dmem_rdata[14] ,
+    \u_riscv_top.core3_dmem_rdata[13] ,
+    \u_riscv_top.core3_dmem_rdata[12] ,
+    \u_riscv_top.core3_dmem_rdata[11] ,
+    \u_riscv_top.core3_dmem_rdata[10] ,
+    \u_riscv_top.core3_dmem_rdata[9] ,
+    \u_riscv_top.core3_dmem_rdata[8] ,
+    \u_riscv_top.core3_dmem_rdata[7] ,
+    \u_riscv_top.core3_dmem_rdata[6] ,
+    \u_riscv_top.core3_dmem_rdata[5] ,
+    \u_riscv_top.core3_dmem_rdata[4] ,
+    \u_riscv_top.core3_dmem_rdata[3] ,
+    \u_riscv_top.core3_dmem_rdata[2] ,
+    \u_riscv_top.core3_dmem_rdata[1] ,
+    \u_riscv_top.core3_dmem_rdata[0] }),
+    .core3_dmem_resp({\u_riscv_top.core3_dmem_resp[1] ,
+    \u_riscv_top.core3_dmem_resp[0] }),
+    .core3_dmem_wdata({\u_riscv_top.core3_dmem_wdata[31] ,
+    \u_riscv_top.core3_dmem_wdata[30] ,
+    \u_riscv_top.core3_dmem_wdata[29] ,
+    \u_riscv_top.core3_dmem_wdata[28] ,
+    \u_riscv_top.core3_dmem_wdata[27] ,
+    \u_riscv_top.core3_dmem_wdata[26] ,
+    \u_riscv_top.core3_dmem_wdata[25] ,
+    \u_riscv_top.core3_dmem_wdata[24] ,
+    \u_riscv_top.core3_dmem_wdata[23] ,
+    \u_riscv_top.core3_dmem_wdata[22] ,
+    \u_riscv_top.core3_dmem_wdata[21] ,
+    \u_riscv_top.core3_dmem_wdata[20] ,
+    \u_riscv_top.core3_dmem_wdata[19] ,
+    \u_riscv_top.core3_dmem_wdata[18] ,
+    \u_riscv_top.core3_dmem_wdata[17] ,
+    \u_riscv_top.core3_dmem_wdata[16] ,
+    \u_riscv_top.core3_dmem_wdata[15] ,
+    \u_riscv_top.core3_dmem_wdata[14] ,
+    \u_riscv_top.core3_dmem_wdata[13] ,
+    \u_riscv_top.core3_dmem_wdata[12] ,
+    \u_riscv_top.core3_dmem_wdata[11] ,
+    \u_riscv_top.core3_dmem_wdata[10] ,
+    \u_riscv_top.core3_dmem_wdata[9] ,
+    \u_riscv_top.core3_dmem_wdata[8] ,
+    \u_riscv_top.core3_dmem_wdata[7] ,
+    \u_riscv_top.core3_dmem_wdata[6] ,
+    \u_riscv_top.core3_dmem_wdata[5] ,
+    \u_riscv_top.core3_dmem_wdata[4] ,
+    \u_riscv_top.core3_dmem_wdata[3] ,
+    \u_riscv_top.core3_dmem_wdata[2] ,
+    \u_riscv_top.core3_dmem_wdata[1] ,
+    \u_riscv_top.core3_dmem_wdata[0] }),
+    .core3_dmem_width({\u_riscv_top.core3_dmem_width[1] ,
+    \u_riscv_top.core3_dmem_width[0] }),
+    .core3_imem_addr({\u_riscv_top.core3_imem_addr[31] ,
+    \u_riscv_top.core3_imem_addr[30] ,
+    \u_riscv_top.core3_imem_addr[29] ,
+    \u_riscv_top.core3_imem_addr[28] ,
+    \u_riscv_top.core3_imem_addr[27] ,
+    \u_riscv_top.core3_imem_addr[26] ,
+    \u_riscv_top.core3_imem_addr[25] ,
+    \u_riscv_top.core3_imem_addr[24] ,
+    \u_riscv_top.core3_imem_addr[23] ,
+    \u_riscv_top.core3_imem_addr[22] ,
+    \u_riscv_top.core3_imem_addr[21] ,
+    \u_riscv_top.core3_imem_addr[20] ,
+    \u_riscv_top.core3_imem_addr[19] ,
+    \u_riscv_top.core3_imem_addr[18] ,
+    \u_riscv_top.core3_imem_addr[17] ,
+    \u_riscv_top.core3_imem_addr[16] ,
+    \u_riscv_top.core3_imem_addr[15] ,
+    \u_riscv_top.core3_imem_addr[14] ,
+    \u_riscv_top.core3_imem_addr[13] ,
+    \u_riscv_top.core3_imem_addr[12] ,
+    \u_riscv_top.core3_imem_addr[11] ,
+    \u_riscv_top.core3_imem_addr[10] ,
+    \u_riscv_top.core3_imem_addr[9] ,
+    \u_riscv_top.core3_imem_addr[8] ,
+    \u_riscv_top.core3_imem_addr[7] ,
+    \u_riscv_top.core3_imem_addr[6] ,
+    \u_riscv_top.core3_imem_addr[5] ,
+    \u_riscv_top.core3_imem_addr[4] ,
+    \u_riscv_top.core3_imem_addr[3] ,
+    \u_riscv_top.core3_imem_addr[2] ,
+    \u_riscv_top.core3_imem_addr[1] ,
+    \u_riscv_top.core3_imem_addr[0] }),
+    .core3_imem_bl({\u_riscv_top.core3_imem_bl[2] ,
+    \u_riscv_top.core3_imem_bl[1] ,
+    \u_riscv_top.core3_imem_bl[0] }),
+    .core3_imem_rdata({\u_riscv_top.core3_imem_rdata[31] ,
+    \u_riscv_top.core3_imem_rdata[30] ,
+    \u_riscv_top.core3_imem_rdata[29] ,
+    \u_riscv_top.core3_imem_rdata[28] ,
+    \u_riscv_top.core3_imem_rdata[27] ,
+    \u_riscv_top.core3_imem_rdata[26] ,
+    \u_riscv_top.core3_imem_rdata[25] ,
+    \u_riscv_top.core3_imem_rdata[24] ,
+    \u_riscv_top.core3_imem_rdata[23] ,
+    \u_riscv_top.core3_imem_rdata[22] ,
+    \u_riscv_top.core3_imem_rdata[21] ,
+    \u_riscv_top.core3_imem_rdata[20] ,
+    \u_riscv_top.core3_imem_rdata[19] ,
+    \u_riscv_top.core3_imem_rdata[18] ,
+    \u_riscv_top.core3_imem_rdata[17] ,
+    \u_riscv_top.core3_imem_rdata[16] ,
+    \u_riscv_top.core3_imem_rdata[15] ,
+    \u_riscv_top.core3_imem_rdata[14] ,
+    \u_riscv_top.core3_imem_rdata[13] ,
+    \u_riscv_top.core3_imem_rdata[12] ,
+    \u_riscv_top.core3_imem_rdata[11] ,
+    \u_riscv_top.core3_imem_rdata[10] ,
+    \u_riscv_top.core3_imem_rdata[9] ,
+    \u_riscv_top.core3_imem_rdata[8] ,
+    \u_riscv_top.core3_imem_rdata[7] ,
+    \u_riscv_top.core3_imem_rdata[6] ,
+    \u_riscv_top.core3_imem_rdata[5] ,
+    \u_riscv_top.core3_imem_rdata[4] ,
+    \u_riscv_top.core3_imem_rdata[3] ,
+    \u_riscv_top.core3_imem_rdata[2] ,
+    \u_riscv_top.core3_imem_rdata[1] ,
+    \u_riscv_top.core3_imem_rdata[0] }),
+    .core3_imem_resp({\u_riscv_top.core3_imem_resp[1] ,
+    \u_riscv_top.core3_imem_resp[0] }),
+    .core3_irq_lines({\u_riscv_top.core3_irq_lines[31] ,
+    \u_riscv_top.core3_irq_lines[30] ,
+    \u_riscv_top.core3_irq_lines[29] ,
+    \u_riscv_top.core3_irq_lines[28] ,
+    \u_riscv_top.core3_irq_lines[27] ,
+    \u_riscv_top.core3_irq_lines[26] ,
+    \u_riscv_top.core3_irq_lines[25] ,
+    \u_riscv_top.core3_irq_lines[24] ,
+    \u_riscv_top.core3_irq_lines[23] ,
+    \u_riscv_top.core3_irq_lines[22] ,
+    \u_riscv_top.core3_irq_lines[21] ,
+    \u_riscv_top.core3_irq_lines[20] ,
+    \u_riscv_top.core3_irq_lines[19] ,
+    \u_riscv_top.core3_irq_lines[18] ,
+    \u_riscv_top.core3_irq_lines[17] ,
+    \u_riscv_top.core3_irq_lines[16] ,
+    \u_riscv_top.core3_irq_lines[15] ,
+    \u_riscv_top.core3_irq_lines[14] ,
+    \u_riscv_top.core3_irq_lines[13] ,
+    \u_riscv_top.core3_irq_lines[12] ,
+    \u_riscv_top.core3_irq_lines[11] ,
+    \u_riscv_top.core3_irq_lines[10] ,
+    \u_riscv_top.core3_irq_lines[9] ,
+    \u_riscv_top.core3_irq_lines[8] ,
+    \u_riscv_top.core3_irq_lines[7] ,
+    \u_riscv_top.core3_irq_lines[6] ,
+    \u_riscv_top.core3_irq_lines[5] ,
+    \u_riscv_top.core3_irq_lines[4] ,
+    \u_riscv_top.core3_irq_lines[3] ,
+    \u_riscv_top.core3_irq_lines[2] ,
+    \u_riscv_top.core3_irq_lines[1] ,
+    \u_riscv_top.core3_irq_lines[0] }),
+    .core3_timer_val({\u_riscv_top.core3_timer_val[63] ,
+    \u_riscv_top.core3_timer_val[62] ,
+    \u_riscv_top.core3_timer_val[61] ,
+    \u_riscv_top.core3_timer_val[60] ,
+    \u_riscv_top.core3_timer_val[59] ,
+    \u_riscv_top.core3_timer_val[58] ,
+    \u_riscv_top.core3_timer_val[57] ,
+    \u_riscv_top.core3_timer_val[56] ,
+    \u_riscv_top.core3_timer_val[55] ,
+    \u_riscv_top.core3_timer_val[54] ,
+    \u_riscv_top.core3_timer_val[53] ,
+    \u_riscv_top.core3_timer_val[52] ,
+    \u_riscv_top.core3_timer_val[51] ,
+    \u_riscv_top.core3_timer_val[50] ,
+    \u_riscv_top.core3_timer_val[49] ,
+    \u_riscv_top.core3_timer_val[48] ,
+    \u_riscv_top.core3_timer_val[47] ,
+    \u_riscv_top.core3_timer_val[46] ,
+    \u_riscv_top.core3_timer_val[45] ,
+    \u_riscv_top.core3_timer_val[44] ,
+    \u_riscv_top.core3_timer_val[43] ,
+    \u_riscv_top.core3_timer_val[42] ,
+    \u_riscv_top.core3_timer_val[41] ,
+    \u_riscv_top.core3_timer_val[40] ,
+    \u_riscv_top.core3_timer_val[39] ,
+    \u_riscv_top.core3_timer_val[38] ,
+    \u_riscv_top.core3_timer_val[37] ,
+    \u_riscv_top.core3_timer_val[36] ,
+    \u_riscv_top.core3_timer_val[35] ,
+    \u_riscv_top.core3_timer_val[34] ,
+    \u_riscv_top.core3_timer_val[33] ,
+    \u_riscv_top.core3_timer_val[32] ,
+    \u_riscv_top.core3_timer_val[31] ,
+    \u_riscv_top.core3_timer_val[30] ,
+    \u_riscv_top.core3_timer_val[29] ,
+    \u_riscv_top.core3_timer_val[28] ,
+    \u_riscv_top.core3_timer_val[27] ,
+    \u_riscv_top.core3_timer_val[26] ,
+    \u_riscv_top.core3_timer_val[25] ,
+    \u_riscv_top.core3_timer_val[24] ,
+    \u_riscv_top.core3_timer_val[23] ,
+    \u_riscv_top.core3_timer_val[22] ,
+    \u_riscv_top.core3_timer_val[21] ,
+    \u_riscv_top.core3_timer_val[20] ,
+    \u_riscv_top.core3_timer_val[19] ,
+    \u_riscv_top.core3_timer_val[18] ,
+    \u_riscv_top.core3_timer_val[17] ,
+    \u_riscv_top.core3_timer_val[16] ,
+    \u_riscv_top.core3_timer_val[15] ,
+    \u_riscv_top.core3_timer_val[14] ,
+    \u_riscv_top.core3_timer_val[13] ,
+    \u_riscv_top.core3_timer_val[12] ,
+    \u_riscv_top.core3_timer_val[11] ,
+    \u_riscv_top.core3_timer_val[10] ,
+    \u_riscv_top.core3_timer_val[9] ,
+    \u_riscv_top.core3_timer_val[8] ,
+    \u_riscv_top.core3_timer_val[7] ,
+    \u_riscv_top.core3_timer_val[6] ,
+    \u_riscv_top.core3_timer_val[5] ,
+    \u_riscv_top.core3_timer_val[4] ,
+    \u_riscv_top.core3_timer_val[3] ,
+    \u_riscv_top.core3_timer_val[2] ,
+    \u_riscv_top.core3_timer_val[1] ,
+    \u_riscv_top.core3_timer_val[0] }),
+    .core3_uid({\u_riscv_top.core3_uid[1] ,
+    \u_riscv_top.core3_uid[0] }),
+    .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+    \u_riscv_top.core_dcache_addr[30] ,
+    \u_riscv_top.core_dcache_addr[29] ,
+    \u_riscv_top.core_dcache_addr[28] ,
+    \u_riscv_top.core_dcache_addr[27] ,
+    \u_riscv_top.core_dcache_addr[26] ,
+    \u_riscv_top.core_dcache_addr[25] ,
+    \u_riscv_top.core_dcache_addr[24] ,
+    \u_riscv_top.core_dcache_addr[23] ,
+    \u_riscv_top.core_dcache_addr[22] ,
+    \u_riscv_top.core_dcache_addr[21] ,
+    \u_riscv_top.core_dcache_addr[20] ,
+    \u_riscv_top.core_dcache_addr[19] ,
+    \u_riscv_top.core_dcache_addr[18] ,
+    \u_riscv_top.core_dcache_addr[17] ,
+    \u_riscv_top.core_dcache_addr[16] ,
+    \u_riscv_top.core_dcache_addr[15] ,
+    \u_riscv_top.core_dcache_addr[14] ,
+    \u_riscv_top.core_dcache_addr[13] ,
+    \u_riscv_top.core_dcache_addr[12] ,
+    \u_riscv_top.core_dcache_addr[11] ,
+    \u_riscv_top.core_dcache_addr[10] ,
+    \u_riscv_top.core_dcache_addr[9] ,
+    \u_riscv_top.core_dcache_addr[8] ,
+    \u_riscv_top.core_dcache_addr[7] ,
+    \u_riscv_top.core_dcache_addr[6] ,
+    \u_riscv_top.core_dcache_addr[5] ,
+    \u_riscv_top.core_dcache_addr[4] ,
+    \u_riscv_top.core_dcache_addr[3] ,
+    \u_riscv_top.core_dcache_addr[2] ,
+    \u_riscv_top.core_dcache_addr[1] ,
+    \u_riscv_top.core_dcache_addr[0] }),
+    .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+    \u_riscv_top.core_dcache_rdata[30] ,
+    \u_riscv_top.core_dcache_rdata[29] ,
+    \u_riscv_top.core_dcache_rdata[28] ,
+    \u_riscv_top.core_dcache_rdata[27] ,
+    \u_riscv_top.core_dcache_rdata[26] ,
+    \u_riscv_top.core_dcache_rdata[25] ,
+    \u_riscv_top.core_dcache_rdata[24] ,
+    \u_riscv_top.core_dcache_rdata[23] ,
+    \u_riscv_top.core_dcache_rdata[22] ,
+    \u_riscv_top.core_dcache_rdata[21] ,
+    \u_riscv_top.core_dcache_rdata[20] ,
+    \u_riscv_top.core_dcache_rdata[19] ,
+    \u_riscv_top.core_dcache_rdata[18] ,
+    \u_riscv_top.core_dcache_rdata[17] ,
+    \u_riscv_top.core_dcache_rdata[16] ,
+    \u_riscv_top.core_dcache_rdata[15] ,
+    \u_riscv_top.core_dcache_rdata[14] ,
+    \u_riscv_top.core_dcache_rdata[13] ,
+    \u_riscv_top.core_dcache_rdata[12] ,
+    \u_riscv_top.core_dcache_rdata[11] ,
+    \u_riscv_top.core_dcache_rdata[10] ,
+    \u_riscv_top.core_dcache_rdata[9] ,
+    \u_riscv_top.core_dcache_rdata[8] ,
+    \u_riscv_top.core_dcache_rdata[7] ,
+    \u_riscv_top.core_dcache_rdata[6] ,
+    \u_riscv_top.core_dcache_rdata[5] ,
+    \u_riscv_top.core_dcache_rdata[4] ,
+    \u_riscv_top.core_dcache_rdata[3] ,
+    \u_riscv_top.core_dcache_rdata[2] ,
+    \u_riscv_top.core_dcache_rdata[1] ,
+    \u_riscv_top.core_dcache_rdata[0] }),
+    .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+    \u_riscv_top.core_dcache_resp[0] }),
+    .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+    \u_riscv_top.core_dcache_wdata[30] ,
+    \u_riscv_top.core_dcache_wdata[29] ,
+    \u_riscv_top.core_dcache_wdata[28] ,
+    \u_riscv_top.core_dcache_wdata[27] ,
+    \u_riscv_top.core_dcache_wdata[26] ,
+    \u_riscv_top.core_dcache_wdata[25] ,
+    \u_riscv_top.core_dcache_wdata[24] ,
+    \u_riscv_top.core_dcache_wdata[23] ,
+    \u_riscv_top.core_dcache_wdata[22] ,
+    \u_riscv_top.core_dcache_wdata[21] ,
+    \u_riscv_top.core_dcache_wdata[20] ,
+    \u_riscv_top.core_dcache_wdata[19] ,
+    \u_riscv_top.core_dcache_wdata[18] ,
+    \u_riscv_top.core_dcache_wdata[17] ,
+    \u_riscv_top.core_dcache_wdata[16] ,
+    \u_riscv_top.core_dcache_wdata[15] ,
+    \u_riscv_top.core_dcache_wdata[14] ,
+    \u_riscv_top.core_dcache_wdata[13] ,
+    \u_riscv_top.core_dcache_wdata[12] ,
+    \u_riscv_top.core_dcache_wdata[11] ,
+    \u_riscv_top.core_dcache_wdata[10] ,
+    \u_riscv_top.core_dcache_wdata[9] ,
+    \u_riscv_top.core_dcache_wdata[8] ,
+    \u_riscv_top.core_dcache_wdata[7] ,
+    \u_riscv_top.core_dcache_wdata[6] ,
+    \u_riscv_top.core_dcache_wdata[5] ,
+    \u_riscv_top.core_dcache_wdata[4] ,
+    \u_riscv_top.core_dcache_wdata[3] ,
+    \u_riscv_top.core_dcache_wdata[2] ,
+    \u_riscv_top.core_dcache_wdata[1] ,
+    \u_riscv_top.core_dcache_wdata[0] }),
+    .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+    \u_riscv_top.core_dcache_width[0] }),
+    .core_debug_sel({\cfg_riscv_ctrl[9] ,
+    \cfg_riscv_ctrl[8] }),
+    .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+    \u_riscv_top.core_dmem_addr[30] ,
+    \u_riscv_top.core_dmem_addr[29] ,
+    \u_riscv_top.core_dmem_addr[28] ,
+    \u_riscv_top.core_dmem_addr[27] ,
+    \u_riscv_top.core_dmem_addr[26] ,
+    \u_riscv_top.core_dmem_addr[25] ,
+    \u_riscv_top.core_dmem_addr[24] ,
+    \u_riscv_top.core_dmem_addr[23] ,
+    \u_riscv_top.core_dmem_addr[22] ,
+    \u_riscv_top.core_dmem_addr[21] ,
+    \u_riscv_top.core_dmem_addr[20] ,
+    \u_riscv_top.core_dmem_addr[19] ,
+    \u_riscv_top.core_dmem_addr[18] ,
+    \u_riscv_top.core_dmem_addr[17] ,
+    \u_riscv_top.core_dmem_addr[16] ,
+    \u_riscv_top.core_dmem_addr[15] ,
+    \u_riscv_top.core_dmem_addr[14] ,
+    \u_riscv_top.core_dmem_addr[13] ,
+    \u_riscv_top.core_dmem_addr[12] ,
+    \u_riscv_top.core_dmem_addr[11] ,
+    \u_riscv_top.core_dmem_addr[10] ,
+    \u_riscv_top.core_dmem_addr[9] ,
+    \u_riscv_top.core_dmem_addr[8] ,
+    \u_riscv_top.core_dmem_addr[7] ,
+    \u_riscv_top.core_dmem_addr[6] ,
+    \u_riscv_top.core_dmem_addr[5] ,
+    \u_riscv_top.core_dmem_addr[4] ,
+    \u_riscv_top.core_dmem_addr[3] ,
+    \u_riscv_top.core_dmem_addr[2] ,
+    \u_riscv_top.core_dmem_addr[1] ,
+    \u_riscv_top.core_dmem_addr[0] }),
+    .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] ,
+    \u_riscv_top.core_dmem_bl[1] ,
+    \u_riscv_top.core_dmem_bl[0] }),
+    .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+    \u_riscv_top.core_dmem_rdata[30] ,
+    \u_riscv_top.core_dmem_rdata[29] ,
+    \u_riscv_top.core_dmem_rdata[28] ,
+    \u_riscv_top.core_dmem_rdata[27] ,
+    \u_riscv_top.core_dmem_rdata[26] ,
+    \u_riscv_top.core_dmem_rdata[25] ,
+    \u_riscv_top.core_dmem_rdata[24] ,
+    \u_riscv_top.core_dmem_rdata[23] ,
+    \u_riscv_top.core_dmem_rdata[22] ,
+    \u_riscv_top.core_dmem_rdata[21] ,
+    \u_riscv_top.core_dmem_rdata[20] ,
+    \u_riscv_top.core_dmem_rdata[19] ,
+    \u_riscv_top.core_dmem_rdata[18] ,
+    \u_riscv_top.core_dmem_rdata[17] ,
+    \u_riscv_top.core_dmem_rdata[16] ,
+    \u_riscv_top.core_dmem_rdata[15] ,
+    \u_riscv_top.core_dmem_rdata[14] ,
+    \u_riscv_top.core_dmem_rdata[13] ,
+    \u_riscv_top.core_dmem_rdata[12] ,
+    \u_riscv_top.core_dmem_rdata[11] ,
+    \u_riscv_top.core_dmem_rdata[10] ,
+    \u_riscv_top.core_dmem_rdata[9] ,
+    \u_riscv_top.core_dmem_rdata[8] ,
+    \u_riscv_top.core_dmem_rdata[7] ,
+    \u_riscv_top.core_dmem_rdata[6] ,
+    \u_riscv_top.core_dmem_rdata[5] ,
+    \u_riscv_top.core_dmem_rdata[4] ,
+    \u_riscv_top.core_dmem_rdata[3] ,
+    \u_riscv_top.core_dmem_rdata[2] ,
+    \u_riscv_top.core_dmem_rdata[1] ,
+    \u_riscv_top.core_dmem_rdata[0] }),
+    .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+    \u_riscv_top.core_dmem_resp[0] }),
+    .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+    \u_riscv_top.core_dmem_wdata[30] ,
+    \u_riscv_top.core_dmem_wdata[29] ,
+    \u_riscv_top.core_dmem_wdata[28] ,
+    \u_riscv_top.core_dmem_wdata[27] ,
+    \u_riscv_top.core_dmem_wdata[26] ,
+    \u_riscv_top.core_dmem_wdata[25] ,
+    \u_riscv_top.core_dmem_wdata[24] ,
+    \u_riscv_top.core_dmem_wdata[23] ,
+    \u_riscv_top.core_dmem_wdata[22] ,
+    \u_riscv_top.core_dmem_wdata[21] ,
+    \u_riscv_top.core_dmem_wdata[20] ,
+    \u_riscv_top.core_dmem_wdata[19] ,
+    \u_riscv_top.core_dmem_wdata[18] ,
+    \u_riscv_top.core_dmem_wdata[17] ,
+    \u_riscv_top.core_dmem_wdata[16] ,
+    \u_riscv_top.core_dmem_wdata[15] ,
+    \u_riscv_top.core_dmem_wdata[14] ,
+    \u_riscv_top.core_dmem_wdata[13] ,
+    \u_riscv_top.core_dmem_wdata[12] ,
+    \u_riscv_top.core_dmem_wdata[11] ,
+    \u_riscv_top.core_dmem_wdata[10] ,
+    \u_riscv_top.core_dmem_wdata[9] ,
+    \u_riscv_top.core_dmem_wdata[8] ,
+    \u_riscv_top.core_dmem_wdata[7] ,
+    \u_riscv_top.core_dmem_wdata[6] ,
+    \u_riscv_top.core_dmem_wdata[5] ,
+    \u_riscv_top.core_dmem_wdata[4] ,
+    \u_riscv_top.core_dmem_wdata[3] ,
+    \u_riscv_top.core_dmem_wdata[2] ,
+    \u_riscv_top.core_dmem_wdata[1] ,
+    \u_riscv_top.core_dmem_wdata[0] }),
+    .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+    \u_riscv_top.core_dmem_width[0] }),
+    .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+    \u_riscv_top.core_icache_addr[30] ,
+    \u_riscv_top.core_icache_addr[29] ,
+    \u_riscv_top.core_icache_addr[28] ,
+    \u_riscv_top.core_icache_addr[27] ,
+    \u_riscv_top.core_icache_addr[26] ,
+    \u_riscv_top.core_icache_addr[25] ,
+    \u_riscv_top.core_icache_addr[24] ,
+    \u_riscv_top.core_icache_addr[23] ,
+    \u_riscv_top.core_icache_addr[22] ,
+    \u_riscv_top.core_icache_addr[21] ,
+    \u_riscv_top.core_icache_addr[20] ,
+    \u_riscv_top.core_icache_addr[19] ,
+    \u_riscv_top.core_icache_addr[18] ,
+    \u_riscv_top.core_icache_addr[17] ,
+    \u_riscv_top.core_icache_addr[16] ,
+    \u_riscv_top.core_icache_addr[15] ,
+    \u_riscv_top.core_icache_addr[14] ,
+    \u_riscv_top.core_icache_addr[13] ,
+    \u_riscv_top.core_icache_addr[12] ,
+    \u_riscv_top.core_icache_addr[11] ,
+    \u_riscv_top.core_icache_addr[10] ,
+    \u_riscv_top.core_icache_addr[9] ,
+    \u_riscv_top.core_icache_addr[8] ,
+    \u_riscv_top.core_icache_addr[7] ,
+    \u_riscv_top.core_icache_addr[6] ,
+    \u_riscv_top.core_icache_addr[5] ,
+    \u_riscv_top.core_icache_addr[4] ,
+    \u_riscv_top.core_icache_addr[3] ,
+    \u_riscv_top.core_icache_addr[2] ,
+    \u_riscv_top.core_icache_addr[1] ,
+    \u_riscv_top.core_icache_addr[0] }),
+    .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+    \u_riscv_top.core_icache_bl[1] ,
+    \u_riscv_top.core_icache_bl[0] }),
+    .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+    \u_riscv_top.core_icache_rdata[30] ,
+    \u_riscv_top.core_icache_rdata[29] ,
+    \u_riscv_top.core_icache_rdata[28] ,
+    \u_riscv_top.core_icache_rdata[27] ,
+    \u_riscv_top.core_icache_rdata[26] ,
+    \u_riscv_top.core_icache_rdata[25] ,
+    \u_riscv_top.core_icache_rdata[24] ,
+    \u_riscv_top.core_icache_rdata[23] ,
+    \u_riscv_top.core_icache_rdata[22] ,
+    \u_riscv_top.core_icache_rdata[21] ,
+    \u_riscv_top.core_icache_rdata[20] ,
+    \u_riscv_top.core_icache_rdata[19] ,
+    \u_riscv_top.core_icache_rdata[18] ,
+    \u_riscv_top.core_icache_rdata[17] ,
+    \u_riscv_top.core_icache_rdata[16] ,
+    \u_riscv_top.core_icache_rdata[15] ,
+    \u_riscv_top.core_icache_rdata[14] ,
+    \u_riscv_top.core_icache_rdata[13] ,
+    \u_riscv_top.core_icache_rdata[12] ,
+    \u_riscv_top.core_icache_rdata[11] ,
+    \u_riscv_top.core_icache_rdata[10] ,
+    \u_riscv_top.core_icache_rdata[9] ,
+    \u_riscv_top.core_icache_rdata[8] ,
+    \u_riscv_top.core_icache_rdata[7] ,
+    \u_riscv_top.core_icache_rdata[6] ,
+    \u_riscv_top.core_icache_rdata[5] ,
+    \u_riscv_top.core_icache_rdata[4] ,
+    \u_riscv_top.core_icache_rdata[3] ,
+    \u_riscv_top.core_icache_rdata[2] ,
+    \u_riscv_top.core_icache_rdata[1] ,
+    \u_riscv_top.core_icache_rdata[0] }),
+    .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+    \u_riscv_top.core_icache_resp[0] }),
+    .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+    \u_riscv_top.core_icache_width[0] }),
+    .core_irq_lines_i({\u_riscv_top.irq_lines[31] ,
+    \u_riscv_top.irq_lines[30] ,
+    \u_riscv_top.irq_lines[29] ,
+    \u_riscv_top.irq_lines[28] ,
+    \u_riscv_top.irq_lines[27] ,
+    \u_riscv_top.irq_lines[26] ,
+    \u_riscv_top.irq_lines[25] ,
+    \u_riscv_top.irq_lines[24] ,
+    \u_riscv_top.irq_lines[23] ,
+    \u_riscv_top.irq_lines[22] ,
+    \u_riscv_top.irq_lines[21] ,
+    \u_riscv_top.irq_lines[20] ,
+    \u_riscv_top.irq_lines[19] ,
+    \u_riscv_top.irq_lines[18] ,
+    \u_riscv_top.irq_lines[17] ,
+    \u_riscv_top.irq_lines[16] ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] }),
+    .riscv_debug({\u_riscv_top.riscv_debug[63] ,
+    \u_riscv_top.riscv_debug[62] ,
+    \u_riscv_top.riscv_debug[61] ,
+    \u_riscv_top.riscv_debug[60] ,
+    \u_riscv_top.riscv_debug[59] ,
+    \u_riscv_top.riscv_debug[58] ,
+    \u_riscv_top.riscv_debug[57] ,
+    \u_riscv_top.riscv_debug[56] ,
+    \u_riscv_top.riscv_debug[55] ,
+    \u_riscv_top.riscv_debug[54] ,
+    \u_riscv_top.riscv_debug[53] ,
+    \u_riscv_top.riscv_debug[52] ,
+    \u_riscv_top.riscv_debug[51] ,
+    \u_riscv_top.riscv_debug[50] ,
+    \u_riscv_top.riscv_debug[49] ,
+    \u_riscv_top.riscv_debug[48] ,
+    \u_riscv_top.riscv_debug[47] ,
+    \u_riscv_top.riscv_debug[46] ,
+    \u_riscv_top.riscv_debug[45] ,
+    \u_riscv_top.riscv_debug[44] ,
+    \u_riscv_top.riscv_debug[43] ,
+    \u_riscv_top.riscv_debug[42] ,
+    \u_riscv_top.riscv_debug[41] ,
+    \u_riscv_top.riscv_debug[40] ,
+    \u_riscv_top.riscv_debug[39] ,
+    \u_riscv_top.riscv_debug[38] ,
+    \u_riscv_top.riscv_debug[37] ,
+    \u_riscv_top.riscv_debug[36] ,
+    \u_riscv_top.riscv_debug[35] ,
+    \u_riscv_top.riscv_debug[34] ,
+    \u_riscv_top.riscv_debug[33] ,
+    \u_riscv_top.riscv_debug[32] ,
+    \u_riscv_top.riscv_debug[31] ,
+    \u_riscv_top.riscv_debug[30] ,
+    \u_riscv_top.riscv_debug[29] ,
+    \u_riscv_top.riscv_debug[28] ,
+    \u_riscv_top.riscv_debug[27] ,
+    \u_riscv_top.riscv_debug[26] ,
+    \u_riscv_top.riscv_debug[25] ,
+    \u_riscv_top.riscv_debug[24] ,
+    \u_riscv_top.riscv_debug[23] ,
+    \u_riscv_top.riscv_debug[22] ,
+    \u_riscv_top.riscv_debug[21] ,
+    \u_riscv_top.riscv_debug[20] ,
+    \u_riscv_top.riscv_debug[19] ,
+    \u_riscv_top.riscv_debug[18] ,
+    \u_riscv_top.riscv_debug[17] ,
+    \u_riscv_top.riscv_debug[16] ,
+    \u_riscv_top.riscv_debug[15] ,
+    \u_riscv_top.riscv_debug[14] ,
+    \u_riscv_top.riscv_debug[13] ,
+    \u_riscv_top.riscv_debug[12] ,
+    \u_riscv_top.riscv_debug[11] ,
+    \u_riscv_top.riscv_debug[10] ,
+    \u_riscv_top.riscv_debug[9] ,
+    \u_riscv_top.riscv_debug[8] ,
+    \u_riscv_top.riscv_debug[7] ,
+    \u_riscv_top.riscv_debug[6] ,
+    \u_riscv_top.riscv_debug[5] ,
+    \u_riscv_top.riscv_debug[4] ,
+    \u_riscv_top.riscv_debug[3] ,
+    \u_riscv_top.riscv_debug[2] ,
+    \u_riscv_top.riscv_debug[1] ,
+    \u_riscv_top.riscv_debug[0] }),
+    .sram0_addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .sram0_addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .sram0_din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .sram0_dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .sram0_dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .sram0_wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }));
+ ycr_intf \u_riscv_top.u_intf  (.cfg_bypass_dcache(\cfg_riscv_ctrl[11] ),
+    .cfg_bypass_icache(\cfg_riscv_ctrl[10] ),
+    .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+    .cfg_dcache_pfet_dis(\cfg_riscv_ctrl[6] ),
+    .cfg_icache_ntag_pfet_dis(\cfg_riscv_ctrl[5] ),
+    .cfg_icache_pfet_dis(\cfg_riscv_ctrl[4] ),
+    .core_clk(\u_riscv_top.core_clk_intf_skew ),
+    .core_clk_int(\u_riscv_top.core_clk_int[0] ),
+    .core_clk_skew(\u_riscv_top.core_clk_intf_skew ),
+    .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+    .core_dcache_req(\u_riscv_top.core_dcache_req ),
+    .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+    .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+    .core_dmem_req(\u_riscv_top.core_dmem_req ),
+    .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+    .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+    .core_icache_req(\u_riscv_top.core_icache_req ),
+    .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .dcache_mem_clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .dcache_mem_clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .dcache_mem_csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .dcache_mem_csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .dcache_mem_web0(\u_riscv_top.dcache_mem_web0 ),
+    .icache_mem_clk0(\u_riscv_top.icache_mem_clk0 ),
+    .icache_mem_clk1(\u_riscv_top.icache_mem_clk1 ),
+    .icache_mem_csb0(\u_riscv_top.icache_mem_csb0 ),
+    .icache_mem_csb1(\u_riscv_top.icache_mem_csb1 ),
+    .icache_mem_web0(\u_riscv_top.icache_mem_web0 ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wb_clk(\u_riscv_top.wb_clk ),
+    .wb_dcache_ack_i(\u_riscv_top.wb_dcache_ack_i ),
+    .wb_dcache_bry_o(\u_riscv_top.wb_dcache_bry_o ),
+    .wb_dcache_cyc_o(\u_riscv_top.wb_dcache_cyc_o ),
+    .wb_dcache_err_i(\u_riscv_top.wb_dcache_err_i ),
+    .wb_dcache_lack_i(\u_riscv_top.wb_dcache_lack_i ),
+    .wb_dcache_stb_o(\u_riscv_top.wb_dcache_stb_o ),
+    .wb_dcache_we_o(\u_riscv_top.wb_dcache_we_o ),
+    .wb_icache_ack_i(\u_riscv_top.wb_icache_ack_i ),
+    .wb_icache_bry_o(\u_riscv_top.wb_icache_bry_o ),
+    .wb_icache_cyc_o(\u_riscv_top.wb_icache_cyc_o ),
+    .wb_icache_err_i(\u_riscv_top.wb_icache_err_i ),
+    .wb_icache_lack_i(\u_riscv_top.wb_icache_lack_i ),
+    .wb_icache_stb_o(\u_riscv_top.wb_icache_stb_o ),
+    .wb_icache_we_o(\u_riscv_top.wb_icache_we_o ),
+    .wb_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbd_clk_int(\u_riscv_top.wbd_clk_int ),
+    .wbd_clk_skew(\u_riscv_top.wb_clk ),
+    .wbd_dmem_ack_i(\u_riscv_top.wbd_dmem_ack_i ),
+    .wbd_dmem_bry_o(\u_riscv_top.wbd_dmem_bry_o ),
+    .wbd_dmem_err_i(\u_riscv_top.wbd_dmem_err_i ),
+    .wbd_dmem_lack_i(\u_riscv_top.wbd_dmem_lack_i ),
+    .wbd_dmem_stb_o(\u_riscv_top.wbd_dmem_stb_o ),
+    .wbd_dmem_we_o(\u_riscv_top.wbd_dmem_we_o ),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_intf[3] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[2] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[1] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[0] }),
+    .cfg_sram_lphase({\cfg_riscv_ctrl[1] ,
+    \cfg_riscv_ctrl[0] }),
+    .cfg_wcska({\u_riscv_top.cfg_wcska_riscv_intf[3] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[2] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[1] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[0] }),
+    .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+    \u_riscv_top.core_dcache_addr[30] ,
+    \u_riscv_top.core_dcache_addr[29] ,
+    \u_riscv_top.core_dcache_addr[28] ,
+    \u_riscv_top.core_dcache_addr[27] ,
+    \u_riscv_top.core_dcache_addr[26] ,
+    \u_riscv_top.core_dcache_addr[25] ,
+    \u_riscv_top.core_dcache_addr[24] ,
+    \u_riscv_top.core_dcache_addr[23] ,
+    \u_riscv_top.core_dcache_addr[22] ,
+    \u_riscv_top.core_dcache_addr[21] ,
+    \u_riscv_top.core_dcache_addr[20] ,
+    \u_riscv_top.core_dcache_addr[19] ,
+    \u_riscv_top.core_dcache_addr[18] ,
+    \u_riscv_top.core_dcache_addr[17] ,
+    \u_riscv_top.core_dcache_addr[16] ,
+    \u_riscv_top.core_dcache_addr[15] ,
+    \u_riscv_top.core_dcache_addr[14] ,
+    \u_riscv_top.core_dcache_addr[13] ,
+    \u_riscv_top.core_dcache_addr[12] ,
+    \u_riscv_top.core_dcache_addr[11] ,
+    \u_riscv_top.core_dcache_addr[10] ,
+    \u_riscv_top.core_dcache_addr[9] ,
+    \u_riscv_top.core_dcache_addr[8] ,
+    \u_riscv_top.core_dcache_addr[7] ,
+    \u_riscv_top.core_dcache_addr[6] ,
+    \u_riscv_top.core_dcache_addr[5] ,
+    \u_riscv_top.core_dcache_addr[4] ,
+    \u_riscv_top.core_dcache_addr[3] ,
+    \u_riscv_top.core_dcache_addr[2] ,
+    \u_riscv_top.core_dcache_addr[1] ,
+    \u_riscv_top.core_dcache_addr[0] }),
+    .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+    \u_riscv_top.core_dcache_rdata[30] ,
+    \u_riscv_top.core_dcache_rdata[29] ,
+    \u_riscv_top.core_dcache_rdata[28] ,
+    \u_riscv_top.core_dcache_rdata[27] ,
+    \u_riscv_top.core_dcache_rdata[26] ,
+    \u_riscv_top.core_dcache_rdata[25] ,
+    \u_riscv_top.core_dcache_rdata[24] ,
+    \u_riscv_top.core_dcache_rdata[23] ,
+    \u_riscv_top.core_dcache_rdata[22] ,
+    \u_riscv_top.core_dcache_rdata[21] ,
+    \u_riscv_top.core_dcache_rdata[20] ,
+    \u_riscv_top.core_dcache_rdata[19] ,
+    \u_riscv_top.core_dcache_rdata[18] ,
+    \u_riscv_top.core_dcache_rdata[17] ,
+    \u_riscv_top.core_dcache_rdata[16] ,
+    \u_riscv_top.core_dcache_rdata[15] ,
+    \u_riscv_top.core_dcache_rdata[14] ,
+    \u_riscv_top.core_dcache_rdata[13] ,
+    \u_riscv_top.core_dcache_rdata[12] ,
+    \u_riscv_top.core_dcache_rdata[11] ,
+    \u_riscv_top.core_dcache_rdata[10] ,
+    \u_riscv_top.core_dcache_rdata[9] ,
+    \u_riscv_top.core_dcache_rdata[8] ,
+    \u_riscv_top.core_dcache_rdata[7] ,
+    \u_riscv_top.core_dcache_rdata[6] ,
+    \u_riscv_top.core_dcache_rdata[5] ,
+    \u_riscv_top.core_dcache_rdata[4] ,
+    \u_riscv_top.core_dcache_rdata[3] ,
+    \u_riscv_top.core_dcache_rdata[2] ,
+    \u_riscv_top.core_dcache_rdata[1] ,
+    \u_riscv_top.core_dcache_rdata[0] }),
+    .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+    \u_riscv_top.core_dcache_resp[0] }),
+    .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+    \u_riscv_top.core_dcache_wdata[30] ,
+    \u_riscv_top.core_dcache_wdata[29] ,
+    \u_riscv_top.core_dcache_wdata[28] ,
+    \u_riscv_top.core_dcache_wdata[27] ,
+    \u_riscv_top.core_dcache_wdata[26] ,
+    \u_riscv_top.core_dcache_wdata[25] ,
+    \u_riscv_top.core_dcache_wdata[24] ,
+    \u_riscv_top.core_dcache_wdata[23] ,
+    \u_riscv_top.core_dcache_wdata[22] ,
+    \u_riscv_top.core_dcache_wdata[21] ,
+    \u_riscv_top.core_dcache_wdata[20] ,
+    \u_riscv_top.core_dcache_wdata[19] ,
+    \u_riscv_top.core_dcache_wdata[18] ,
+    \u_riscv_top.core_dcache_wdata[17] ,
+    \u_riscv_top.core_dcache_wdata[16] ,
+    \u_riscv_top.core_dcache_wdata[15] ,
+    \u_riscv_top.core_dcache_wdata[14] ,
+    \u_riscv_top.core_dcache_wdata[13] ,
+    \u_riscv_top.core_dcache_wdata[12] ,
+    \u_riscv_top.core_dcache_wdata[11] ,
+    \u_riscv_top.core_dcache_wdata[10] ,
+    \u_riscv_top.core_dcache_wdata[9] ,
+    \u_riscv_top.core_dcache_wdata[8] ,
+    \u_riscv_top.core_dcache_wdata[7] ,
+    \u_riscv_top.core_dcache_wdata[6] ,
+    \u_riscv_top.core_dcache_wdata[5] ,
+    \u_riscv_top.core_dcache_wdata[4] ,
+    \u_riscv_top.core_dcache_wdata[3] ,
+    \u_riscv_top.core_dcache_wdata[2] ,
+    \u_riscv_top.core_dcache_wdata[1] ,
+    \u_riscv_top.core_dcache_wdata[0] }),
+    .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+    \u_riscv_top.core_dcache_width[0] }),
+    .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+    \u_riscv_top.core_dmem_addr[30] ,
+    \u_riscv_top.core_dmem_addr[29] ,
+    \u_riscv_top.core_dmem_addr[28] ,
+    \u_riscv_top.core_dmem_addr[27] ,
+    \u_riscv_top.core_dmem_addr[26] ,
+    \u_riscv_top.core_dmem_addr[25] ,
+    \u_riscv_top.core_dmem_addr[24] ,
+    \u_riscv_top.core_dmem_addr[23] ,
+    \u_riscv_top.core_dmem_addr[22] ,
+    \u_riscv_top.core_dmem_addr[21] ,
+    \u_riscv_top.core_dmem_addr[20] ,
+    \u_riscv_top.core_dmem_addr[19] ,
+    \u_riscv_top.core_dmem_addr[18] ,
+    \u_riscv_top.core_dmem_addr[17] ,
+    \u_riscv_top.core_dmem_addr[16] ,
+    \u_riscv_top.core_dmem_addr[15] ,
+    \u_riscv_top.core_dmem_addr[14] ,
+    \u_riscv_top.core_dmem_addr[13] ,
+    \u_riscv_top.core_dmem_addr[12] ,
+    \u_riscv_top.core_dmem_addr[11] ,
+    \u_riscv_top.core_dmem_addr[10] ,
+    \u_riscv_top.core_dmem_addr[9] ,
+    \u_riscv_top.core_dmem_addr[8] ,
+    \u_riscv_top.core_dmem_addr[7] ,
+    \u_riscv_top.core_dmem_addr[6] ,
+    \u_riscv_top.core_dmem_addr[5] ,
+    \u_riscv_top.core_dmem_addr[4] ,
+    \u_riscv_top.core_dmem_addr[3] ,
+    \u_riscv_top.core_dmem_addr[2] ,
+    \u_riscv_top.core_dmem_addr[1] ,
+    \u_riscv_top.core_dmem_addr[0] }),
+    .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] ,
+    \u_riscv_top.core_dmem_bl[1] ,
+    \u_riscv_top.core_dmem_bl[0] }),
+    .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+    \u_riscv_top.core_dmem_rdata[30] ,
+    \u_riscv_top.core_dmem_rdata[29] ,
+    \u_riscv_top.core_dmem_rdata[28] ,
+    \u_riscv_top.core_dmem_rdata[27] ,
+    \u_riscv_top.core_dmem_rdata[26] ,
+    \u_riscv_top.core_dmem_rdata[25] ,
+    \u_riscv_top.core_dmem_rdata[24] ,
+    \u_riscv_top.core_dmem_rdata[23] ,
+    \u_riscv_top.core_dmem_rdata[22] ,
+    \u_riscv_top.core_dmem_rdata[21] ,
+    \u_riscv_top.core_dmem_rdata[20] ,
+    \u_riscv_top.core_dmem_rdata[19] ,
+    \u_riscv_top.core_dmem_rdata[18] ,
+    \u_riscv_top.core_dmem_rdata[17] ,
+    \u_riscv_top.core_dmem_rdata[16] ,
+    \u_riscv_top.core_dmem_rdata[15] ,
+    \u_riscv_top.core_dmem_rdata[14] ,
+    \u_riscv_top.core_dmem_rdata[13] ,
+    \u_riscv_top.core_dmem_rdata[12] ,
+    \u_riscv_top.core_dmem_rdata[11] ,
+    \u_riscv_top.core_dmem_rdata[10] ,
+    \u_riscv_top.core_dmem_rdata[9] ,
+    \u_riscv_top.core_dmem_rdata[8] ,
+    \u_riscv_top.core_dmem_rdata[7] ,
+    \u_riscv_top.core_dmem_rdata[6] ,
+    \u_riscv_top.core_dmem_rdata[5] ,
+    \u_riscv_top.core_dmem_rdata[4] ,
+    \u_riscv_top.core_dmem_rdata[3] ,
+    \u_riscv_top.core_dmem_rdata[2] ,
+    \u_riscv_top.core_dmem_rdata[1] ,
+    \u_riscv_top.core_dmem_rdata[0] }),
+    .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+    \u_riscv_top.core_dmem_resp[0] }),
+    .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+    \u_riscv_top.core_dmem_wdata[30] ,
+    \u_riscv_top.core_dmem_wdata[29] ,
+    \u_riscv_top.core_dmem_wdata[28] ,
+    \u_riscv_top.core_dmem_wdata[27] ,
+    \u_riscv_top.core_dmem_wdata[26] ,
+    \u_riscv_top.core_dmem_wdata[25] ,
+    \u_riscv_top.core_dmem_wdata[24] ,
+    \u_riscv_top.core_dmem_wdata[23] ,
+    \u_riscv_top.core_dmem_wdata[22] ,
+    \u_riscv_top.core_dmem_wdata[21] ,
+    \u_riscv_top.core_dmem_wdata[20] ,
+    \u_riscv_top.core_dmem_wdata[19] ,
+    \u_riscv_top.core_dmem_wdata[18] ,
+    \u_riscv_top.core_dmem_wdata[17] ,
+    \u_riscv_top.core_dmem_wdata[16] ,
+    \u_riscv_top.core_dmem_wdata[15] ,
+    \u_riscv_top.core_dmem_wdata[14] ,
+    \u_riscv_top.core_dmem_wdata[13] ,
+    \u_riscv_top.core_dmem_wdata[12] ,
+    \u_riscv_top.core_dmem_wdata[11] ,
+    \u_riscv_top.core_dmem_wdata[10] ,
+    \u_riscv_top.core_dmem_wdata[9] ,
+    \u_riscv_top.core_dmem_wdata[8] ,
+    \u_riscv_top.core_dmem_wdata[7] ,
+    \u_riscv_top.core_dmem_wdata[6] ,
+    \u_riscv_top.core_dmem_wdata[5] ,
+    \u_riscv_top.core_dmem_wdata[4] ,
+    \u_riscv_top.core_dmem_wdata[3] ,
+    \u_riscv_top.core_dmem_wdata[2] ,
+    \u_riscv_top.core_dmem_wdata[1] ,
+    \u_riscv_top.core_dmem_wdata[0] }),
+    .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+    \u_riscv_top.core_dmem_width[0] }),
+    .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+    \u_riscv_top.core_icache_addr[30] ,
+    \u_riscv_top.core_icache_addr[29] ,
+    \u_riscv_top.core_icache_addr[28] ,
+    \u_riscv_top.core_icache_addr[27] ,
+    \u_riscv_top.core_icache_addr[26] ,
+    \u_riscv_top.core_icache_addr[25] ,
+    \u_riscv_top.core_icache_addr[24] ,
+    \u_riscv_top.core_icache_addr[23] ,
+    \u_riscv_top.core_icache_addr[22] ,
+    \u_riscv_top.core_icache_addr[21] ,
+    \u_riscv_top.core_icache_addr[20] ,
+    \u_riscv_top.core_icache_addr[19] ,
+    \u_riscv_top.core_icache_addr[18] ,
+    \u_riscv_top.core_icache_addr[17] ,
+    \u_riscv_top.core_icache_addr[16] ,
+    \u_riscv_top.core_icache_addr[15] ,
+    \u_riscv_top.core_icache_addr[14] ,
+    \u_riscv_top.core_icache_addr[13] ,
+    \u_riscv_top.core_icache_addr[12] ,
+    \u_riscv_top.core_icache_addr[11] ,
+    \u_riscv_top.core_icache_addr[10] ,
+    \u_riscv_top.core_icache_addr[9] ,
+    \u_riscv_top.core_icache_addr[8] ,
+    \u_riscv_top.core_icache_addr[7] ,
+    \u_riscv_top.core_icache_addr[6] ,
+    \u_riscv_top.core_icache_addr[5] ,
+    \u_riscv_top.core_icache_addr[4] ,
+    \u_riscv_top.core_icache_addr[3] ,
+    \u_riscv_top.core_icache_addr[2] ,
+    \u_riscv_top.core_icache_addr[1] ,
+    \u_riscv_top.core_icache_addr[0] }),
+    .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+    \u_riscv_top.core_icache_bl[1] ,
+    \u_riscv_top.core_icache_bl[0] }),
+    .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+    \u_riscv_top.core_icache_rdata[30] ,
+    \u_riscv_top.core_icache_rdata[29] ,
+    \u_riscv_top.core_icache_rdata[28] ,
+    \u_riscv_top.core_icache_rdata[27] ,
+    \u_riscv_top.core_icache_rdata[26] ,
+    \u_riscv_top.core_icache_rdata[25] ,
+    \u_riscv_top.core_icache_rdata[24] ,
+    \u_riscv_top.core_icache_rdata[23] ,
+    \u_riscv_top.core_icache_rdata[22] ,
+    \u_riscv_top.core_icache_rdata[21] ,
+    \u_riscv_top.core_icache_rdata[20] ,
+    \u_riscv_top.core_icache_rdata[19] ,
+    \u_riscv_top.core_icache_rdata[18] ,
+    \u_riscv_top.core_icache_rdata[17] ,
+    \u_riscv_top.core_icache_rdata[16] ,
+    \u_riscv_top.core_icache_rdata[15] ,
+    \u_riscv_top.core_icache_rdata[14] ,
+    \u_riscv_top.core_icache_rdata[13] ,
+    \u_riscv_top.core_icache_rdata[12] ,
+    \u_riscv_top.core_icache_rdata[11] ,
+    \u_riscv_top.core_icache_rdata[10] ,
+    \u_riscv_top.core_icache_rdata[9] ,
+    \u_riscv_top.core_icache_rdata[8] ,
+    \u_riscv_top.core_icache_rdata[7] ,
+    \u_riscv_top.core_icache_rdata[6] ,
+    \u_riscv_top.core_icache_rdata[5] ,
+    \u_riscv_top.core_icache_rdata[4] ,
+    \u_riscv_top.core_icache_rdata[3] ,
+    \u_riscv_top.core_icache_rdata[2] ,
+    \u_riscv_top.core_icache_rdata[1] ,
+    \u_riscv_top.core_icache_rdata[0] }),
+    .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+    \u_riscv_top.core_icache_resp[0] }),
+    .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+    \u_riscv_top.core_icache_width[0] }),
+    .dcache_mem_addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .dcache_mem_addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .dcache_mem_din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dcache_mem_dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dcache_mem_dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .dcache_mem_wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }),
+    .icache_mem_addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .icache_mem_addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .icache_mem_din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .icache_mem_dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .icache_mem_wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }),
+    .wb_dcache_adr_o({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .wb_dcache_bl_o({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .wb_dcache_dat_i({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .wb_dcache_dat_o({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .wb_dcache_sel_o({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .wb_icache_adr_o({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .wb_icache_bl_o({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .wb_icache_dat_i({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .wb_icache_sel_o({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .wbd_dmem_adr_o({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .wbd_dmem_bl_o({\u_riscv_top.wbd_dmem_bl_o[2] ,
+    \u_riscv_top.wbd_dmem_bl_o[1] ,
+    \u_riscv_top.wbd_dmem_bl_o[0] }),
+    .wbd_dmem_dat_i({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .wbd_dmem_dat_o({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .wbd_dmem_sel_o({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }));
+ bus_rep_east u_rp_east (.vccd1(vccd1),
+    .vssd1(vssd1),
+    .ch_in({io_in[0],
+    \io_out_int[0] ,
+    \io_oeb_int[0] ,
+    io_in[1],
+    \io_out_int[1] ,
+    \io_oeb_int[1] ,
+    io_in[2],
+    \io_out_int[2] ,
+    \io_oeb_int[2] ,
+    io_in[3],
+    \io_out_int[3] ,
+    \io_oeb_int[3] ,
+    io_in[4],
+    \io_out_int[4] ,
+    \io_oeb_int[4] ,
+    io_in[5],
+    \io_out_int[5] ,
+    \io_oeb_int[5] ,
+    io_in[6],
+    \io_out_int[6] ,
+    \io_oeb_int[6] ,
+    io_in[7],
+    \io_out_int[7] ,
+    \io_oeb_int[7] ,
+    io_in[8],
+    \io_out_int[8] ,
+    \io_oeb_int[8] ,
+    io_in[9],
+    \io_out_int[9] ,
+    \io_oeb_int[9] ,
+    io_in[10],
+    \io_out_int[10] ,
+    \io_oeb_int[10] ,
+    io_in[11],
+    \io_out_int[11] ,
+    \io_oeb_int[11] ,
+    io_in[12],
+    \io_out_int[12] ,
+    \io_oeb_int[12] ,
+    io_in[13],
+    \io_out_int[13] ,
+    \io_oeb_int[13] ,
+    io_in[14],
+    \io_out_int[14] ,
+    \io_oeb_int[14] }),
+    .ch_out({\ch_out_east[44] ,
+    io_out[0],
+    io_oeb[0],
+    \ch_out_east[41] ,
+    io_out[1],
+    io_oeb[1],
+    \ch_out_east[38] ,
+    io_out[2],
+    io_oeb[2],
+    \ch_out_east[35] ,
+    io_out[3],
+    io_oeb[3],
+    \ch_out_east[32] ,
+    io_out[4],
+    io_oeb[4],
+    \ch_out_east[29] ,
+    io_out[5],
+    io_oeb[5],
+    \ch_out_east[26] ,
+    io_out[6],
+    io_oeb[6],
+    \ch_out_east[23] ,
+    io_out[7],
+    io_oeb[7],
+    \ch_out_east[20] ,
+    io_out[8],
+    io_oeb[8],
+    \ch_out_east[17] ,
+    io_out[9],
+    io_oeb[9],
+    \ch_out_east[14] ,
+    io_out[10],
+    io_oeb[10],
+    \ch_out_east[11] ,
+    io_out[11],
+    io_oeb[11],
+    \ch_out_east[8] ,
+    io_out[12],
+    io_oeb[12],
+    \ch_out_east[5] ,
+    io_out[13],
+    io_oeb[13],
+    \ch_out_east[2] ,
+    io_out[14],
+    io_oeb[14]}));
+ bus_rep_north u_rp_north (.vccd1(vccd1),
+    .vssd1(vssd1),
+    .buf_in({\io_oeb_int[37] ,
+    \io_out_int[37] ,
+    \ch_out_west[39] ,
+    \io_oeb_int[36] ,
+    \io_out_int[36] ,
+    \ch_out_west[36] ,
+    \io_oeb_int[35] ,
+    \io_out_int[35] ,
+    \ch_out_west[33] ,
+    \io_oeb_int[34] ,
+    \io_out_int[34] ,
+    \ch_out_west[30] ,
+    \io_oeb_int[33] ,
+    \io_out_int[33] ,
+    \ch_out_west[27] ,
+    \io_oeb_int[32] ,
+    \io_out_int[32] ,
+    \ch_out_west[24] ,
+    \io_oeb_int[31] ,
+    \io_out_int[31] ,
+    \ch_out_west[21] ,
+    \io_oeb_int[30] ,
+    \io_out_int[30] ,
+    \ch_out_west[18] ,
+    \io_oeb_int[29] ,
+    \io_out_int[29] ,
+    \ch_out_west[15] ,
+    \io_oeb_int[28] ,
+    \io_out_int[28] ,
+    \ch_out_west[12] ,
+    \io_oeb_int[27] ,
+    \io_out_int[27] ,
+    \ch_out_west[9] ,
+    \io_oeb_int[26] ,
+    \io_out_int[26] ,
+    \ch_out_west[6] ,
+    \io_oeb_int[25] ,
+    \io_out_int[25] ,
+    \ch_out_west[3] ,
+    \io_oeb_int[24] ,
+    \io_out_int[24] ,
+    \ch_out_west[0] }),
+    .buf_out({\buf_out_north[41] ,
+    \buf_out_north[40] ,
+    \buf_out_north[39] ,
+    \buf_out_north[38] ,
+    \buf_out_north[37] ,
+    \buf_out_north[36] ,
+    \buf_out_north[35] ,
+    \buf_out_north[34] ,
+    \buf_out_north[33] ,
+    \buf_out_north[32] ,
+    \buf_out_north[31] ,
+    \buf_out_north[30] ,
+    \buf_out_north[29] ,
+    \buf_out_north[28] ,
+    \buf_out_north[27] ,
+    \buf_out_north[26] ,
+    \buf_out_north[25] ,
+    \buf_out_north[24] ,
+    \buf_out_north[23] ,
+    \buf_out_north[22] ,
+    \buf_out_north[21] ,
+    \buf_out_north[20] ,
+    \buf_out_north[19] ,
+    \buf_out_north[18] ,
+    \buf_out_north[17] ,
+    \buf_out_north[16] ,
+    \buf_out_north[15] ,
+    \buf_out_north[14] ,
+    \buf_out_north[13] ,
+    \buf_out_north[12] ,
+    \buf_out_north[11] ,
+    \buf_out_north[10] ,
+    \buf_out_north[9] ,
+    \buf_out_north[8] ,
+    \buf_out_north[7] ,
+    \buf_out_north[6] ,
+    \buf_out_north[5] ,
+    \buf_out_north[4] ,
+    \buf_out_north[3] ,
+    \buf_out_north[2] ,
+    \buf_out_north[1] ,
+    \buf_out_north[0] }),
+    .ch_in({io_in[15],
+    \io_out_int[15] ,
+    \io_oeb_int[15] ,
+    io_in[16],
+    \io_out_int[16] ,
+    \io_oeb_int[16] ,
+    io_in[17],
+    \io_out_int[17] ,
+    \io_oeb_int[17] ,
+    io_in[18],
+    \io_out_int[18] ,
+    \io_oeb_int[18] ,
+    io_in[19],
+    \io_out_int[19] ,
+    \io_oeb_int[19] ,
+    io_in[20],
+    \io_out_int[20] ,
+    \io_oeb_int[20] ,
+    io_in[21],
+    \io_out_int[21] ,
+    \io_oeb_int[21] ,
+    io_in[22],
+    \io_out_int[22] ,
+    \io_oeb_int[22] ,
+    io_in[23],
+    \io_out_int[23] ,
+    \io_oeb_int[23] }),
+    .ch_out({\ch_out_north[26] ,
+    io_out[15],
+    io_oeb[15],
+    \ch_out_north[23] ,
+    io_out[16],
+    io_oeb[16],
+    \ch_out_north[20] ,
+    io_out[17],
+    io_oeb[17],
+    \ch_out_north[17] ,
+    io_out[18],
+    io_oeb[18],
+    \ch_out_north[14] ,
+    io_out[19],
+    io_oeb[19],
+    \ch_out_north[11] ,
+    io_out[20],
+    io_oeb[20],
+    \ch_out_north[8] ,
+    io_out[21],
+    io_oeb[21],
+    \ch_out_north[5] ,
+    io_out[22],
+    io_oeb[22],
+    \ch_out_north[2] ,
+    io_out[23],
+    io_oeb[23]}));
+ bus_rep_south u_rp_south (.vccd1(vccd1),
+    .vssd1(vssd1),
+    .ch_in({user_clock2,
+    \pinmux_debug[31] ,
+    \pinmux_debug[30] ,
+    \pinmux_debug[29] ,
+    \pinmux_debug[28] ,
+    \pinmux_debug[27] ,
+    \pinmux_debug[26] ,
+    \pinmux_debug[25] ,
+    \pinmux_debug[24] ,
+    \pinmux_debug[23] ,
+    \pinmux_debug[22] ,
+    \pinmux_debug[21] ,
+    \pinmux_debug[20] ,
+    \pinmux_debug[19] ,
+    \pinmux_debug[18] ,
+    \pinmux_debug[17] ,
+    \pinmux_debug[16] ,
+    \pinmux_debug[15] ,
+    \pinmux_debug[14] ,
+    \pinmux_debug[13] ,
+    \pinmux_debug[12] ,
+    \pinmux_debug[11] ,
+    \pinmux_debug[10] ,
+    \pinmux_debug[9] ,
+    \pinmux_debug[8] ,
+    \pinmux_debug[7] ,
+    \pinmux_debug[6] ,
+    \pinmux_debug[5] ,
+    \pinmux_debug[4] ,
+    \pinmux_debug[3] ,
+    \pinmux_debug[2] ,
+    \pinmux_debug[1] ,
+    \pinmux_debug[0] ,
+    \spi_debug[31] ,
+    \spi_debug[30] ,
+    \spi_debug[29] ,
+    \spi_debug[28] ,
+    \spi_debug[27] ,
+    \spi_debug[26] ,
+    \spi_debug[25] ,
+    \spi_debug[24] ,
+    \spi_debug[23] ,
+    \spi_debug[22] ,
+    \spi_debug[21] ,
+    \spi_debug[20] ,
+    \spi_debug[19] ,
+    \spi_debug[18] ,
+    \spi_debug[17] ,
+    \spi_debug[16] ,
+    \spi_debug[15] ,
+    \spi_debug[14] ,
+    \spi_debug[13] ,
+    \spi_debug[12] ,
+    \spi_debug[11] ,
+    \spi_debug[10] ,
+    \spi_debug[9] ,
+    \spi_debug[8] ,
+    \spi_debug[7] ,
+    \spi_debug[6] ,
+    \spi_debug[5] ,
+    \spi_debug[4] ,
+    \spi_debug[3] ,
+    \spi_debug[2] ,
+    \spi_debug[1] ,
+    \spi_debug[0] ,
+    \u_riscv_top.riscv_debug[63] ,
+    \u_riscv_top.riscv_debug[62] ,
+    \u_riscv_top.riscv_debug[61] ,
+    \u_riscv_top.riscv_debug[60] ,
+    \u_riscv_top.riscv_debug[59] ,
+    \u_riscv_top.riscv_debug[58] ,
+    \u_riscv_top.riscv_debug[57] ,
+    \u_riscv_top.riscv_debug[56] ,
+    \u_riscv_top.riscv_debug[55] ,
+    \u_riscv_top.riscv_debug[54] ,
+    \u_riscv_top.riscv_debug[53] ,
+    \u_riscv_top.riscv_debug[52] ,
+    \u_riscv_top.riscv_debug[51] ,
+    \u_riscv_top.riscv_debug[50] ,
+    \u_riscv_top.riscv_debug[49] ,
+    \u_riscv_top.riscv_debug[48] ,
+    \u_riscv_top.riscv_debug[47] ,
+    \u_riscv_top.riscv_debug[46] ,
+    \u_riscv_top.riscv_debug[45] ,
+    \u_riscv_top.riscv_debug[44] ,
+    \u_riscv_top.riscv_debug[43] ,
+    \u_riscv_top.riscv_debug[42] ,
+    \u_riscv_top.riscv_debug[41] ,
+    \u_riscv_top.riscv_debug[40] ,
+    \u_riscv_top.riscv_debug[39] ,
+    \u_riscv_top.riscv_debug[38] ,
+    \u_riscv_top.riscv_debug[37] ,
+    \u_riscv_top.riscv_debug[36] ,
+    \u_riscv_top.riscv_debug[35] ,
+    \u_riscv_top.riscv_debug[34] ,
+    \u_riscv_top.riscv_debug[33] ,
+    \u_riscv_top.riscv_debug[32] ,
+    \u_riscv_top.riscv_debug[31] ,
+    \u_riscv_top.riscv_debug[30] ,
+    \u_riscv_top.riscv_debug[29] ,
+    \u_riscv_top.riscv_debug[28] ,
+    \u_riscv_top.riscv_debug[27] ,
+    \u_riscv_top.riscv_debug[26] ,
+    \u_riscv_top.riscv_debug[25] ,
+    \u_riscv_top.riscv_debug[24] ,
+    \u_riscv_top.riscv_debug[23] ,
+    \u_riscv_top.riscv_debug[22] ,
+    \u_riscv_top.riscv_debug[21] ,
+    \u_riscv_top.riscv_debug[20] ,
+    \u_riscv_top.riscv_debug[19] ,
+    \u_riscv_top.riscv_debug[18] ,
+    \u_riscv_top.riscv_debug[17] ,
+    la_data_in[17],
+    \u_riscv_top.riscv_debug[16] ,
+    la_data_in[16],
+    \u_riscv_top.riscv_debug[15] ,
+    la_data_in[15],
+    \u_riscv_top.riscv_debug[14] ,
+    la_data_in[14],
+    \u_riscv_top.riscv_debug[13] ,
+    la_data_in[13],
+    \u_riscv_top.riscv_debug[12] ,
+    la_data_in[12],
+    \u_riscv_top.riscv_debug[11] ,
+    la_data_in[11],
+    \u_riscv_top.riscv_debug[10] ,
+    la_data_in[10],
+    \u_riscv_top.riscv_debug[9] ,
+    la_data_in[9],
+    \u_riscv_top.riscv_debug[8] ,
+    la_data_in[8],
+    \u_riscv_top.riscv_debug[7] ,
+    la_data_in[7],
+    \u_riscv_top.riscv_debug[6] ,
+    la_data_in[6],
+    \u_riscv_top.riscv_debug[5] ,
+    la_data_in[5],
+    \u_riscv_top.riscv_debug[4] ,
+    la_data_in[4],
+    \u_riscv_top.riscv_debug[3] ,
+    la_data_in[3],
+    \u_riscv_top.riscv_debug[2] ,
+    la_data_in[2],
+    \u_riscv_top.riscv_debug[1] ,
+    la_data_in[1],
+    \u_riscv_top.riscv_debug[0] ,
+    la_data_in[0],
+    \wbs_dat_int_o[31] ,
+    wbs_dat_i[31],
+    wbs_adr_i[31],
+    \wbs_dat_int_o[30] ,
+    wbs_dat_i[30],
+    wbs_adr_i[30],
+    \wbs_dat_int_o[29] ,
+    wbs_dat_i[29],
+    wbs_adr_i[29],
+    \wbs_dat_int_o[28] ,
+    wbs_dat_i[28],
+    wbs_adr_i[28],
+    \wbs_dat_int_o[27] ,
+    wbs_dat_i[27],
+    wbs_adr_i[27],
+    \wbs_dat_int_o[26] ,
+    wbs_dat_i[26],
+    wbs_adr_i[26],
+    \wbs_dat_int_o[25] ,
+    wbs_dat_i[25],
+    wbs_adr_i[25],
+    \wbs_dat_int_o[24] ,
+    wbs_dat_i[24],
+    wbs_adr_i[24],
+    \wbs_dat_int_o[23] ,
+    wbs_dat_i[23],
+    wbs_adr_i[23],
+    \wbs_dat_int_o[22] ,
+    wbs_dat_i[22],
+    wbs_adr_i[22],
+    \wbs_dat_int_o[21] ,
+    wbs_dat_i[21],
+    wbs_adr_i[21],
+    \wbs_dat_int_o[20] ,
+    wbs_dat_i[20],
+    wbs_adr_i[20],
+    \wbs_dat_int_o[19] ,
+    wbs_dat_i[19],
+    wbs_adr_i[19],
+    \wbs_dat_int_o[18] ,
+    wbs_dat_i[18],
+    wbs_adr_i[18],
+    \wbs_dat_int_o[17] ,
+    wbs_dat_i[17],
+    wbs_adr_i[17],
+    \wbs_dat_int_o[16] ,
+    wbs_dat_i[16],
+    wbs_adr_i[16],
+    \wbs_dat_int_o[15] ,
+    wbs_dat_i[15],
+    wbs_adr_i[15],
+    \wbs_dat_int_o[14] ,
+    wbs_dat_i[14],
+    wbs_adr_i[14],
+    \wbs_dat_int_o[13] ,
+    wbs_dat_i[13],
+    wbs_adr_i[13],
+    \wbs_dat_int_o[12] ,
+    wbs_dat_i[12],
+    wbs_adr_i[12],
+    \wbs_dat_int_o[11] ,
+    wbs_dat_i[11],
+    wbs_adr_i[11],
+    \wbs_dat_int_o[10] ,
+    wbs_dat_i[10],
+    wbs_adr_i[10],
+    \wbs_dat_int_o[9] ,
+    wbs_dat_i[9],
+    wbs_adr_i[9],
+    \wbs_dat_int_o[8] ,
+    wbs_dat_i[8],
+    wbs_adr_i[8],
+    \wbs_dat_int_o[7] ,
+    wbs_dat_i[7],
+    wbs_adr_i[7],
+    \wbs_dat_int_o[6] ,
+    wbs_dat_i[6],
+    wbs_adr_i[6],
+    \wbs_dat_int_o[5] ,
+    wbs_dat_i[5],
+    wbs_adr_i[5],
+    \wbs_dat_int_o[4] ,
+    wbs_dat_i[4],
+    wbs_adr_i[4],
+    wbs_sel_i[3],
+    \wbs_dat_int_o[3] ,
+    wbs_dat_i[3],
+    wbs_adr_i[3],
+    wbs_sel_i[2],
+    \wbs_dat_int_o[2] ,
+    wbs_dat_i[2],
+    wbs_adr_i[2],
+    wbs_sel_i[1],
+    \wbs_dat_int_o[1] ,
+    wbs_dat_i[1],
+    wbs_adr_i[1],
+    wbs_sel_i[0],
+    \wbs_dat_int_o[0] ,
+    wbs_dat_i[0],
+    wbs_adr_i[0],
+    wbs_we_i,
+    wbs_stb_i,
+    wbs_cyc_i,
+    wbs_ack_int_o,
+    wb_rst_i,
+    wb_clk_i}),
+    .ch_out({\ch_out_south[252] ,
+    la_data_out[127],
+    la_data_out[126],
+    la_data_out[125],
+    la_data_out[124],
+    la_data_out[123],
+    la_data_out[122],
+    la_data_out[121],
+    la_data_out[120],
+    la_data_out[119],
+    la_data_out[118],
+    la_data_out[117],
+    la_data_out[116],
+    la_data_out[115],
+    la_data_out[114],
+    la_data_out[113],
+    la_data_out[112],
+    la_data_out[111],
+    la_data_out[110],
+    la_data_out[109],
+    la_data_out[108],
+    la_data_out[107],
+    la_data_out[106],
+    la_data_out[105],
+    la_data_out[104],
+    la_data_out[103],
+    la_data_out[102],
+    la_data_out[101],
+    la_data_out[100],
+    la_data_out[99],
+    la_data_out[98],
+    la_data_out[97],
+    la_data_out[96],
+    la_data_out[95],
+    la_data_out[94],
+    la_data_out[93],
+    la_data_out[92],
+    la_data_out[91],
+    la_data_out[90],
+    la_data_out[89],
+    la_data_out[88],
+    la_data_out[87],
+    la_data_out[86],
+    la_data_out[85],
+    la_data_out[84],
+    la_data_out[83],
+    la_data_out[82],
+    la_data_out[81],
+    la_data_out[80],
+    la_data_out[79],
+    la_data_out[78],
+    la_data_out[77],
+    la_data_out[76],
+    la_data_out[75],
+    la_data_out[74],
+    la_data_out[73],
+    la_data_out[72],
+    la_data_out[71],
+    la_data_out[70],
+    la_data_out[69],
+    la_data_out[68],
+    la_data_out[67],
+    la_data_out[66],
+    la_data_out[65],
+    la_data_out[64],
+    la_data_out[63],
+    la_data_out[62],
+    la_data_out[61],
+    la_data_out[60],
+    la_data_out[59],
+    la_data_out[58],
+    la_data_out[57],
+    la_data_out[56],
+    la_data_out[55],
+    la_data_out[54],
+    la_data_out[53],
+    la_data_out[52],
+    la_data_out[51],
+    la_data_out[50],
+    la_data_out[49],
+    la_data_out[48],
+    la_data_out[47],
+    la_data_out[46],
+    la_data_out[45],
+    la_data_out[44],
+    la_data_out[43],
+    la_data_out[42],
+    la_data_out[41],
+    la_data_out[40],
+    la_data_out[39],
+    la_data_out[38],
+    la_data_out[37],
+    la_data_out[36],
+    la_data_out[35],
+    la_data_out[34],
+    la_data_out[33],
+    la_data_out[32],
+    la_data_out[31],
+    la_data_out[30],
+    la_data_out[29],
+    la_data_out[28],
+    la_data_out[27],
+    la_data_out[26],
+    la_data_out[25],
+    la_data_out[24],
+    la_data_out[23],
+    la_data_out[22],
+    la_data_out[21],
+    la_data_out[20],
+    la_data_out[19],
+    la_data_out[18],
+    la_data_out[17],
+    \ch_out_south[140] ,
+    la_data_out[16],
+    \ch_out_south[138] ,
+    la_data_out[15],
+    \ch_out_south[136] ,
+    la_data_out[14],
+    \ch_out_south[134] ,
+    la_data_out[13],
+    \ch_out_south[132] ,
+    la_data_out[12],
+    \ch_out_south[130] ,
+    la_data_out[11],
+    \ch_out_south[128] ,
+    la_data_out[10],
+    \ch_out_south[126] ,
+    la_data_out[9],
+    \ch_out_south[124] ,
+    la_data_out[8],
+    \ch_out_south[122] ,
+    la_data_out[7],
+    \ch_out_south[120] ,
+    la_data_out[6],
+    \ch_out_south[118] ,
+    la_data_out[5],
+    \ch_out_south[116] ,
+    la_data_out[4],
+    \ch_out_south[114] ,
+    la_data_out[3],
+    \ch_out_south[112] ,
+    la_data_out[2],
+    \ch_out_south[110] ,
+    la_data_out[1],
+    \ch_out_south[108] ,
+    la_data_out[0],
+    \ch_out_south[106] ,
+    wbs_dat_o[31],
+    \ch_out_south[104] ,
+    \ch_out_south[103] ,
+    wbs_dat_o[30],
+    \ch_out_south[101] ,
+    \ch_out_south[100] ,
+    wbs_dat_o[29],
+    \ch_out_south[98] ,
+    \ch_out_south[97] ,
+    wbs_dat_o[28],
+    \ch_out_south[95] ,
+    \ch_out_south[94] ,
+    wbs_dat_o[27],
+    \ch_out_south[92] ,
+    \ch_out_south[91] ,
+    wbs_dat_o[26],
+    \ch_out_south[89] ,
+    \ch_out_south[88] ,
+    wbs_dat_o[25],
+    \ch_out_south[86] ,
+    \ch_out_south[85] ,
+    wbs_dat_o[24],
+    \ch_out_south[83] ,
+    \ch_out_south[82] ,
+    wbs_dat_o[23],
+    \ch_out_south[80] ,
+    \ch_out_south[79] ,
+    wbs_dat_o[22],
+    \ch_out_south[77] ,
+    \ch_out_south[76] ,
+    wbs_dat_o[21],
+    \ch_out_south[74] ,
+    \ch_out_south[73] ,
+    wbs_dat_o[20],
+    \ch_out_south[71] ,
+    \ch_out_south[70] ,
+    wbs_dat_o[19],
+    \ch_out_south[68] ,
+    \ch_out_south[67] ,
+    wbs_dat_o[18],
+    \ch_out_south[65] ,
+    \ch_out_south[64] ,
+    wbs_dat_o[17],
+    \ch_out_south[62] ,
+    \ch_out_south[61] ,
+    wbs_dat_o[16],
+    \ch_out_south[59] ,
+    \ch_out_south[58] ,
+    wbs_dat_o[15],
+    \ch_out_south[56] ,
+    \ch_out_south[55] ,
+    wbs_dat_o[14],
+    \ch_out_south[53] ,
+    \ch_out_south[52] ,
+    wbs_dat_o[13],
+    \ch_out_south[50] ,
+    \ch_out_south[49] ,
+    wbs_dat_o[12],
+    \ch_out_south[47] ,
+    \ch_out_south[46] ,
+    wbs_dat_o[11],
+    \ch_out_south[44] ,
+    \ch_out_south[43] ,
+    wbs_dat_o[10],
+    \ch_out_south[41] ,
+    \ch_out_south[40] ,
+    wbs_dat_o[9],
+    \ch_out_south[38] ,
+    \ch_out_south[37] ,
+    wbs_dat_o[8],
+    \ch_out_south[35] ,
+    \ch_out_south[34] ,
+    wbs_dat_o[7],
+    \ch_out_south[32] ,
+    \ch_out_south[31] ,
+    wbs_dat_o[6],
+    \ch_out_south[29] ,
+    \ch_out_south[28] ,
+    wbs_dat_o[5],
+    \ch_out_south[26] ,
+    \ch_out_south[25] ,
+    wbs_dat_o[4],
+    \ch_out_south[23] ,
+    \ch_out_south[22] ,
+    \ch_out_south[21] ,
+    wbs_dat_o[3],
+    \ch_out_south[19] ,
+    \ch_out_south[18] ,
+    \ch_out_south[17] ,
+    wbs_dat_o[2],
+    \ch_out_south[15] ,
+    \ch_out_south[14] ,
+    \ch_out_south[13] ,
+    wbs_dat_o[1],
+    \ch_out_south[11] ,
+    \ch_out_south[10] ,
+    \ch_out_south[9] ,
+    wbs_dat_o[0],
+    \ch_out_south[7] ,
+    \ch_out_south[6] ,
+    \ch_out_south[5] ,
+    \ch_out_south[4] ,
+    \ch_out_south[3] ,
+    wbs_ack_o,
+    \ch_out_south[1] ,
+    \ch_out_south[0] }));
+ bus_rep_west u_rp_west (.vccd1(vccd1),
+    .vssd1(vssd1),
+    .ch_in({\buf_out_north[41] ,
+    \buf_out_north[40] ,
+    io_in[37],
+    \buf_out_north[38] ,
+    \buf_out_north[37] ,
+    io_in[36],
+    \buf_out_north[35] ,
+    \buf_out_north[34] ,
+    io_in[35],
+    \buf_out_north[32] ,
+    \buf_out_north[31] ,
+    io_in[34],
+    \buf_out_north[29] ,
+    \buf_out_north[28] ,
+    io_in[33],
+    \buf_out_north[26] ,
+    \buf_out_north[25] ,
+    io_in[32],
+    \buf_out_north[23] ,
+    \buf_out_north[22] ,
+    io_in[31],
+    \buf_out_north[20] ,
+    \buf_out_north[19] ,
+    io_in[30],
+    \buf_out_north[17] ,
+    \buf_out_north[16] ,
+    io_in[29],
+    \buf_out_north[14] ,
+    \buf_out_north[13] ,
+    io_in[28],
+    \buf_out_north[11] ,
+    \buf_out_north[10] ,
+    io_in[27],
+    \buf_out_north[8] ,
+    \buf_out_north[7] ,
+    io_in[26],
+    \buf_out_north[5] ,
+    \buf_out_north[4] ,
+    io_in[25],
+    \buf_out_north[2] ,
+    \buf_out_north[1] ,
+    io_in[24]}),
+    .ch_out({io_oeb[37],
+    io_out[37],
+    \ch_out_west[39] ,
+    io_oeb[36],
+    io_out[36],
+    \ch_out_west[36] ,
+    io_oeb[35],
+    io_out[35],
+    \ch_out_west[33] ,
+    io_oeb[34],
+    io_out[34],
+    \ch_out_west[30] ,
+    io_oeb[33],
+    io_out[33],
+    \ch_out_west[27] ,
+    io_oeb[32],
+    io_out[32],
+    \ch_out_west[24] ,
+    io_oeb[31],
+    io_out[31],
+    \ch_out_west[21] ,
+    io_oeb[30],
+    io_out[30],
+    \ch_out_west[18] ,
+    io_oeb[29],
+    io_out[29],
+    \ch_out_west[15] ,
+    io_oeb[28],
+    io_out[28],
+    \ch_out_west[12] ,
+    io_oeb[27],
+    io_out[27],
+    \ch_out_west[9] ,
+    io_oeb[26],
+    io_out[26],
+    \ch_out_west[6] ,
+    io_oeb[25],
+    io_out[25],
+    \ch_out_west[3] ,
+    io_oeb[24],
+    io_out[24],
+    \ch_out_west[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(\u_riscv_top.sram0_csb0 ),
+    .csb1(\u_riscv_top.sram0_csb1 ),
+    .web0(\u_riscv_top.sram0_web0 ),
+    .clk0(\u_riscv_top.sram0_clk0 ),
+    .clk1(\u_riscv_top.sram0_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }));
+ uart_i2c_usb_spi_top u_uart_i2c_usb_spi (.app_clk(wbd_clk_uart_skew),
+    .i2c_rstn(i2c_rst_n),
+    .i2cm_intr_o(i2cm_intr_o),
+    .reg_ack(wbd_uart_ack_i),
+    .reg_cs(wbd_uart_stb_o),
+    .reg_wr(wbd_uart_we_o),
+    .scl_pad_i(i2cm_clk_i),
+    .scl_pad_o(i2cm_clk_o),
+    .scl_pad_oen_o(i2cm_clk_oen),
+    .sda_pad_i(i2cm_data_i),
+    .sda_pad_o(i2cm_data_o),
+    .sda_padoen_o(i2cm_data_oen),
+    .spi_rstn(sspim_rst_n),
+    .sspim_sck(sspim_sck),
+    .sspim_si(sspim_si),
+    .sspim_so(sspim_so),
+    .usb_clk(usb_clk),
+    .usb_in_dn(usb_dn_i),
+    .usb_in_dp(usb_dp_i),
+    .usb_intr_o(usb_intr_o),
+    .usb_out_dn(usb_dn_o),
+    .usb_out_dp(usb_dp_o),
+    .usb_out_tx_oen(usb_oen),
+    .usb_rstn(usb_rst_n),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_uart_rp),
+    .wbd_clk_uart(wbd_clk_uart_skew),
+    .cfg_cska_uart({\cfg_wcska_uart_rp[3] ,
+    \cfg_wcska_uart_rp[2] ,
+    \cfg_wcska_uart_rp[1] ,
+    \cfg_wcska_uart_rp[0] }),
+    .reg_addr({\wbd_uart_adr_o[8] ,
+    \wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .reg_be({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .reg_rdata({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .reg_wdata({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .sspim_ssn({\sspim_ssn[3] ,
+    \sspim_ssn[2] ,
+    \sspim_ssn[1] ,
+    \sspim_ssn[0] }),
+    .uart_rstn({\uart_rst_n[1] ,
+    \uart_rst_n[0] }),
+    .uart_rxd({\uart_rxd[1] ,
+    \uart_rxd[0] }),
+    .uart_txd({\uart_txd[1] ,
+    \uart_txd[0] }));
+ wb_host u_wb_host (.cfg_strap_pad_ctrl(cfg_strap_pad_ctrl),
+    .cpu_clk(cpu_clk),
+    .e_reset_n(e_reset_n),
+    .int_pll_clock(\pll_clk_out[0] ),
+    .p_reset_n(p_reset_n),
+    .s_reset_n(s_reset_n),
+    .sclk(sspis_sck),
+    .sdin(sspis_si),
+    .sdout(sspis_so),
+    .ssn(sspis_ssn),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .user_clock1(\ch_out_south[0] ),
+    .user_clock2(\ch_out_south[252] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wh(wbd_clk_wh),
+    .wbd_int_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbd_pll_rst_n(wbd_pll_rst_n),
+    .wbm_ack_o(wbs_ack_int_o),
+    .wbm_clk_i(\ch_out_south[0] ),
+    .wbm_cyc_i(\ch_out_south[3] ),
+    .wbm_rst_i(\ch_out_south[1] ),
+    .wbm_stb_i(\ch_out_south[4] ),
+    .wbm_we_i(\ch_out_south[5] ),
+    .wbs_ack_i(wbd_int_ack_o),
+    .wbs_clk_i(wbd_clk_wh),
+    .wbs_clk_out(wbd_clk_int),
+    .wbs_cyc_o(wbd_int_cyc_i),
+    .wbs_err_i(wbd_int_err_o),
+    .wbs_stb_o(wbd_int_stb_i),
+    .wbs_we_o(wbd_int_we_i),
+    .xtal_clk(xtal_clk),
+    .cfg_clk_skew_ctrl1({\cfg_clk_skew_ctrl1[31] ,
+    \cfg_clk_skew_ctrl1[30] ,
+    \cfg_clk_skew_ctrl1[29] ,
+    \cfg_clk_skew_ctrl1[28] ,
+    \cfg_clk_skew_ctrl1[27] ,
+    \cfg_clk_skew_ctrl1[26] ,
+    \cfg_clk_skew_ctrl1[25] ,
+    \cfg_clk_skew_ctrl1[24] ,
+    \cfg_clk_skew_ctrl1[23] ,
+    \cfg_clk_skew_ctrl1[22] ,
+    \cfg_clk_skew_ctrl1[21] ,
+    \cfg_clk_skew_ctrl1[20] ,
+    \cfg_clk_skew_ctrl1[19] ,
+    \cfg_clk_skew_ctrl1[18] ,
+    \cfg_clk_skew_ctrl1[17] ,
+    \cfg_clk_skew_ctrl1[16] ,
+    \cfg_clk_skew_ctrl1[15] ,
+    \cfg_clk_skew_ctrl1[14] ,
+    \cfg_clk_skew_ctrl1[13] ,
+    \cfg_clk_skew_ctrl1[12] ,
+    \cfg_clk_skew_ctrl1[11] ,
+    \cfg_clk_skew_ctrl1[10] ,
+    \cfg_clk_skew_ctrl1[9] ,
+    \cfg_clk_skew_ctrl1[8] ,
+    \cfg_clk_skew_ctrl1[7] ,
+    \cfg_clk_skew_ctrl1[6] ,
+    \cfg_clk_skew_ctrl1[5] ,
+    \cfg_clk_skew_ctrl1[4] ,
+    \cfg_clk_skew_ctrl1[3] ,
+    \cfg_clk_skew_ctrl1[2] ,
+    \cfg_clk_skew_ctrl1[1] ,
+    \cfg_clk_skew_ctrl1[0] }),
+    .cfg_clk_skew_ctrl2({\cfg_clk_skew_ctrl2[31] ,
+    \cfg_clk_skew_ctrl2[30] ,
+    \cfg_clk_skew_ctrl2[29] ,
+    \cfg_clk_skew_ctrl2[28] ,
+    \cfg_clk_skew_ctrl2[27] ,
+    \cfg_clk_skew_ctrl2[26] ,
+    \cfg_clk_skew_ctrl2[25] ,
+    \cfg_clk_skew_ctrl2[24] ,
+    \cfg_clk_skew_ctrl2[23] ,
+    \cfg_clk_skew_ctrl2[22] ,
+    \cfg_clk_skew_ctrl2[21] ,
+    \cfg_clk_skew_ctrl2[20] ,
+    \cfg_clk_skew_ctrl2[19] ,
+    \cfg_clk_skew_ctrl2[18] ,
+    \cfg_clk_skew_ctrl2[17] ,
+    \cfg_clk_skew_ctrl2[16] ,
+    \cfg_clk_skew_ctrl2[15] ,
+    \cfg_clk_skew_ctrl2[14] ,
+    \cfg_clk_skew_ctrl2[13] ,
+    \cfg_clk_skew_ctrl2[12] ,
+    \cfg_clk_skew_ctrl2[11] ,
+    \cfg_clk_skew_ctrl2[10] ,
+    \cfg_clk_skew_ctrl2[9] ,
+    \cfg_clk_skew_ctrl2[8] ,
+    \cfg_clk_skew_ctrl2[7] ,
+    \cfg_clk_skew_ctrl2[6] ,
+    \cfg_clk_skew_ctrl2[5] ,
+    \cfg_clk_skew_ctrl2[4] ,
+    \cfg_clk_skew_ctrl2[3] ,
+    \cfg_clk_skew_ctrl2[2] ,
+    \cfg_clk_skew_ctrl2[1] ,
+    \cfg_clk_skew_ctrl2[0] }),
+    .cfg_cska_wh({\cfg_clk_skew_ctrl1[7] ,
+    \cfg_clk_skew_ctrl1[6] ,
+    \cfg_clk_skew_ctrl1[5] ,
+    \cfg_clk_skew_ctrl1[4] }),
+    .la_data_in({\ch_out_south[140] ,
+    \ch_out_south[138] ,
+    \ch_out_south[136] ,
+    \ch_out_south[134] ,
+    \ch_out_south[132] ,
+    \ch_out_south[130] ,
+    \ch_out_south[128] ,
+    \ch_out_south[126] ,
+    \ch_out_south[124] ,
+    \ch_out_south[122] ,
+    \ch_out_south[120] ,
+    \ch_out_south[118] ,
+    \ch_out_south[116] ,
+    \ch_out_south[114] ,
+    \ch_out_south[112] ,
+    \ch_out_south[110] ,
+    \ch_out_south[108] ,
+    \ch_out_south[106] }),
+    .strap_sticky({\strap_sticky_rp[31] ,
+    \strap_sticky_rp[30] ,
+    \strap_sticky_rp[29] ,
+    \strap_sticky_rp[28] ,
+    \strap_sticky_rp[27] ,
+    \strap_sticky_rp[26] ,
+    \strap_sticky_rp[25] ,
+    \strap_sticky_rp[24] ,
+    \strap_sticky_rp[23] ,
+    \strap_sticky_rp[22] ,
+    \strap_sticky_rp[21] ,
+    \strap_sticky_rp[20] ,
+    \strap_sticky_rp[19] ,
+    \strap_sticky_rp[18] ,
+    \strap_sticky_rp[17] ,
+    \strap_sticky_rp[16] ,
+    \strap_sticky_rp[15] ,
+    \strap_sticky_rp[14] ,
+    \strap_sticky_rp[13] ,
+    \strap_sticky_rp[12] ,
+    \strap_sticky_rp[11] ,
+    \strap_sticky_rp[10] ,
+    \strap_sticky_rp[9] ,
+    \strap_sticky_rp[8] ,
+    \strap_sticky_rp[7] ,
+    \strap_sticky_rp[6] ,
+    \strap_sticky_rp[5] ,
+    \strap_sticky_rp[4] ,
+    \strap_sticky_rp[3] ,
+    \strap_sticky_rp[2] ,
+    \strap_sticky_rp[1] ,
+    \strap_sticky_rp[0] }),
+    .strap_uartm({\strap_uartm_rp[1] ,
+    \strap_uartm_rp[0] }),
+    .system_strap({\system_strap[31] ,
+    \system_strap[30] ,
+    \system_strap[29] ,
+    \system_strap[28] ,
+    \system_strap[27] ,
+    \system_strap[26] ,
+    \system_strap[25] ,
+    \system_strap[24] ,
+    \system_strap[23] ,
+    \system_strap[22] ,
+    \system_strap[21] ,
+    \system_strap[20] ,
+    \system_strap[19] ,
+    \system_strap[18] ,
+    \system_strap[17] ,
+    \system_strap[16] ,
+    \system_strap[15] ,
+    \system_strap[14] ,
+    \system_strap[13] ,
+    \system_strap[12] ,
+    \system_strap[11] ,
+    \system_strap[10] ,
+    \system_strap[9] ,
+    \system_strap[8] ,
+    \system_strap[7] ,
+    \system_strap[6] ,
+    \system_strap[5] ,
+    \system_strap[4] ,
+    \system_strap[3] ,
+    \system_strap[2] ,
+    \system_strap[1] ,
+    \system_strap[0] }),
+    .wbm_adr_i({\ch_out_south[103] ,
+    \ch_out_south[100] ,
+    \ch_out_south[97] ,
+    \ch_out_south[94] ,
+    \ch_out_south[91] ,
+    \ch_out_south[88] ,
+    \ch_out_south[85] ,
+    \ch_out_south[82] ,
+    \ch_out_south[79] ,
+    \ch_out_south[76] ,
+    \ch_out_south[73] ,
+    \ch_out_south[70] ,
+    \ch_out_south[67] ,
+    \ch_out_south[64] ,
+    \ch_out_south[61] ,
+    \ch_out_south[58] ,
+    \ch_out_south[55] ,
+    \ch_out_south[52] ,
+    \ch_out_south[49] ,
+    \ch_out_south[46] ,
+    \ch_out_south[43] ,
+    \ch_out_south[40] ,
+    \ch_out_south[37] ,
+    \ch_out_south[34] ,
+    \ch_out_south[31] ,
+    \ch_out_south[28] ,
+    \ch_out_south[25] ,
+    \ch_out_south[22] ,
+    \ch_out_south[18] ,
+    \ch_out_south[14] ,
+    \ch_out_south[10] ,
+    \ch_out_south[6] }),
+    .wbm_dat_i({\ch_out_south[104] ,
+    \ch_out_south[101] ,
+    \ch_out_south[98] ,
+    \ch_out_south[95] ,
+    \ch_out_south[92] ,
+    \ch_out_south[89] ,
+    \ch_out_south[86] ,
+    \ch_out_south[83] ,
+    \ch_out_south[80] ,
+    \ch_out_south[77] ,
+    \ch_out_south[74] ,
+    \ch_out_south[71] ,
+    \ch_out_south[68] ,
+    \ch_out_south[65] ,
+    \ch_out_south[62] ,
+    \ch_out_south[59] ,
+    \ch_out_south[56] ,
+    \ch_out_south[53] ,
+    \ch_out_south[50] ,
+    \ch_out_south[47] ,
+    \ch_out_south[44] ,
+    \ch_out_south[41] ,
+    \ch_out_south[38] ,
+    \ch_out_south[35] ,
+    \ch_out_south[32] ,
+    \ch_out_south[29] ,
+    \ch_out_south[26] ,
+    \ch_out_south[23] ,
+    \ch_out_south[19] ,
+    \ch_out_south[15] ,
+    \ch_out_south[11] ,
+    \ch_out_south[7] }),
+    .wbm_dat_o({\wbs_dat_int_o[31] ,
+    \wbs_dat_int_o[30] ,
+    \wbs_dat_int_o[29] ,
+    \wbs_dat_int_o[28] ,
+    \wbs_dat_int_o[27] ,
+    \wbs_dat_int_o[26] ,
+    \wbs_dat_int_o[25] ,
+    \wbs_dat_int_o[24] ,
+    \wbs_dat_int_o[23] ,
+    \wbs_dat_int_o[22] ,
+    \wbs_dat_int_o[21] ,
+    \wbs_dat_int_o[20] ,
+    \wbs_dat_int_o[19] ,
+    \wbs_dat_int_o[18] ,
+    \wbs_dat_int_o[17] ,
+    \wbs_dat_int_o[16] ,
+    \wbs_dat_int_o[15] ,
+    \wbs_dat_int_o[14] ,
+    \wbs_dat_int_o[13] ,
+    \wbs_dat_int_o[12] ,
+    \wbs_dat_int_o[11] ,
+    \wbs_dat_int_o[10] ,
+    \wbs_dat_int_o[9] ,
+    \wbs_dat_int_o[8] ,
+    \wbs_dat_int_o[7] ,
+    \wbs_dat_int_o[6] ,
+    \wbs_dat_int_o[5] ,
+    \wbs_dat_int_o[4] ,
+    \wbs_dat_int_o[3] ,
+    \wbs_dat_int_o[2] ,
+    \wbs_dat_int_o[1] ,
+    \wbs_dat_int_o[0] }),
+    .wbm_sel_i({\ch_out_south[21] ,
+    \ch_out_south[17] ,
+    \ch_out_south[13] ,
+    \ch_out_south[9] }),
+    .wbs_adr_o({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .wbs_dat_i({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .wbs_dat_o({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .wbs_sel_o({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }));
+endmodule
diff --git a/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..6549450
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,193568 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1671012960
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< metal1 >>
+rect 309042 700476 309048 700528
+rect 309100 700516 309106 700528
+rect 364978 700516 364984 700528
+rect 309100 700488 364984 700516
+rect 309100 700476 309106 700488
+rect 364978 700476 364984 700488
+rect 365036 700476 365042 700528
+rect 259362 700408 259368 700460
+rect 259420 700448 259426 700460
+rect 300118 700448 300124 700460
+rect 259420 700420 300124 700448
+rect 259420 700408 259426 700420
+rect 300118 700408 300124 700420
+rect 300176 700408 300182 700460
+rect 360102 700408 360108 700460
+rect 360160 700448 360166 700460
+rect 429838 700448 429844 700460
+rect 360160 700420 429844 700448
+rect 360160 700408 360166 700420
+rect 429838 700408 429844 700420
+rect 429896 700408 429902 700460
+rect 208302 700340 208308 700392
+rect 208360 700380 208366 700392
+rect 235166 700380 235172 700392
+rect 208360 700352 235172 700380
+rect 208360 700340 208366 700352
+rect 235166 700340 235172 700352
+rect 235224 700340 235230 700392
+rect 241422 700340 241428 700392
+rect 241480 700380 241486 700392
+rect 283834 700380 283840 700392
+rect 241480 700352 283840 700380
+rect 241480 700340 241486 700352
+rect 283834 700340 283840 700352
+rect 283892 700340 283898 700392
+rect 292482 700340 292488 700392
+rect 292540 700380 292546 700392
+rect 348786 700380 348792 700392
+rect 292540 700352 348792 700380
+rect 292540 700340 292546 700352
+rect 348786 700340 348792 700352
+rect 348844 700340 348850 700392
+rect 411162 700340 411168 700392
+rect 411220 700380 411226 700392
+rect 494790 700380 494796 700392
+rect 411220 700352 494796 700380
+rect 411220 700340 411226 700352
+rect 494790 700340 494796 700352
+rect 494848 700340 494854 700392
+rect 24302 700272 24308 700324
+rect 24360 700312 24366 700324
+rect 35894 700312 35900 700324
+rect 24360 700284 35900 700312
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+rect -6806 -5146 590730 -5114
+rect -6806 -5702 -6774 -5146
+rect -6218 -5702 13066 -5146
+rect 13942 -5702 29066 -5146
+rect 29942 -5702 45066 -5146
+rect 45942 -5702 61066 -5146
+rect 61942 -5702 77066 -5146
+rect 77942 -5702 93066 -5146
+rect 93942 -5702 109066 -5146
+rect 109942 -5702 125066 -5146
+rect 125942 -5702 141066 -5146
+rect 141942 -5702 157066 -5146
+rect 157942 -5702 173066 -5146
+rect 173942 -5702 189066 -5146
+rect 189942 -5702 205066 -5146
+rect 205942 -5702 221066 -5146
+rect 221942 -5702 237066 -5146
+rect 237942 -5702 253066 -5146
+rect 253942 -5702 269066 -5146
+rect 269942 -5702 285066 -5146
+rect 285942 -5702 301066 -5146
+rect 301942 -5702 317066 -5146
+rect 317942 -5702 333066 -5146
+rect 333942 -5702 349066 -5146
+rect 349942 -5702 365066 -5146
+rect 365942 -5702 381066 -5146
+rect 381942 -5702 397066 -5146
+rect 397942 -5702 413066 -5146
+rect 413942 -5702 429066 -5146
+rect 429942 -5702 445066 -5146
+rect 445942 -5702 461066 -5146
+rect 461942 -5702 477066 -5146
+rect 477942 -5702 493066 -5146
+rect 493942 -5702 509066 -5146
+rect 509942 -5702 525066 -5146
+rect 525942 -5702 541066 -5146
+rect 541942 -5702 557066 -5146
+rect 557942 -5702 590142 -5146
+rect 590698 -5702 590730 -5146
+rect -6806 -5734 590730 -5702
+rect -7766 -6106 591690 -6074
+rect -7766 -6662 -7734 -6106
+rect -7178 -6662 591102 -6106
+rect 591658 -6662 591690 -6106
+rect -7766 -6694 591690 -6662
+rect -8726 -7066 592650 -7034
+rect -8726 -7622 -8694 -7066
+rect -8138 -7622 592062 -7066
+rect 592618 -7622 592650 -7066
+rect -8726 -7654 592650 -7622
+use dac_top  u_4x8bit_dac
+timestamp 0
+transform 1 0 370000 0 1 500000
+box -800 2128 48000 110800
+use sky130_sram_2kbyte_1rw1r_32x512_8  u_dcache_2kb $PDK_PATH/libs.ref/sky130_sram_macros/maglef
+timestamp 1666464484
+transform 1 0 30000 0 1 26000
+box 0 0 136620 83308
+use sky130_sram_2kbyte_1rw1r_32x512_8  u_icache_2kb
+timestamp 1666464484
+transform 1 0 190000 0 1 26000
+box 0 0 136620 83308
+use wb_interconnect  u_intercon
+timestamp 0
+transform 1 0 370000 0 1 130000
+box 0 0 60000 357456
+use peri_top  u_peri
+timestamp 0
+transform 1 0 440000 0 1 580000
+box -800 -800 78882 77840
+use pinmux_top  u_pinmux
+timestamp 0
+transform 1 0 450000 0 1 380000
+box -800 -800 104800 180800
+use dg_pll  u_pll
+timestamp 0
+transform 1 0 530000 0 1 580000
+box 0 0 18000 20000
+use qspim_top  u_qspi_master
+timestamp 0
+transform 1 0 450000 0 1 70000
+box 0 0 90000 107760
+use ycr_core_top  u_riscv_top.i_core_top_0
+timestamp 0
+transform 1 0 30000 0 1 280000
+box 1066 144 100000 182832
+use ycr_core_top  u_riscv_top.i_core_top_1
+timestamp 0
+transform -1 0 340000 0 1 280000
+box 1066 144 100000 182832
+use ycr_core_top  u_riscv_top.i_core_top_2
+timestamp 0
+transform 1 0 30000 0 1 480000
+box 1066 144 100000 182832
+use ycr_core_top  u_riscv_top.i_core_top_3
+timestamp 0
+transform -1 0 340000 0 1 480000
+box 1066 144 100000 182832
+use ycr4_iconnect  u_riscv_top.u_connect
+timestamp 0
+transform 1 0 148000 0 1 280000
+box 0 0 80000 377584
+use ycr_intf  u_riscv_top.u_intf
+timestamp 0
+transform 1 0 190000 0 1 130000
+box 0 0 155000 126000
+use bus_rep_east  u_rp_east
+timestamp 0
+transform 0 1 564000 -1 0 694000
+box -1076 -4 685004 10000
+use bus_rep_north  u_rp_north
+timestamp 0
+transform 1 0 20000 0 1 680000
+box -1076 -4 530996 10000
+use bus_rep_south  u_rp_south
+timestamp 0
+transform 1 0 20000 0 1 4000
+box -1076 -4 530996 10000
+use bus_rep_west  u_rp_west
+timestamp 0
+transform 0 1 10000 -1 0 670000
+box -1076 -4 651056 10000
+use sky130_sram_2kbyte_1rw1r_32x512_8  u_tsram0_2kb
+timestamp 1666464484
+transform 1 0 30000 0 1 150000
+box 0 0 136620 83308
+use uart_i2c_usb_spi_top  u_uart_i2c_usb_spi
+timestamp 0
+transform 1 0 450000 0 1 200000
+box 0 0 102894 160000
+use wb_host  u_wb_host
+timestamp 0
+transform 1 0 350000 0 1 20000
+box 106 -800 85800 85800
+<< labels >>
+rlabel metal5 s -8726 658656 592650 659696 4 vccd1
+port 1 nsew
+rlabel metal4 s 587230 -2854 587850 706790 4 vccd2
+port 2 nsew
+rlabel metal5 s -8726 102456 592650 103496 4 vdda1
+port 3 nsew
+rlabel metal4 s 591070 -6694 591690 710630 4 vdda2
+port 4 nsew
+rlabel metal5 s -8726 62056 592650 63096 4 vssa1
+port 5 nsew
+rlabel metal4 s 592030 -7654 592650 711590 4 vssa2
+port 6 nsew
+rlabel metal5 s -8726 666256 592650 667296 4 vssd1
+port 7 nsew
+rlabel metal4 s 588190 -3814 588810 707750 4 vssd2
+port 8 nsew
+rlabel metal2 s 121670 701277 121670 701277 4 analog_io[15]
+port 9 nsew
+rlabel metal2 s 56810 698489 56810 698489 4 analog_io[16]
+port 10 nsew
+rlabel metal3 s 1878 697340 1878 697340 4 analog_io[17]
+port 11 nsew
+rlabel metal4 s 19964 662796 19964 662796 4 analog_io[18]
+port 12 nsew
+rlabel metal3 s 1878 384404 1878 384404 4 analog_io[23]
+port 13 nsew
+rlabel metal1 s 431516 679694 431516 679694 4 buf_out_north\[0\]
+port 14 nsew
+rlabel metal2 s 42826 678334 42826 678334 4 buf_out_north\[10\]
+port 15 nsew
+rlabel metal2 s 42918 677620 42918 677620 4 buf_out_north\[11\]
+port 16 nsew
+rlabel metal1 s 428458 679558 428458 679558 4 buf_out_north\[12\]
+port 17 nsew
+rlabel metal1 s 43320 679626 43320 679626 4 buf_out_north\[13\]
+port 18 nsew
+rlabel metal2 s 43746 677008 43746 677008 4 buf_out_north\[14\]
+port 19 nsew
+rlabel metal1 s 427363 679694 427363 679694 4 buf_out_north\[15\]
+port 20 nsew
+rlabel metal1 s 44367 679694 44367 679694 4 buf_out_north\[16\]
+port 21 nsew
+rlabel metal1 s 44643 679694 44643 679694 4 buf_out_north\[17\]
+port 22 nsew
+rlabel metal2 s 426305 679694 426305 679694 4 buf_out_north\[18\]
+port 23 nsew
+rlabel metal2 s 45126 678300 45126 678300 4 buf_out_north\[19\]
+port 24 nsew
+rlabel metal1 s 40308 679694 40308 679694 4 buf_out_north\[1\]
+port 25 nsew
+rlabel metal1 s 44804 678878 44804 678878 4 buf_out_north\[20\]
+port 26 nsew
+rlabel metal1 s 425808 679694 425808 679694 4 buf_out_north\[21\]
+port 27 nsew
+rlabel metal1 s 19918 643817 19918 643817 4 buf_out_north\[22\]
+port 28 nsew
+rlabel metal1 s 24295 643654 24295 643654 4 buf_out_north\[23\]
+port 29 nsew
+rlabel metal1 s 424756 679694 424756 679694 4 buf_out_north\[24\]
+port 30 nsew
+rlabel metal1 s 24847 643110 24847 643110 4 buf_out_north\[25\]
+port 31 nsew
+rlabel metal1 s 19918 642729 19918 642729 4 buf_out_north\[26\]
+port 32 nsew
+rlabel metal1 s 424442 679490 424442 679490 4 buf_out_north\[27\]
+port 33 nsew
+rlabel metal1 s 23651 642294 23651 642294 4 buf_out_north\[28\]
+port 34 nsew
+rlabel metal1 s 24111 642022 24111 642022 4 buf_out_north\[29\]
+port 35 nsew
+rlabel metal1 s 40490 679626 40490 679626 4 buf_out_north\[2\]
+port 36 nsew
+rlabel metal1 s 423292 679694 423292 679694 4 buf_out_north\[30\]
+port 37 nsew
+rlabel metal1 s 19918 641369 19918 641369 4 buf_out_north\[31\]
+port 38 nsew
+rlabel metal1 s 23513 641206 23513 641206 4 buf_out_north\[32\]
+port 39 nsew
+rlabel metal2 s 422970 623390 422970 623390 4 buf_out_north\[33\]
+port 40 nsew
+rlabel metal1 s 24387 640662 24387 640662 4 buf_out_north\[34\]
+port 41 nsew
+rlabel metal1 s 22087 640390 22087 640390 4 buf_out_north\[35\]
+port 42 nsew
+rlabel metal2 s 450110 577233 450110 577233 4 buf_out_north\[36\]
+port 43 nsew
+rlabel metal1 s 19918 639737 19918 639737 4 buf_out_north\[37\]
+port 44 nsew
+rlabel metal1 s 22041 639574 22041 639574 4 buf_out_north\[38\]
+port 45 nsew
+rlabel metal2 s 450478 560786 450478 560786 4 buf_out_north\[39\]
+port 46 nsew
+rlabel metal1 s 430422 679857 430422 679857 4 buf_out_north\[3\]
+port 47 nsew
+rlabel metal1 s 25353 639030 25353 639030 4 buf_out_north\[40\]
+port 48 nsew
+rlabel metal1 s 22133 638758 22133 638758 4 buf_out_north\[41\]
+port 49 nsew
+rlabel metal1 s 40618 679558 40618 679558 4 buf_out_north\[4\]
+port 50 nsew
+rlabel metal1 s 41538 679694 41538 679694 4 buf_out_north\[5\]
+port 51 nsew
+rlabel metal1 s 430422 678674 430422 678674 4 buf_out_north\[6\]
+port 52 nsew
+rlabel metal2 s 41998 678368 41998 678368 4 buf_out_north\[7\]
+port 53 nsew
+rlabel metal2 s 42274 676940 42274 676940 4 buf_out_north\[8\]
+port 54 nsew
+rlabel metal1 s 428912 679626 428912 679626 4 buf_out_north\[9\]
+port 55 nsew
+rlabel metal2 s 382904 105883 382904 105883 4 cfg_clk_skew_ctrl1\[0\]
+port 56 nsew
+rlabel metal2 s 381800 105883 381800 105883 4 cfg_clk_skew_ctrl1\[10\]
+port 57 nsew
+rlabel metal2 s 381616 105883 381616 105883 4 cfg_clk_skew_ctrl1\[11\]
+port 58 nsew
+rlabel metal2 s 381432 105883 381432 105883 4 cfg_clk_skew_ctrl1\[12\]
+port 59 nsew
+rlabel metal2 s 381248 105883 381248 105883 4 cfg_clk_skew_ctrl1\[13\]
+port 60 nsew
+rlabel metal2 s 381064 105883 381064 105883 4 cfg_clk_skew_ctrl1\[14\]
+port 61 nsew
+rlabel metal2 s 380880 105883 380880 105883 4 cfg_clk_skew_ctrl1\[15\]
+port 62 nsew
+rlabel metal2 s 380696 105883 380696 105883 4 cfg_clk_skew_ctrl1\[16\]
+port 63 nsew
+rlabel metal2 s 380512 105883 380512 105883 4 cfg_clk_skew_ctrl1\[17\]
+port 64 nsew
+rlabel metal2 s 380328 105883 380328 105883 4 cfg_clk_skew_ctrl1\[18\]
+port 65 nsew
+rlabel metal2 s 380144 105883 380144 105883 4 cfg_clk_skew_ctrl1\[19\]
+port 66 nsew
+rlabel metal2 s 382720 105883 382720 105883 4 cfg_clk_skew_ctrl1\[1\]
+port 67 nsew
+rlabel metal2 s 379960 105883 379960 105883 4 cfg_clk_skew_ctrl1\[20\]
+port 68 nsew
+rlabel metal2 s 379776 105883 379776 105883 4 cfg_clk_skew_ctrl1\[21\]
+port 69 nsew
+rlabel metal2 s 379592 105866 379592 105866 4 cfg_clk_skew_ctrl1\[22\]
+port 70 nsew
+rlabel metal2 s 379408 105883 379408 105883 4 cfg_clk_skew_ctrl1\[23\]
+port 71 nsew
+rlabel metal2 s 379224 105883 379224 105883 4 cfg_clk_skew_ctrl1\[24\]
+port 72 nsew
+rlabel metal2 s 379040 105883 379040 105883 4 cfg_clk_skew_ctrl1\[25\]
+port 73 nsew
+rlabel metal2 s 378856 105883 378856 105883 4 cfg_clk_skew_ctrl1\[26\]
+port 74 nsew
+rlabel metal2 s 378672 105883 378672 105883 4 cfg_clk_skew_ctrl1\[27\]
+port 75 nsew
+rlabel metal2 s 415656 105883 415656 105883 4 cfg_clk_skew_ctrl1\[28\]
+port 76 nsew
+rlabel metal2 s 415472 105883 415472 105883 4 cfg_clk_skew_ctrl1\[29\]
+port 77 nsew
+rlabel metal2 s 382536 105866 382536 105866 4 cfg_clk_skew_ctrl1\[2\]
+port 78 nsew
+rlabel metal2 s 415288 105883 415288 105883 4 cfg_clk_skew_ctrl1\[30\]
+port 79 nsew
+rlabel metal2 s 415104 105883 415104 105883 4 cfg_clk_skew_ctrl1\[31\]
+port 80 nsew
+rlabel metal2 s 382352 105883 382352 105883 4 cfg_clk_skew_ctrl1\[3\]
+port 81 nsew
+rlabel metal2 s 351256 105815 351256 105815 4 cfg_clk_skew_ctrl1\[4\]
+port 82 nsew
+rlabel metal2 s 350888 105815 350888 105815 4 cfg_clk_skew_ctrl1\[5\]
+port 83 nsew
+rlabel metal2 s 350520 105815 350520 105815 4 cfg_clk_skew_ctrl1\[6\]
+port 84 nsew
+rlabel metal2 s 350152 105815 350152 105815 4 cfg_clk_skew_ctrl1\[7\]
+port 85 nsew
+rlabel metal2 s 382168 105883 382168 105883 4 cfg_clk_skew_ctrl1\[8\]
+port 86 nsew
+rlabel metal2 s 381984 105883 381984 105883 4 cfg_clk_skew_ctrl1\[9\]
+port 87 nsew
+rlabel metal2 s 378488 105883 378488 105883 4 cfg_clk_skew_ctrl2\[0\]
+port 88 nsew
+rlabel metal2 s 376648 105883 376648 105883 4 cfg_clk_skew_ctrl2\[10\]
+port 89 nsew
+rlabel metal2 s 376464 105883 376464 105883 4 cfg_clk_skew_ctrl2\[11\]
+port 90 nsew
+rlabel metal2 s 376280 105883 376280 105883 4 cfg_clk_skew_ctrl2\[12\]
+port 91 nsew
+rlabel metal2 s 376096 105883 376096 105883 4 cfg_clk_skew_ctrl2\[13\]
+port 92 nsew
+rlabel metal2 s 375912 105883 375912 105883 4 cfg_clk_skew_ctrl2\[14\]
+port 93 nsew
+rlabel metal2 s 375728 105866 375728 105866 4 cfg_clk_skew_ctrl2\[15\]
+port 94 nsew
+rlabel metal2 s 375544 105883 375544 105883 4 cfg_clk_skew_ctrl2\[16\]
+port 95 nsew
+rlabel metal2 s 375360 105883 375360 105883 4 cfg_clk_skew_ctrl2\[17\]
+port 96 nsew
+rlabel metal2 s 375176 105883 375176 105883 4 cfg_clk_skew_ctrl2\[18\]
+port 97 nsew
+rlabel metal2 s 374992 105883 374992 105883 4 cfg_clk_skew_ctrl2\[19\]
+port 98 nsew
+rlabel metal2 s 378304 105883 378304 105883 4 cfg_clk_skew_ctrl2\[1\]
+port 99 nsew
+rlabel metal2 s 374808 105883 374808 105883 4 cfg_clk_skew_ctrl2\[20\]
+port 100 nsew
+rlabel metal2 s 374624 105883 374624 105883 4 cfg_clk_skew_ctrl2\[21\]
+port 101 nsew
+rlabel metal2 s 374440 105883 374440 105883 4 cfg_clk_skew_ctrl2\[22\]
+port 102 nsew
+rlabel metal2 s 374256 105883 374256 105883 4 cfg_clk_skew_ctrl2\[23\]
+port 103 nsew
+rlabel metal2 s 417128 105866 417128 105866 4 cfg_clk_skew_ctrl2\[24\]
+port 104 nsew
+rlabel metal2 s 416944 105883 416944 105883 4 cfg_clk_skew_ctrl2\[25\]
+port 105 nsew
+rlabel metal2 s 416760 105883 416760 105883 4 cfg_clk_skew_ctrl2\[26\]
+port 106 nsew
+rlabel metal2 s 416576 105883 416576 105883 4 cfg_clk_skew_ctrl2\[27\]
+port 107 nsew
+rlabel metal2 s 416392 105883 416392 105883 4 cfg_clk_skew_ctrl2\[28\]
+port 108 nsew
+rlabel metal2 s 416208 105883 416208 105883 4 cfg_clk_skew_ctrl2\[29\]
+port 109 nsew
+rlabel metal2 s 378120 105883 378120 105883 4 cfg_clk_skew_ctrl2\[2\]
+port 110 nsew
+rlabel metal2 s 416024 105883 416024 105883 4 cfg_clk_skew_ctrl2\[30\]
+port 111 nsew
+rlabel metal2 s 415840 105866 415840 105866 4 cfg_clk_skew_ctrl2\[31\]
+port 112 nsew
+rlabel metal2 s 377936 105883 377936 105883 4 cfg_clk_skew_ctrl2\[3\]
+port 113 nsew
+rlabel metal2 s 377752 105883 377752 105883 4 cfg_clk_skew_ctrl2\[4\]
+port 114 nsew
+rlabel metal2 s 377568 105883 377568 105883 4 cfg_clk_skew_ctrl2\[5\]
+port 115 nsew
+rlabel metal2 s 377384 105883 377384 105883 4 cfg_clk_skew_ctrl2\[6\]
+port 116 nsew
+rlabel metal2 s 377200 105866 377200 105866 4 cfg_clk_skew_ctrl2\[7\]
+port 117 nsew
+rlabel metal2 s 377016 105883 377016 105883 4 cfg_clk_skew_ctrl2\[8\]
+port 118 nsew
+rlabel metal2 s 376832 105883 376832 105883 4 cfg_clk_skew_ctrl2\[9\]
+port 119 nsew
+rlabel metal2 s 427294 601698 427294 601698 4 cfg_dac0_mux_sel\[0\]
+port 120 nsew
+rlabel metal2 s 376510 611344 376510 611344 4 cfg_dac0_mux_sel\[1\]
+port 121 nsew
+rlabel metal2 s 427386 600508 427386 600508 4 cfg_dac0_mux_sel\[2\]
+port 122 nsew
+rlabel metal2 s 377430 610283 377430 610283 4 cfg_dac0_mux_sel\[3\]
+port 123 nsew
+rlabel metal2 s 377614 611208 377614 611208 4 cfg_dac0_mux_sel\[4\]
+port 124 nsew
+rlabel metal2 s 378074 610181 378074 610181 4 cfg_dac0_mux_sel\[5\]
+port 125 nsew
+rlabel metal2 s 423246 600406 423246 600406 4 cfg_dac0_mux_sel\[6\]
+port 126 nsew
+rlabel metal2 s 424534 599624 424534 599624 4 cfg_dac0_mux_sel\[7\]
+port 127 nsew
+rlabel metal2 s 386078 611106 386078 611106 4 cfg_dac1_mux_sel\[0\]
+port 128 nsew
+rlabel metal2 s 386630 610317 386630 610317 4 cfg_dac1_mux_sel\[1\]
+port 129 nsew
+rlabel metal2 s 386814 611140 386814 611140 4 cfg_dac1_mux_sel\[2\]
+port 130 nsew
+rlabel metal2 s 387366 610045 387366 610045 4 cfg_dac1_mux_sel\[3\]
+port 131 nsew
+rlabel metal2 s 387550 611888 387550 611888 4 cfg_dac1_mux_sel\[4\]
+port 132 nsew
+rlabel metal2 s 387918 611276 387918 611276 4 cfg_dac1_mux_sel\[5\]
+port 133 nsew
+rlabel metal2 s 388286 611854 388286 611854 4 cfg_dac1_mux_sel\[6\]
+port 134 nsew
+rlabel metal2 s 388654 612024 388654 612024 4 cfg_dac1_mux_sel\[7\]
+port 135 nsew
+rlabel metal2 s 424442 600406 424442 600406 4 cfg_dac2_mux_sel\[0\]
+port 136 nsew
+rlabel metal2 s 425730 599760 425730 599760 4 cfg_dac2_mux_sel\[1\]
+port 137 nsew
+rlabel metal2 s 431434 599624 431434 599624 4 cfg_dac2_mux_sel\[2\]
+port 138 nsew
+rlabel metal1 s 434700 586262 434700 586262 4 cfg_dac2_mux_sel\[3\]
+port 139 nsew
+rlabel metal2 s 436310 585803 436310 585803 4 cfg_dac2_mux_sel\[4\]
+port 140 nsew
+rlabel metal3 s 437422 585140 437422 585140 4 cfg_dac2_mux_sel\[5\]
+port 141 nsew
+rlabel metal3 s 438296 584868 438296 584868 4 cfg_dac2_mux_sel\[6\]
+port 142 nsew
+rlabel metal2 s 424350 598468 424350 598468 4 cfg_dac2_mux_sel\[7\]
+port 143 nsew
+rlabel metal2 s 406318 610555 406318 610555 4 cfg_dac3_mux_sel\[0\]
+port 144 nsew
+rlabel metal2 s 406502 611752 406502 611752 4 cfg_dac3_mux_sel\[1\]
+port 145 nsew
+rlabel metal2 s 406870 611038 406870 611038 4 cfg_dac3_mux_sel\[2\]
+port 146 nsew
+rlabel metal2 s 407422 609467 407422 609467 4 cfg_dac3_mux_sel\[3\]
+port 147 nsew
+rlabel metal1 s 407790 609008 407790 609008 4 cfg_dac3_mux_sel\[4\]
+port 148 nsew
+rlabel metal2 s 407974 611786 407974 611786 4 cfg_dac3_mux_sel\[5\]
+port 149 nsew
+rlabel metal2 s 408434 610453 408434 610453 4 cfg_dac3_mux_sel\[6\]
+port 150 nsew
+rlabel metal2 s 408894 610419 408894 610419 4 cfg_dac3_mux_sel\[7\]
+port 151 nsew
+rlabel metal1 s 526332 583814 526332 583814 4 cfg_dc_trim\[0\]
+port 152 nsew
+rlabel metal1 s 513958 563210 513958 563210 4 cfg_dc_trim\[10\]
+port 153 nsew
+rlabel metal2 s 513912 563244 513912 563244 4 cfg_dc_trim\[11\]
+port 154 nsew
+rlabel metal1 s 513636 563142 513636 563142 4 cfg_dc_trim\[12\]
+port 155 nsew
+rlabel metal2 s 526746 589016 526746 589016 4 cfg_dc_trim\[13\]
+port 156 nsew
+rlabel metal2 s 525182 583610 525182 583610 4 cfg_dc_trim\[14\]
+port 157 nsew
+rlabel metal2 s 523986 587078 523986 587078 4 cfg_dc_trim\[15\]
+port 158 nsew
+rlabel metal2 s 522514 586432 522514 586432 4 cfg_dc_trim\[16\]
+port 159 nsew
+rlabel metal2 s 521134 588370 521134 588370 4 cfg_dc_trim\[17\]
+port 160 nsew
+rlabel metal2 s 525274 585548 525274 585548 4 cfg_dc_trim\[18\]
+port 161 nsew
+rlabel metal1 s 524216 599046 524216 599046 4 cfg_dc_trim\[19\]
+port 162 nsew
+rlabel metal1 s 523710 583882 523710 583882 4 cfg_dc_trim\[1\]
+port 163 nsew
+rlabel metal3 s 548174 581604 548174 581604 4 cfg_dc_trim\[20\]
+port 164 nsew
+rlabel metal3 s 548036 581332 548036 581332 4 cfg_dc_trim\[21\]
+port 165 nsew
+rlabel metal3 s 548082 581060 548082 581060 4 cfg_dc_trim\[22\]
+port 166 nsew
+rlabel metal3 s 547055 578068 547055 578068 4 cfg_dc_trim\[23\]
+port 167 nsew
+rlabel metal4 s 547285 578204 547285 578204 4 cfg_dc_trim\[24\]
+port 168 nsew
+rlabel metal2 s 546526 578289 546526 578289 4 cfg_dc_trim\[25\]
+port 169 nsew
+rlabel metal2 s 521502 580312 521502 580312 4 cfg_dc_trim\[2\]
+port 170 nsew
+rlabel metal2 s 526838 575025 526838 575025 4 cfg_dc_trim\[3\]
+port 171 nsew
+rlabel metal1 s 524998 582454 524998 582454 4 cfg_dc_trim\[4\]
+port 172 nsew
+rlabel metal1 s 524906 582386 524906 582386 4 cfg_dc_trim\[5\]
+port 173 nsew
+rlabel metal2 s 528310 578765 528310 578765 4 cfg_dc_trim\[6\]
+port 174 nsew
+rlabel metal2 s 524078 589152 524078 589152 4 cfg_dc_trim\[7\]
+port 175 nsew
+rlabel metal1 s 522514 563074 522514 563074 4 cfg_dc_trim\[8\]
+port 176 nsew
+rlabel metal2 s 519938 581264 519938 581264 4 cfg_dc_trim\[9\]
+port 177 nsew
+rlabel metal2 s 528126 577881 528126 577881 4 cfg_dco_mode
+port 178 nsew
+rlabel metal2 s 526930 575025 526930 575025 4 cfg_pll_enb
+port 179 nsew
+rlabel metal1 s 524308 581094 524308 581094 4 cfg_pll_fed_div\[0\]
+port 180 nsew
+rlabel metal2 s 527298 580295 527298 580295 4 cfg_pll_fed_div\[1\]
+port 181 nsew
+rlabel metal1 s 523664 581162 523664 581162 4 cfg_pll_fed_div\[2\]
+port 182 nsew
+rlabel metal1 s 525688 581026 525688 581026 4 cfg_pll_fed_div\[3\]
+port 183 nsew
+rlabel metal1 s 525826 579734 525826 579734 4 cfg_pll_fed_div\[4\]
+port 184 nsew
+rlabel metal2 s 368138 484738 368138 484738 4 cfg_riscv_ctrl\[0\]
+port 185 nsew
+rlabel metal2 s 365470 481950 365470 481950 4 cfg_riscv_ctrl\[10\]
+port 186 nsew
+rlabel metal2 s 249734 275621 249734 275621 4 cfg_riscv_ctrl\[11\]
+port 187 nsew
+rlabel metal2 s 346702 254677 346702 254677 4 cfg_riscv_ctrl\[1\]
+port 188 nsew
+rlabel metal1 s 348450 462026 348450 462026 4 cfg_riscv_ctrl\[2\]
+port 189 nsew
+rlabel metal2 s 365470 485928 365470 485928 4 cfg_riscv_ctrl\[3\]
+port 190 nsew
+rlabel metal2 s 347622 253487 347622 253487 4 cfg_riscv_ctrl\[4\]
+port 191 nsew
+rlabel metal3 s 347714 253589 347714 253589 4 cfg_riscv_ctrl\[5\]
+port 192 nsew
+rlabel metal3 s 347714 253861 347714 253861 4 cfg_riscv_ctrl\[6\]
+port 193 nsew
+rlabel metal2 s 365654 486302 365654 486302 4 cfg_riscv_ctrl\[8\]
+port 194 nsew
+rlabel metal2 s 365562 486404 365562 486404 4 cfg_riscv_ctrl\[9\]
+port 195 nsew
+rlabel metal2 s 429456 105866 429456 105866 4 cfg_strap_pad_ctrl
+port 196 nsew
+rlabel metal2 s 447258 398463 447258 398463 4 cfg_strap_pad_ctrl_rp
+port 197 nsew
+rlabel metal2 s 433274 481491 433274 481491 4 cfg_wcska_peri_rp\[0\]
+port 198 nsew
+rlabel metal3 s 431472 480692 431472 480692 4 cfg_wcska_peri_rp\[1\]
+port 199 nsew
+rlabel metal2 s 432262 481287 432262 481287 4 cfg_wcska_peri_rp\[2\]
+port 200 nsew
+rlabel metal3 s 431380 481236 431380 481236 4 cfg_wcska_peri_rp\[3\]
+port 201 nsew
+rlabel metal2 s 447166 430015 447166 430015 4 cfg_wcska_pinmux_rp\[0\]
+port 202 nsew
+rlabel metal2 s 447258 429811 447258 429811 4 cfg_wcska_pinmux_rp\[1\]
+port 203 nsew
+rlabel metal2 s 447166 429641 447166 429641 4 cfg_wcska_pinmux_rp\[2\]
+port 204 nsew
+rlabel metal2 s 447442 428791 447442 428791 4 cfg_wcska_pinmux_rp\[3\]
+port 205 nsew
+rlabel metal2 s 447166 130713 447166 130713 4 cfg_wcska_qspi_co_rp\[0\]
+port 206 nsew
+rlabel metal3 s 430138 130764 430138 130764 4 cfg_wcska_qspi_co_rp\[1\]
+port 207 nsew
+rlabel metal3 s 430184 130492 430184 130492 4 cfg_wcska_qspi_co_rp\[2\]
+port 208 nsew
+rlabel metal3 s 429916 129933 429916 129933 4 cfg_wcska_qspi_co_rp\[3\]
+port 209 nsew
+rlabel metal2 s 447258 132039 447258 132039 4 cfg_wcska_qspi_rp\[0\]
+port 210 nsew
+rlabel metal3 s 447166 131869 447166 131869 4 cfg_wcska_qspi_rp\[1\]
+port 211 nsew
+rlabel metal2 s 447166 131665 447166 131665 4 cfg_wcska_qspi_rp\[2\]
+port 212 nsew
+rlabel metal2 s 447442 131665 447442 131665 4 cfg_wcska_qspi_rp\[3\]
+port 213 nsew
+rlabel metal2 s 447258 261307 447258 261307 4 cfg_wcska_uart_rp\[0\]
+port 214 nsew
+rlabel metal2 s 447350 260457 447350 260457 4 cfg_wcska_uart_rp\[1\]
+port 215 nsew
+rlabel metal2 s 447258 260389 447258 260389 4 cfg_wcska_uart_rp\[2\]
+port 216 nsew
+rlabel metal3 s 447166 260219 447166 260219 4 cfg_wcska_uart_rp\[3\]
+port 217 nsew
+rlabel metal3 s 556086 458116 556086 458116 4 ch_out_east\[11\]
+port 218 nsew
+rlabel metal3 s 555764 456484 555764 456484 4 ch_out_east\[14\]
+port 219 nsew
+rlabel metal3 s 555442 454852 555442 454852 4 ch_out_east\[17\]
+port 220 nsew
+rlabel metal3 s 555534 453220 555534 453220 4 ch_out_east\[20\]
+port 221 nsew
+rlabel metal1 s 564098 456409 564098 456409 4 ch_out_east\[23\]
+port 222 nsew
+rlabel metal1 s 564098 455185 564098 455185 4 ch_out_east\[26\]
+port 223 nsew
+rlabel metal3 s 556086 448324 556086 448324 4 ch_out_east\[29\]
+port 224 nsew
+rlabel metal3 s 555672 463012 555672 463012 4 ch_out_east\[2\]
+port 225 nsew
+rlabel metal1 s 564098 452771 564098 452771 4 ch_out_east\[32\]
+port 226 nsew
+rlabel metal3 s 555488 445060 555488 445060 4 ch_out_east\[35\]
+port 227 nsew
+rlabel metal3 s 555442 443428 555442 443428 4 ch_out_east\[38\]
+port 228 nsew
+rlabel metal3 s 555442 441796 555442 441796 4 ch_out_east\[41\]
+port 229 nsew
+rlabel metal3 s 555442 440164 555442 440164 4 ch_out_east\[44\]
+port 230 nsew
+rlabel metal3 s 555580 461380 555580 461380 4 ch_out_east\[5\]
+port 231 nsew
+rlabel metal3 s 555994 459748 555994 459748 4 ch_out_east\[8\]
+port 232 nsew
+rlabel metal2 s 523710 621248 523710 621248 4 ch_out_north\[11\]
+port 233 nsew
+rlabel metal2 s 519570 621350 519570 621350 4 ch_out_north\[14\]
+port 234 nsew
+rlabel metal2 s 518926 679286 518926 679286 4 ch_out_north\[17\]
+port 235 nsew
+rlabel metal1 s 525366 678878 525366 678878 4 ch_out_north\[20\]
+port 236 nsew
+rlabel metal1 s 525770 678946 525770 678946 4 ch_out_north\[23\]
+port 237 nsew
+rlabel metal1 s 528414 679694 528414 679694 4 ch_out_north\[26\]
+port 238 nsew
+rlabel metal2 s 502182 678300 502182 678300 4 ch_out_north\[2\]
+port 239 nsew
+rlabel metal2 s 505494 679014 505494 679014 4 ch_out_north\[5\]
+port 240 nsew
+rlabel metal2 s 508990 679082 508990 679082 4 ch_out_north\[8\]
+port 241 nsew
+rlabel metal2 s 350336 19169 350336 19169 4 ch_out_south\[0\]
+port 242 nsew
+rlabel metal2 s 368897 18972 368897 18972 4 ch_out_south\[100\]
+port 243 nsew
+rlabel metal3 s 368851 17884 368851 17884 4 ch_out_south\[101\]
+port 244 nsew
+rlabel metal3 s 368943 17340 368943 17340 4 ch_out_south\[103\]
+port 245 nsew
+rlabel metal2 s 369610 18020 369610 18020 4 ch_out_south\[104\]
+port 246 nsew
+rlabel metal1 s 380098 14049 380098 14049 4 ch_out_south\[106\]
+port 247 nsew
+rlabel metal1 s 381182 14049 381182 14049 4 ch_out_south\[108\]
+port 248 nsew
+rlabel metal2 s 352337 18972 352337 18972 4 ch_out_south\[10\]
+port 249 nsew
+rlabel metal1 s 382260 14015 382260 14015 4 ch_out_south\[110\]
+port 250 nsew
+rlabel metal1 s 383364 14015 383364 14015 4 ch_out_south\[112\]
+port 251 nsew
+rlabel metal1 s 384446 14083 384446 14083 4 ch_out_south\[114\]
+port 252 nsew
+rlabel metal1 s 385526 14083 385526 14083 4 ch_out_south\[116\]
+port 253 nsew
+rlabel metal1 s 386630 14015 386630 14015 4 ch_out_south\[118\]
+port 254 nsew
+rlabel metal2 s 352521 18972 352521 18972 4 ch_out_south\[11\]
+port 255 nsew
+rlabel metal1 s 387710 14049 387710 14049 4 ch_out_south\[120\]
+port 256 nsew
+rlabel metal1 s 388792 14049 388792 14049 4 ch_out_south\[122\]
+port 257 nsew
+rlabel metal2 s 401718 18105 401718 18105 4 ch_out_south\[124\]
+port 258 nsew
+rlabel metal2 s 401902 18309 401902 18309 4 ch_out_south\[126\]
+port 259 nsew
+rlabel metal2 s 402086 18377 402086 18377 4 ch_out_south\[128\]
+port 260 nsew
+rlabel metal2 s 402270 18411 402270 18411 4 ch_out_south\[130\]
+port 261 nsew
+rlabel metal2 s 400614 16218 400614 16218 4 ch_out_south\[132\]
+port 262 nsew
+rlabel metal2 s 402638 17221 402638 17221 4 ch_out_south\[134\]
+port 263 nsew
+rlabel metal2 s 400154 15946 400154 15946 4 ch_out_south\[136\]
+port 264 nsew
+rlabel metal2 s 402914 15997 402914 15997 4 ch_out_south\[138\]
+port 265 nsew
+rlabel metal2 s 352866 18564 352866 18564 4 ch_out_south\[13\]
+port 266 nsew
+rlabel metal2 s 401718 16014 401718 16014 4 ch_out_south\[140\]
+port 267 nsew
+rlabel metal2 s 352590 2431 352590 2431 4 ch_out_south\[14\]
+port 268 nsew
+rlabel metal2 s 353234 18632 353234 18632 4 ch_out_south\[15\]
+port 269 nsew
+rlabel metal2 s 353625 18972 353625 18972 4 ch_out_south\[17\]
+port 270 nsew
+rlabel metal2 s 353786 17884 353786 17884 4 ch_out_south\[18\]
+port 271 nsew
+rlabel metal3 s 231081 3876 231081 3876 4 ch_out_south\[19\]
+port 272 nsew
+rlabel metal2 s 350658 18904 350658 18904 4 ch_out_south\[1\]
+port 273 nsew
+rlabel metal4 s 334259 3060 334259 3060 4 ch_out_south\[21\]
+port 274 nsew
+rlabel metal2 s 354545 18972 354545 18972 4 ch_out_south\[22\]
+port 275 nsew
+rlabel metal1 s 232602 14151 232602 14151 4 ch_out_south\[23\]
+port 276 nsew
+rlabel metal2 s 350122 19244 350122 19244 4 ch_out_south\[252\]
+port 277 nsew
+rlabel metal1 s 233680 14185 233680 14185 4 ch_out_south\[25\]
+port 278 nsew
+rlabel metal1 s 234232 14151 234232 14151 4 ch_out_south\[26\]
+port 279 nsew
+rlabel metal4 s 235267 14076 235267 14076 4 ch_out_south\[28\]
+port 280 nsew
+rlabel metal2 s 348174 19278 348174 19278 4 ch_out_south\[29\]
+port 281 nsew
+rlabel metal1 s 236946 14151 236946 14151 4 ch_out_south\[31\]
+port 282 nsew
+rlabel metal2 s 348910 19414 348910 19414 4 ch_out_south\[32\]
+port 283 nsew
+rlabel metal1 s 238586 14117 238586 14117 4 ch_out_south\[34\]
+port 284 nsew
+rlabel metal2 s 356914 18479 356914 18479 4 ch_out_south\[35\]
+port 285 nsew
+rlabel metal3 s 288328 1836 288328 1836 4 ch_out_south\[37\]
+port 286 nsew
+rlabel metal2 s 353878 18785 353878 18785 4 ch_out_south\[38\]
+port 287 nsew
+rlabel metal2 s 351049 18972 351049 18972 4 ch_out_south\[3\]
+port 288 nsew
+rlabel metal2 s 357857 18972 357857 18972 4 ch_out_south\[40\]
+port 289 nsew
+rlabel metal2 s 358018 18513 358018 18513 4 ch_out_south\[41\]
+port 290 nsew
+rlabel metal1 s 358432 19278 358432 19278 4 ch_out_south\[43\]
+port 291 nsew
+rlabel metal2 s 358593 18972 358593 18972 4 ch_out_south\[44\]
+port 292 nsew
+rlabel metal1 s 358984 19312 358984 19312 4 ch_out_south\[46\]
+port 293 nsew
+rlabel metal2 s 359122 18547 359122 18547 4 ch_out_south\[47\]
+port 294 nsew
+rlabel metal2 s 359513 18972 359513 18972 4 ch_out_south\[49\]
+port 295 nsew
+rlabel metal2 s 350658 1887 350658 1887 4 ch_out_south\[4\]
+port 296 nsew
+rlabel metal1 s 359720 19380 359720 19380 4 ch_out_south\[50\]
+port 297 nsew
+rlabel metal2 s 360042 18615 360042 18615 4 ch_out_south\[52\]
+port 298 nsew
+rlabel metal1 s 248922 14015 248922 14015 4 ch_out_south\[53\]
+port 299 nsew
+rlabel metal1 s 250010 14151 250010 14151 4 ch_out_south\[55\]
+port 300 nsew
+rlabel metal1 s 250562 14151 250562 14151 4 ch_out_south\[56\]
+port 301 nsew
+rlabel metal1 s 251642 14151 251642 14151 4 ch_out_south\[58\]
+port 302 nsew
+rlabel metal1 s 252172 14151 252172 14151 4 ch_out_south\[59\]
+port 303 nsew
+rlabel metal3 s 351164 19244 351164 19244 4 ch_out_south\[5\]
+port 304 nsew
+rlabel metal1 s 253276 14185 253276 14185 4 ch_out_south\[61\]
+port 305 nsew
+rlabel metal2 s 349830 19482 349830 19482 4 ch_out_south\[62\]
+port 306 nsew
+rlabel metal2 s 362319 18972 362319 18972 4 ch_out_south\[64\]
+port 307 nsew
+rlabel metal2 s 362480 19948 362480 19948 4 ch_out_south\[65\]
+port 308 nsew
+rlabel metal2 s 346334 20434 346334 20434 4 ch_out_south\[67\]
+port 309 nsew
+rlabel metal2 s 362986 18173 362986 18173 4 ch_out_south\[68\]
+port 310 nsew
+rlabel metal2 s 351578 18088 351578 18088 4 ch_out_south\[6\]
+port 311 nsew
+rlabel metal2 s 350474 17510 350474 17510 4 ch_out_south\[70\]
+port 312 nsew
+rlabel metal2 s 349462 19346 349462 19346 4 ch_out_south\[71\]
+port 313 nsew
+rlabel metal2 s 363906 18309 363906 18309 4 ch_out_south\[73\]
+port 314 nsew
+rlabel metal2 s 364090 18309 364090 18309 4 ch_out_south\[74\]
+port 315 nsew
+rlabel metal2 s 364458 18207 364458 18207 4 ch_out_south\[76\]
+port 316 nsew
+rlabel metal2 s 364665 18972 364665 18972 4 ch_out_south\[77\]
+port 317 nsew
+rlabel metal2 s 365033 18972 365033 18972 4 ch_out_south\[79\]
+port 318 nsew
+rlabel metal2 s 351762 18139 351762 18139 4 ch_out_south\[7\]
+port 319 nsew
+rlabel metal2 s 365194 18275 365194 18275 4 ch_out_south\[80\]
+port 320 nsew
+rlabel metal2 s 365562 18377 365562 18377 4 ch_out_south\[82\]
+port 321 nsew
+rlabel metal2 s 365746 18343 365746 18343 4 ch_out_south\[83\]
+port 322 nsew
+rlabel metal2 s 366137 18972 366137 18972 4 ch_out_south\[85\]
+port 323 nsew
+rlabel metal2 s 366321 18972 366321 18972 4 ch_out_south\[86\]
+port 324 nsew
+rlabel metal4 s 366643 17884 366643 17884 4 ch_out_south\[88\]
+port 325 nsew
+rlabel metal2 s 366850 17969 366850 17969 4 ch_out_south\[89\]
+port 326 nsew
+rlabel metal2 s 367218 18071 367218 18071 4 ch_out_south\[91\]
+port 327 nsew
+rlabel metal2 s 367402 18003 367402 18003 4 ch_out_south\[92\]
+port 328 nsew
+rlabel metal3 s 367655 17884 367655 17884 4 ch_out_south\[94\]
+port 329 nsew
+rlabel metal3 s 367655 17340 367655 17340 4 ch_out_south\[95\]
+port 330 nsew
+rlabel metal3 s 367747 17204 367747 17204 4 ch_out_south\[97\]
+port 331 nsew
+rlabel metal2 s 368506 18037 368506 18037 4 ch_out_south\[98\]
+port 332 nsew
+rlabel metal2 s 352130 18156 352130 18156 4 ch_out_south\[9\]
+port 333 nsew
+rlabel metal2 s 40158 677688 40158 677688 4 ch_out_west\[0\]
+port 334 nsew
+rlabel metal1 s 43276 679694 43276 679694 4 ch_out_west\[12\]
+port 335 nsew
+rlabel metal2 s 44183 679694 44183 679694 4 ch_out_west\[15\]
+port 336 nsew
+rlabel metal1 s 44229 678946 44229 678946 4 ch_out_west\[18\]
+port 337 nsew
+rlabel metal1 s 22317 644198 22317 644198 4 ch_out_west\[21\]
+port 338 nsew
+rlabel metal1 s 21351 643382 21351 643382 4 ch_out_west\[24\]
+port 339 nsew
+rlabel metal1 s 21673 642566 21673 642566 4 ch_out_west\[27\]
+port 340 nsew
+rlabel metal1 s 21581 641750 21581 641750 4 ch_out_west\[30\]
+port 341 nsew
+rlabel metal1 s 22823 640934 22823 640934 4 ch_out_west\[33\]
+port 342 nsew
+rlabel metal1 s 21489 640118 21489 640118 4 ch_out_west\[36\]
+port 343 nsew
+rlabel metal1 s 22731 639302 22731 639302 4 ch_out_west\[39\]
+port 344 nsew
+rlabel metal1 s 40066 678946 40066 678946 4 ch_out_west\[3\]
+port 345 nsew
+rlabel metal1 s 41722 679857 41722 679857 4 ch_out_west\[6\]
+port 346 nsew
+rlabel metal2 s 42550 679082 42550 679082 4 ch_out_west\[9\]
+port 347 nsew
+rlabel metal2 s 369994 105740 369994 105740 4 cpu_clk
+port 348 nsew
+rlabel metal2 s 432860 382228 432860 382228 4 cpu_clk_rp\[2\]
+port 349 nsew
+rlabel metal2 s 429640 105883 429640 105883 4 e_reset_n
+port 350 nsew
+rlabel metal2 s 447534 398259 447534 398259 4 e_reset_n_rp
+port 351 nsew
+rlabel metal3 s 450156 200396 450156 200396 4 i2c_rst_n
+port 352 nsew
+rlabel metal2 s 450110 360458 450110 360458 4 i2cm_clk_i
+port 353 nsew
+rlabel metal2 s 450294 360866 450294 360866 4 i2cm_clk_o
+port 354 nsew
+rlabel metal2 s 450478 363212 450478 363212 4 i2cm_clk_oen
+port 355 nsew
+rlabel metal2 s 450662 360050 450662 360050 4 i2cm_data_i
+port 356 nsew
+rlabel metal2 s 450846 361104 450846 361104 4 i2cm_data_o
+port 357 nsew
+rlabel metal2 s 451030 361172 451030 361172 4 i2cm_data_oen
+port 358 nsew
+rlabel metal2 s 452870 361036 452870 361036 4 i2cm_intr_o
+port 359 nsew
+rlabel metal3 s 581218 6596 581218 6596 4 io_in[0]
+port 360 nsew
+rlabel metal1 s 578588 458150 578588 458150 4 io_in[10]
+port 361 nsew
+rlabel metal3 s 581218 511292 581218 511292 4 io_in[11]
+port 362 nsew
+rlabel metal3 s 580198 564349 580198 564349 4 io_in[12]
+port 363 nsew
+rlabel metal2 s 580198 617253 580198 617253 4 io_in[13]
+port 364 nsew
+rlabel metal3 s 581908 670684 581908 670684 4 io_in[14]
+port 365 nsew
+rlabel metal1 s 462116 690139 462116 690139 4 io_in[15]
+port 366 nsew
+rlabel metal1 s 411102 690139 411102 690139 4 io_in[16]
+port 367 nsew
+rlabel metal2 s 429870 702008 429870 702008 4 io_in[17]
+port 368 nsew
+rlabel metal1 s 309102 690139 309102 690139 4 io_in[18]
+port 369 nsew
+rlabel metal1 s 279772 700434 279772 700434 4 io_in[19]
+port 370 nsew
+rlabel metal1 s 578634 46886 578634 46886 4 io_in[1]
+port 371 nsew
+rlabel metal2 s 235198 701974 235198 701974 4 io_in[20]
+port 372 nsew
+rlabel metal1 s 156102 690683 156102 690683 4 io_in[21]
+port 373 nsew
+rlabel metal1 s 105110 690139 105110 690139 4 io_in[22]
+port 374 nsew
+rlabel metal2 s 40526 701940 40526 701940 4 io_in[23]
+port 375 nsew
+rlabel metal3 s 1556 684284 1556 684284 4 io_in[24]
+port 376 nsew
+rlabel metal3 s 1878 632060 1878 632060 4 io_in[25]
+port 377 nsew
+rlabel metal3 s 1648 579972 1648 579972 4 io_in[26]
+port 378 nsew
+rlabel metal3 s 1740 527884 1740 527884 4 io_in[27]
+port 379 nsew
+rlabel metal3 s 1648 475660 1648 475660 4 io_in[28]
+port 380 nsew
+rlabel metal3 s 1556 423572 1556 423572 4 io_in[29]
+port 381 nsew
+rlabel metal2 s 580198 86547 580198 86547 4 io_in[2]
+port 382 nsew
+rlabel metal3 s 1556 371348 1556 371348 4 io_in[30]
+port 383 nsew
+rlabel metal3 s 1878 319260 1878 319260 4 io_in[31]
+port 384 nsew
+rlabel metal3 s 1878 267172 1878 267172 4 io_in[32]
+port 385 nsew
+rlabel metal3 s 1878 214948 1878 214948 4 io_in[33]
+port 386 nsew
+rlabel metal3 s 1924 162860 1924 162860 4 io_in[34]
+port 387 nsew
+rlabel metal3 s 1878 110636 1878 110636 4 io_in[35]
+port 388 nsew
+rlabel metal3 s 1970 71604 1970 71604 4 io_in[36]
+port 389 nsew
+rlabel metal3 s 1924 32436 1924 32436 4 io_in[37]
+port 390 nsew
+rlabel metal2 s 580198 126463 580198 126463 4 io_in[3]
+port 391 nsew
+rlabel metal2 s 580198 166413 580198 166413 4 io_in[4]
+port 392 nsew
+rlabel metal2 s 580198 206329 580198 206329 4 io_in[5]
+port 393 nsew
+rlabel metal3 s 580198 245565 580198 245565 4 io_in[6]
+port 394 nsew
+rlabel metal2 s 579646 299081 579646 299081 4 io_in[7]
+port 395 nsew
+rlabel metal2 s 580198 352563 580198 352563 4 io_in[8]
+port 396 nsew
+rlabel metal2 s 580198 405297 580198 405297 4 io_in[9]
+port 397 nsew
+rlabel metal3 s 581218 33116 581218 33116 4 io_oeb[0]
+port 398 nsew
+rlabel metal2 s 580198 485197 580198 485197 4 io_oeb[10]
+port 399 nsew
+rlabel metal3 s 581218 537812 581218 537812 4 io_oeb[11]
+port 400 nsew
+rlabel metal2 s 580198 591481 580198 591481 4 io_oeb[12]
+port 401 nsew
+rlabel metal3 s 581218 644028 581218 644028 4 io_oeb[13]
+port 402 nsew
+rlabel metal2 s 578174 696252 578174 696252 4 io_oeb[14]
+port 403 nsew
+rlabel metal1 s 428102 690139 428102 690139 4 io_oeb[15]
+port 404 nsew
+rlabel metal2 s 390770 692750 390770 692750 4 io_oeb[16]
+port 405 nsew
+rlabel metal1 s 326094 690139 326094 690139 4 io_oeb[17]
+port 406 nsew
+rlabel metal1 s 275102 690139 275102 690139 4 io_oeb[18]
+port 407 nsew
+rlabel metal1 s 246284 700298 246284 700298 4 io_oeb[19]
+port 408 nsew
+rlabel metal2 s 580198 73049 580198 73049 4 io_oeb[1]
+port 409 nsew
+rlabel metal1 s 173098 690139 173098 690139 4 io_oeb[20]
+port 410 nsew
+rlabel metal1 s 122102 690139 122102 690139 4 io_oeb[21]
+port 411 nsew
+rlabel metal1 s 72358 699686 72358 699686 4 io_oeb[22]
+port 412 nsew
+rlabel metal1 s 11316 700230 11316 700230 4 io_oeb[23]
+port 413 nsew
+rlabel metal3 s 1878 658172 1878 658172 4 io_oeb[24]
+port 414 nsew
+rlabel metal3 s 1878 606084 1878 606084 4 io_oeb[25]
+port 415 nsew
+rlabel metal3 s 1740 553860 1740 553860 4 io_oeb[26]
+port 416 nsew
+rlabel metal3 s 1694 501772 1694 501772 4 io_oeb[27]
+port 417 nsew
+rlabel metal3 s 1740 449548 1740 449548 4 io_oeb[28]
+port 418 nsew
+rlabel metal3 s 1648 397460 1648 397460 4 io_oeb[29]
+port 419 nsew
+rlabel metal2 s 579830 112965 579830 112965 4 io_oeb[2]
+port 420 nsew
+rlabel metal3 s 1556 345372 1556 345372 4 io_oeb[30]
+port 421 nsew
+rlabel metal3 s 1970 293148 1970 293148 4 io_oeb[31]
+port 422 nsew
+rlabel metal3 s 2016 241060 2016 241060 4 io_oeb[32]
+port 423 nsew
+rlabel metal3 s 2016 188836 2016 188836 4 io_oeb[33]
+port 424 nsew
+rlabel metal3 s 1970 136748 1970 136748 4 io_oeb[34]
+port 425 nsew
+rlabel metal3 s 1924 84660 1924 84660 4 io_oeb[35]
+port 426 nsew
+rlabel metal3 s 1878 45492 1878 45492 4 io_oeb[36]
+port 427 nsew
+rlabel metal3 s 1878 6460 1878 6460 4 io_oeb[37]
+port 428 nsew
+rlabel metal2 s 580198 152915 580198 152915 4 io_oeb[3]
+port 429 nsew
+rlabel metal2 s 580198 192831 580198 192831 4 io_oeb[4]
+port 430 nsew
+rlabel metal2 s 580106 232781 580106 232781 4 io_oeb[5]
+port 431 nsew
+rlabel metal2 s 579922 272697 579922 272697 4 io_oeb[6]
+port 432 nsew
+rlabel metal2 s 579922 325431 579922 325431 4 io_oeb[7]
+port 433 nsew
+rlabel metal2 s 580198 378947 580198 378947 4 io_oeb[8]
+port 434 nsew
+rlabel metal2 s 579830 431749 579830 431749 4 io_oeb[9]
+port 435 nsew
+rlabel metal3 s 555442 441252 555442 441252 4 io_oeb_int\[0\]
+port 436 nsew
+rlabel metal3 s 555948 457572 555948 457572 4 io_oeb_int\[10\]
+port 437 nsew
+rlabel metal3 s 555902 459204 555902 459204 4 io_oeb_int\[11\]
+port 438 nsew
+rlabel metal3 s 556086 460836 556086 460836 4 io_oeb_int\[12\]
+port 439 nsew
+rlabel metal3 s 555856 462468 555856 462468 4 io_oeb_int\[13\]
+port 440 nsew
+rlabel metal3 s 555580 464100 555580 464100 4 io_oeb_int\[14\]
+port 441 nsew
+rlabel metal1 s 526631 679694 526631 679694 4 io_oeb_int\[15\]
+port 442 nsew
+rlabel metal1 s 522928 679694 522928 679694 4 io_oeb_int\[16\]
+port 443 nsew
+rlabel metal1 s 522008 678946 522008 678946 4 io_oeb_int\[17\]
+port 444 nsew
+rlabel metal2 s 519846 611660 519846 611660 4 io_oeb_int\[18\]
+port 445 nsew
+rlabel metal2 s 526654 612136 526654 612136 4 io_oeb_int\[19\]
+port 446 nsew
+rlabel metal3 s 555442 442884 555442 442884 4 io_oeb_int\[1\]
+port 447 nsew
+rlabel metal1 s 510196 679694 510196 679694 4 io_oeb_int\[20\]
+port 448 nsew
+rlabel metal2 s 507518 679048 507518 679048 4 io_oeb_int\[21\]
+port 449 nsew
+rlabel metal1 s 503482 679694 503482 679694 4 io_oeb_int\[22\]
+port 450 nsew
+rlabel metal1 s 500470 679694 500470 679694 4 io_oeb_int\[23\]
+port 451 nsew
+rlabel metal1 s 431296 679626 431296 679626 4 io_oeb_int\[24\]
+port 452 nsew
+rlabel metal2 s 429870 679218 429870 679218 4 io_oeb_int\[25\]
+port 453 nsew
+rlabel metal1 s 428950 679694 428950 679694 4 io_oeb_int\[26\]
+port 454 nsew
+rlabel metal2 s 428674 679014 428674 679014 4 io_oeb_int\[27\]
+port 455 nsew
+rlabel metal1 s 427593 679762 427593 679762 4 io_oeb_int\[28\]
+port 456 nsew
+rlabel metal1 s 428122 678946 428122 678946 4 io_oeb_int\[29\]
+port 457 nsew
+rlabel metal3 s 555442 444516 555442 444516 4 io_oeb_int\[2\]
+port 458 nsew
+rlabel metal1 s 426696 678946 426696 678946 4 io_oeb_int\[30\]
+port 459 nsew
+rlabel metal1 s 424846 679626 424846 679626 4 io_oeb_int\[31\]
+port 460 nsew
+rlabel metal1 s 424534 679558 424534 679558 4 io_oeb_int\[32\]
+port 461 nsew
+rlabel metal2 s 423338 679014 423338 679014 4 io_oeb_int\[33\]
+port 462 nsew
+rlabel metal2 s 422694 679048 422694 679048 4 io_oeb_int\[34\]
+port 463 nsew
+rlabel metal2 s 451214 561942 451214 561942 4 io_oeb_int\[35\]
+port 464 nsew
+rlabel metal2 s 448362 560031 448362 560031 4 io_oeb_int\[36\]
+port 465 nsew
+rlabel metal2 s 449742 560133 449742 560133 4 io_oeb_int\[37\]
+port 466 nsew
+rlabel metal1 s 564098 452329 564098 452329 4 io_oeb_int\[3\]
+port 467 nsew
+rlabel metal1 s 564098 453553 564098 453553 4 io_oeb_int\[4\]
+port 468 nsew
+rlabel metal1 s 564098 454777 564098 454777 4 io_oeb_int\[5\]
+port 469 nsew
+rlabel metal1 s 564098 456001 564098 456001 4 io_oeb_int\[6\]
+port 470 nsew
+rlabel metal2 s 557014 456921 557014 456921 4 io_oeb_int\[7\]
+port 471 nsew
+rlabel metal3 s 555580 454308 555580 454308 4 io_oeb_int\[8\]
+port 472 nsew
+rlabel metal3 s 555856 455940 555856 455940 4 io_oeb_int\[9\]
+port 473 nsew
+rlabel metal3 s 581264 19788 581264 19788 4 io_out[0]
+port 474 nsew
+rlabel metal2 s 580198 471699 580198 471699 4 io_out[10]
+port 475 nsew
+rlabel metal3 s 581264 524484 581264 524484 4 io_out[11]
+port 476 nsew
+rlabel metal3 s 581218 577660 581218 577660 4 io_out[12]
+port 477 nsew
+rlabel metal2 s 579554 631533 579554 631533 4 io_out[13]
+port 478 nsew
+rlabel metal3 s 582230 683876 582230 683876 4 io_out[14]
+port 479 nsew
+rlabel metal1 s 445096 690683 445096 690683 4 io_out[15]
+port 480 nsew
+rlabel metal1 s 436954 698938 436954 698938 4 io_out[16]
+port 481 nsew
+rlabel metal1 s 378626 700298 378626 700298 4 io_out[17]
+port 482 nsew
+rlabel metal1 s 292100 690139 292100 690139 4 io_out[18]
+port 483 nsew
+rlabel metal1 s 262660 700366 262660 700366 4 io_out[19]
+port 484 nsew
+rlabel metal1 s 578726 60690 578726 60690 4 io_out[1]
+port 485 nsew
+rlabel metal2 s 219006 700580 219006 700580 4 io_out[20]
+port 486 nsew
+rlabel metal1 s 139104 690683 139104 690683 4 io_out[21]
+port 487 nsew
+rlabel metal1 s 88734 699686 88734 699686 4 io_out[22]
+port 488 nsew
+rlabel metal2 s 24334 701940 24334 701940 4 io_out[23]
+port 489 nsew
+rlabel metal3 s 1648 671228 1648 671228 4 io_out[24]
+port 490 nsew
+rlabel metal3 s 1924 619140 1924 619140 4 io_out[25]
+port 491 nsew
+rlabel metal3 s 1786 566916 1786 566916 4 io_out[26]
+port 492 nsew
+rlabel metal3 s 1878 514828 1878 514828 4 io_out[27]
+port 493 nsew
+rlabel metal3 s 1648 462604 1648 462604 4 io_out[28]
+port 494 nsew
+rlabel metal3 s 1556 410516 1556 410516 4 io_out[29]
+port 495 nsew
+rlabel metal2 s 580198 100079 580198 100079 4 io_out[2]
+port 496 nsew
+rlabel metal3 s 1786 358428 1786 358428 4 io_out[30]
+port 497 nsew
+rlabel metal3 s 1924 306204 1924 306204 4 io_out[31]
+port 498 nsew
+rlabel metal3 s 1924 254116 1924 254116 4 io_out[32]
+port 499 nsew
+rlabel metal3 s 1970 201892 1970 201892 4 io_out[33]
+port 500 nsew
+rlabel metal3 s 1556 149804 1556 149804 4 io_out[34]
+port 501 nsew
+rlabel metal3 s 1556 97580 1556 97580 4 io_out[35]
+port 502 nsew
+rlabel metal3 s 1648 58548 1648 58548 4 io_out[36]
+port 503 nsew
+rlabel metal3 s 1970 19380 1970 19380 4 io_out[37]
+port 504 nsew
+rlabel metal3 s 580198 139349 580198 139349 4 io_out[3]
+port 505 nsew
+rlabel metal3 s 581908 179180 581908 179180 4 io_out[4]
+port 506 nsew
+rlabel metal3 s 581954 219028 581954 219028 4 io_out[5]
+port 507 nsew
+rlabel metal3 s 581908 258876 581908 258876 4 io_out[6]
+port 508 nsew
+rlabel metal3 s 581908 312052 581908 312052 4 io_out[7]
+port 509 nsew
+rlabel metal2 s 580198 365381 580198 365381 4 io_out[8]
+port 510 nsew
+rlabel metal2 s 580198 418863 580198 418863 4 io_out[9]
+port 511 nsew
+rlabel metal3 s 555488 440708 555488 440708 4 io_out_int\[0\]
+port 512 nsew
+rlabel metal3 s 555764 457028 555764 457028 4 io_out_int\[10\]
+port 513 nsew
+rlabel metal3 s 556040 458660 556040 458660 4 io_out_int\[11\]
+port 514 nsew
+rlabel metal3 s 555948 460292 555948 460292 4 io_out_int\[12\]
+port 515 nsew
+rlabel metal3 s 556040 461924 556040 461924 4 io_out_int\[13\]
+port 516 nsew
+rlabel metal3 s 556086 463556 556086 463556 4 io_out_int\[14\]
+port 517 nsew
+rlabel metal1 s 527252 679483 527252 679483 4 io_out_int\[15\]
+port 518 nsew
+rlabel metal1 s 524170 679694 524170 679694 4 io_out_int\[16\]
+port 519 nsew
+rlabel metal1 s 521157 679694 521157 679694 4 io_out_int\[17\]
+port 520 nsew
+rlabel metal2 s 527850 621180 527850 621180 4 io_out_int\[18\]
+port 521 nsew
+rlabel metal2 s 525090 615502 525090 615502 4 io_out_int\[19\]
+port 522 nsew
+rlabel metal3 s 555442 442340 555442 442340 4 io_out_int\[1\]
+port 523 nsew
+rlabel metal2 s 522422 626008 522422 626008 4 io_out_int\[20\]
+port 524 nsew
+rlabel metal1 s 507725 679694 507725 679694 4 io_out_int\[21\]
+port 525 nsew
+rlabel metal1 s 504712 679694 504712 679694 4 io_out_int\[22\]
+port 526 nsew
+rlabel metal2 s 502274 678980 502274 678980 4 io_out_int\[23\]
+port 527 nsew
+rlabel metal2 s 431066 679082 431066 679082 4 io_out_int\[24\]
+port 528 nsew
+rlabel metal1 s 430146 679449 430146 679449 4 io_out_int\[25\]
+port 529 nsew
+rlabel metal1 s 429916 678810 429916 678810 4 io_out_int\[26\]
+port 530 nsew
+rlabel metal2 s 428398 677654 428398 677654 4 io_out_int\[27\]
+port 531 nsew
+rlabel metal1 s 429594 678606 429594 678606 4 io_out_int\[28\]
+port 532 nsew
+rlabel metal1 s 427271 679626 427271 679626 4 io_out_int\[29\]
+port 533 nsew
+rlabel metal3 s 555442 443972 555442 443972 4 io_out_int\[2\]
+port 534 nsew
+rlabel metal2 s 426190 676974 426190 676974 4 io_out_int\[30\]
+port 535 nsew
+rlabel metal2 s 425362 678300 425362 678300 4 io_out_int\[31\]
+port 536 nsew
+rlabel metal1 s 425776 678878 425776 678878 4 io_out_int\[32\]
+port 537 nsew
+rlabel metal1 s 423614 679857 423614 679857 4 io_out_int\[33\]
+port 538 nsew
+rlabel metal1 s 423108 679626 423108 679626 4 io_out_int\[34\]
+port 539 nsew
+rlabel metal2 s 421970 679694 421970 679694 4 io_out_int\[35\]
+port 540 nsew
+rlabel metal2 s 450846 561602 450846 561602 4 io_out_int\[36\]
+port 541 nsew
+rlabel metal2 s 450294 560820 450294 560820 4 io_out_int\[37\]
+port 542 nsew
+rlabel metal3 s 555442 445604 555442 445604 4 io_out_int\[3\]
+port 543 nsew
+rlabel metal1 s 564098 453145 564098 453145 4 io_out_int\[4\]
+port 544 nsew
+rlabel metal1 s 564098 454369 564098 454369 4 io_out_int\[5\]
+port 545 nsew
+rlabel metal1 s 564098 455695 564098 455695 4 io_out_int\[6\]
+port 546 nsew
+rlabel metal3 s 555948 452132 555948 452132 4 io_out_int\[7\]
+port 547 nsew
+rlabel metal3 s 555672 453764 555672 453764 4 io_out_int\[8\]
+port 548 nsew
+rlabel metal3 s 555626 455396 555626 455396 4 io_out_int\[9\]
+port 549 nsew
+rlabel metal2 s 481137 579020 481137 579020 4 ir_intr
+port 550 nsew
+rlabel metal2 s 480769 579020 480769 579020 4 ir_rx
+port 551 nsew
+rlabel metal1 s 480470 563346 480470 563346 4 ir_tx
+port 552 nsew
+rlabel metal2 s 447166 428791 447166 428791 4 irq_lines\[0\]
+port 553 nsew
+rlabel metal2 s 447166 426071 447166 426071 4 irq_lines\[10\]
+port 554 nsew
+rlabel metal3 s 447166 425867 447166 425867 4 irq_lines\[11\]
+port 555 nsew
+rlabel metal2 s 447258 425697 447258 425697 4 irq_lines\[12\]
+port 556 nsew
+rlabel metal2 s 447350 425629 447350 425629 4 irq_lines\[13\]
+port 557 nsew
+rlabel metal2 s 447166 425391 447166 425391 4 irq_lines\[14\]
+port 558 nsew
+rlabel metal2 s 447442 424575 447442 424575 4 irq_lines\[15\]
+port 559 nsew
+rlabel metal3 s 447166 424507 447166 424507 4 irq_lines\[16\]
+port 560 nsew
+rlabel metal2 s 447350 424439 447350 424439 4 irq_lines\[17\]
+port 561 nsew
+rlabel metal2 s 447258 424201 447258 424201 4 irq_lines\[18\]
+port 562 nsew
+rlabel metal2 s 447534 424133 447534 424133 4 irq_lines\[19\]
+port 563 nsew
+rlabel metal2 s 447166 428553 447166 428553 4 irq_lines\[1\]
+port 564 nsew
+rlabel metal2 s 447258 423249 447258 423249 4 irq_lines\[20\]
+port 565 nsew
+rlabel metal3 s 447166 423181 447166 423181 4 irq_lines\[21\]
+port 566 nsew
+rlabel metal2 s 447350 423011 447350 423011 4 irq_lines\[22\]
+port 567 nsew
+rlabel metal2 s 447166 422807 447166 422807 4 irq_lines\[23\]
+port 568 nsew
+rlabel metal2 s 447258 422637 447258 422637 4 irq_lines\[24\]
+port 569 nsew
+rlabel metal2 s 447166 421957 447166 421957 4 irq_lines\[25\]
+port 570 nsew
+rlabel metal2 s 447258 421685 447258 421685 4 irq_lines\[26\]
+port 571 nsew
+rlabel metal2 s 447166 421583 447166 421583 4 irq_lines\[27\]
+port 572 nsew
+rlabel metal2 s 447350 421481 447350 421481 4 irq_lines\[28\]
+port 573 nsew
+rlabel metal2 s 447442 421379 447442 421379 4 irq_lines\[29\]
+port 574 nsew
+rlabel metal2 s 447258 428451 447258 428451 4 irq_lines\[2\]
+port 575 nsew
+rlabel metal2 s 447350 420495 447350 420495 4 irq_lines\[30\]
+port 576 nsew
+rlabel metal2 s 447258 420325 447258 420325 4 irq_lines\[31\]
+port 577 nsew
+rlabel metal2 s 447350 428349 447350 428349 4 irq_lines\[3\]
+port 578 nsew
+rlabel metal2 s 447534 427431 447534 427431 4 irq_lines\[4\]
+port 579 nsew
+rlabel metal2 s 447258 427397 447258 427397 4 irq_lines\[5\]
+port 580 nsew
+rlabel metal3 s 447166 427227 447166 427227 4 irq_lines\[6\]
+port 581 nsew
+rlabel metal2 s 447350 427193 447350 427193 4 irq_lines\[7\]
+port 582 nsew
+rlabel metal2 s 447442 427023 447442 427023 4 irq_lines\[8\]
+port 583 nsew
+rlabel metal2 s 447258 426785 447258 426785 4 irq_lines\[9\]
+port 584 nsew
+rlabel metal2 s 139426 3332 139426 3332 4 la_data_in[0]
+port 585 nsew
+rlabel metal2 s 161322 1894 161322 1894 4 la_data_in[10]
+port 586 nsew
+rlabel metal2 s 164910 1690 164910 1690 4 la_data_in[11]
+port 587 nsew
+rlabel metal2 s 190578 3366 190578 3366 4 la_data_in[12]
+port 588 nsew
+rlabel metal2 s 193246 3638 193246 3638 4 la_data_in[13]
+port 589 nsew
+rlabel metal2 s 197386 3638 197386 3638 4 la_data_in[14]
+port 590 nsew
+rlabel metal2 s 203826 3400 203826 3400 4 la_data_in[15]
+port 591 nsew
+rlabel metal2 s 206126 3536 206126 3536 4 la_data_in[16]
+port 592 nsew
+rlabel metal1 s 212542 3869 212542 3869 4 la_data_in[17]
+port 593 nsew
+rlabel metal2 s 143290 3468 143290 3468 4 la_data_in[1]
+port 594 nsew
+rlabel metal2 s 146694 3434 146694 3434 4 la_data_in[2]
+port 595 nsew
+rlabel metal2 s 152122 3604 152122 3604 4 la_data_in[3]
+port 596 nsew
+rlabel metal2 s 140070 1996 140070 1996 4 la_data_in[4]
+port 597 nsew
+rlabel metal2 s 155342 2992 155342 2992 4 la_data_in[5]
+port 598 nsew
+rlabel metal2 s 147154 1690 147154 1690 4 la_data_in[6]
+port 599 nsew
+rlabel metal2 s 150650 1724 150650 1724 4 la_data_in[7]
+port 600 nsew
+rlabel metal2 s 154238 1622 154238 1622 4 la_data_in[8]
+port 601 nsew
+rlabel metal2 s 157826 1792 157826 1792 4 la_data_in[9]
+port 602 nsew
+rlabel metal2 s 140806 3434 140806 3434 4 la_data_out[0]
+port 603 nsew
+rlabel metal2 s 481758 1622 481758 1622 4 la_data_out[100]
+port 604 nsew
+rlabel metal2 s 485254 1588 485254 1588 4 la_data_out[101]
+port 605 nsew
+rlabel metal2 s 463634 3094 463634 3094 4 la_data_out[102]
+port 606 nsew
+rlabel metal2 s 465014 2958 465014 2958 4 la_data_out[103]
+port 607 nsew
+rlabel metal2 s 467130 3094 467130 3094 4 la_data_out[104]
+port 608 nsew
+rlabel metal2 s 470074 3060 470074 3060 4 la_data_out[105]
+port 609 nsew
+rlabel metal2 s 503010 1282 503010 1282 4 la_data_out[106]
+port 610 nsew
+rlabel metal2 s 506506 1112 506506 1112 4 la_data_out[107]
+port 611 nsew
+rlabel metal2 s 476054 2856 476054 2856 4 la_data_out[108]
+port 612 nsew
+rlabel metal2 s 478814 2958 478814 2958 4 la_data_out[109]
+port 613 nsew
+rlabel metal2 s 162518 2030 162518 2030 4 la_data_out[10]
+port 614 nsew
+rlabel metal2 s 480194 2890 480194 2890 4 la_data_out[110]
+port 615 nsew
+rlabel metal2 s 482954 2890 482954 2890 4 la_data_out[111]
+port 616 nsew
+rlabel metal2 s 489026 2652 489026 2652 4 la_data_out[112]
+port 617 nsew
+rlabel metal1 s 486726 3359 486726 3359 4 la_data_out[113]
+port 618 nsew
+rlabel metal2 s 489394 3196 489394 3196 4 la_data_out[114]
+port 619 nsew
+rlabel metal2 s 491234 3128 491234 3128 4 la_data_out[115]
+port 620 nsew
+rlabel metal2 s 538430 1384 538430 1384 4 la_data_out[116]
+port 621 nsew
+rlabel metal2 s 542018 1418 542018 1418 4 la_data_out[117]
+port 622 nsew
+rlabel metal2 s 545514 1350 545514 1350 4 la_data_out[118]
+port 623 nsew
+rlabel metal2 s 500894 3026 500894 3026 4 la_data_out[119]
+port 624 nsew
+rlabel metal2 s 166106 1826 166106 1826 4 la_data_out[11]
+port 625 nsew
+rlabel metal2 s 502274 3468 502274 3468 4 la_data_out[120]
+port 626 nsew
+rlabel metal2 s 504114 3434 504114 3434 4 la_data_out[121]
+port 627 nsew
+rlabel metal2 s 506414 2992 506414 2992 4 la_data_out[122]
+port 628 nsew
+rlabel metal2 s 508898 3366 508898 3366 4 la_data_out[123]
+port 629 nsew
+rlabel metal2 s 566858 1690 566858 1690 4 la_data_out[124]
+port 630 nsew
+rlabel metal2 s 513314 3332 513314 3332 4 la_data_out[125]
+port 631 nsew
+rlabel metal2 s 516074 2958 516074 2958 4 la_data_out[126]
+port 632 nsew
+rlabel metal2 s 577438 1792 577438 1792 4 la_data_out[127]
+port 633 nsew
+rlabel metal2 s 191682 3672 191682 3672 4 la_data_out[12]
+port 634 nsew
+rlabel metal1 s 197310 3937 197310 3937 4 la_data_out[13]
+port 635 nsew
+rlabel metal2 s 199594 3434 199594 3434 4 la_data_out[14]
+port 636 nsew
+rlabel metal2 s 203090 3672 203090 3672 4 la_data_out[15]
+port 637 nsew
+rlabel metal2 s 210358 3502 210358 3502 4 la_data_out[16]
+port 638 nsew
+rlabel metal2 s 212658 3468 212658 3468 4 la_data_out[17]
+port 639 nsew
+rlabel metal2 s 190854 1622 190854 1622 4 la_data_out[18]
+port 640 nsew
+rlabel metal2 s 194442 1860 194442 1860 4 la_data_out[19]
+port 641 nsew
+rlabel metal2 s 146326 3536 146326 3536 4 la_data_out[1]
+port 642 nsew
+rlabel metal2 s 197938 1996 197938 1996 4 la_data_out[20]
+port 643 nsew
+rlabel metal2 s 201526 1894 201526 1894 4 la_data_out[21]
+port 644 nsew
+rlabel metal2 s 205114 1928 205114 1928 4 la_data_out[22]
+port 645 nsew
+rlabel metal2 s 208610 1962 208610 1962 4 la_data_out[23]
+port 646 nsew
+rlabel metal2 s 212198 1656 212198 1656 4 la_data_out[24]
+port 647 nsew
+rlabel metal2 s 215694 1758 215694 1758 4 la_data_out[25]
+port 648 nsew
+rlabel metal2 s 219282 1826 219282 1826 4 la_data_out[26]
+port 649 nsew
+rlabel metal2 s 222778 2098 222778 2098 4 la_data_out[27]
+port 650 nsew
+rlabel metal2 s 226366 2030 226366 2030 4 la_data_out[28]
+port 651 nsew
+rlabel metal2 s 229862 2132 229862 2132 4 la_data_out[29]
+port 652 nsew
+rlabel metal2 s 150926 3366 150926 3366 4 la_data_out[2]
+port 653 nsew
+rlabel metal2 s 233450 2064 233450 2064 4 la_data_out[30]
+port 654 nsew
+rlabel metal1 s 268364 3937 268364 3937 4 la_data_out[31]
+port 655 nsew
+rlabel metal2 s 269146 3434 269146 3434 4 la_data_out[32]
+port 656 nsew
+rlabel metal2 s 272734 3366 272734 3366 4 la_data_out[33]
+port 657 nsew
+rlabel metal2 s 272826 3230 272826 3230 4 la_data_out[34]
+port 658 nsew
+rlabel metal2 s 268042 3060 268042 3060 4 la_data_out[35]
+port 659 nsew
+rlabel metal1 s 273286 2856 273286 2856 4 la_data_out[36]
+port 660 nsew
+rlabel metal1 s 273562 3060 273562 3060 4 la_data_out[37]
+port 661 nsew
+rlabel metal2 s 272550 3298 272550 3298 4 la_data_out[38]
+port 662 nsew
+rlabel metal1 s 272458 3264 272458 3264 4 la_data_out[39]
+port 663 nsew
+rlabel metal2 s 153594 3672 153594 3672 4 la_data_out[3]
+port 664 nsew
+rlabel metal2 s 268870 1724 268870 1724 4 la_data_out[40]
+port 665 nsew
+rlabel metal2 s 272557 340 272557 340 4 la_data_out[41]
+port 666 nsew
+rlabel metal2 s 276046 959 276046 959 4 la_data_out[42]
+port 667 nsew
+rlabel metal2 s 292606 3468 292606 3468 4 la_data_out[43]
+port 668 nsew
+rlabel metal2 s 292606 2856 292606 2856 4 la_data_out[44]
+port 669 nsew
+rlabel metal2 s 295366 3366 295366 3366 4 la_data_out[45]
+port 670 nsew
+rlabel metal2 s 290214 1588 290214 1588 4 la_data_out[46]
+port 671 nsew
+rlabel metal2 s 293710 1690 293710 1690 4 la_data_out[47]
+port 672 nsew
+rlabel metal2 s 297298 1622 297298 1622 4 la_data_out[48]
+port 673 nsew
+rlabel metal1 s 307538 3937 307538 3937 4 la_data_out[49]
+port 674 nsew
+rlabel metal2 s 141266 2030 141266 2030 4 la_data_out[4]
+port 675 nsew
+rlabel metal2 s 309718 3400 309718 3400 4 la_data_out[50]
+port 676 nsew
+rlabel metal2 s 307970 1588 307970 1588 4 la_data_out[51]
+port 677 nsew
+rlabel metal2 s 311466 2098 311466 2098 4 la_data_out[52]
+port 678 nsew
+rlabel metal2 s 315054 2098 315054 2098 4 la_data_out[53]
+port 679 nsew
+rlabel metal2 s 318550 2098 318550 2098 4 la_data_out[54]
+port 680 nsew
+rlabel metal2 s 322138 2098 322138 2098 4 la_data_out[55]
+port 681 nsew
+rlabel metal2 s 325634 1554 325634 1554 4 la_data_out[56]
+port 682 nsew
+rlabel metal2 s 329222 1214 329222 1214 4 la_data_out[57]
+port 683 nsew
+rlabel metal2 s 332718 1214 332718 1214 4 la_data_out[58]
+port 684 nsew
+rlabel metal2 s 332718 2720 332718 2720 4 la_data_out[59]
+port 685 nsew
+rlabel metal2 s 160126 3570 160126 3570 4 la_data_out[5]
+port 686 nsew
+rlabel metal2 s 332534 3264 332534 3264 4 la_data_out[60]
+port 687 nsew
+rlabel metal2 s 333638 2958 333638 2958 4 la_data_out[61]
+port 688 nsew
+rlabel metal2 s 346978 1520 346978 1520 4 la_data_out[62]
+port 689 nsew
+rlabel metal2 s 350474 1588 350474 1588 4 la_data_out[63]
+port 690 nsew
+rlabel metal2 s 354062 1588 354062 1588 4 la_data_out[64]
+port 691 nsew
+rlabel metal2 s 357558 1622 357558 1622 4 la_data_out[65]
+port 692 nsew
+rlabel metal2 s 384054 3230 384054 3230 4 la_data_out[66]
+port 693 nsew
+rlabel metal2 s 364642 1690 364642 1690 4 la_data_out[67]
+port 694 nsew
+rlabel metal2 s 368230 1724 368230 1724 4 la_data_out[68]
+port 695 nsew
+rlabel metal2 s 371726 1792 371726 1792 4 la_data_out[69]
+port 696 nsew
+rlabel metal2 s 148350 1826 148350 1826 4 la_data_out[6]
+port 697 nsew
+rlabel metal2 s 393162 3468 393162 3468 4 la_data_out[70]
+port 698 nsew
+rlabel metal2 s 378902 1826 378902 1826 4 la_data_out[71]
+port 699 nsew
+rlabel metal2 s 382398 1027 382398 1027 4 la_data_out[72]
+port 700 nsew
+rlabel metal2 s 385986 1588 385986 1588 4 la_data_out[73]
+port 701 nsew
+rlabel metal2 s 389482 1656 389482 1656 4 la_data_out[74]
+port 702 nsew
+rlabel metal2 s 393070 1690 393070 1690 4 la_data_out[75]
+port 703 nsew
+rlabel metal2 s 403282 3434 403282 3434 4 la_data_out[76]
+port 704 nsew
+rlabel metal2 s 406318 3400 406318 3400 4 la_data_out[77]
+port 705 nsew
+rlabel metal2 s 403650 2030 403650 2030 4 la_data_out[78]
+port 706 nsew
+rlabel metal2 s 407238 1996 407238 1996 4 la_data_out[79]
+port 707 nsew
+rlabel metal2 s 151846 1656 151846 1656 4 la_data_out[7]
+port 708 nsew
+rlabel metal2 s 410826 2064 410826 2064 4 la_data_out[80]
+port 709 nsew
+rlabel metal2 s 414322 2064 414322 2064 4 la_data_out[81]
+port 710 nsew
+rlabel metal2 s 417910 2064 417910 2064 4 la_data_out[82]
+port 711 nsew
+rlabel metal2 s 421406 2064 421406 2064 4 la_data_out[83]
+port 712 nsew
+rlabel metal2 s 424994 1214 424994 1214 4 la_data_out[84]
+port 713 nsew
+rlabel metal2 s 428490 2064 428490 2064 4 la_data_out[85]
+port 714 nsew
+rlabel metal2 s 429134 3264 429134 3264 4 la_data_out[86]
+port 715 nsew
+rlabel metal1 s 430146 3393 430146 3393 4 la_data_out[87]
+port 716 nsew
+rlabel metal2 s 439162 1520 439162 1520 4 la_data_out[88]
+port 717 nsew
+rlabel metal2 s 442658 1316 442658 1316 4 la_data_out[89]
+port 718 nsew
+rlabel metal2 s 155434 1758 155434 1758 4 la_data_out[8]
+port 719 nsew
+rlabel metal2 s 446246 1214 446246 1214 4 la_data_out[90]
+port 720 nsew
+rlabel metal2 s 449834 1282 449834 1282 4 la_data_out[91]
+port 721 nsew
+rlabel metal2 s 441278 2924 441278 2924 4 la_data_out[92]
+port 722 nsew
+rlabel metal1 s 443210 3393 443210 3393 4 la_data_out[93]
+port 723 nsew
+rlabel metal2 s 445694 3196 445694 3196 4 la_data_out[94]
+port 724 nsew
+rlabel metal2 s 448454 2924 448454 2924 4 la_data_out[95]
+port 725 nsew
+rlabel metal2 s 449834 3026 449834 3026 4 la_data_out[96]
+port 726 nsew
+rlabel metal2 s 452594 3026 452594 3026 4 la_data_out[97]
+port 727 nsew
+rlabel metal1 s 460920 2516 460920 2516 4 la_data_out[98]
+port 728 nsew
+rlabel metal1 s 458574 2720 458574 2720 4 la_data_out[99]
+port 729 nsew
+rlabel metal2 s 158930 1894 158930 1894 4 la_data_out[9]
+port 730 nsew
+rlabel metal2 s 429824 105883 429824 105883 4 p_reset_n
+port 731 nsew
+rlabel metal2 s 447166 398259 447166 398259 4 p_reset_n_rp
+port 732 nsew
+rlabel metal1 s 500046 14151 500046 14151 4 pinmux_debug\[0\]
+port 733 nsew
+rlabel metal1 s 502780 14151 502780 14151 4 pinmux_debug\[10\]
+port 734 nsew
+rlabel metal1 s 503038 14185 503038 14185 4 pinmux_debug\[11\]
+port 735 nsew
+rlabel metal1 s 503310 14151 503310 14151 4 pinmux_debug\[12\]
+port 736 nsew
+rlabel metal1 s 503582 14151 503582 14151 4 pinmux_debug\[13\]
+port 737 nsew
+rlabel metal1 s 503854 14219 503854 14219 4 pinmux_debug\[14\]
+port 738 nsew
+rlabel metal1 s 504114 14185 504114 14185 4 pinmux_debug\[15\]
+port 739 nsew
+rlabel metal1 s 504390 14151 504390 14151 4 pinmux_debug\[16\]
+port 740 nsew
+rlabel metal1 s 504666 14083 504666 14083 4 pinmux_debug\[17\]
+port 741 nsew
+rlabel metal1 s 504942 14151 504942 14151 4 pinmux_debug\[18\]
+port 742 nsew
+rlabel metal1 s 505218 14151 505218 14151 4 pinmux_debug\[19\]
+port 743 nsew
+rlabel metal1 s 500318 14185 500318 14185 4 pinmux_debug\[1\]
+port 744 nsew
+rlabel metal1 s 505494 14151 505494 14151 4 pinmux_debug\[20\]
+port 745 nsew
+rlabel metal1 s 505770 14185 505770 14185 4 pinmux_debug\[21\]
+port 746 nsew
+rlabel metal1 s 506030 14151 506030 14151 4 pinmux_debug\[22\]
+port 747 nsew
+rlabel metal1 s 506302 14151 506302 14151 4 pinmux_debug\[23\]
+port 748 nsew
+rlabel metal1 s 506574 14219 506574 14219 4 pinmux_debug\[24\]
+port 749 nsew
+rlabel metal1 s 506846 14151 506846 14151 4 pinmux_debug\[25\]
+port 750 nsew
+rlabel metal1 s 507104 14117 507104 14117 4 pinmux_debug\[26\]
+port 751 nsew
+rlabel metal1 s 507380 14185 507380 14185 4 pinmux_debug\[27\]
+port 752 nsew
+rlabel metal1 s 507656 14151 507656 14151 4 pinmux_debug\[28\]
+port 753 nsew
+rlabel metal1 s 507932 14219 507932 14219 4 pinmux_debug\[29\]
+port 754 nsew
+rlabel metal1 s 500590 14151 500590 14151 4 pinmux_debug\[2\]
+port 755 nsew
+rlabel metal1 s 508208 14185 508208 14185 4 pinmux_debug\[30\]
+port 756 nsew
+rlabel metal1 s 508484 14151 508484 14151 4 pinmux_debug\[31\]
+port 757 nsew
+rlabel metal1 s 500848 14151 500848 14151 4 pinmux_debug\[3\]
+port 758 nsew
+rlabel metal1 s 501124 14151 501124 14151 4 pinmux_debug\[4\]
+port 759 nsew
+rlabel metal1 s 501400 14117 501400 14117 4 pinmux_debug\[5\]
+port 760 nsew
+rlabel metal1 s 501676 14083 501676 14083 4 pinmux_debug\[6\]
+port 761 nsew
+rlabel metal1 s 501952 14049 501952 14049 4 pinmux_debug\[7\]
+port 762 nsew
+rlabel metal1 s 502228 14117 502228 14117 4 pinmux_debug\[8\]
+port 763 nsew
+rlabel metal1 s 502504 14219 502504 14219 4 pinmux_debug\[9\]
+port 764 nsew
+rlabel metal2 s 447166 366690 447166 366690 4 pll_clk_out\[0\]
+port 765 nsew
+rlabel metal2 s 530334 578860 530334 578860 4 pll_ref_clk
+port 766 nsew
+rlabel metal2 s 449919 70652 449919 70652 4 qspim_rst_n
+port 767 nsew
+rlabel metal2 s 504965 579020 504965 579020 4 reg_peri_ack
+port 768 nsew
+rlabel metal2 s 492085 579020 492085 579020 4 reg_peri_addr\[0\]
+port 769 nsew
+rlabel metal2 s 490475 579020 490475 579020 4 reg_peri_addr\[10\]
+port 770 nsew
+rlabel metal2 s 491924 563652 491924 563652 4 reg_peri_addr\[1\]
+port 771 nsew
+rlabel metal2 s 491740 563380 491740 563380 4 reg_peri_addr\[2\]
+port 772 nsew
+rlabel metal2 s 491602 563244 491602 563244 4 reg_peri_addr\[3\]
+port 773 nsew
+rlabel metal2 s 491418 563108 491418 563108 4 reg_peri_addr\[4\]
+port 774 nsew
+rlabel metal2 s 491395 579020 491395 579020 4 reg_peri_addr\[5\]
+port 775 nsew
+rlabel metal1 s 490590 563346 490590 563346 4 reg_peri_addr\[6\]
+port 776 nsew
+rlabel metal1 s 490636 563210 490636 563210 4 reg_peri_addr\[7\]
+port 777 nsew
+rlabel metal1 s 490452 563278 490452 563278 4 reg_peri_addr\[8\]
+port 778 nsew
+rlabel metal1 s 490268 563142 490268 563142 4 reg_peri_addr\[9\]
+port 779 nsew
+rlabel metal2 s 492913 579020 492913 579020 4 reg_peri_be\[0\]
+port 780 nsew
+rlabel metal1 s 493074 563414 493074 563414 4 reg_peri_be\[1\]
+port 781 nsew
+rlabel metal2 s 492683 579020 492683 579020 4 reg_peri_be\[2\]
+port 782 nsew
+rlabel metal1 s 491924 563754 491924 563754 4 reg_peri_be\[3\]
+port 783 nsew
+rlabel metal2 s 490107 579020 490107 579020 4 reg_peri_cs
+port 784 nsew
+rlabel metal2 s 504781 579020 504781 579020 4 reg_peri_rdata\[0\]
+port 785 nsew
+rlabel metal2 s 502941 579020 502941 579020 4 reg_peri_rdata\[10\]
+port 786 nsew
+rlabel metal2 s 502803 579020 502803 579020 4 reg_peri_rdata\[11\]
+port 787 nsew
+rlabel metal2 s 502573 579020 502573 579020 4 reg_peri_rdata\[12\]
+port 788 nsew
+rlabel metal2 s 502389 579020 502389 579020 4 reg_peri_rdata\[13\]
+port 789 nsew
+rlabel metal2 s 502205 579020 502205 579020 4 reg_peri_rdata\[14\]
+port 790 nsew
+rlabel metal2 s 502021 579020 502021 579020 4 reg_peri_rdata\[15\]
+port 791 nsew
+rlabel metal2 s 501837 579020 501837 579020 4 reg_peri_rdata\[16\]
+port 792 nsew
+rlabel metal2 s 501699 579020 501699 579020 4 reg_peri_rdata\[17\]
+port 793 nsew
+rlabel metal2 s 501515 579020 501515 579020 4 reg_peri_rdata\[18\]
+port 794 nsew
+rlabel metal2 s 501285 579020 501285 579020 4 reg_peri_rdata\[19\]
+port 795 nsew
+rlabel metal2 s 504643 579020 504643 579020 4 reg_peri_rdata\[1\]
+port 796 nsew
+rlabel metal2 s 501101 579020 501101 579020 4 reg_peri_rdata\[20\]
+port 797 nsew
+rlabel metal2 s 500963 579020 500963 579020 4 reg_peri_rdata\[21\]
+port 798 nsew
+rlabel metal2 s 500733 579020 500733 579020 4 reg_peri_rdata\[22\]
+port 799 nsew
+rlabel metal2 s 500549 579020 500549 579020 4 reg_peri_rdata\[23\]
+port 800 nsew
+rlabel metal2 s 500365 579020 500365 579020 4 reg_peri_rdata\[24\]
+port 801 nsew
+rlabel metal2 s 500227 579020 500227 579020 4 reg_peri_rdata\[25\]
+port 802 nsew
+rlabel metal2 s 500043 579020 500043 579020 4 reg_peri_rdata\[26\]
+port 803 nsew
+rlabel metal2 s 499859 579020 499859 579020 4 reg_peri_rdata\[27\]
+port 804 nsew
+rlabel metal2 s 499675 579020 499675 579020 4 reg_peri_rdata\[28\]
+port 805 nsew
+rlabel metal2 s 499445 579020 499445 579020 4 reg_peri_rdata\[29\]
+port 806 nsew
+rlabel metal2 s 504321 579020 504321 579020 4 reg_peri_rdata\[2\]
+port 807 nsew
+rlabel metal2 s 499261 579020 499261 579020 4 reg_peri_rdata\[30\]
+port 808 nsew
+rlabel metal2 s 499077 579020 499077 579020 4 reg_peri_rdata\[31\]
+port 809 nsew
+rlabel metal1 s 504022 579020 504022 579020 4 reg_peri_rdata\[3\]
+port 810 nsew
+rlabel metal2 s 504091 579020 504091 579020 4 reg_peri_rdata\[4\]
+port 811 nsew
+rlabel metal2 s 503907 579020 503907 579020 4 reg_peri_rdata\[5\]
+port 812 nsew
+rlabel metal2 s 503723 579020 503723 579020 4 reg_peri_rdata\[6\]
+port 813 nsew
+rlabel metal2 s 503493 579020 503493 579020 4 reg_peri_rdata\[7\]
+port 814 nsew
+rlabel metal2 s 503309 579020 503309 579020 4 reg_peri_rdata\[8\]
+port 815 nsew
+rlabel metal1 s 502872 578034 502872 578034 4 reg_peri_rdata\[9\]
+port 816 nsew
+rlabel metal1 s 498732 578034 498732 578034 4 reg_peri_wdata\[0\]
+port 817 nsew
+rlabel metal1 s 497490 579020 497490 579020 4 reg_peri_wdata\[10\]
+port 818 nsew
+rlabel metal2 s 497007 579020 497007 579020 4 reg_peri_wdata\[11\]
+port 819 nsew
+rlabel metal2 s 496685 579020 496685 579020 4 reg_peri_wdata\[12\]
+port 820 nsew
+rlabel metal2 s 496501 579020 496501 579020 4 reg_peri_wdata\[13\]
+port 821 nsew
+rlabel metal2 s 496317 579020 496317 579020 4 reg_peri_wdata\[14\]
+port 822 nsew
+rlabel metal2 s 496179 579020 496179 579020 4 reg_peri_wdata\[15\]
+port 823 nsew
+rlabel metal2 s 495995 579020 495995 579020 4 reg_peri_wdata\[16\]
+port 824 nsew
+rlabel metal2 s 495765 579020 495765 579020 4 reg_peri_wdata\[17\]
+port 825 nsew
+rlabel metal2 s 495581 579020 495581 579020 4 reg_peri_wdata\[18\]
+port 826 nsew
+rlabel metal2 s 495443 579020 495443 579020 4 reg_peri_wdata\[19\]
+port 827 nsew
+rlabel metal2 s 498709 579020 498709 579020 4 reg_peri_wdata\[1\]
+port 828 nsew
+rlabel metal1 s 494684 563142 494684 563142 4 reg_peri_wdata\[20\]
+port 829 nsew
+rlabel metal1 s 494638 563210 494638 563210 4 reg_peri_wdata\[21\]
+port 830 nsew
+rlabel metal2 s 494845 579020 494845 579020 4 reg_peri_wdata\[22\]
+port 831 nsew
+rlabel metal1 s 494408 563278 494408 563278 4 reg_peri_wdata\[23\]
+port 832 nsew
+rlabel metal2 s 494523 579020 494523 579020 4 reg_peri_wdata\[24\]
+port 833 nsew
+rlabel metal2 s 494339 579020 494339 579020 4 reg_peri_wdata\[25\]
+port 834 nsew
+rlabel metal2 s 494155 579020 494155 579020 4 reg_peri_wdata\[26\]
+port 835 nsew
+rlabel metal1 s 493580 563074 493580 563074 4 reg_peri_wdata\[27\]
+port 836 nsew
+rlabel metal1 s 493718 563244 493718 563244 4 reg_peri_wdata\[28\]
+port 837 nsew
+rlabel metal1 s 493304 563142 493304 563142 4 reg_peri_wdata\[29\]
+port 838 nsew
+rlabel metal1 s 498870 579088 498870 579088 4 reg_peri_wdata\[2\]
+port 839 nsew
+rlabel metal2 s 493396 563142 493396 563142 4 reg_peri_wdata\[30\]
+port 840 nsew
+rlabel metal1 s 493028 563210 493028 563210 4 reg_peri_wdata\[31\]
+port 841 nsew
+rlabel metal2 s 498479 579020 498479 579020 4 reg_peri_wdata\[3\]
+port 842 nsew
+rlabel metal2 s 498203 579020 498203 579020 4 reg_peri_wdata\[4\]
+port 843 nsew
+rlabel metal2 s 497973 579020 497973 579020 4 reg_peri_wdata\[5\]
+port 844 nsew
+rlabel metal2 s 497789 579020 497789 579020 4 reg_peri_wdata\[6\]
+port 845 nsew
+rlabel metal2 s 497651 579020 497651 579020 4 reg_peri_wdata\[7\]
+port 846 nsew
+rlabel metal2 s 497421 579020 497421 579020 4 reg_peri_wdata\[8\]
+port 847 nsew
+rlabel metal2 s 497283 579020 497283 579020 4 reg_peri_wdata\[9\]
+port 848 nsew
+rlabel metal2 s 490176 563142 490176 563142 4 reg_peri_wr
+port 849 nsew
+rlabel metal2 s 480401 579020 480401 579020 4 rtc_intr
+port 850 nsew
+rlabel metal3 s 541504 171020 541504 171020 4 sflash_di\[0\]
+port 851 nsew
+rlabel metal3 s 541780 170748 541780 170748 4 sflash_di\[1\]
+port 852 nsew
+rlabel metal3 s 541596 170476 541596 170476 4 sflash_di\[2\]
+port 853 nsew
+rlabel metal3 s 541688 170204 541688 170204 4 sflash_di\[3\]
+port 854 nsew
+rlabel metal3 s 541642 172108 541642 172108 4 sflash_do\[0\]
+port 855 nsew
+rlabel metal3 s 541734 171836 541734 171836 4 sflash_do\[1\]
+port 856 nsew
+rlabel metal3 s 541550 171564 541550 171564 4 sflash_do\[2\]
+port 857 nsew
+rlabel metal3 s 541458 171292 541458 171292 4 sflash_do\[3\]
+port 858 nsew
+rlabel metal3 s 541780 174556 541780 174556 4 sflash_oen\[0\]
+port 859 nsew
+rlabel metal3 s 541182 174284 541182 174284 4 sflash_oen\[1\]
+port 860 nsew
+rlabel metal3 s 541826 174012 541826 174012 4 sflash_oen\[2\]
+port 861 nsew
+rlabel metal3 s 541780 173740 541780 173740 4 sflash_oen\[3\]
+port 862 nsew
+rlabel metal3 s 541780 172380 541780 172380 4 sflash_sck
+port 863 nsew
+rlabel metal2 s 447166 420257 447166 420257 4 soft_irq
+port 864 nsew
+rlabel metal3 s 541228 173468 541228 173468 4 spi_csn\[0\]
+port 865 nsew
+rlabel metal3 s 541182 173196 541182 173196 4 spi_csn\[1\]
+port 866 nsew
+rlabel metal3 s 541458 172924 541458 172924 4 spi_csn\[2\]
+port 867 nsew
+rlabel metal3 s 541780 172652 541780 172652 4 spi_csn\[3\]
+port 868 nsew
+rlabel metal1 s 460062 14151 460062 14151 4 spi_debug\[0\]
+port 869 nsew
+rlabel metal1 s 462782 14151 462782 14151 4 spi_debug\[10\]
+port 870 nsew
+rlabel metal1 s 463054 14015 463054 14015 4 spi_debug\[11\]
+port 871 nsew
+rlabel metal1 s 463312 14219 463312 14219 4 spi_debug\[12\]
+port 872 nsew
+rlabel metal1 s 463588 14253 463588 14253 4 spi_debug\[13\]
+port 873 nsew
+rlabel metal1 s 463864 14219 463864 14219 4 spi_debug\[14\]
+port 874 nsew
+rlabel metal1 s 464140 14151 464140 14151 4 spi_debug\[15\]
+port 875 nsew
+rlabel metal1 s 464416 14151 464416 14151 4 spi_debug\[16\]
+port 876 nsew
+rlabel metal1 s 464692 14083 464692 14083 4 spi_debug\[17\]
+port 877 nsew
+rlabel metal1 s 464968 14185 464968 14185 4 spi_debug\[18\]
+port 878 nsew
+rlabel metal1 s 465244 14083 465244 14083 4 spi_debug\[19\]
+port 879 nsew
+rlabel metal1 s 460322 14185 460322 14185 4 spi_debug\[1\]
+port 880 nsew
+rlabel metal1 s 465502 14083 465502 14083 4 spi_debug\[20\]
+port 881 nsew
+rlabel metal1 s 465774 14117 465774 14117 4 spi_debug\[21\]
+port 882 nsew
+rlabel metal1 s 466046 14185 466046 14185 4 spi_debug\[22\]
+port 883 nsew
+rlabel metal1 s 466318 14185 466318 14185 4 spi_debug\[23\]
+port 884 nsew
+rlabel metal1 s 466578 14185 466578 14185 4 spi_debug\[24\]
+port 885 nsew
+rlabel metal1 s 466854 14117 466854 14117 4 spi_debug\[25\]
+port 886 nsew
+rlabel metal1 s 467130 14151 467130 14151 4 spi_debug\[26\]
+port 887 nsew
+rlabel metal1 s 467406 14219 467406 14219 4 spi_debug\[27\]
+port 888 nsew
+rlabel metal1 s 467682 14151 467682 14151 4 spi_debug\[28\]
+port 889 nsew
+rlabel metal1 s 467958 14151 467958 14151 4 spi_debug\[29\]
+port 890 nsew
+rlabel metal1 s 460598 14219 460598 14219 4 spi_debug\[2\]
+port 891 nsew
+rlabel metal1 s 468234 14151 468234 14151 4 spi_debug\[30\]
+port 892 nsew
+rlabel metal1 s 468494 14185 468494 14185 4 spi_debug\[31\]
+port 893 nsew
+rlabel metal1 s 460874 14253 460874 14253 4 spi_debug\[3\]
+port 894 nsew
+rlabel metal1 s 461150 14219 461150 14219 4 spi_debug\[4\]
+port 895 nsew
+rlabel metal1 s 461426 14151 461426 14151 4 spi_debug\[5\]
+port 896 nsew
+rlabel metal1 s 461702 14185 461702 14185 4 spi_debug\[6\]
+port 897 nsew
+rlabel metal1 s 461978 14355 461978 14355 4 spi_debug\[7\]
+port 898 nsew
+rlabel metal1 s 462238 14389 462238 14389 4 spi_debug\[8\]
+port 899 nsew
+rlabel metal1 s 462510 14185 462510 14185 4 spi_debug\[9\]
+port 900 nsew
+rlabel metal1 s 450110 361794 450110 361794 4 sspim_rst_n
+port 901 nsew
+rlabel metal2 s 453422 360968 453422 360968 4 sspim_sck
+port 902 nsew
+rlabel metal2 s 453606 360798 453606 360798 4 sspim_si
+port 903 nsew
+rlabel metal2 s 453790 360866 453790 360866 4 sspim_so
+port 904 nsew
+rlabel metal2 s 454526 360934 454526 360934 4 sspim_ssn\[0\]
+port 905 nsew
+rlabel metal2 s 454342 360900 454342 360900 4 sspim_ssn\[1\]
+port 906 nsew
+rlabel metal2 s 454158 360764 454158 360764 4 sspim_ssn\[2\]
+port 907 nsew
+rlabel metal2 s 453974 360832 453974 360832 4 sspim_ssn\[3\]
+port 908 nsew
+rlabel metal3 s 436578 80716 436578 80716 4 sspis_sck
+port 909 nsew
+rlabel metal2 s 461058 370879 461058 370879 4 sspis_si
+port 910 nsew
+rlabel metal2 s 447810 221850 447810 221850 4 sspis_so
+port 911 nsew
+rlabel metal2 s 443762 225114 443762 225114 4 sspis_ssn
+port 912 nsew
+rlabel metal3 s 447166 388637 447166 388637 4 strap_sticky\[0\]
+port 913 nsew
+rlabel metal3 s 447166 385883 447166 385883 4 strap_sticky\[10\]
+port 914 nsew
+rlabel metal2 s 447350 385781 447350 385781 4 strap_sticky\[11\]
+port 915 nsew
+rlabel metal2 s 447258 385577 447258 385577 4 strap_sticky\[12\]
+port 916 nsew
+rlabel metal2 s 447166 385407 447166 385407 4 strap_sticky\[13\]
+port 917 nsew
+rlabel metal2 s 447350 384625 447350 384625 4 strap_sticky\[14\]
+port 918 nsew
+rlabel metal2 s 447166 384421 447166 384421 4 strap_sticky\[15\]
+port 919 nsew
+rlabel metal2 s 447258 384387 447258 384387 4 strap_sticky\[16\]
+port 920 nsew
+rlabel metal2 s 447534 384285 447534 384285 4 strap_sticky\[17\]
+port 921 nsew
+rlabel metal2 s 447442 384047 447442 384047 4 strap_sticky\[18\]
+port 922 nsew
+rlabel metal2 s 447442 383197 447442 383197 4 strap_sticky\[19\]
+port 923 nsew
+rlabel metal2 s 447350 388535 447350 388535 4 strap_sticky\[1\]
+port 924 nsew
+rlabel metal3 s 447166 383197 447166 383197 4 strap_sticky\[20\]
+port 925 nsew
+rlabel metal2 s 447166 382993 447166 382993 4 strap_sticky\[21\]
+port 926 nsew
+rlabel metal2 s 447350 382891 447350 382891 4 strap_sticky\[22\]
+port 927 nsew
+rlabel metal2 s 447258 382687 447258 382687 4 strap_sticky\[23\]
+port 928 nsew
+rlabel metal2 s 447442 381837 447442 381837 4 strap_sticky\[24\]
+port 929 nsew
+rlabel metal3 s 447166 381803 447166 381803 4 strap_sticky\[25\]
+port 930 nsew
+rlabel metal2 s 447258 381633 447258 381633 4 strap_sticky\[26\]
+port 931 nsew
+rlabel metal2 s 447350 381463 447350 381463 4 strap_sticky\[27\]
+port 932 nsew
+rlabel metal2 s 447166 381259 447166 381259 4 strap_sticky\[28\]
+port 933 nsew
+rlabel metal2 s 447350 380443 447350 380443 4 strap_sticky\[29\]
+port 934 nsew
+rlabel metal2 s 447258 388331 447258 388331 4 strap_sticky\[2\]
+port 935 nsew
+rlabel metal2 s 447258 380375 447258 380375 4 strap_sticky\[30\]
+port 936 nsew
+rlabel metal3 s 447166 380205 447166 380205 4 strap_sticky\[31\]
+port 937 nsew
+rlabel metal2 s 447166 388161 447166 388161 4 strap_sticky\[3\]
+port 938 nsew
+rlabel metal2 s 447442 387311 447442 387311 4 strap_sticky\[4\]
+port 939 nsew
+rlabel metal3 s 447166 387277 447166 387277 4 strap_sticky\[5\]
+port 940 nsew
+rlabel metal2 s 447350 387175 447350 387175 4 strap_sticky\[6\]
+port 941 nsew
+rlabel metal2 s 447258 386971 447258 386971 4 strap_sticky\[7\]
+port 942 nsew
+rlabel metal2 s 447166 386801 447166 386801 4 strap_sticky\[8\]
+port 943 nsew
+rlabel metal2 s 447442 385917 447442 385917 4 strap_sticky\[9\]
+port 944 nsew
+rlabel metal2 s 423016 105883 423016 105883 4 strap_sticky_rp\[0\]
+port 945 nsew
+rlabel metal2 s 421176 105883 421176 105883 4 strap_sticky_rp\[10\]
+port 946 nsew
+rlabel metal2 s 420992 105883 420992 105883 4 strap_sticky_rp\[11\]
+port 947 nsew
+rlabel metal2 s 420808 105883 420808 105883 4 strap_sticky_rp\[12\]
+port 948 nsew
+rlabel metal2 s 420624 105883 420624 105883 4 strap_sticky_rp\[13\]
+port 949 nsew
+rlabel metal2 s 420440 105883 420440 105883 4 strap_sticky_rp\[14\]
+port 950 nsew
+rlabel metal2 s 420256 105883 420256 105883 4 strap_sticky_rp\[15\]
+port 951 nsew
+rlabel metal2 s 420072 105866 420072 105866 4 strap_sticky_rp\[16\]
+port 952 nsew
+rlabel metal2 s 419888 105883 419888 105883 4 strap_sticky_rp\[17\]
+port 953 nsew
+rlabel metal2 s 419704 105883 419704 105883 4 strap_sticky_rp\[18\]
+port 954 nsew
+rlabel metal2 s 419520 105883 419520 105883 4 strap_sticky_rp\[19\]
+port 955 nsew
+rlabel metal2 s 422832 105883 422832 105883 4 strap_sticky_rp\[1\]
+port 956 nsew
+rlabel metal2 s 419336 105883 419336 105883 4 strap_sticky_rp\[20\]
+port 957 nsew
+rlabel metal2 s 419152 105883 419152 105883 4 strap_sticky_rp\[21\]
+port 958 nsew
+rlabel metal2 s 418968 105883 418968 105883 4 strap_sticky_rp\[22\]
+port 959 nsew
+rlabel metal2 s 418784 105883 418784 105883 4 strap_sticky_rp\[23\]
+port 960 nsew
+rlabel metal2 s 418600 105883 418600 105883 4 strap_sticky_rp\[24\]
+port 961 nsew
+rlabel metal2 s 418416 105883 418416 105883 4 strap_sticky_rp\[25\]
+port 962 nsew
+rlabel metal2 s 418232 105883 418232 105883 4 strap_sticky_rp\[26\]
+port 963 nsew
+rlabel metal2 s 418048 105883 418048 105883 4 strap_sticky_rp\[27\]
+port 964 nsew
+rlabel metal2 s 417864 105883 417864 105883 4 strap_sticky_rp\[28\]
+port 965 nsew
+rlabel metal2 s 417680 105883 417680 105883 4 strap_sticky_rp\[29\]
+port 966 nsew
+rlabel metal2 s 422648 105883 422648 105883 4 strap_sticky_rp\[2\]
+port 967 nsew
+rlabel metal2 s 417496 105883 417496 105883 4 strap_sticky_rp\[30\]
+port 968 nsew
+rlabel metal2 s 417312 105883 417312 105883 4 strap_sticky_rp\[31\]
+port 969 nsew
+rlabel metal2 s 422464 105883 422464 105883 4 strap_sticky_rp\[3\]
+port 970 nsew
+rlabel metal2 s 422280 105883 422280 105883 4 strap_sticky_rp\[4\]
+port 971 nsew
+rlabel metal2 s 422096 105883 422096 105883 4 strap_sticky_rp\[5\]
+port 972 nsew
+rlabel metal2 s 421912 105883 421912 105883 4 strap_sticky_rp\[6\]
+port 973 nsew
+rlabel metal2 s 421728 105883 421728 105883 4 strap_sticky_rp\[7\]
+port 974 nsew
+rlabel metal2 s 421544 105883 421544 105883 4 strap_sticky_rp\[8\]
+port 975 nsew
+rlabel metal2 s 421360 105883 421360 105883 4 strap_sticky_rp\[9\]
+port 976 nsew
+rlabel metal2 s 447626 389657 447626 389657 4 strap_uartm\[0\]
+port 977 nsew
+rlabel metal2 s 447442 388671 447442 388671 4 strap_uartm\[1\]
+port 978 nsew
+rlabel metal2 s 423384 105883 423384 105883 4 strap_uartm_rp\[0\]
+port 979 nsew
+rlabel metal2 s 423200 105883 423200 105883 4 strap_uartm_rp\[1\]
+port 980 nsew
+rlabel metal2 s 429272 105883 429272 105883 4 system_strap\[0\]
+port 981 nsew
+rlabel metal2 s 427432 105883 427432 105883 4 system_strap\[10\]
+port 982 nsew
+rlabel metal2 s 427248 105883 427248 105883 4 system_strap\[11\]
+port 983 nsew
+rlabel metal2 s 427064 105883 427064 105883 4 system_strap\[12\]
+port 984 nsew
+rlabel metal2 s 426880 105883 426880 105883 4 system_strap\[13\]
+port 985 nsew
+rlabel metal2 s 426696 105883 426696 105883 4 system_strap\[14\]
+port 986 nsew
+rlabel metal2 s 426512 105883 426512 105883 4 system_strap\[15\]
+port 987 nsew
+rlabel metal2 s 426328 105883 426328 105883 4 system_strap\[16\]
+port 988 nsew
+rlabel metal2 s 426144 105883 426144 105883 4 system_strap\[17\]
+port 989 nsew
+rlabel metal2 s 425960 105883 425960 105883 4 system_strap\[18\]
+port 990 nsew
+rlabel metal2 s 425776 105883 425776 105883 4 system_strap\[19\]
+port 991 nsew
+rlabel metal2 s 429088 105883 429088 105883 4 system_strap\[1\]
+port 992 nsew
+rlabel metal2 s 425592 105866 425592 105866 4 system_strap\[20\]
+port 993 nsew
+rlabel metal2 s 425408 105815 425408 105815 4 system_strap\[21\]
+port 994 nsew
+rlabel metal2 s 425224 105883 425224 105883 4 system_strap\[22\]
+port 995 nsew
+rlabel metal2 s 425040 105883 425040 105883 4 system_strap\[23\]
+port 996 nsew
+rlabel metal2 s 424856 105883 424856 105883 4 system_strap\[24\]
+port 997 nsew
+rlabel metal2 s 424672 105883 424672 105883 4 system_strap\[25\]
+port 998 nsew
+rlabel metal2 s 424488 105883 424488 105883 4 system_strap\[26\]
+port 999 nsew
+rlabel metal2 s 424304 105883 424304 105883 4 system_strap\[27\]
+port 1000 nsew
+rlabel metal2 s 424120 105866 424120 105866 4 system_strap\[28\]
+port 1001 nsew
+rlabel metal2 s 423936 105866 423936 105866 4 system_strap\[29\]
+port 1002 nsew
+rlabel metal2 s 428904 105883 428904 105883 4 system_strap\[2\]
+port 1003 nsew
+rlabel metal2 s 423752 105883 423752 105883 4 system_strap\[30\]
+port 1004 nsew
+rlabel metal2 s 423568 105883 423568 105883 4 system_strap\[31\]
+port 1005 nsew
+rlabel metal2 s 428720 105883 428720 105883 4 system_strap\[3\]
+port 1006 nsew
+rlabel metal2 s 428536 105883 428536 105883 4 system_strap\[4\]
+port 1007 nsew
+rlabel metal2 s 428352 105883 428352 105883 4 system_strap\[5\]
+port 1008 nsew
+rlabel metal2 s 428168 105883 428168 105883 4 system_strap\[6\]
+port 1009 nsew
+rlabel metal2 s 427984 105883 427984 105883 4 system_strap\[7\]
+port 1010 nsew
+rlabel metal2 s 427800 105883 427800 105883 4 system_strap\[8\]
+port 1011 nsew
+rlabel metal2 s 427616 105883 427616 105883 4 system_strap\[9\]
+port 1012 nsew
+rlabel metal2 s 447442 398089 447442 398089 4 system_strap_rp\[0\]
+port 1013 nsew
+rlabel metal2 s 447350 395301 447350 395301 4 system_strap_rp\[10\]
+port 1014 nsew
+rlabel metal2 s 447166 395131 447166 395131 4 system_strap_rp\[11\]
+port 1015 nsew
+rlabel metal2 s 447350 394349 447350 394349 4 system_strap_rp\[12\]
+port 1016 nsew
+rlabel metal2 s 447442 394145 447442 394145 4 system_strap_rp\[13\]
+port 1017 nsew
+rlabel metal2 s 447258 394145 447258 394145 4 system_strap_rp\[14\]
+port 1018 nsew
+rlabel metal2 s 447166 393907 447166 393907 4 system_strap_rp\[15\]
+port 1019 nsew
+rlabel metal2 s 447534 393839 447534 393839 4 system_strap_rp\[16\]
+port 1020 nsew
+rlabel metal2 s 447442 392955 447442 392955 4 system_strap_rp\[17\]
+port 1021 nsew
+rlabel metal2 s 447258 392853 447258 392853 4 system_strap_rp\[18\]
+port 1022 nsew
+rlabel metal2 s 447166 392785 447166 392785 4 system_strap_rp\[19\]
+port 1023 nsew
+rlabel metal2 s 447350 397885 447350 397885 4 system_strap_rp\[1\]
+port 1024 nsew
+rlabel metal2 s 447350 392615 447350 392615 4 system_strap_rp\[20\]
+port 1025 nsew
+rlabel metal2 s 447166 392377 447166 392377 4 system_strap_rp\[21\]
+port 1026 nsew
+rlabel metal2 s 447442 391595 447442 391595 4 system_strap_rp\[22\]
+port 1027 nsew
+rlabel metal2 s 447350 391425 447350 391425 4 system_strap_rp\[23\]
+port 1028 nsew
+rlabel metal3 s 447166 391357 447166 391357 4 system_strap_rp\[24\]
+port 1029 nsew
+rlabel metal2 s 447258 391255 447258 391255 4 system_strap_rp\[25\]
+port 1030 nsew
+rlabel metal2 s 447534 391153 447534 391153 4 system_strap_rp\[26\]
+port 1031 nsew
+rlabel metal2 s 447442 390201 447442 390201 4 system_strap_rp\[27\]
+port 1032 nsew
+rlabel metal2 s 447258 390099 447258 390099 4 system_strap_rp\[28\]
+port 1033 nsew
+rlabel metal2 s 447166 389895 447166 389895 4 system_strap_rp\[29\]
+port 1034 nsew
+rlabel metal2 s 447442 397069 447442 397069 4 system_strap_rp\[2\]
+port 1035 nsew
+rlabel metal2 s 447350 389861 447350 389861 4 system_strap_rp\[30\]
+port 1036 nsew
+rlabel metal2 s 447534 389759 447534 389759 4 system_strap_rp\[31\]
+port 1037 nsew
+rlabel metal3 s 447166 397035 447166 397035 4 system_strap_rp\[3\]
+port 1038 nsew
+rlabel metal2 s 447166 396831 447166 396831 4 system_strap_rp\[4\]
+port 1039 nsew
+rlabel metal2 s 447350 396729 447350 396729 4 system_strap_rp\[5\]
+port 1040 nsew
+rlabel metal2 s 447258 396491 447258 396491 4 system_strap_rp\[6\]
+port 1041 nsew
+rlabel metal2 s 447442 395641 447442 395641 4 system_strap_rp\[7\]
+port 1042 nsew
+rlabel metal2 s 447166 395641 447166 395641 4 system_strap_rp\[8\]
+port 1043 nsew
+rlabel metal2 s 447258 395471 447258 395471 4 system_strap_rp\[9\]
+port 1044 nsew
+rlabel metal2 s 367218 264537 367218 264537 4 u_riscv_top.cfg_ccska_riscv_core0\[0\]
+port 1045 nsew
+rlabel metal2 s 367126 264333 367126 264333 4 u_riscv_top.cfg_ccska_riscv_core0\[1\]
+port 1046 nsew
+rlabel metal2 s 367402 264231 367402 264231 4 u_riscv_top.cfg_ccska_riscv_core0\[2\]
+port 1047 nsew
+rlabel metal2 s 367310 263789 367310 263789 4 u_riscv_top.cfg_ccska_riscv_core0\[3\]
+port 1048 nsew
+rlabel metal3 s 369112 263092 369112 263092 4 u_riscv_top.cfg_ccska_riscv_core1\[0\]
+port 1049 nsew
+rlabel metal3 s 368974 262820 368974 262820 4 u_riscv_top.cfg_ccska_riscv_core1\[1\]
+port 1050 nsew
+rlabel metal3 s 369204 262548 369204 262548 4 u_riscv_top.cfg_ccska_riscv_core1\[2\]
+port 1051 nsew
+rlabel metal2 s 367218 262905 367218 262905 4 u_riscv_top.cfg_ccska_riscv_core1\[3\]
+port 1052 nsew
+rlabel metal2 s 367218 262089 367218 262089 4 u_riscv_top.cfg_ccska_riscv_core2\[0\]
+port 1053 nsew
+rlabel metal2 s 367126 261919 367126 261919 4 u_riscv_top.cfg_ccska_riscv_core2\[1\]
+port 1054 nsew
+rlabel metal4 s 139932 395760 139932 395760 4 u_riscv_top.cfg_ccska_riscv_core2\[2\]
+port 1055 nsew
+rlabel metal4 s 140116 395692 140116 395692 4 u_riscv_top.cfg_ccska_riscv_core2\[3\]
+port 1056 nsew
+rlabel metal2 s 367310 261477 367310 261477 4 u_riscv_top.cfg_ccska_riscv_core3\[0\]
+port 1057 nsew
+rlabel metal3 s 368238 260644 368238 260644 4 u_riscv_top.cfg_ccska_riscv_core3\[1\]
+port 1058 nsew
+rlabel metal2 s 367218 260559 367218 260559 4 u_riscv_top.cfg_ccska_riscv_core3\[2\]
+port 1059 nsew
+rlabel metal2 s 367310 260389 367310 260389 4 u_riscv_top.cfg_ccska_riscv_core3\[3\]
+port 1060 nsew
+rlabel metal2 s 230414 280483 230414 280483 4 u_riscv_top.cfg_ccska_riscv_icon\[0\]
+port 1061 nsew
+rlabel metal2 s 367310 280347 367310 280347 4 u_riscv_top.cfg_ccska_riscv_icon\[1\]
+port 1062 nsew
+rlabel metal2 s 367126 280177 367126 280177 4 u_riscv_top.cfg_ccska_riscv_icon\[2\]
+port 1063 nsew
+rlabel metal2 s 367218 279769 367218 279769 4 u_riscv_top.cfg_ccska_riscv_icon\[3\]
+port 1064 nsew
+rlabel metal2 s 347714 130713 347714 130713 4 u_riscv_top.cfg_ccska_riscv_intf\[0\]
+port 1065 nsew
+rlabel metal2 s 345230 129421 345230 129421 4 u_riscv_top.cfg_ccska_riscv_intf\[1\]
+port 1066 nsew
+rlabel metal2 s 345138 129319 345138 129319 4 u_riscv_top.cfg_ccska_riscv_intf\[2\]
+port 1067 nsew
+rlabel metal2 s 367218 130033 367218 130033 4 u_riscv_top.cfg_ccska_riscv_intf\[3\]
+port 1068 nsew
+rlabel metal2 s 249550 257064 249550 257064 4 u_riscv_top.cfg_dcache_force_flush
+port 1069 nsew
+rlabel metal2 s 346794 141219 346794 141219 4 u_riscv_top.cfg_wcska_riscv_intf\[0\]
+port 1070 nsew
+rlabel metal2 s 346794 140437 346794 140437 4 u_riscv_top.cfg_wcska_riscv_intf\[1\]
+port 1071 nsew
+rlabel metal2 s 347622 140267 347622 140267 4 u_riscv_top.cfg_wcska_riscv_intf\[2\]
+port 1072 nsew
+rlabel metal2 s 347714 140097 347714 140097 4 u_riscv_top.cfg_wcska_riscv_intf\[3\]
+port 1073 nsew
+rlabel metal3 s 130540 320212 130540 320212 4 u_riscv_top.core0_clk
+port 1074 nsew
+rlabel metal3 s 130678 393244 130678 393244 4 u_riscv_top.core0_debug\[0\]
+port 1075 nsew
+rlabel metal3 s 130494 390524 130494 390524 4 u_riscv_top.core0_debug\[10\]
+port 1076 nsew
+rlabel metal3 s 130540 390252 130540 390252 4 u_riscv_top.core0_debug\[11\]
+port 1077 nsew
+rlabel metal3 s 130494 389980 130494 389980 4 u_riscv_top.core0_debug\[12\]
+port 1078 nsew
+rlabel metal3 s 130586 389708 130586 389708 4 u_riscv_top.core0_debug\[13\]
+port 1079 nsew
+rlabel metal3 s 130540 389436 130540 389436 4 u_riscv_top.core0_debug\[14\]
+port 1080 nsew
+rlabel metal3 s 130632 389164 130632 389164 4 u_riscv_top.core0_debug\[15\]
+port 1081 nsew
+rlabel metal3 s 130540 388892 130540 388892 4 u_riscv_top.core0_debug\[16\]
+port 1082 nsew
+rlabel metal3 s 130494 388620 130494 388620 4 u_riscv_top.core0_debug\[17\]
+port 1083 nsew
+rlabel metal3 s 130494 388348 130494 388348 4 u_riscv_top.core0_debug\[18\]
+port 1084 nsew
+rlabel metal3 s 130586 388076 130586 388076 4 u_riscv_top.core0_debug\[19\]
+port 1085 nsew
+rlabel metal3 s 130540 392972 130540 392972 4 u_riscv_top.core0_debug\[1\]
+port 1086 nsew
+rlabel metal3 s 130540 387804 130540 387804 4 u_riscv_top.core0_debug\[20\]
+port 1087 nsew
+rlabel metal3 s 130632 387532 130632 387532 4 u_riscv_top.core0_debug\[21\]
+port 1088 nsew
+rlabel metal3 s 130494 387260 130494 387260 4 u_riscv_top.core0_debug\[22\]
+port 1089 nsew
+rlabel metal3 s 130586 386988 130586 386988 4 u_riscv_top.core0_debug\[23\]
+port 1090 nsew
+rlabel metal3 s 130540 386716 130540 386716 4 u_riscv_top.core0_debug\[24\]
+port 1091 nsew
+rlabel metal3 s 130678 386444 130678 386444 4 u_riscv_top.core0_debug\[25\]
+port 1092 nsew
+rlabel metal3 s 130540 386172 130540 386172 4 u_riscv_top.core0_debug\[26\]
+port 1093 nsew
+rlabel metal3 s 130494 385900 130494 385900 4 u_riscv_top.core0_debug\[27\]
+port 1094 nsew
+rlabel metal3 s 130494 385628 130494 385628 4 u_riscv_top.core0_debug\[28\]
+port 1095 nsew
+rlabel metal3 s 130540 385356 130540 385356 4 u_riscv_top.core0_debug\[29\]
+port 1096 nsew
+rlabel metal3 s 130494 392700 130494 392700 4 u_riscv_top.core0_debug\[2\]
+port 1097 nsew
+rlabel metal3 s 130586 385084 130586 385084 4 u_riscv_top.core0_debug\[30\]
+port 1098 nsew
+rlabel metal3 s 130632 384812 130632 384812 4 u_riscv_top.core0_debug\[31\]
+port 1099 nsew
+rlabel metal3 s 130494 384540 130494 384540 4 u_riscv_top.core0_debug\[32\]
+port 1100 nsew
+rlabel metal3 s 130494 384268 130494 384268 4 u_riscv_top.core0_debug\[33\]
+port 1101 nsew
+rlabel metal3 s 130586 383996 130586 383996 4 u_riscv_top.core0_debug\[34\]
+port 1102 nsew
+rlabel metal3 s 130540 383724 130540 383724 4 u_riscv_top.core0_debug\[35\]
+port 1103 nsew
+rlabel metal3 s 130586 383452 130586 383452 4 u_riscv_top.core0_debug\[36\]
+port 1104 nsew
+rlabel metal3 s 130494 383180 130494 383180 4 u_riscv_top.core0_debug\[37\]
+port 1105 nsew
+rlabel metal3 s 130540 382908 130540 382908 4 u_riscv_top.core0_debug\[38\]
+port 1106 nsew
+rlabel metal3 s 130678 382636 130678 382636 4 u_riscv_top.core0_debug\[39\]
+port 1107 nsew
+rlabel metal3 s 130586 392428 130586 392428 4 u_riscv_top.core0_debug\[3\]
+port 1108 nsew
+rlabel metal3 s 130632 382364 130632 382364 4 u_riscv_top.core0_debug\[40\]
+port 1109 nsew
+rlabel metal3 s 130632 382092 130632 382092 4 u_riscv_top.core0_debug\[41\]
+port 1110 nsew
+rlabel metal3 s 130494 381820 130494 381820 4 u_riscv_top.core0_debug\[42\]
+port 1111 nsew
+rlabel metal3 s 130586 381548 130586 381548 4 u_riscv_top.core0_debug\[43\]
+port 1112 nsew
+rlabel metal3 s 130540 381276 130540 381276 4 u_riscv_top.core0_debug\[44\]
+port 1113 nsew
+rlabel metal3 s 130494 381004 130494 381004 4 u_riscv_top.core0_debug\[45\]
+port 1114 nsew
+rlabel metal3 s 130540 380732 130540 380732 4 u_riscv_top.core0_debug\[46\]
+port 1115 nsew
+rlabel metal3 s 130494 380460 130494 380460 4 u_riscv_top.core0_debug\[47\]
+port 1116 nsew
+rlabel metal3 s 130494 380188 130494 380188 4 u_riscv_top.core0_debug\[48\]
+port 1117 nsew
+rlabel metal3 s 130632 392156 130632 392156 4 u_riscv_top.core0_debug\[4\]
+port 1118 nsew
+rlabel metal3 s 130494 391884 130494 391884 4 u_riscv_top.core0_debug\[5\]
+port 1119 nsew
+rlabel metal3 s 130540 391612 130540 391612 4 u_riscv_top.core0_debug\[6\]
+port 1120 nsew
+rlabel metal3 s 130494 391340 130494 391340 4 u_riscv_top.core0_debug\[7\]
+port 1121 nsew
+rlabel metal3 s 130494 391068 130494 391068 4 u_riscv_top.core0_debug\[8\]
+port 1122 nsew
+rlabel metal3 s 130540 390796 130540 390796 4 u_riscv_top.core0_debug\[9\]
+port 1123 nsew
+rlabel metal3 s 130540 359924 130540 359924 4 u_riscv_top.core0_dmem_addr\[0\]
+port 1124 nsew
+rlabel metal3 s 130494 357204 130494 357204 4 u_riscv_top.core0_dmem_addr\[10\]
+port 1125 nsew
+rlabel metal3 s 130540 356932 130540 356932 4 u_riscv_top.core0_dmem_addr\[11\]
+port 1126 nsew
+rlabel metal3 s 130494 356660 130494 356660 4 u_riscv_top.core0_dmem_addr\[12\]
+port 1127 nsew
+rlabel metal3 s 130586 356388 130586 356388 4 u_riscv_top.core0_dmem_addr\[13\]
+port 1128 nsew
+rlabel metal3 s 130632 356116 130632 356116 4 u_riscv_top.core0_dmem_addr\[14\]
+port 1129 nsew
+rlabel metal3 s 130540 355844 130540 355844 4 u_riscv_top.core0_dmem_addr\[15\]
+port 1130 nsew
+rlabel metal3 s 130494 355572 130494 355572 4 u_riscv_top.core0_dmem_addr\[16\]
+port 1131 nsew
+rlabel metal3 s 130678 355300 130678 355300 4 u_riscv_top.core0_dmem_addr\[17\]
+port 1132 nsew
+rlabel metal3 s 130632 355028 130632 355028 4 u_riscv_top.core0_dmem_addr\[18\]
+port 1133 nsew
+rlabel metal3 s 130586 354756 130586 354756 4 u_riscv_top.core0_dmem_addr\[19\]
+port 1134 nsew
+rlabel metal3 s 130494 359652 130494 359652 4 u_riscv_top.core0_dmem_addr\[1\]
+port 1135 nsew
+rlabel metal3 s 130540 354484 130540 354484 4 u_riscv_top.core0_dmem_addr\[20\]
+port 1136 nsew
+rlabel metal3 s 130494 354212 130494 354212 4 u_riscv_top.core0_dmem_addr\[21\]
+port 1137 nsew
+rlabel metal3 s 130494 353940 130494 353940 4 u_riscv_top.core0_dmem_addr\[22\]
+port 1138 nsew
+rlabel metal3 s 130586 353668 130586 353668 4 u_riscv_top.core0_dmem_addr\[23\]
+port 1139 nsew
+rlabel metal3 s 130540 353396 130540 353396 4 u_riscv_top.core0_dmem_addr\[24\]
+port 1140 nsew
+rlabel metal3 s 130494 353124 130494 353124 4 u_riscv_top.core0_dmem_addr\[25\]
+port 1141 nsew
+rlabel metal3 s 130586 352852 130586 352852 4 u_riscv_top.core0_dmem_addr\[26\]
+port 1142 nsew
+rlabel metal3 s 130540 352580 130540 352580 4 u_riscv_top.core0_dmem_addr\[27\]
+port 1143 nsew
+rlabel metal3 s 130494 352308 130494 352308 4 u_riscv_top.core0_dmem_addr\[28\]
+port 1144 nsew
+rlabel metal3 s 130632 352036 130632 352036 4 u_riscv_top.core0_dmem_addr\[29\]
+port 1145 nsew
+rlabel metal3 s 130586 359380 130586 359380 4 u_riscv_top.core0_dmem_addr\[2\]
+port 1146 nsew
+rlabel metal3 s 130632 351764 130632 351764 4 u_riscv_top.core0_dmem_addr\[30\]
+port 1147 nsew
+rlabel metal3 s 130494 351492 130494 351492 4 u_riscv_top.core0_dmem_addr\[31\]
+port 1148 nsew
+rlabel metal3 s 130540 359108 130540 359108 4 u_riscv_top.core0_dmem_addr\[3\]
+port 1149 nsew
+rlabel metal3 s 130632 358836 130632 358836 4 u_riscv_top.core0_dmem_addr\[4\]
+port 1150 nsew
+rlabel metal3 s 130494 358564 130494 358564 4 u_riscv_top.core0_dmem_addr\[5\]
+port 1151 nsew
+rlabel metal3 s 130540 358292 130540 358292 4 u_riscv_top.core0_dmem_addr\[6\]
+port 1152 nsew
+rlabel metal3 s 130494 358020 130494 358020 4 u_riscv_top.core0_dmem_addr\[7\]
+port 1153 nsew
+rlabel metal3 s 130586 357748 130586 357748 4 u_riscv_top.core0_dmem_addr\[8\]
+port 1154 nsew
+rlabel metal3 s 130632 357476 130632 357476 4 u_riscv_top.core0_dmem_addr\[9\]
+port 1155 nsew
+rlabel metal3 s 130494 350676 130494 350676 4 u_riscv_top.core0_dmem_cmd
+port 1156 nsew
+rlabel metal3 s 130586 377332 130586 377332 4 u_riscv_top.core0_dmem_rdata\[0\]
+port 1157 nsew
+rlabel metal3 s 130494 374612 130494 374612 4 u_riscv_top.core0_dmem_rdata\[10\]
+port 1158 nsew
+rlabel metal3 s 130540 374340 130540 374340 4 u_riscv_top.core0_dmem_rdata\[11\]
+port 1159 nsew
+rlabel metal3 s 130632 374068 130632 374068 4 u_riscv_top.core0_dmem_rdata\[12\]
+port 1160 nsew
+rlabel metal3 s 130540 373796 130540 373796 4 u_riscv_top.core0_dmem_rdata\[13\]
+port 1161 nsew
+rlabel metal3 s 130494 373524 130494 373524 4 u_riscv_top.core0_dmem_rdata\[14\]
+port 1162 nsew
+rlabel metal3 s 130494 373252 130494 373252 4 u_riscv_top.core0_dmem_rdata\[15\]
+port 1163 nsew
+rlabel metal3 s 130586 372980 130586 372980 4 u_riscv_top.core0_dmem_rdata\[16\]
+port 1164 nsew
+rlabel metal3 s 130540 372708 130540 372708 4 u_riscv_top.core0_dmem_rdata\[17\]
+port 1165 nsew
+rlabel metal3 s 130586 372436 130586 372436 4 u_riscv_top.core0_dmem_rdata\[18\]
+port 1166 nsew
+rlabel metal3 s 130632 372164 130632 372164 4 u_riscv_top.core0_dmem_rdata\[19\]
+port 1167 nsew
+rlabel metal3 s 130540 377060 130540 377060 4 u_riscv_top.core0_dmem_rdata\[1\]
+port 1168 nsew
+rlabel metal3 s 130494 371892 130494 371892 4 u_riscv_top.core0_dmem_rdata\[20\]
+port 1169 nsew
+rlabel metal3 s 130540 371620 130540 371620 4 u_riscv_top.core0_dmem_rdata\[21\]
+port 1170 nsew
+rlabel metal3 s 130678 371348 130678 371348 4 u_riscv_top.core0_dmem_rdata\[22\]
+port 1171 nsew
+rlabel metal3 s 130540 371076 130540 371076 4 u_riscv_top.core0_dmem_rdata\[23\]
+port 1172 nsew
+rlabel metal3 s 130494 370804 130494 370804 4 u_riscv_top.core0_dmem_rdata\[24\]
+port 1173 nsew
+rlabel metal3 s 130586 370532 130586 370532 4 u_riscv_top.core0_dmem_rdata\[25\]
+port 1174 nsew
+rlabel metal3 s 130494 370260 130494 370260 4 u_riscv_top.core0_dmem_rdata\[26\]
+port 1175 nsew
+rlabel metal3 s 130540 369988 130540 369988 4 u_riscv_top.core0_dmem_rdata\[27\]
+port 1176 nsew
+rlabel metal3 s 130494 369716 130494 369716 4 u_riscv_top.core0_dmem_rdata\[28\]
+port 1177 nsew
+rlabel metal3 s 130540 369444 130540 369444 4 u_riscv_top.core0_dmem_rdata\[29\]
+port 1178 nsew
+rlabel metal3 s 130632 376788 130632 376788 4 u_riscv_top.core0_dmem_rdata\[2\]
+port 1179 nsew
+rlabel metal3 s 130494 369172 130494 369172 4 u_riscv_top.core0_dmem_rdata\[30\]
+port 1180 nsew
+rlabel metal3 s 130586 368900 130586 368900 4 u_riscv_top.core0_dmem_rdata\[31\]
+port 1181 nsew
+rlabel metal3 s 130494 376516 130494 376516 4 u_riscv_top.core0_dmem_rdata\[3\]
+port 1182 nsew
+rlabel metal3 s 130540 376244 130540 376244 4 u_riscv_top.core0_dmem_rdata\[4\]
+port 1183 nsew
+rlabel metal3 s 130632 375972 130632 375972 4 u_riscv_top.core0_dmem_rdata\[5\]
+port 1184 nsew
+rlabel metal3 s 130494 375700 130494 375700 4 u_riscv_top.core0_dmem_rdata\[6\]
+port 1185 nsew
+rlabel metal3 s 130586 375428 130586 375428 4 u_riscv_top.core0_dmem_rdata\[7\]
+port 1186 nsew
+rlabel metal3 s 130586 375156 130586 375156 4 u_riscv_top.core0_dmem_rdata\[8\]
+port 1187 nsew
+rlabel metal3 s 130494 374884 130494 374884 4 u_riscv_top.core0_dmem_rdata\[9\]
+port 1188 nsew
+rlabel metal3 s 130540 350404 130540 350404 4 u_riscv_top.core0_dmem_req
+port 1189 nsew
+rlabel metal3 s 130494 350132 130494 350132 4 u_riscv_top.core0_dmem_req_ack
+port 1190 nsew
+rlabel metal3 s 130540 377876 130540 377876 4 u_riscv_top.core0_dmem_resp\[0\]
+port 1191 nsew
+rlabel metal3 s 130494 377604 130494 377604 4 u_riscv_top.core0_dmem_resp\[1\]
+port 1192 nsew
+rlabel metal3 s 130632 368628 130632 368628 4 u_riscv_top.core0_dmem_wdata\[0\]
+port 1193 nsew
+rlabel metal3 s 130494 365908 130494 365908 4 u_riscv_top.core0_dmem_wdata\[10\]
+port 1194 nsew
+rlabel metal3 s 130632 365636 130632 365636 4 u_riscv_top.core0_dmem_wdata\[11\]
+port 1195 nsew
+rlabel metal3 s 130586 365364 130586 365364 4 u_riscv_top.core0_dmem_wdata\[12\]
+port 1196 nsew
+rlabel metal3 s 130494 365092 130494 365092 4 u_riscv_top.core0_dmem_wdata\[13\]
+port 1197 nsew
+rlabel metal3 s 130540 364820 130540 364820 4 u_riscv_top.core0_dmem_wdata\[14\]
+port 1198 nsew
+rlabel metal3 s 130678 364548 130678 364548 4 u_riscv_top.core0_dmem_wdata\[15\]
+port 1199 nsew
+rlabel metal3 s 130586 364276 130586 364276 4 u_riscv_top.core0_dmem_wdata\[16\]
+port 1200 nsew
+rlabel metal3 s 130632 364004 130632 364004 4 u_riscv_top.core0_dmem_wdata\[17\]
+port 1201 nsew
+rlabel metal3 s 130494 363732 130494 363732 4 u_riscv_top.core0_dmem_wdata\[18\]
+port 1202 nsew
+rlabel metal3 s 130678 363460 130678 363460 4 u_riscv_top.core0_dmem_wdata\[19\]
+port 1203 nsew
+rlabel metal3 s 130586 368356 130586 368356 4 u_riscv_top.core0_dmem_wdata\[1\]
+port 1204 nsew
+rlabel metal3 s 130540 363188 130540 363188 4 u_riscv_top.core0_dmem_wdata\[20\]
+port 1205 nsew
+rlabel metal3 s 130586 362916 130586 362916 4 u_riscv_top.core0_dmem_wdata\[21\]
+port 1206 nsew
+rlabel metal3 s 130494 362644 130494 362644 4 u_riscv_top.core0_dmem_wdata\[22\]
+port 1207 nsew
+rlabel metal3 s 130540 362372 130540 362372 4 u_riscv_top.core0_dmem_wdata\[23\]
+port 1208 nsew
+rlabel metal3 s 130494 362100 130494 362100 4 u_riscv_top.core0_dmem_wdata\[24\]
+port 1209 nsew
+rlabel metal3 s 130632 361828 130632 361828 4 u_riscv_top.core0_dmem_wdata\[25\]
+port 1210 nsew
+rlabel metal3 s 130632 361556 130632 361556 4 u_riscv_top.core0_dmem_wdata\[26\]
+port 1211 nsew
+rlabel metal3 s 130494 361284 130494 361284 4 u_riscv_top.core0_dmem_wdata\[27\]
+port 1212 nsew
+rlabel metal3 s 130494 361012 130494 361012 4 u_riscv_top.core0_dmem_wdata\[28\]
+port 1213 nsew
+rlabel metal3 s 130540 360740 130540 360740 4 u_riscv_top.core0_dmem_wdata\[29\]
+port 1214 nsew
+rlabel metal3 s 130632 368084 130632 368084 4 u_riscv_top.core0_dmem_wdata\[2\]
+port 1215 nsew
+rlabel metal3 s 130586 360468 130586 360468 4 u_riscv_top.core0_dmem_wdata\[30\]
+port 1216 nsew
+rlabel metal3 s 130678 360196 130678 360196 4 u_riscv_top.core0_dmem_wdata\[31\]
+port 1217 nsew
+rlabel metal3 s 130494 367812 130494 367812 4 u_riscv_top.core0_dmem_wdata\[3\]
+port 1218 nsew
+rlabel metal3 s 130540 367540 130540 367540 4 u_riscv_top.core0_dmem_wdata\[4\]
+port 1219 nsew
+rlabel metal3 s 130678 367268 130678 367268 4 u_riscv_top.core0_dmem_wdata\[5\]
+port 1220 nsew
+rlabel metal3 s 130632 366996 130632 366996 4 u_riscv_top.core0_dmem_wdata\[6\]
+port 1221 nsew
+rlabel metal3 s 130540 366724 130540 366724 4 u_riscv_top.core0_dmem_wdata\[7\]
+port 1222 nsew
+rlabel metal3 s 130494 366452 130494 366452 4 u_riscv_top.core0_dmem_wdata\[8\]
+port 1223 nsew
+rlabel metal3 s 130586 366180 130586 366180 4 u_riscv_top.core0_dmem_wdata\[9\]
+port 1224 nsew
+rlabel metal3 s 130540 351220 130540 351220 4 u_riscv_top.core0_dmem_width\[0\]
+port 1225 nsew
+rlabel metal3 s 130586 350948 130586 350948 4 u_riscv_top.core0_dmem_width\[1\]
+port 1226 nsew
+rlabel metal3 s 130494 330276 130494 330276 4 u_riscv_top.core0_imem_addr\[0\]
+port 1227 nsew
+rlabel metal3 s 130540 327556 130540 327556 4 u_riscv_top.core0_imem_addr\[10\]
+port 1228 nsew
+rlabel metal3 s 130678 327284 130678 327284 4 u_riscv_top.core0_imem_addr\[11\]
+port 1229 nsew
+rlabel metal3 s 130494 327012 130494 327012 4 u_riscv_top.core0_imem_addr\[12\]
+port 1230 nsew
+rlabel metal3 s 130540 326740 130540 326740 4 u_riscv_top.core0_imem_addr\[13\]
+port 1231 nsew
+rlabel metal3 s 130494 326468 130494 326468 4 u_riscv_top.core0_imem_addr\[14\]
+port 1232 nsew
+rlabel metal3 s 130540 326196 130540 326196 4 u_riscv_top.core0_imem_addr\[15\]
+port 1233 nsew
+rlabel metal3 s 130586 325924 130586 325924 4 u_riscv_top.core0_imem_addr\[16\]
+port 1234 nsew
+rlabel metal3 s 130540 325652 130540 325652 4 u_riscv_top.core0_imem_addr\[17\]
+port 1235 nsew
+rlabel metal3 s 130678 325380 130678 325380 4 u_riscv_top.core0_imem_addr\[18\]
+port 1236 nsew
+rlabel metal3 s 130494 325108 130494 325108 4 u_riscv_top.core0_imem_addr\[19\]
+port 1237 nsew
+rlabel metal3 s 130632 330004 130632 330004 4 u_riscv_top.core0_imem_addr\[1\]
+port 1238 nsew
+rlabel metal3 s 130632 324836 130632 324836 4 u_riscv_top.core0_imem_addr\[20\]
+port 1239 nsew
+rlabel metal3 s 130586 324564 130586 324564 4 u_riscv_top.core0_imem_addr\[21\]
+port 1240 nsew
+rlabel metal3 s 130540 324292 130540 324292 4 u_riscv_top.core0_imem_addr\[22\]
+port 1241 nsew
+rlabel metal3 s 130494 324020 130494 324020 4 u_riscv_top.core0_imem_addr\[23\]
+port 1242 nsew
+rlabel metal3 s 130494 323748 130494 323748 4 u_riscv_top.core0_imem_addr\[24\]
+port 1243 nsew
+rlabel metal3 s 130586 323476 130586 323476 4 u_riscv_top.core0_imem_addr\[25\]
+port 1244 nsew
+rlabel metal3 s 130494 323204 130494 323204 4 u_riscv_top.core0_imem_addr\[26\]
+port 1245 nsew
+rlabel metal3 s 130540 322932 130540 322932 4 u_riscv_top.core0_imem_addr\[27\]
+port 1246 nsew
+rlabel metal3 s 130494 322660 130494 322660 4 u_riscv_top.core0_imem_addr\[28\]
+port 1247 nsew
+rlabel metal3 s 130540 322388 130540 322388 4 u_riscv_top.core0_imem_addr\[29\]
+port 1248 nsew
+rlabel metal3 s 130494 329732 130494 329732 4 u_riscv_top.core0_imem_addr\[2\]
+port 1249 nsew
+rlabel metal3 s 130494 322116 130494 322116 4 u_riscv_top.core0_imem_addr\[30\]
+port 1250 nsew
+rlabel metal3 s 130632 321844 130632 321844 4 u_riscv_top.core0_imem_addr\[31\]
+port 1251 nsew
+rlabel metal3 s 130540 329460 130540 329460 4 u_riscv_top.core0_imem_addr\[3\]
+port 1252 nsew
+rlabel metal3 s 130494 329188 130494 329188 4 u_riscv_top.core0_imem_addr\[4\]
+port 1253 nsew
+rlabel metal3 s 130494 328916 130494 328916 4 u_riscv_top.core0_imem_addr\[5\]
+port 1254 nsew
+rlabel metal3 s 130540 328644 130540 328644 4 u_riscv_top.core0_imem_addr\[6\]
+port 1255 nsew
+rlabel metal3 s 130586 328372 130586 328372 4 u_riscv_top.core0_imem_addr\[7\]
+port 1256 nsew
+rlabel metal3 s 130632 328100 130632 328100 4 u_riscv_top.core0_imem_addr\[8\]
+port 1257 nsew
+rlabel metal3 s 130494 327828 130494 327828 4 u_riscv_top.core0_imem_addr\[9\]
+port 1258 nsew
+rlabel metal3 s 130586 331092 130586 331092 4 u_riscv_top.core0_imem_bl\[0\]
+port 1259 nsew
+rlabel metal3 s 130494 330820 130494 330820 4 u_riscv_top.core0_imem_bl\[1\]
+port 1260 nsew
+rlabel metal3 s 130540 330548 130540 330548 4 u_riscv_top.core0_imem_bl\[2\]
+port 1261 nsew
+rlabel metal3 s 130586 321572 130586 321572 4 u_riscv_top.core0_imem_cmd
+port 1262 nsew
+rlabel metal3 s 130632 339796 130632 339796 4 u_riscv_top.core0_imem_rdata\[0\]
+port 1263 nsew
+rlabel metal3 s 130540 337076 130540 337076 4 u_riscv_top.core0_imem_rdata\[10\]
+port 1264 nsew
+rlabel metal3 s 130632 336804 130632 336804 4 u_riscv_top.core0_imem_rdata\[11\]
+port 1265 nsew
+rlabel metal3 s 130586 336532 130586 336532 4 u_riscv_top.core0_imem_rdata\[12\]
+port 1266 nsew
+rlabel metal3 s 130494 336260 130494 336260 4 u_riscv_top.core0_imem_rdata\[13\]
+port 1267 nsew
+rlabel metal3 s 130540 335988 130540 335988 4 u_riscv_top.core0_imem_rdata\[14\]
+port 1268 nsew
+rlabel metal3 s 130494 335716 130494 335716 4 u_riscv_top.core0_imem_rdata\[15\]
+port 1269 nsew
+rlabel metal3 s 130632 335444 130632 335444 4 u_riscv_top.core0_imem_rdata\[16\]
+port 1270 nsew
+rlabel metal3 s 130678 335172 130678 335172 4 u_riscv_top.core0_imem_rdata\[17\]
+port 1271 nsew
+rlabel metal3 s 130494 334900 130494 334900 4 u_riscv_top.core0_imem_rdata\[18\]
+port 1272 nsew
+rlabel metal3 s 130540 334628 130540 334628 4 u_riscv_top.core0_imem_rdata\[19\]
+port 1273 nsew
+rlabel metal3 s 130586 339524 130586 339524 4 u_riscv_top.core0_imem_rdata\[1\]
+port 1274 nsew
+rlabel metal3 s 130586 334356 130586 334356 4 u_riscv_top.core0_imem_rdata\[20\]
+port 1275 nsew
+rlabel metal3 s 130632 334084 130632 334084 4 u_riscv_top.core0_imem_rdata\[21\]
+port 1276 nsew
+rlabel metal3 s 130494 333812 130494 333812 4 u_riscv_top.core0_imem_rdata\[22\]
+port 1277 nsew
+rlabel metal3 s 130540 333540 130540 333540 4 u_riscv_top.core0_imem_rdata\[23\]
+port 1278 nsew
+rlabel metal3 s 130494 333268 130494 333268 4 u_riscv_top.core0_imem_rdata\[24\]
+port 1279 nsew
+rlabel metal3 s 130586 332996 130586 332996 4 u_riscv_top.core0_imem_rdata\[25\]
+port 1280 nsew
+rlabel metal3 s 130632 332724 130632 332724 4 u_riscv_top.core0_imem_rdata\[26\]
+port 1281 nsew
+rlabel metal3 s 130540 332452 130540 332452 4 u_riscv_top.core0_imem_rdata\[27\]
+port 1282 nsew
+rlabel metal3 s 130586 332180 130586 332180 4 u_riscv_top.core0_imem_rdata\[28\]
+port 1283 nsew
+rlabel metal3 s 130494 331908 130494 331908 4 u_riscv_top.core0_imem_rdata\[29\]
+port 1284 nsew
+rlabel metal3 s 130494 339252 130494 339252 4 u_riscv_top.core0_imem_rdata\[2\]
+port 1285 nsew
+rlabel metal3 s 130632 331636 130632 331636 4 u_riscv_top.core0_imem_rdata\[30\]
+port 1286 nsew
+rlabel metal3 s 130678 331364 130678 331364 4 u_riscv_top.core0_imem_rdata\[31\]
+port 1287 nsew
+rlabel metal3 s 130540 338980 130540 338980 4 u_riscv_top.core0_imem_rdata\[3\]
+port 1288 nsew
+rlabel metal3 s 130494 338708 130494 338708 4 u_riscv_top.core0_imem_rdata\[4\]
+port 1289 nsew
+rlabel metal3 s 130632 338436 130632 338436 4 u_riscv_top.core0_imem_rdata\[5\]
+port 1290 nsew
+rlabel metal3 s 130586 338164 130586 338164 4 u_riscv_top.core0_imem_rdata\[6\]
+port 1291 nsew
+rlabel metal3 s 130586 337892 130586 337892 4 u_riscv_top.core0_imem_rdata\[7\]
+port 1292 nsew
+rlabel metal3 s 130494 337620 130494 337620 4 u_riscv_top.core0_imem_rdata\[8\]
+port 1293 nsew
+rlabel metal3 s 130494 337348 130494 337348 4 u_riscv_top.core0_imem_rdata\[9\]
+port 1294 nsew
+rlabel metal3 s 130540 321300 130540 321300 4 u_riscv_top.core0_imem_req
+port 1295 nsew
+rlabel metal3 s 130494 321028 130494 321028 4 u_riscv_top.core0_imem_req_ack
+port 1296 nsew
+rlabel metal3 s 130494 340340 130494 340340 4 u_riscv_top.core0_imem_resp\[0\]
+port 1297 nsew
+rlabel metal3 s 130540 340068 130540 340068 4 u_riscv_top.core0_imem_resp\[1\]
+port 1298 nsew
+rlabel metal3 s 130540 426292 130540 426292 4 u_riscv_top.core0_irq_lines\[0\]
+port 1299 nsew
+rlabel metal3 s 130678 423572 130678 423572 4 u_riscv_top.core0_irq_lines\[10\]
+port 1300 nsew
+rlabel metal3 s 130632 423300 130632 423300 4 u_riscv_top.core0_irq_lines\[11\]
+port 1301 nsew
+rlabel metal3 s 130494 423028 130494 423028 4 u_riscv_top.core0_irq_lines\[12\]
+port 1302 nsew
+rlabel metal3 s 130540 422756 130540 422756 4 u_riscv_top.core0_irq_lines\[13\]
+port 1303 nsew
+rlabel metal3 s 130586 422484 130586 422484 4 u_riscv_top.core0_irq_lines\[14\]
+port 1304 nsew
+rlabel metal3 s 130540 422212 130540 422212 4 u_riscv_top.core0_irq_lines\[15\]
+port 1305 nsew
+rlabel metal3 s 130494 421940 130494 421940 4 u_riscv_top.core0_irq_lines\[16\]
+port 1306 nsew
+rlabel metal3 s 130494 421668 130494 421668 4 u_riscv_top.core0_irq_lines\[17\]
+port 1307 nsew
+rlabel metal3 s 130540 421396 130540 421396 4 u_riscv_top.core0_irq_lines\[18\]
+port 1308 nsew
+rlabel metal3 s 130586 421124 130586 421124 4 u_riscv_top.core0_irq_lines\[19\]
+port 1309 nsew
+rlabel metal3 s 130494 426020 130494 426020 4 u_riscv_top.core0_irq_lines\[1\]
+port 1310 nsew
+rlabel metal3 s 130540 420852 130540 420852 4 u_riscv_top.core0_irq_lines\[20\]
+port 1311 nsew
+rlabel metal3 s 130586 420580 130586 420580 4 u_riscv_top.core0_irq_lines\[21\]
+port 1312 nsew
+rlabel metal3 s 130494 420308 130494 420308 4 u_riscv_top.core0_irq_lines\[22\]
+port 1313 nsew
+rlabel metal3 s 130632 420036 130632 420036 4 u_riscv_top.core0_irq_lines\[23\]
+port 1314 nsew
+rlabel metal3 s 130678 419764 130678 419764 4 u_riscv_top.core0_irq_lines\[24\]
+port 1315 nsew
+rlabel metal3 s 130586 419492 130586 419492 4 u_riscv_top.core0_irq_lines\[25\]
+port 1316 nsew
+rlabel metal3 s 130632 419220 130632 419220 4 u_riscv_top.core0_irq_lines\[26\]
+port 1317 nsew
+rlabel metal3 s 130494 418948 130494 418948 4 u_riscv_top.core0_irq_lines\[27\]
+port 1318 nsew
+rlabel metal3 s 130540 418676 130540 418676 4 u_riscv_top.core0_irq_lines\[28\]
+port 1319 nsew
+rlabel metal3 s 130678 418404 130678 418404 4 u_riscv_top.core0_irq_lines\[29\]
+port 1320 nsew
+rlabel metal3 s 130494 425748 130494 425748 4 u_riscv_top.core0_irq_lines\[2\]
+port 1321 nsew
+rlabel metal3 s 130540 418132 130540 418132 4 u_riscv_top.core0_irq_lines\[30\]
+port 1322 nsew
+rlabel metal3 s 130586 417860 130586 417860 4 u_riscv_top.core0_irq_lines\[31\]
+port 1323 nsew
+rlabel metal3 s 130586 425476 130586 425476 4 u_riscv_top.core0_irq_lines\[3\]
+port 1324 nsew
+rlabel metal3 s 130540 425204 130540 425204 4 u_riscv_top.core0_irq_lines\[4\]
+port 1325 nsew
+rlabel metal3 s 130586 424932 130586 424932 4 u_riscv_top.core0_irq_lines\[5\]
+port 1326 nsew
+rlabel metal3 s 130678 424660 130678 424660 4 u_riscv_top.core0_irq_lines\[6\]
+port 1327 nsew
+rlabel metal3 s 130494 424388 130494 424388 4 u_riscv_top.core0_irq_lines\[7\]
+port 1328 nsew
+rlabel metal3 s 130540 424116 130540 424116 4 u_riscv_top.core0_irq_lines\[8\]
+port 1329 nsew
+rlabel metal3 s 130632 423844 130632 423844 4 u_riscv_top.core0_irq_lines\[9\]
+port 1330 nsew
+rlabel metal3 s 130494 426564 130494 426564 4 u_riscv_top.core0_soft_irq
+port 1331 nsew
+rlabel metal3 s 130494 400180 130494 400180 4 u_riscv_top.core0_timer_irq
+port 1332 nsew
+rlabel metal3 s 130494 417588 130494 417588 4 u_riscv_top.core0_timer_val\[0\]
+port 1333 nsew
+rlabel metal3 s 130494 414868 130494 414868 4 u_riscv_top.core0_timer_val\[10\]
+port 1334 nsew
+rlabel metal3 s 130632 414596 130632 414596 4 u_riscv_top.core0_timer_val\[11\]
+port 1335 nsew
+rlabel metal3 s 130540 414324 130540 414324 4 u_riscv_top.core0_timer_val\[12\]
+port 1336 nsew
+rlabel metal3 s 130678 414052 130678 414052 4 u_riscv_top.core0_timer_val\[13\]
+port 1337 nsew
+rlabel metal3 s 130678 413780 130678 413780 4 u_riscv_top.core0_timer_val\[14\]
+port 1338 nsew
+rlabel metal3 s 130494 413508 130494 413508 4 u_riscv_top.core0_timer_val\[15\]
+port 1339 nsew
+rlabel metal3 s 130632 413236 130632 413236 4 u_riscv_top.core0_timer_val\[16\]
+port 1340 nsew
+rlabel metal3 s 130586 412964 130586 412964 4 u_riscv_top.core0_timer_val\[17\]
+port 1341 nsew
+rlabel metal3 s 130540 412692 130540 412692 4 u_riscv_top.core0_timer_val\[18\]
+port 1342 nsew
+rlabel metal3 s 130632 412420 130632 412420 4 u_riscv_top.core0_timer_val\[19\]
+port 1343 nsew
+rlabel metal3 s 130494 417316 130494 417316 4 u_riscv_top.core0_timer_val\[1\]
+port 1344 nsew
+rlabel metal3 s 130494 412148 130494 412148 4 u_riscv_top.core0_timer_val\[20\]
+port 1345 nsew
+rlabel metal3 s 130540 411876 130540 411876 4 u_riscv_top.core0_timer_val\[21\]
+port 1346 nsew
+rlabel metal3 s 130494 411604 130494 411604 4 u_riscv_top.core0_timer_val\[22\]
+port 1347 nsew
+rlabel metal3 s 130586 411332 130586 411332 4 u_riscv_top.core0_timer_val\[23\]
+port 1348 nsew
+rlabel metal3 s 130540 411060 130540 411060 4 u_riscv_top.core0_timer_val\[24\]
+port 1349 nsew
+rlabel metal3 s 130494 410788 130494 410788 4 u_riscv_top.core0_timer_val\[25\]
+port 1350 nsew
+rlabel metal3 s 130494 410516 130494 410516 4 u_riscv_top.core0_timer_val\[26\]
+port 1351 nsew
+rlabel metal3 s 130586 410244 130586 410244 4 u_riscv_top.core0_timer_val\[27\]
+port 1352 nsew
+rlabel metal3 s 130540 409972 130540 409972 4 u_riscv_top.core0_timer_val\[28\]
+port 1353 nsew
+rlabel metal3 s 130632 409700 130632 409700 4 u_riscv_top.core0_timer_val\[29\]
+port 1354 nsew
+rlabel metal3 s 130632 417044 130632 417044 4 u_riscv_top.core0_timer_val\[2\]
+port 1355 nsew
+rlabel metal3 s 130494 409428 130494 409428 4 u_riscv_top.core0_timer_val\[30\]
+port 1356 nsew
+rlabel metal3 s 130540 409156 130540 409156 4 u_riscv_top.core0_timer_val\[31\]
+port 1357 nsew
+rlabel metal3 s 130586 408884 130586 408884 4 u_riscv_top.core0_timer_val\[32\]
+port 1358 nsew
+rlabel metal3 s 130494 408612 130494 408612 4 u_riscv_top.core0_timer_val\[33\]
+port 1359 nsew
+rlabel metal3 s 130540 408340 130540 408340 4 u_riscv_top.core0_timer_val\[34\]
+port 1360 nsew
+rlabel metal3 s 130494 408068 130494 408068 4 u_riscv_top.core0_timer_val\[35\]
+port 1361 nsew
+rlabel metal3 s 130494 407796 130494 407796 4 u_riscv_top.core0_timer_val\[36\]
+port 1362 nsew
+rlabel metal3 s 130540 407524 130540 407524 4 u_riscv_top.core0_timer_val\[37\]
+port 1363 nsew
+rlabel metal3 s 130586 407252 130586 407252 4 u_riscv_top.core0_timer_val\[38\]
+port 1364 nsew
+rlabel metal3 s 130678 406980 130678 406980 4 u_riscv_top.core0_timer_val\[39\]
+port 1365 nsew
+rlabel metal3 s 130540 416772 130540 416772 4 u_riscv_top.core0_timer_val\[3\]
+port 1366 nsew
+rlabel metal3 s 130494 406708 130494 406708 4 u_riscv_top.core0_timer_val\[40\]
+port 1367 nsew
+rlabel metal3 s 130540 406436 130540 406436 4 u_riscv_top.core0_timer_val\[41\]
+port 1368 nsew
+rlabel metal3 s 130632 406164 130632 406164 4 u_riscv_top.core0_timer_val\[42\]
+port 1369 nsew
+rlabel metal3 s 130586 405892 130586 405892 4 u_riscv_top.core0_timer_val\[43\]
+port 1370 nsew
+rlabel metal3 s 130632 405620 130632 405620 4 u_riscv_top.core0_timer_val\[44\]
+port 1371 nsew
+rlabel metal3 s 130494 405348 130494 405348 4 u_riscv_top.core0_timer_val\[45\]
+port 1372 nsew
+rlabel metal3 s 130540 405076 130540 405076 4 u_riscv_top.core0_timer_val\[46\]
+port 1373 nsew
+rlabel metal3 s 130586 404804 130586 404804 4 u_riscv_top.core0_timer_val\[47\]
+port 1374 nsew
+rlabel metal3 s 130494 404532 130494 404532 4 u_riscv_top.core0_timer_val\[48\]
+port 1375 nsew
+rlabel metal3 s 130678 404260 130678 404260 4 u_riscv_top.core0_timer_val\[49\]
+port 1376 nsew
+rlabel metal3 s 130540 416500 130540 416500 4 u_riscv_top.core0_timer_val\[4\]
+port 1377 nsew
+rlabel metal3 s 130586 403988 130586 403988 4 u_riscv_top.core0_timer_val\[50\]
+port 1378 nsew
+rlabel metal3 s 130494 403716 130494 403716 4 u_riscv_top.core0_timer_val\[51\]
+port 1379 nsew
+rlabel metal3 s 130632 403444 130632 403444 4 u_riscv_top.core0_timer_val\[52\]
+port 1380 nsew
+rlabel metal3 s 130540 403172 130540 403172 4 u_riscv_top.core0_timer_val\[53\]
+port 1381 nsew
+rlabel metal3 s 130586 402900 130586 402900 4 u_riscv_top.core0_timer_val\[54\]
+port 1382 nsew
+rlabel metal3 s 130540 402628 130540 402628 4 u_riscv_top.core0_timer_val\[55\]
+port 1383 nsew
+rlabel metal3 s 130494 402356 130494 402356 4 u_riscv_top.core0_timer_val\[56\]
+port 1384 nsew
+rlabel metal3 s 130540 402084 130540 402084 4 u_riscv_top.core0_timer_val\[57\]
+port 1385 nsew
+rlabel metal3 s 130632 401812 130632 401812 4 u_riscv_top.core0_timer_val\[58\]
+port 1386 nsew
+rlabel metal3 s 130632 401540 130632 401540 4 u_riscv_top.core0_timer_val\[59\]
+port 1387 nsew
+rlabel metal3 s 130494 416228 130494 416228 4 u_riscv_top.core0_timer_val\[5\]
+port 1388 nsew
+rlabel metal3 s 130494 401268 130494 401268 4 u_riscv_top.core0_timer_val\[60\]
+port 1389 nsew
+rlabel metal3 s 130540 400996 130540 400996 4 u_riscv_top.core0_timer_val\[61\]
+port 1390 nsew
+rlabel metal3 s 130494 400724 130494 400724 4 u_riscv_top.core0_timer_val\[62\]
+port 1391 nsew
+rlabel metal3 s 130586 400452 130586 400452 4 u_riscv_top.core0_timer_val\[63\]
+port 1392 nsew
+rlabel metal3 s 130586 415956 130586 415956 4 u_riscv_top.core0_timer_val\[6\]
+port 1393 nsew
+rlabel metal3 s 130494 415684 130494 415684 4 u_riscv_top.core0_timer_val\[7\]
+port 1394 nsew
+rlabel metal3 s 130540 415412 130540 415412 4 u_riscv_top.core0_timer_val\[8\]
+port 1395 nsew
+rlabel metal3 s 130586 415140 130586 415140 4 u_riscv_top.core0_timer_val\[9\]
+port 1396 nsew
+rlabel metal3 s 130494 320756 130494 320756 4 u_riscv_top.core0_uid\[0\]
+port 1397 nsew
+rlabel metal3 s 130586 320484 130586 320484 4 u_riscv_top.core0_uid\[1\]
+port 1398 nsew
+rlabel metal3 s 230414 320229 230414 320229 4 u_riscv_top.core1_clk
+port 1399 nsew
+rlabel metal3 s 230414 393261 230414 393261 4 u_riscv_top.core1_debug\[0\]
+port 1400 nsew
+rlabel metal3 s 230414 390507 230414 390507 4 u_riscv_top.core1_debug\[10\]
+port 1401 nsew
+rlabel metal3 s 230414 390235 230414 390235 4 u_riscv_top.core1_debug\[11\]
+port 1402 nsew
+rlabel metal3 s 230414 389997 230414 389997 4 u_riscv_top.core1_debug\[12\]
+port 1403 nsew
+rlabel metal3 s 230414 389725 230414 389725 4 u_riscv_top.core1_debug\[13\]
+port 1404 nsew
+rlabel metal3 s 230414 389453 230414 389453 4 u_riscv_top.core1_debug\[14\]
+port 1405 nsew
+rlabel metal3 s 230414 389181 230414 389181 4 u_riscv_top.core1_debug\[15\]
+port 1406 nsew
+rlabel metal3 s 230414 388909 230414 388909 4 u_riscv_top.core1_debug\[16\]
+port 1407 nsew
+rlabel metal3 s 230414 388637 230414 388637 4 u_riscv_top.core1_debug\[17\]
+port 1408 nsew
+rlabel metal3 s 230414 388365 230414 388365 4 u_riscv_top.core1_debug\[18\]
+port 1409 nsew
+rlabel metal3 s 230414 388093 230414 388093 4 u_riscv_top.core1_debug\[19\]
+port 1410 nsew
+rlabel metal3 s 230414 392989 230414 392989 4 u_riscv_top.core1_debug\[1\]
+port 1411 nsew
+rlabel metal3 s 230414 387821 230414 387821 4 u_riscv_top.core1_debug\[20\]
+port 1412 nsew
+rlabel metal3 s 230414 387549 230414 387549 4 u_riscv_top.core1_debug\[21\]
+port 1413 nsew
+rlabel metal3 s 230414 387277 230414 387277 4 u_riscv_top.core1_debug\[22\]
+port 1414 nsew
+rlabel metal3 s 230414 387005 230414 387005 4 u_riscv_top.core1_debug\[23\]
+port 1415 nsew
+rlabel metal3 s 230414 386699 230414 386699 4 u_riscv_top.core1_debug\[24\]
+port 1416 nsew
+rlabel metal3 s 230414 386461 230414 386461 4 u_riscv_top.core1_debug\[25\]
+port 1417 nsew
+rlabel metal3 s 230414 386189 230414 386189 4 u_riscv_top.core1_debug\[26\]
+port 1418 nsew
+rlabel metal3 s 230414 385917 230414 385917 4 u_riscv_top.core1_debug\[27\]
+port 1419 nsew
+rlabel metal3 s 230414 385645 230414 385645 4 u_riscv_top.core1_debug\[28\]
+port 1420 nsew
+rlabel metal3 s 230414 385339 230414 385339 4 u_riscv_top.core1_debug\[29\]
+port 1421 nsew
+rlabel metal3 s 230414 392717 230414 392717 4 u_riscv_top.core1_debug\[2\]
+port 1422 nsew
+rlabel metal3 s 230414 385101 230414 385101 4 u_riscv_top.core1_debug\[30\]
+port 1423 nsew
+rlabel metal3 s 230414 384829 230414 384829 4 u_riscv_top.core1_debug\[31\]
+port 1424 nsew
+rlabel metal3 s 230414 384557 230414 384557 4 u_riscv_top.core1_debug\[32\]
+port 1425 nsew
+rlabel metal3 s 230414 384285 230414 384285 4 u_riscv_top.core1_debug\[33\]
+port 1426 nsew
+rlabel metal3 s 230414 383979 230414 383979 4 u_riscv_top.core1_debug\[34\]
+port 1427 nsew
+rlabel metal3 s 230414 383741 230414 383741 4 u_riscv_top.core1_debug\[35\]
+port 1428 nsew
+rlabel metal3 s 230414 383469 230414 383469 4 u_riscv_top.core1_debug\[36\]
+port 1429 nsew
+rlabel metal3 s 230414 383197 230414 383197 4 u_riscv_top.core1_debug\[37\]
+port 1430 nsew
+rlabel metal3 s 230414 382925 230414 382925 4 u_riscv_top.core1_debug\[38\]
+port 1431 nsew
+rlabel metal3 s 230414 382619 230414 382619 4 u_riscv_top.core1_debug\[39\]
+port 1432 nsew
+rlabel metal3 s 230414 392445 230414 392445 4 u_riscv_top.core1_debug\[3\]
+port 1433 nsew
+rlabel metal3 s 230414 382381 230414 382381 4 u_riscv_top.core1_debug\[40\]
+port 1434 nsew
+rlabel metal3 s 230414 382109 230414 382109 4 u_riscv_top.core1_debug\[41\]
+port 1435 nsew
+rlabel metal3 s 230414 381837 230414 381837 4 u_riscv_top.core1_debug\[42\]
+port 1436 nsew
+rlabel metal3 s 230414 381565 230414 381565 4 u_riscv_top.core1_debug\[43\]
+port 1437 nsew
+rlabel metal3 s 230414 381259 230414 381259 4 u_riscv_top.core1_debug\[44\]
+port 1438 nsew
+rlabel metal3 s 230414 381021 230414 381021 4 u_riscv_top.core1_debug\[45\]
+port 1439 nsew
+rlabel metal3 s 230414 380749 230414 380749 4 u_riscv_top.core1_debug\[46\]
+port 1440 nsew
+rlabel metal3 s 230414 380477 230414 380477 4 u_riscv_top.core1_debug\[47\]
+port 1441 nsew
+rlabel metal3 s 230414 380171 230414 380171 4 u_riscv_top.core1_debug\[48\]
+port 1442 nsew
+rlabel metal3 s 230414 392173 230414 392173 4 u_riscv_top.core1_debug\[4\]
+port 1443 nsew
+rlabel metal3 s 230414 391867 230414 391867 4 u_riscv_top.core1_debug\[5\]
+port 1444 nsew
+rlabel metal3 s 230414 391595 230414 391595 4 u_riscv_top.core1_debug\[6\]
+port 1445 nsew
+rlabel metal3 s 230414 391357 230414 391357 4 u_riscv_top.core1_debug\[7\]
+port 1446 nsew
+rlabel metal3 s 230414 391085 230414 391085 4 u_riscv_top.core1_debug\[8\]
+port 1447 nsew
+rlabel metal3 s 230414 390779 230414 390779 4 u_riscv_top.core1_debug\[9\]
+port 1448 nsew
+rlabel metal3 s 230414 359907 230414 359907 4 u_riscv_top.core1_dmem_addr\[0\]
+port 1449 nsew
+rlabel metal3 s 230414 357221 230414 357221 4 u_riscv_top.core1_dmem_addr\[10\]
+port 1450 nsew
+rlabel metal3 s 230414 356949 230414 356949 4 u_riscv_top.core1_dmem_addr\[11\]
+port 1451 nsew
+rlabel metal3 s 230414 356677 230414 356677 4 u_riscv_top.core1_dmem_addr\[12\]
+port 1452 nsew
+rlabel metal3 s 230414 356371 230414 356371 4 u_riscv_top.core1_dmem_addr\[13\]
+port 1453 nsew
+rlabel metal3 s 230414 356133 230414 356133 4 u_riscv_top.core1_dmem_addr\[14\]
+port 1454 nsew
+rlabel metal3 s 230414 355861 230414 355861 4 u_riscv_top.core1_dmem_addr\[15\]
+port 1455 nsew
+rlabel metal3 s 230414 355589 230414 355589 4 u_riscv_top.core1_dmem_addr\[16\]
+port 1456 nsew
+rlabel metal3 s 230414 355317 230414 355317 4 u_riscv_top.core1_dmem_addr\[17\]
+port 1457 nsew
+rlabel metal3 s 230414 355045 230414 355045 4 u_riscv_top.core1_dmem_addr\[18\]
+port 1458 nsew
+rlabel metal3 s 230414 354739 230414 354739 4 u_riscv_top.core1_dmem_addr\[19\]
+port 1459 nsew
+rlabel metal3 s 230414 359669 230414 359669 4 u_riscv_top.core1_dmem_addr\[1\]
+port 1460 nsew
+rlabel metal3 s 230414 354467 230414 354467 4 u_riscv_top.core1_dmem_addr\[20\]
+port 1461 nsew
+rlabel metal3 s 230414 354229 230414 354229 4 u_riscv_top.core1_dmem_addr\[21\]
+port 1462 nsew
+rlabel metal3 s 230414 353957 230414 353957 4 u_riscv_top.core1_dmem_addr\[22\]
+port 1463 nsew
+rlabel metal3 s 230414 353685 230414 353685 4 u_riscv_top.core1_dmem_addr\[23\]
+port 1464 nsew
+rlabel metal3 s 230414 353379 230414 353379 4 u_riscv_top.core1_dmem_addr\[24\]
+port 1465 nsew
+rlabel metal3 s 230414 353141 230414 353141 4 u_riscv_top.core1_dmem_addr\[25\]
+port 1466 nsew
+rlabel metal3 s 230414 352869 230414 352869 4 u_riscv_top.core1_dmem_addr\[26\]
+port 1467 nsew
+rlabel metal3 s 230414 352597 230414 352597 4 u_riscv_top.core1_dmem_addr\[27\]
+port 1468 nsew
+rlabel metal3 s 230414 352325 230414 352325 4 u_riscv_top.core1_dmem_addr\[28\]
+port 1469 nsew
+rlabel metal3 s 230414 352053 230414 352053 4 u_riscv_top.core1_dmem_addr\[29\]
+port 1470 nsew
+rlabel metal3 s 230414 359397 230414 359397 4 u_riscv_top.core1_dmem_addr\[2\]
+port 1471 nsew
+rlabel metal3 s 230414 351781 230414 351781 4 u_riscv_top.core1_dmem_addr\[30\]
+port 1472 nsew
+rlabel metal3 s 230414 351509 230414 351509 4 u_riscv_top.core1_dmem_addr\[31\]
+port 1473 nsew
+rlabel metal3 s 230414 359091 230414 359091 4 u_riscv_top.core1_dmem_addr\[3\]
+port 1474 nsew
+rlabel metal3 s 230414 358853 230414 358853 4 u_riscv_top.core1_dmem_addr\[4\]
+port 1475 nsew
+rlabel metal3 s 230414 358581 230414 358581 4 u_riscv_top.core1_dmem_addr\[5\]
+port 1476 nsew
+rlabel metal3 s 230414 358309 230414 358309 4 u_riscv_top.core1_dmem_addr\[6\]
+port 1477 nsew
+rlabel metal3 s 230414 358037 230414 358037 4 u_riscv_top.core1_dmem_addr\[7\]
+port 1478 nsew
+rlabel metal3 s 230414 357731 230414 357731 4 u_riscv_top.core1_dmem_addr\[8\]
+port 1479 nsew
+rlabel metal3 s 230414 357493 230414 357493 4 u_riscv_top.core1_dmem_addr\[9\]
+port 1480 nsew
+rlabel metal3 s 230414 350693 230414 350693 4 u_riscv_top.core1_dmem_cmd
+port 1481 nsew
+rlabel metal3 s 230414 377349 230414 377349 4 u_riscv_top.core1_dmem_rdata\[0\]
+port 1482 nsew
+rlabel metal3 s 230414 374629 230414 374629 4 u_riscv_top.core1_dmem_rdata\[10\]
+port 1483 nsew
+rlabel metal3 s 230414 374323 230414 374323 4 u_riscv_top.core1_dmem_rdata\[11\]
+port 1484 nsew
+rlabel metal3 s 230414 374085 230414 374085 4 u_riscv_top.core1_dmem_rdata\[12\]
+port 1485 nsew
+rlabel metal3 s 230414 373813 230414 373813 4 u_riscv_top.core1_dmem_rdata\[13\]
+port 1486 nsew
+rlabel metal3 s 230414 373541 230414 373541 4 u_riscv_top.core1_dmem_rdata\[14\]
+port 1487 nsew
+rlabel metal3 s 230414 373269 230414 373269 4 u_riscv_top.core1_dmem_rdata\[15\]
+port 1488 nsew
+rlabel metal3 s 230414 372963 230414 372963 4 u_riscv_top.core1_dmem_rdata\[16\]
+port 1489 nsew
+rlabel metal3 s 230414 372725 230414 372725 4 u_riscv_top.core1_dmem_rdata\[17\]
+port 1490 nsew
+rlabel metal3 s 230414 372453 230414 372453 4 u_riscv_top.core1_dmem_rdata\[18\]
+port 1491 nsew
+rlabel metal3 s 230414 372181 230414 372181 4 u_riscv_top.core1_dmem_rdata\[19\]
+port 1492 nsew
+rlabel metal3 s 230414 377043 230414 377043 4 u_riscv_top.core1_dmem_rdata\[1\]
+port 1493 nsew
+rlabel metal3 s 230414 371909 230414 371909 4 u_riscv_top.core1_dmem_rdata\[20\]
+port 1494 nsew
+rlabel metal3 s 230414 371603 230414 371603 4 u_riscv_top.core1_dmem_rdata\[21\]
+port 1495 nsew
+rlabel metal3 s 230414 371365 230414 371365 4 u_riscv_top.core1_dmem_rdata\[22\]
+port 1496 nsew
+rlabel metal3 s 230414 371093 230414 371093 4 u_riscv_top.core1_dmem_rdata\[23\]
+port 1497 nsew
+rlabel metal3 s 230414 370821 230414 370821 4 u_riscv_top.core1_dmem_rdata\[24\]
+port 1498 nsew
+rlabel metal3 s 230414 370549 230414 370549 4 u_riscv_top.core1_dmem_rdata\[25\]
+port 1499 nsew
+rlabel metal3 s 230414 370277 230414 370277 4 u_riscv_top.core1_dmem_rdata\[26\]
+port 1500 nsew
+rlabel metal3 s 230414 370005 230414 370005 4 u_riscv_top.core1_dmem_rdata\[27\]
+port 1501 nsew
+rlabel metal3 s 230414 369733 230414 369733 4 u_riscv_top.core1_dmem_rdata\[28\]
+port 1502 nsew
+rlabel metal3 s 230414 369461 230414 369461 4 u_riscv_top.core1_dmem_rdata\[29\]
+port 1503 nsew
+rlabel metal3 s 230414 376805 230414 376805 4 u_riscv_top.core1_dmem_rdata\[2\]
+port 1504 nsew
+rlabel metal3 s 230414 369189 230414 369189 4 u_riscv_top.core1_dmem_rdata\[30\]
+port 1505 nsew
+rlabel metal3 s 230414 368917 230414 368917 4 u_riscv_top.core1_dmem_rdata\[31\]
+port 1506 nsew
+rlabel metal3 s 230414 376533 230414 376533 4 u_riscv_top.core1_dmem_rdata\[3\]
+port 1507 nsew
+rlabel metal3 s 230414 376261 230414 376261 4 u_riscv_top.core1_dmem_rdata\[4\]
+port 1508 nsew
+rlabel metal3 s 230414 375989 230414 375989 4 u_riscv_top.core1_dmem_rdata\[5\]
+port 1509 nsew
+rlabel metal3 s 230414 375683 230414 375683 4 u_riscv_top.core1_dmem_rdata\[6\]
+port 1510 nsew
+rlabel metal3 s 230414 375445 230414 375445 4 u_riscv_top.core1_dmem_rdata\[7\]
+port 1511 nsew
+rlabel metal3 s 230414 375173 230414 375173 4 u_riscv_top.core1_dmem_rdata\[8\]
+port 1512 nsew
+rlabel metal3 s 230414 374901 230414 374901 4 u_riscv_top.core1_dmem_rdata\[9\]
+port 1513 nsew
+rlabel metal3 s 230414 350421 230414 350421 4 u_riscv_top.core1_dmem_req
+port 1514 nsew
+rlabel metal3 s 230414 350149 230414 350149 4 u_riscv_top.core1_dmem_req_ack
+port 1515 nsew
+rlabel metal3 s 230414 377859 230414 377859 4 u_riscv_top.core1_dmem_resp\[0\]
+port 1516 nsew
+rlabel metal3 s 230414 377621 230414 377621 4 u_riscv_top.core1_dmem_resp\[1\]
+port 1517 nsew
+rlabel metal3 s 230414 368645 230414 368645 4 u_riscv_top.core1_dmem_wdata\[0\]
+port 1518 nsew
+rlabel metal3 s 229586 365925 229586 365925 4 u_riscv_top.core1_dmem_wdata\[10\]
+port 1519 nsew
+rlabel metal3 s 230414 365619 230414 365619 4 u_riscv_top.core1_dmem_wdata\[11\]
+port 1520 nsew
+rlabel metal3 s 230414 365381 230414 365381 4 u_riscv_top.core1_dmem_wdata\[12\]
+port 1521 nsew
+rlabel metal3 s 230414 365109 230414 365109 4 u_riscv_top.core1_dmem_wdata\[13\]
+port 1522 nsew
+rlabel metal3 s 230414 364837 230414 364837 4 u_riscv_top.core1_dmem_wdata\[14\]
+port 1523 nsew
+rlabel metal3 s 230414 364565 230414 364565 4 u_riscv_top.core1_dmem_wdata\[15\]
+port 1524 nsew
+rlabel metal3 s 230414 364259 230414 364259 4 u_riscv_top.core1_dmem_wdata\[16\]
+port 1525 nsew
+rlabel metal3 s 230414 364021 230414 364021 4 u_riscv_top.core1_dmem_wdata\[17\]
+port 1526 nsew
+rlabel metal3 s 230414 363749 230414 363749 4 u_riscv_top.core1_dmem_wdata\[18\]
+port 1527 nsew
+rlabel metal3 s 230414 363477 230414 363477 4 u_riscv_top.core1_dmem_wdata\[19\]
+port 1528 nsew
+rlabel metal3 s 230414 368373 230414 368373 4 u_riscv_top.core1_dmem_wdata\[1\]
+port 1529 nsew
+rlabel metal3 s 230414 363205 230414 363205 4 u_riscv_top.core1_dmem_wdata\[20\]
+port 1530 nsew
+rlabel metal3 s 230414 362899 230414 362899 4 u_riscv_top.core1_dmem_wdata\[21\]
+port 1531 nsew
+rlabel metal3 s 230414 362627 230414 362627 4 u_riscv_top.core1_dmem_wdata\[22\]
+port 1532 nsew
+rlabel metal3 s 230414 362389 230414 362389 4 u_riscv_top.core1_dmem_wdata\[23\]
+port 1533 nsew
+rlabel metal3 s 230414 362117 230414 362117 4 u_riscv_top.core1_dmem_wdata\[24\]
+port 1534 nsew
+rlabel metal3 s 230414 361845 230414 361845 4 u_riscv_top.core1_dmem_wdata\[25\]
+port 1535 nsew
+rlabel metal3 s 230414 361539 230414 361539 4 u_riscv_top.core1_dmem_wdata\[26\]
+port 1536 nsew
+rlabel metal3 s 230414 361267 230414 361267 4 u_riscv_top.core1_dmem_wdata\[27\]
+port 1537 nsew
+rlabel metal3 s 230414 361029 230414 361029 4 u_riscv_top.core1_dmem_wdata\[28\]
+port 1538 nsew
+rlabel metal3 s 230414 360757 230414 360757 4 u_riscv_top.core1_dmem_wdata\[29\]
+port 1539 nsew
+rlabel metal3 s 230414 368101 230414 368101 4 u_riscv_top.core1_dmem_wdata\[2\]
+port 1540 nsew
+rlabel metal3 s 230414 360485 230414 360485 4 u_riscv_top.core1_dmem_wdata\[30\]
+port 1541 nsew
+rlabel metal3 s 230414 360213 230414 360213 4 u_riscv_top.core1_dmem_wdata\[31\]
+port 1542 nsew
+rlabel metal3 s 230414 367829 230414 367829 4 u_riscv_top.core1_dmem_wdata\[3\]
+port 1543 nsew
+rlabel metal3 s 230414 367557 230414 367557 4 u_riscv_top.core1_dmem_wdata\[4\]
+port 1544 nsew
+rlabel metal3 s 230414 367285 230414 367285 4 u_riscv_top.core1_dmem_wdata\[5\]
+port 1545 nsew
+rlabel metal3 s 230414 366979 230414 366979 4 u_riscv_top.core1_dmem_wdata\[6\]
+port 1546 nsew
+rlabel metal3 s 230414 366741 230414 366741 4 u_riscv_top.core1_dmem_wdata\[7\]
+port 1547 nsew
+rlabel metal3 s 230414 366469 230414 366469 4 u_riscv_top.core1_dmem_wdata\[8\]
+port 1548 nsew
+rlabel metal3 s 230414 366197 230414 366197 4 u_riscv_top.core1_dmem_wdata\[9\]
+port 1549 nsew
+rlabel metal3 s 230414 351237 230414 351237 4 u_riscv_top.core1_dmem_width\[0\]
+port 1550 nsew
+rlabel metal3 s 230414 350965 230414 350965 4 u_riscv_top.core1_dmem_width\[1\]
+port 1551 nsew
+rlabel metal3 s 229310 330293 229310 330293 4 u_riscv_top.core1_imem_addr\[0\]
+port 1552 nsew
+rlabel metal3 s 229310 327573 229310 327573 4 u_riscv_top.core1_imem_addr\[10\]
+port 1553 nsew
+rlabel metal3 s 230414 327267 230414 327267 4 u_riscv_top.core1_imem_addr\[11\]
+port 1554 nsew
+rlabel metal3 s 230414 327029 230414 327029 4 u_riscv_top.core1_imem_addr\[12\]
+port 1555 nsew
+rlabel metal3 s 230414 326757 230414 326757 4 u_riscv_top.core1_imem_addr\[13\]
+port 1556 nsew
+rlabel metal3 s 230414 326485 230414 326485 4 u_riscv_top.core1_imem_addr\[14\]
+port 1557 nsew
+rlabel metal3 s 230414 326179 230414 326179 4 u_riscv_top.core1_imem_addr\[15\]
+port 1558 nsew
+rlabel metal3 s 230414 325907 230414 325907 4 u_riscv_top.core1_imem_addr\[16\]
+port 1559 nsew
+rlabel metal3 s 230414 325635 230414 325635 4 u_riscv_top.core1_imem_addr\[17\]
+port 1560 nsew
+rlabel metal3 s 230414 325363 230414 325363 4 u_riscv_top.core1_imem_addr\[18\]
+port 1561 nsew
+rlabel metal3 s 230414 325125 230414 325125 4 u_riscv_top.core1_imem_addr\[19\]
+port 1562 nsew
+rlabel metal3 s 230414 329987 230414 329987 4 u_riscv_top.core1_imem_addr\[1\]
+port 1563 nsew
+rlabel metal3 s 230414 324853 230414 324853 4 u_riscv_top.core1_imem_addr\[20\]
+port 1564 nsew
+rlabel metal3 s 230414 324581 230414 324581 4 u_riscv_top.core1_imem_addr\[21\]
+port 1565 nsew
+rlabel metal3 s 230414 324275 230414 324275 4 u_riscv_top.core1_imem_addr\[22\]
+port 1566 nsew
+rlabel metal3 s 230414 324003 230414 324003 4 u_riscv_top.core1_imem_addr\[23\]
+port 1567 nsew
+rlabel metal3 s 230414 323765 230414 323765 4 u_riscv_top.core1_imem_addr\[24\]
+port 1568 nsew
+rlabel metal3 s 230414 323493 230414 323493 4 u_riscv_top.core1_imem_addr\[25\]
+port 1569 nsew
+rlabel metal3 s 230414 323221 230414 323221 4 u_riscv_top.core1_imem_addr\[26\]
+port 1570 nsew
+rlabel metal3 s 230414 322949 230414 322949 4 u_riscv_top.core1_imem_addr\[27\]
+port 1571 nsew
+rlabel metal3 s 230414 322677 230414 322677 4 u_riscv_top.core1_imem_addr\[28\]
+port 1572 nsew
+rlabel metal3 s 230414 322405 230414 322405 4 u_riscv_top.core1_imem_addr\[29\]
+port 1573 nsew
+rlabel metal3 s 230414 329749 230414 329749 4 u_riscv_top.core1_imem_addr\[2\]
+port 1574 nsew
+rlabel metal3 s 230414 322133 230414 322133 4 u_riscv_top.core1_imem_addr\[30\]
+port 1575 nsew
+rlabel metal3 s 230414 321861 230414 321861 4 u_riscv_top.core1_imem_addr\[31\]
+port 1576 nsew
+rlabel metal3 s 230414 329477 230414 329477 4 u_riscv_top.core1_imem_addr\[3\]
+port 1577 nsew
+rlabel metal3 s 230414 329205 230414 329205 4 u_riscv_top.core1_imem_addr\[4\]
+port 1578 nsew
+rlabel metal3 s 230414 328933 230414 328933 4 u_riscv_top.core1_imem_addr\[5\]
+port 1579 nsew
+rlabel metal3 s 230414 328627 230414 328627 4 u_riscv_top.core1_imem_addr\[6\]
+port 1580 nsew
+rlabel metal3 s 230414 328389 230414 328389 4 u_riscv_top.core1_imem_addr\[7\]
+port 1581 nsew
+rlabel metal3 s 230414 328117 230414 328117 4 u_riscv_top.core1_imem_addr\[8\]
+port 1582 nsew
+rlabel metal3 s 230414 327845 230414 327845 4 u_riscv_top.core1_imem_addr\[9\]
+port 1583 nsew
+rlabel metal3 s 230414 331109 230414 331109 4 u_riscv_top.core1_imem_bl\[0\]
+port 1584 nsew
+rlabel metal3 s 230414 330803 230414 330803 4 u_riscv_top.core1_imem_bl\[1\]
+port 1585 nsew
+rlabel metal3 s 230414 330565 230414 330565 4 u_riscv_top.core1_imem_bl\[2\]
+port 1586 nsew
+rlabel metal3 s 230414 321589 230414 321589 4 u_riscv_top.core1_imem_cmd
+port 1587 nsew
+rlabel metal3 s 230414 339779 230414 339779 4 u_riscv_top.core1_imem_rdata\[0\]
+port 1588 nsew
+rlabel metal3 s 230414 337059 230414 337059 4 u_riscv_top.core1_imem_rdata\[10\]
+port 1589 nsew
+rlabel metal3 s 230414 336821 230414 336821 4 u_riscv_top.core1_imem_rdata\[11\]
+port 1590 nsew
+rlabel metal3 s 230414 336549 230414 336549 4 u_riscv_top.core1_imem_rdata\[12\]
+port 1591 nsew
+rlabel metal3 s 230414 336277 230414 336277 4 u_riscv_top.core1_imem_rdata\[13\]
+port 1592 nsew
+rlabel metal3 s 230414 336005 230414 336005 4 u_riscv_top.core1_imem_rdata\[14\]
+port 1593 nsew
+rlabel metal3 s 230414 335699 230414 335699 4 u_riscv_top.core1_imem_rdata\[15\]
+port 1594 nsew
+rlabel metal3 s 230414 335461 230414 335461 4 u_riscv_top.core1_imem_rdata\[16\]
+port 1595 nsew
+rlabel metal3 s 230414 335189 230414 335189 4 u_riscv_top.core1_imem_rdata\[17\]
+port 1596 nsew
+rlabel metal3 s 230414 334917 230414 334917 4 u_riscv_top.core1_imem_rdata\[18\]
+port 1597 nsew
+rlabel metal3 s 230414 334645 230414 334645 4 u_riscv_top.core1_imem_rdata\[19\]
+port 1598 nsew
+rlabel metal3 s 230414 339541 230414 339541 4 u_riscv_top.core1_imem_rdata\[1\]
+port 1599 nsew
+rlabel metal3 s 230414 334373 230414 334373 4 u_riscv_top.core1_imem_rdata\[20\]
+port 1600 nsew
+rlabel metal3 s 230414 334101 230414 334101 4 u_riscv_top.core1_imem_rdata\[21\]
+port 1601 nsew
+rlabel metal3 s 230414 333829 230414 333829 4 u_riscv_top.core1_imem_rdata\[22\]
+port 1602 nsew
+rlabel metal3 s 230414 333557 230414 333557 4 u_riscv_top.core1_imem_rdata\[23\]
+port 1603 nsew
+rlabel metal3 s 230414 333285 230414 333285 4 u_riscv_top.core1_imem_rdata\[24\]
+port 1604 nsew
+rlabel metal3 s 230414 332979 230414 332979 4 u_riscv_top.core1_imem_rdata\[25\]
+port 1605 nsew
+rlabel metal3 s 230414 332741 230414 332741 4 u_riscv_top.core1_imem_rdata\[26\]
+port 1606 nsew
+rlabel metal3 s 230414 332469 230414 332469 4 u_riscv_top.core1_imem_rdata\[27\]
+port 1607 nsew
+rlabel metal3 s 230414 332197 230414 332197 4 u_riscv_top.core1_imem_rdata\[28\]
+port 1608 nsew
+rlabel metal3 s 230414 331925 230414 331925 4 u_riscv_top.core1_imem_rdata\[29\]
+port 1609 nsew
+rlabel metal3 s 230414 339269 230414 339269 4 u_riscv_top.core1_imem_rdata\[2\]
+port 1610 nsew
+rlabel metal3 s 230414 331619 230414 331619 4 u_riscv_top.core1_imem_rdata\[30\]
+port 1611 nsew
+rlabel metal3 s 230414 331381 230414 331381 4 u_riscv_top.core1_imem_rdata\[31\]
+port 1612 nsew
+rlabel metal3 s 230414 338997 230414 338997 4 u_riscv_top.core1_imem_rdata\[3\]
+port 1613 nsew
+rlabel metal3 s 230414 338725 230414 338725 4 u_riscv_top.core1_imem_rdata\[4\]
+port 1614 nsew
+rlabel metal3 s 230414 338419 230414 338419 4 u_riscv_top.core1_imem_rdata\[5\]
+port 1615 nsew
+rlabel metal3 s 230414 338181 230414 338181 4 u_riscv_top.core1_imem_rdata\[6\]
+port 1616 nsew
+rlabel metal3 s 230414 337909 230414 337909 4 u_riscv_top.core1_imem_rdata\[7\]
+port 1617 nsew
+rlabel metal3 s 230414 337637 230414 337637 4 u_riscv_top.core1_imem_rdata\[8\]
+port 1618 nsew
+rlabel metal3 s 230414 337331 230414 337331 4 u_riscv_top.core1_imem_rdata\[9\]
+port 1619 nsew
+rlabel metal3 s 230414 321317 230414 321317 4 u_riscv_top.core1_imem_req
+port 1620 nsew
+rlabel metal3 s 230414 321045 230414 321045 4 u_riscv_top.core1_imem_req_ack
+port 1621 nsew
+rlabel metal3 s 230414 340357 230414 340357 4 u_riscv_top.core1_imem_resp\[0\]
+port 1622 nsew
+rlabel metal3 s 230414 340051 230414 340051 4 u_riscv_top.core1_imem_resp\[1\]
+port 1623 nsew
+rlabel metal3 s 230414 426275 230414 426275 4 u_riscv_top.core1_irq_lines\[0\]
+port 1624 nsew
+rlabel metal3 s 230414 423589 230414 423589 4 u_riscv_top.core1_irq_lines\[10\]
+port 1625 nsew
+rlabel metal3 s 230414 423317 230414 423317 4 u_riscv_top.core1_irq_lines\[11\]
+port 1626 nsew
+rlabel metal3 s 230414 423045 230414 423045 4 u_riscv_top.core1_irq_lines\[12\]
+port 1627 nsew
+rlabel metal3 s 230414 422773 230414 422773 4 u_riscv_top.core1_irq_lines\[13\]
+port 1628 nsew
+rlabel metal3 s 230414 422501 230414 422501 4 u_riscv_top.core1_irq_lines\[14\]
+port 1629 nsew
+rlabel metal3 s 230414 422195 230414 422195 4 u_riscv_top.core1_irq_lines\[15\]
+port 1630 nsew
+rlabel metal3 s 230414 421957 230414 421957 4 u_riscv_top.core1_irq_lines\[16\]
+port 1631 nsew
+rlabel metal3 s 230414 421685 230414 421685 4 u_riscv_top.core1_irq_lines\[17\]
+port 1632 nsew
+rlabel metal3 s 230414 421413 230414 421413 4 u_riscv_top.core1_irq_lines\[18\]
+port 1633 nsew
+rlabel metal3 s 230414 421141 230414 421141 4 u_riscv_top.core1_irq_lines\[19\]
+port 1634 nsew
+rlabel metal3 s 230414 426037 230414 426037 4 u_riscv_top.core1_irq_lines\[1\]
+port 1635 nsew
+rlabel metal3 s 230414 420835 230414 420835 4 u_riscv_top.core1_irq_lines\[20\]
+port 1636 nsew
+rlabel metal3 s 230414 420563 230414 420563 4 u_riscv_top.core1_irq_lines\[21\]
+port 1637 nsew
+rlabel metal3 s 230414 420325 230414 420325 4 u_riscv_top.core1_irq_lines\[22\]
+port 1638 nsew
+rlabel metal3 s 230414 420053 230414 420053 4 u_riscv_top.core1_irq_lines\[23\]
+port 1639 nsew
+rlabel metal3 s 230414 419781 230414 419781 4 u_riscv_top.core1_irq_lines\[24\]
+port 1640 nsew
+rlabel metal3 s 230414 419475 230414 419475 4 u_riscv_top.core1_irq_lines\[25\]
+port 1641 nsew
+rlabel metal3 s 230414 419203 230414 419203 4 u_riscv_top.core1_irq_lines\[26\]
+port 1642 nsew
+rlabel metal3 s 230414 418965 230414 418965 4 u_riscv_top.core1_irq_lines\[27\]
+port 1643 nsew
+rlabel metal3 s 230414 418693 230414 418693 4 u_riscv_top.core1_irq_lines\[28\]
+port 1644 nsew
+rlabel metal3 s 230414 418421 230414 418421 4 u_riscv_top.core1_irq_lines\[29\]
+port 1645 nsew
+rlabel metal3 s 230414 425765 230414 425765 4 u_riscv_top.core1_irq_lines\[2\]
+port 1646 nsew
+rlabel metal3 s 230414 418115 230414 418115 4 u_riscv_top.core1_irq_lines\[30\]
+port 1647 nsew
+rlabel metal3 s 230414 417843 230414 417843 4 u_riscv_top.core1_irq_lines\[31\]
+port 1648 nsew
+rlabel metal3 s 230414 425493 230414 425493 4 u_riscv_top.core1_irq_lines\[3\]
+port 1649 nsew
+rlabel metal3 s 230414 425221 230414 425221 4 u_riscv_top.core1_irq_lines\[4\]
+port 1650 nsew
+rlabel metal3 s 230414 424949 230414 424949 4 u_riscv_top.core1_irq_lines\[5\]
+port 1651 nsew
+rlabel metal3 s 230414 424677 230414 424677 4 u_riscv_top.core1_irq_lines\[6\]
+port 1652 nsew
+rlabel metal3 s 230414 424405 230414 424405 4 u_riscv_top.core1_irq_lines\[7\]
+port 1653 nsew
+rlabel metal3 s 230414 424133 230414 424133 4 u_riscv_top.core1_irq_lines\[8\]
+port 1654 nsew
+rlabel metal3 s 230414 423861 230414 423861 4 u_riscv_top.core1_irq_lines\[9\]
+port 1655 nsew
+rlabel metal3 s 230414 426547 230414 426547 4 u_riscv_top.core1_soft_irq
+port 1656 nsew
+rlabel metal3 s 230414 400163 230414 400163 4 u_riscv_top.core1_timer_irq
+port 1657 nsew
+rlabel metal3 s 230414 417605 230414 417605 4 u_riscv_top.core1_timer_val\[0\]
+port 1658 nsew
+rlabel metal3 s 230414 414885 230414 414885 4 u_riscv_top.core1_timer_val\[10\]
+port 1659 nsew
+rlabel metal3 s 230414 414613 230414 414613 4 u_riscv_top.core1_timer_val\[11\]
+port 1660 nsew
+rlabel metal3 s 230414 414307 230414 414307 4 u_riscv_top.core1_timer_val\[12\]
+port 1661 nsew
+rlabel metal3 s 230414 414069 230414 414069 4 u_riscv_top.core1_timer_val\[13\]
+port 1662 nsew
+rlabel metal3 s 230414 413797 230414 413797 4 u_riscv_top.core1_timer_val\[14\]
+port 1663 nsew
+rlabel metal3 s 230414 413525 230414 413525 4 u_riscv_top.core1_timer_val\[15\]
+port 1664 nsew
+rlabel metal3 s 230414 413253 230414 413253 4 u_riscv_top.core1_timer_val\[16\]
+port 1665 nsew
+rlabel metal3 s 230414 412981 230414 412981 4 u_riscv_top.core1_timer_val\[17\]
+port 1666 nsew
+rlabel metal3 s 230414 412709 230414 412709 4 u_riscv_top.core1_timer_val\[18\]
+port 1667 nsew
+rlabel metal3 s 230414 412437 230414 412437 4 u_riscv_top.core1_timer_val\[19\]
+port 1668 nsew
+rlabel metal3 s 230414 417333 230414 417333 4 u_riscv_top.core1_timer_val\[1\]
+port 1669 nsew
+rlabel metal3 s 230414 412165 230414 412165 4 u_riscv_top.core1_timer_val\[20\]
+port 1670 nsew
+rlabel metal3 s 230414 411893 230414 411893 4 u_riscv_top.core1_timer_val\[21\]
+port 1671 nsew
+rlabel metal3 s 230414 411621 230414 411621 4 u_riscv_top.core1_timer_val\[22\]
+port 1672 nsew
+rlabel metal3 s 230414 411315 230414 411315 4 u_riscv_top.core1_timer_val\[23\]
+port 1673 nsew
+rlabel metal3 s 230414 411077 230414 411077 4 u_riscv_top.core1_timer_val\[24\]
+port 1674 nsew
+rlabel metal3 s 230414 410805 230414 410805 4 u_riscv_top.core1_timer_val\[25\]
+port 1675 nsew
+rlabel metal3 s 230414 410533 230414 410533 4 u_riscv_top.core1_timer_val\[26\]
+port 1676 nsew
+rlabel metal3 s 230414 410261 230414 410261 4 u_riscv_top.core1_timer_val\[27\]
+port 1677 nsew
+rlabel metal3 s 230414 409989 230414 409989 4 u_riscv_top.core1_timer_val\[28\]
+port 1678 nsew
+rlabel metal3 s 230414 409717 230414 409717 4 u_riscv_top.core1_timer_val\[29\]
+port 1679 nsew
+rlabel metal3 s 230414 417061 230414 417061 4 u_riscv_top.core1_timer_val\[2\]
+port 1680 nsew
+rlabel metal3 s 230414 409445 230414 409445 4 u_riscv_top.core1_timer_val\[30\]
+port 1681 nsew
+rlabel metal3 s 230414 409173 230414 409173 4 u_riscv_top.core1_timer_val\[31\]
+port 1682 nsew
+rlabel metal3 s 230414 408901 230414 408901 4 u_riscv_top.core1_timer_val\[32\]
+port 1683 nsew
+rlabel metal3 s 230414 408629 230414 408629 4 u_riscv_top.core1_timer_val\[33\]
+port 1684 nsew
+rlabel metal3 s 230414 408357 230414 408357 4 u_riscv_top.core1_timer_val\[34\]
+port 1685 nsew
+rlabel metal3 s 230414 408085 230414 408085 4 u_riscv_top.core1_timer_val\[35\]
+port 1686 nsew
+rlabel metal3 s 230414 407813 230414 407813 4 u_riscv_top.core1_timer_val\[36\]
+port 1687 nsew
+rlabel metal3 s 230414 407541 230414 407541 4 u_riscv_top.core1_timer_val\[37\]
+port 1688 nsew
+rlabel metal3 s 230414 407269 230414 407269 4 u_riscv_top.core1_timer_val\[38\]
+port 1689 nsew
+rlabel metal3 s 230414 406997 230414 406997 4 u_riscv_top.core1_timer_val\[39\]
+port 1690 nsew
+rlabel metal3 s 230414 416789 230414 416789 4 u_riscv_top.core1_timer_val\[3\]
+port 1691 nsew
+rlabel metal3 s 230414 406725 230414 406725 4 u_riscv_top.core1_timer_val\[40\]
+port 1692 nsew
+rlabel metal3 s 230414 406453 230414 406453 4 u_riscv_top.core1_timer_val\[41\]
+port 1693 nsew
+rlabel metal3 s 230414 406181 230414 406181 4 u_riscv_top.core1_timer_val\[42\]
+port 1694 nsew
+rlabel metal3 s 230414 405875 230414 405875 4 u_riscv_top.core1_timer_val\[43\]
+port 1695 nsew
+rlabel metal3 s 230414 405637 230414 405637 4 u_riscv_top.core1_timer_val\[44\]
+port 1696 nsew
+rlabel metal3 s 230414 405365 230414 405365 4 u_riscv_top.core1_timer_val\[45\]
+port 1697 nsew
+rlabel metal3 s 230414 405093 230414 405093 4 u_riscv_top.core1_timer_val\[46\]
+port 1698 nsew
+rlabel metal3 s 230414 404821 230414 404821 4 u_riscv_top.core1_timer_val\[47\]
+port 1699 nsew
+rlabel metal3 s 230414 404515 230414 404515 4 u_riscv_top.core1_timer_val\[48\]
+port 1700 nsew
+rlabel metal3 s 230414 404277 230414 404277 4 u_riscv_top.core1_timer_val\[49\]
+port 1701 nsew
+rlabel metal3 s 230414 416517 230414 416517 4 u_riscv_top.core1_timer_val\[4\]
+port 1702 nsew
+rlabel metal3 s 230414 404005 230414 404005 4 u_riscv_top.core1_timer_val\[50\]
+port 1703 nsew
+rlabel metal3 s 230414 403733 230414 403733 4 u_riscv_top.core1_timer_val\[51\]
+port 1704 nsew
+rlabel metal3 s 230414 403461 230414 403461 4 u_riscv_top.core1_timer_val\[52\]
+port 1705 nsew
+rlabel metal3 s 230414 403155 230414 403155 4 u_riscv_top.core1_timer_val\[53\]
+port 1706 nsew
+rlabel metal3 s 230414 402917 230414 402917 4 u_riscv_top.core1_timer_val\[54\]
+port 1707 nsew
+rlabel metal3 s 230414 402645 230414 402645 4 u_riscv_top.core1_timer_val\[55\]
+port 1708 nsew
+rlabel metal3 s 230414 402373 230414 402373 4 u_riscv_top.core1_timer_val\[56\]
+port 1709 nsew
+rlabel metal3 s 230414 402101 230414 402101 4 u_riscv_top.core1_timer_val\[57\]
+port 1710 nsew
+rlabel metal3 s 230414 401829 230414 401829 4 u_riscv_top.core1_timer_val\[58\]
+port 1711 nsew
+rlabel metal3 s 230414 401523 230414 401523 4 u_riscv_top.core1_timer_val\[59\]
+port 1712 nsew
+rlabel metal3 s 230414 416245 230414 416245 4 u_riscv_top.core1_timer_val\[5\]
+port 1713 nsew
+rlabel metal3 s 230414 401251 230414 401251 4 u_riscv_top.core1_timer_val\[60\]
+port 1714 nsew
+rlabel metal3 s 230414 401013 230414 401013 4 u_riscv_top.core1_timer_val\[61\]
+port 1715 nsew
+rlabel metal3 s 230414 400741 230414 400741 4 u_riscv_top.core1_timer_val\[62\]
+port 1716 nsew
+rlabel metal3 s 230414 400435 230414 400435 4 u_riscv_top.core1_timer_val\[63\]
+port 1717 nsew
+rlabel metal3 s 230414 415973 230414 415973 4 u_riscv_top.core1_timer_val\[6\]
+port 1718 nsew
+rlabel metal3 s 230414 415701 230414 415701 4 u_riscv_top.core1_timer_val\[7\]
+port 1719 nsew
+rlabel metal3 s 230414 415429 230414 415429 4 u_riscv_top.core1_timer_val\[8\]
+port 1720 nsew
+rlabel metal3 s 230414 415157 230414 415157 4 u_riscv_top.core1_timer_val\[9\]
+port 1721 nsew
+rlabel metal3 s 230414 320773 230414 320773 4 u_riscv_top.core1_uid\[0\]
+port 1722 nsew
+rlabel metal3 s 230414 320501 230414 320501 4 u_riscv_top.core1_uid\[1\]
+port 1723 nsew
+rlabel metal3 s 129919 520200 129919 520200 4 u_riscv_top.core2_clk
+port 1724 nsew
+rlabel metal3 s 130678 593164 130678 593164 4 u_riscv_top.core2_debug\[0\]
+port 1725 nsew
+rlabel metal3 s 130586 590444 130586 590444 4 u_riscv_top.core2_debug\[10\]
+port 1726 nsew
+rlabel metal3 s 130494 590172 130494 590172 4 u_riscv_top.core2_debug\[11\]
+port 1727 nsew
+rlabel metal3 s 130540 589900 130540 589900 4 u_riscv_top.core2_debug\[12\]
+port 1728 nsew
+rlabel metal3 s 130632 589628 130632 589628 4 u_riscv_top.core2_debug\[13\]
+port 1729 nsew
+rlabel metal3 s 130494 589356 130494 589356 4 u_riscv_top.core2_debug\[14\]
+port 1730 nsew
+rlabel metal3 s 130540 589084 130540 589084 4 u_riscv_top.core2_debug\[15\]
+port 1731 nsew
+rlabel metal3 s 130494 588812 130494 588812 4 u_riscv_top.core2_debug\[16\]
+port 1732 nsew
+rlabel metal3 s 130632 588540 130632 588540 4 u_riscv_top.core2_debug\[17\]
+port 1733 nsew
+rlabel metal3 s 130494 588268 130494 588268 4 u_riscv_top.core2_debug\[18\]
+port 1734 nsew
+rlabel metal3 s 130586 587996 130586 587996 4 u_riscv_top.core2_debug\[19\]
+port 1735 nsew
+rlabel metal3 s 130494 592892 130494 592892 4 u_riscv_top.core2_debug\[1\]
+port 1736 nsew
+rlabel metal3 s 130632 587724 130632 587724 4 u_riscv_top.core2_debug\[20\]
+port 1737 nsew
+rlabel metal3 s 130494 587452 130494 587452 4 u_riscv_top.core2_debug\[21\]
+port 1738 nsew
+rlabel metal3 s 130540 587180 130540 587180 4 u_riscv_top.core2_debug\[22\]
+port 1739 nsew
+rlabel metal3 s 130586 586908 130586 586908 4 u_riscv_top.core2_debug\[23\]
+port 1740 nsew
+rlabel metal3 s 130678 586636 130678 586636 4 u_riscv_top.core2_debug\[24\]
+port 1741 nsew
+rlabel metal3 s 130494 586364 130494 586364 4 u_riscv_top.core2_debug\[25\]
+port 1742 nsew
+rlabel metal3 s 130540 586092 130540 586092 4 u_riscv_top.core2_debug\[26\]
+port 1743 nsew
+rlabel metal3 s 130494 585820 130494 585820 4 u_riscv_top.core2_debug\[27\]
+port 1744 nsew
+rlabel metal3 s 130540 585548 130540 585548 4 u_riscv_top.core2_debug\[28\]
+port 1745 nsew
+rlabel metal3 s 130586 585276 130586 585276 4 u_riscv_top.core2_debug\[29\]
+port 1746 nsew
+rlabel metal3 s 130632 592620 130632 592620 4 u_riscv_top.core2_debug\[2\]
+port 1747 nsew
+rlabel metal3 s 130586 585004 130586 585004 4 u_riscv_top.core2_debug\[30\]
+port 1748 nsew
+rlabel metal3 s 130494 584732 130494 584732 4 u_riscv_top.core2_debug\[31\]
+port 1749 nsew
+rlabel metal3 s 130540 584460 130540 584460 4 u_riscv_top.core2_debug\[32\]
+port 1750 nsew
+rlabel metal3 s 130494 584188 130494 584188 4 u_riscv_top.core2_debug\[33\]
+port 1751 nsew
+rlabel metal3 s 130632 583916 130632 583916 4 u_riscv_top.core2_debug\[34\]
+port 1752 nsew
+rlabel metal3 s 130494 583644 130494 583644 4 u_riscv_top.core2_debug\[35\]
+port 1753 nsew
+rlabel metal3 s 130540 583372 130540 583372 4 u_riscv_top.core2_debug\[36\]
+port 1754 nsew
+rlabel metal3 s 130494 583100 130494 583100 4 u_riscv_top.core2_debug\[37\]
+port 1755 nsew
+rlabel metal3 s 130540 582828 130540 582828 4 u_riscv_top.core2_debug\[38\]
+port 1756 nsew
+rlabel metal3 s 130494 582556 130494 582556 4 u_riscv_top.core2_debug\[39\]
+port 1757 nsew
+rlabel metal3 s 130586 592348 130586 592348 4 u_riscv_top.core2_debug\[3\]
+port 1758 nsew
+rlabel metal3 s 130586 582284 130586 582284 4 u_riscv_top.core2_debug\[40\]
+port 1759 nsew
+rlabel metal3 s 130540 582012 130540 582012 4 u_riscv_top.core2_debug\[41\]
+port 1760 nsew
+rlabel metal3 s 130494 581740 130494 581740 4 u_riscv_top.core2_debug\[42\]
+port 1761 nsew
+rlabel metal3 s 130494 581468 130494 581468 4 u_riscv_top.core2_debug\[43\]
+port 1762 nsew
+rlabel metal3 s 130586 581196 130586 581196 4 u_riscv_top.core2_debug\[44\]
+port 1763 nsew
+rlabel metal3 s 130586 580924 130586 580924 4 u_riscv_top.core2_debug\[45\]
+port 1764 nsew
+rlabel metal3 s 130540 580652 130540 580652 4 u_riscv_top.core2_debug\[46\]
+port 1765 nsew
+rlabel metal3 s 130494 580380 130494 580380 4 u_riscv_top.core2_debug\[47\]
+port 1766 nsew
+rlabel metal3 s 129919 580176 129919 580176 4 u_riscv_top.core2_debug\[48\]
+port 1767 nsew
+rlabel metal3 s 130540 592076 130540 592076 4 u_riscv_top.core2_debug\[4\]
+port 1768 nsew
+rlabel metal3 s 130540 591804 130540 591804 4 u_riscv_top.core2_debug\[5\]
+port 1769 nsew
+rlabel metal3 s 130494 591532 130494 591532 4 u_riscv_top.core2_debug\[6\]
+port 1770 nsew
+rlabel metal3 s 130678 591260 130678 591260 4 u_riscv_top.core2_debug\[7\]
+port 1771 nsew
+rlabel metal3 s 130632 590988 130632 590988 4 u_riscv_top.core2_debug\[8\]
+port 1772 nsew
+rlabel metal3 s 130586 590716 130586 590716 4 u_riscv_top.core2_debug\[9\]
+port 1773 nsew
+rlabel metal3 s 130632 559844 130632 559844 4 u_riscv_top.core2_dmem_addr\[0\]
+port 1774 nsew
+rlabel metal3 s 130494 557124 130494 557124 4 u_riscv_top.core2_dmem_addr\[10\]
+port 1775 nsew
+rlabel metal3 s 130540 556852 130540 556852 4 u_riscv_top.core2_dmem_addr\[11\]
+port 1776 nsew
+rlabel metal3 s 130586 556580 130586 556580 4 u_riscv_top.core2_dmem_addr\[12\]
+port 1777 nsew
+rlabel metal3 s 130494 556308 130494 556308 4 u_riscv_top.core2_dmem_addr\[13\]
+port 1778 nsew
+rlabel metal3 s 130494 556036 130494 556036 4 u_riscv_top.core2_dmem_addr\[14\]
+port 1779 nsew
+rlabel metal3 s 130540 555764 130540 555764 4 u_riscv_top.core2_dmem_addr\[15\]
+port 1780 nsew
+rlabel metal3 s 130494 555492 130494 555492 4 u_riscv_top.core2_dmem_addr\[16\]
+port 1781 nsew
+rlabel metal3 s 130586 555220 130586 555220 4 u_riscv_top.core2_dmem_addr\[17\]
+port 1782 nsew
+rlabel metal3 s 130632 554948 130632 554948 4 u_riscv_top.core2_dmem_addr\[18\]
+port 1783 nsew
+rlabel metal3 s 130494 554676 130494 554676 4 u_riscv_top.core2_dmem_addr\[19\]
+port 1784 nsew
+rlabel metal3 s 130540 559572 130540 559572 4 u_riscv_top.core2_dmem_addr\[1\]
+port 1785 nsew
+rlabel metal3 s 130540 554404 130540 554404 4 u_riscv_top.core2_dmem_addr\[20\]
+port 1786 nsew
+rlabel metal3 s 130494 554132 130494 554132 4 u_riscv_top.core2_dmem_addr\[21\]
+port 1787 nsew
+rlabel metal3 s 130494 553860 130494 553860 4 u_riscv_top.core2_dmem_addr\[22\]
+port 1788 nsew
+rlabel metal3 s 130586 553588 130586 553588 4 u_riscv_top.core2_dmem_addr\[23\]
+port 1789 nsew
+rlabel metal3 s 130494 553316 130494 553316 4 u_riscv_top.core2_dmem_addr\[24\]
+port 1790 nsew
+rlabel metal3 s 130494 553044 130494 553044 4 u_riscv_top.core2_dmem_addr\[25\]
+port 1791 nsew
+rlabel metal3 s 130494 552772 130494 552772 4 u_riscv_top.core2_dmem_addr\[26\]
+port 1792 nsew
+rlabel metal3 s 130540 552500 130540 552500 4 u_riscv_top.core2_dmem_addr\[27\]
+port 1793 nsew
+rlabel metal3 s 130586 552228 130586 552228 4 u_riscv_top.core2_dmem_addr\[28\]
+port 1794 nsew
+rlabel metal3 s 130494 551956 130494 551956 4 u_riscv_top.core2_dmem_addr\[29\]
+port 1795 nsew
+rlabel metal3 s 130494 559300 130494 559300 4 u_riscv_top.core2_dmem_addr\[2\]
+port 1796 nsew
+rlabel metal3 s 130586 551684 130586 551684 4 u_riscv_top.core2_dmem_addr\[30\]
+port 1797 nsew
+rlabel metal3 s 130494 551412 130494 551412 4 u_riscv_top.core2_dmem_addr\[31\]
+port 1798 nsew
+rlabel metal3 s 130586 559028 130586 559028 4 u_riscv_top.core2_dmem_addr\[3\]
+port 1799 nsew
+rlabel metal3 s 130540 558756 130540 558756 4 u_riscv_top.core2_dmem_addr\[4\]
+port 1800 nsew
+rlabel metal3 s 130494 558484 130494 558484 4 u_riscv_top.core2_dmem_addr\[5\]
+port 1801 nsew
+rlabel metal3 s 130494 558212 130494 558212 4 u_riscv_top.core2_dmem_addr\[6\]
+port 1802 nsew
+rlabel metal3 s 130586 557940 130586 557940 4 u_riscv_top.core2_dmem_addr\[7\]
+port 1803 nsew
+rlabel metal3 s 130540 557668 130540 557668 4 u_riscv_top.core2_dmem_addr\[8\]
+port 1804 nsew
+rlabel metal3 s 147208 557532 147208 557532 4 u_riscv_top.core2_dmem_addr\[9\]
+port 1805 nsew
+rlabel metal3 s 130494 550596 130494 550596 4 u_riscv_top.core2_dmem_cmd
+port 1806 nsew
+rlabel metal3 s 130586 577252 130586 577252 4 u_riscv_top.core2_dmem_rdata\[0\]
+port 1807 nsew
+rlabel metal3 s 130586 574532 130586 574532 4 u_riscv_top.core2_dmem_rdata\[10\]
+port 1808 nsew
+rlabel metal3 s 130540 574260 130540 574260 4 u_riscv_top.core2_dmem_rdata\[11\]
+port 1809 nsew
+rlabel metal3 s 130494 573988 130494 573988 4 u_riscv_top.core2_dmem_rdata\[12\]
+port 1810 nsew
+rlabel metal3 s 130494 573716 130494 573716 4 u_riscv_top.core2_dmem_rdata\[13\]
+port 1811 nsew
+rlabel metal3 s 130494 573444 130494 573444 4 u_riscv_top.core2_dmem_rdata\[14\]
+port 1812 nsew
+rlabel metal3 s 130540 573172 130540 573172 4 u_riscv_top.core2_dmem_rdata\[15\]
+port 1813 nsew
+rlabel metal3 s 130586 572900 130586 572900 4 u_riscv_top.core2_dmem_rdata\[16\]
+port 1814 nsew
+rlabel metal3 s 130494 572628 130494 572628 4 u_riscv_top.core2_dmem_rdata\[17\]
+port 1815 nsew
+rlabel metal3 s 130586 572356 130586 572356 4 u_riscv_top.core2_dmem_rdata\[18\]
+port 1816 nsew
+rlabel metal3 s 130494 572084 130494 572084 4 u_riscv_top.core2_dmem_rdata\[19\]
+port 1817 nsew
+rlabel metal3 s 130632 576980 130632 576980 4 u_riscv_top.core2_dmem_rdata\[1\]
+port 1818 nsew
+rlabel metal3 s 130540 571812 130540 571812 4 u_riscv_top.core2_dmem_rdata\[20\]
+port 1819 nsew
+rlabel metal3 s 130632 571540 130632 571540 4 u_riscv_top.core2_dmem_rdata\[21\]
+port 1820 nsew
+rlabel metal3 s 130494 571268 130494 571268 4 u_riscv_top.core2_dmem_rdata\[22\]
+port 1821 nsew
+rlabel metal3 s 130494 570996 130494 570996 4 u_riscv_top.core2_dmem_rdata\[23\]
+port 1822 nsew
+rlabel metal3 s 130494 570724 130494 570724 4 u_riscv_top.core2_dmem_rdata\[24\]
+port 1823 nsew
+rlabel metal3 s 130540 570452 130540 570452 4 u_riscv_top.core2_dmem_rdata\[25\]
+port 1824 nsew
+rlabel metal3 s 130586 570180 130586 570180 4 u_riscv_top.core2_dmem_rdata\[26\]
+port 1825 nsew
+rlabel metal3 s 130494 569908 130494 569908 4 u_riscv_top.core2_dmem_rdata\[27\]
+port 1826 nsew
+rlabel metal3 s 130540 569636 130540 569636 4 u_riscv_top.core2_dmem_rdata\[28\]
+port 1827 nsew
+rlabel metal3 s 130494 569364 130494 569364 4 u_riscv_top.core2_dmem_rdata\[29\]
+port 1828 nsew
+rlabel metal3 s 147208 576844 147208 576844 4 u_riscv_top.core2_dmem_rdata\[2\]
+port 1829 nsew
+rlabel metal3 s 130494 569092 130494 569092 4 u_riscv_top.core2_dmem_rdata\[30\]
+port 1830 nsew
+rlabel metal3 s 130540 568820 130540 568820 4 u_riscv_top.core2_dmem_rdata\[31\]
+port 1831 nsew
+rlabel metal3 s 130586 576436 130586 576436 4 u_riscv_top.core2_dmem_rdata\[3\]
+port 1832 nsew
+rlabel metal3 s 130540 576164 130540 576164 4 u_riscv_top.core2_dmem_rdata\[4\]
+port 1833 nsew
+rlabel metal3 s 130632 575892 130632 575892 4 u_riscv_top.core2_dmem_rdata\[5\]
+port 1834 nsew
+rlabel metal3 s 130494 575620 130494 575620 4 u_riscv_top.core2_dmem_rdata\[6\]
+port 1835 nsew
+rlabel metal3 s 130494 575348 130494 575348 4 u_riscv_top.core2_dmem_rdata\[7\]
+port 1836 nsew
+rlabel metal3 s 130540 575076 130540 575076 4 u_riscv_top.core2_dmem_rdata\[8\]
+port 1837 nsew
+rlabel metal3 s 130494 574804 130494 574804 4 u_riscv_top.core2_dmem_rdata\[9\]
+port 1838 nsew
+rlabel metal3 s 130540 550324 130540 550324 4 u_riscv_top.core2_dmem_req
+port 1839 nsew
+rlabel metal3 s 129919 550120 129919 550120 4 u_riscv_top.core2_dmem_req_ack
+port 1840 nsew
+rlabel metal3 s 130540 577796 130540 577796 4 u_riscv_top.core2_dmem_resp\[0\]
+port 1841 nsew
+rlabel metal3 s 130494 577524 130494 577524 4 u_riscv_top.core2_dmem_resp\[1\]
+port 1842 nsew
+rlabel metal3 s 130494 568548 130494 568548 4 u_riscv_top.core2_dmem_wdata\[0\]
+port 1843 nsew
+rlabel metal3 s 130678 565828 130678 565828 4 u_riscv_top.core2_dmem_wdata\[10\]
+port 1844 nsew
+rlabel metal3 s 130494 565556 130494 565556 4 u_riscv_top.core2_dmem_wdata\[11\]
+port 1845 nsew
+rlabel metal3 s 130540 565284 130540 565284 4 u_riscv_top.core2_dmem_wdata\[12\]
+port 1846 nsew
+rlabel metal3 s 130586 565012 130586 565012 4 u_riscv_top.core2_dmem_wdata\[13\]
+port 1847 nsew
+rlabel metal3 s 130494 564740 130494 564740 4 u_riscv_top.core2_dmem_wdata\[14\]
+port 1848 nsew
+rlabel metal3 s 130632 564468 130632 564468 4 u_riscv_top.core2_dmem_wdata\[15\]
+port 1849 nsew
+rlabel metal3 s 130586 564196 130586 564196 4 u_riscv_top.core2_dmem_wdata\[16\]
+port 1850 nsew
+rlabel metal3 s 130494 563924 130494 563924 4 u_riscv_top.core2_dmem_wdata\[17\]
+port 1851 nsew
+rlabel metal3 s 130540 563652 130540 563652 4 u_riscv_top.core2_dmem_wdata\[18\]
+port 1852 nsew
+rlabel metal3 s 130494 563380 130494 563380 4 u_riscv_top.core2_dmem_wdata\[19\]
+port 1853 nsew
+rlabel metal3 s 130586 568276 130586 568276 4 u_riscv_top.core2_dmem_wdata\[1\]
+port 1854 nsew
+rlabel metal3 s 130632 563108 130632 563108 4 u_riscv_top.core2_dmem_wdata\[20\]
+port 1855 nsew
+rlabel metal3 s 130494 562836 130494 562836 4 u_riscv_top.core2_dmem_wdata\[21\]
+port 1856 nsew
+rlabel metal3 s 130540 562564 130540 562564 4 u_riscv_top.core2_dmem_wdata\[22\]
+port 1857 nsew
+rlabel metal3 s 130586 562292 130586 562292 4 u_riscv_top.core2_dmem_wdata\[23\]
+port 1858 nsew
+rlabel metal3 s 130494 562020 130494 562020 4 u_riscv_top.core2_dmem_wdata\[24\]
+port 1859 nsew
+rlabel metal3 s 130632 561748 130632 561748 4 u_riscv_top.core2_dmem_wdata\[25\]
+port 1860 nsew
+rlabel metal3 s 130586 561476 130586 561476 4 u_riscv_top.core2_dmem_wdata\[26\]
+port 1861 nsew
+rlabel metal3 s 130494 561204 130494 561204 4 u_riscv_top.core2_dmem_wdata\[27\]
+port 1862 nsew
+rlabel metal3 s 130494 560932 130494 560932 4 u_riscv_top.core2_dmem_wdata\[28\]
+port 1863 nsew
+rlabel metal3 s 130632 560660 130632 560660 4 u_riscv_top.core2_dmem_wdata\[29\]
+port 1864 nsew
+rlabel metal3 s 130494 568004 130494 568004 4 u_riscv_top.core2_dmem_wdata\[2\]
+port 1865 nsew
+rlabel metal3 s 130540 560388 130540 560388 4 u_riscv_top.core2_dmem_wdata\[30\]
+port 1866 nsew
+rlabel metal3 s 130494 560116 130494 560116 4 u_riscv_top.core2_dmem_wdata\[31\]
+port 1867 nsew
+rlabel metal3 s 130632 567732 130632 567732 4 u_riscv_top.core2_dmem_wdata\[3\]
+port 1868 nsew
+rlabel metal3 s 130540 567460 130540 567460 4 u_riscv_top.core2_dmem_wdata\[4\]
+port 1869 nsew
+rlabel metal3 s 130678 567188 130678 567188 4 u_riscv_top.core2_dmem_wdata\[5\]
+port 1870 nsew
+rlabel metal3 s 130632 566916 130632 566916 4 u_riscv_top.core2_dmem_wdata\[6\]
+port 1871 nsew
+rlabel metal3 s 130494 566644 130494 566644 4 u_riscv_top.core2_dmem_wdata\[7\]
+port 1872 nsew
+rlabel metal3 s 130586 566372 130586 566372 4 u_riscv_top.core2_dmem_wdata\[8\]
+port 1873 nsew
+rlabel metal3 s 130540 566100 130540 566100 4 u_riscv_top.core2_dmem_wdata\[9\]
+port 1874 nsew
+rlabel metal3 s 130540 551140 130540 551140 4 u_riscv_top.core2_dmem_width\[0\]
+port 1875 nsew
+rlabel metal3 s 130632 550868 130632 550868 4 u_riscv_top.core2_dmem_width\[1\]
+port 1876 nsew
+rlabel metal3 s 130540 530196 130540 530196 4 u_riscv_top.core2_imem_addr\[0\]
+port 1877 nsew
+rlabel metal3 s 130494 527476 130494 527476 4 u_riscv_top.core2_imem_addr\[10\]
+port 1878 nsew
+rlabel metal3 s 130632 527204 130632 527204 4 u_riscv_top.core2_imem_addr\[11\]
+port 1879 nsew
+rlabel metal3 s 130540 526932 130540 526932 4 u_riscv_top.core2_imem_addr\[12\]
+port 1880 nsew
+rlabel metal3 s 130494 526660 130494 526660 4 u_riscv_top.core2_imem_addr\[13\]
+port 1881 nsew
+rlabel metal3 s 130632 526388 130632 526388 4 u_riscv_top.core2_imem_addr\[14\]
+port 1882 nsew
+rlabel metal3 s 130494 526116 130494 526116 4 u_riscv_top.core2_imem_addr\[15\]
+port 1883 nsew
+rlabel metal3 s 130586 525844 130586 525844 4 u_riscv_top.core2_imem_addr\[16\]
+port 1884 nsew
+rlabel metal3 s 130632 525572 130632 525572 4 u_riscv_top.core2_imem_addr\[17\]
+port 1885 nsew
+rlabel metal3 s 130494 525300 130494 525300 4 u_riscv_top.core2_imem_addr\[18\]
+port 1886 nsew
+rlabel metal3 s 130540 525028 130540 525028 4 u_riscv_top.core2_imem_addr\[19\]
+port 1887 nsew
+rlabel metal3 s 130724 529924 130724 529924 4 u_riscv_top.core2_imem_addr\[1\]
+port 1888 nsew
+rlabel metal3 s 130586 524756 130586 524756 4 u_riscv_top.core2_imem_addr\[20\]
+port 1889 nsew
+rlabel metal3 s 130678 524484 130678 524484 4 u_riscv_top.core2_imem_addr\[21\]
+port 1890 nsew
+rlabel metal3 s 130494 524212 130494 524212 4 u_riscv_top.core2_imem_addr\[22\]
+port 1891 nsew
+rlabel metal3 s 130540 523940 130540 523940 4 u_riscv_top.core2_imem_addr\[23\]
+port 1892 nsew
+rlabel metal3 s 130632 523668 130632 523668 4 u_riscv_top.core2_imem_addr\[24\]
+port 1893 nsew
+rlabel metal3 s 130494 523396 130494 523396 4 u_riscv_top.core2_imem_addr\[25\]
+port 1894 nsew
+rlabel metal3 s 130586 523124 130586 523124 4 u_riscv_top.core2_imem_addr\[26\]
+port 1895 nsew
+rlabel metal3 s 130678 522852 130678 522852 4 u_riscv_top.core2_imem_addr\[27\]
+port 1896 nsew
+rlabel metal3 s 130494 522580 130494 522580 4 u_riscv_top.core2_imem_addr\[28\]
+port 1897 nsew
+rlabel metal3 s 130540 522308 130540 522308 4 u_riscv_top.core2_imem_addr\[29\]
+port 1898 nsew
+rlabel metal3 s 130540 529652 130540 529652 4 u_riscv_top.core2_imem_addr\[2\]
+port 1899 nsew
+rlabel metal3 s 130586 522036 130586 522036 4 u_riscv_top.core2_imem_addr\[30\]
+port 1900 nsew
+rlabel metal3 s 130632 521764 130632 521764 4 u_riscv_top.core2_imem_addr\[31\]
+port 1901 nsew
+rlabel metal3 s 130494 529380 130494 529380 4 u_riscv_top.core2_imem_addr\[3\]
+port 1902 nsew
+rlabel metal3 s 130632 529108 130632 529108 4 u_riscv_top.core2_imem_addr\[4\]
+port 1903 nsew
+rlabel metal3 s 130494 528836 130494 528836 4 u_riscv_top.core2_imem_addr\[5\]
+port 1904 nsew
+rlabel metal3 s 130586 528564 130586 528564 4 u_riscv_top.core2_imem_addr\[6\]
+port 1905 nsew
+rlabel metal3 s 130586 528292 130586 528292 4 u_riscv_top.core2_imem_addr\[7\]
+port 1906 nsew
+rlabel metal3 s 130494 528020 130494 528020 4 u_riscv_top.core2_imem_addr\[8\]
+port 1907 nsew
+rlabel metal3 s 130540 527748 130540 527748 4 u_riscv_top.core2_imem_addr\[9\]
+port 1908 nsew
+rlabel metal3 s 130632 531012 130632 531012 4 u_riscv_top.core2_imem_bl\[0\]
+port 1909 nsew
+rlabel metal3 s 130494 530740 130494 530740 4 u_riscv_top.core2_imem_bl\[1\]
+port 1910 nsew
+rlabel metal3 s 130678 530468 130678 530468 4 u_riscv_top.core2_imem_bl\[2\]
+port 1911 nsew
+rlabel metal3 s 130632 521492 130632 521492 4 u_riscv_top.core2_imem_cmd
+port 1912 nsew
+rlabel metal3 s 130586 539716 130586 539716 4 u_riscv_top.core2_imem_rdata\[0\]
+port 1913 nsew
+rlabel metal3 s 130632 536996 130632 536996 4 u_riscv_top.core2_imem_rdata\[10\]
+port 1914 nsew
+rlabel metal3 s 130632 536724 130632 536724 4 u_riscv_top.core2_imem_rdata\[11\]
+port 1915 nsew
+rlabel metal3 s 130494 536452 130494 536452 4 u_riscv_top.core2_imem_rdata\[12\]
+port 1916 nsew
+rlabel metal3 s 130540 536180 130540 536180 4 u_riscv_top.core2_imem_rdata\[13\]
+port 1917 nsew
+rlabel metal3 s 130494 535908 130494 535908 4 u_riscv_top.core2_imem_rdata\[14\]
+port 1918 nsew
+rlabel metal3 s 130586 535636 130586 535636 4 u_riscv_top.core2_imem_rdata\[15\]
+port 1919 nsew
+rlabel metal3 s 130494 535364 130494 535364 4 u_riscv_top.core2_imem_rdata\[16\]
+port 1920 nsew
+rlabel metal3 s 130586 535092 130586 535092 4 u_riscv_top.core2_imem_rdata\[17\]
+port 1921 nsew
+rlabel metal3 s 130494 534820 130494 534820 4 u_riscv_top.core2_imem_rdata\[18\]
+port 1922 nsew
+rlabel metal3 s 130540 534548 130540 534548 4 u_riscv_top.core2_imem_rdata\[19\]
+port 1923 nsew
+rlabel metal3 s 130494 539444 130494 539444 4 u_riscv_top.core2_imem_rdata\[1\]
+port 1924 nsew
+rlabel metal3 s 130632 534276 130632 534276 4 u_riscv_top.core2_imem_rdata\[20\]
+port 1925 nsew
+rlabel metal3 s 130494 534004 130494 534004 4 u_riscv_top.core2_imem_rdata\[21\]
+port 1926 nsew
+rlabel metal3 s 130540 533732 130540 533732 4 u_riscv_top.core2_imem_rdata\[22\]
+port 1927 nsew
+rlabel metal3 s 130494 533460 130494 533460 4 u_riscv_top.core2_imem_rdata\[23\]
+port 1928 nsew
+rlabel metal3 s 130586 533188 130586 533188 4 u_riscv_top.core2_imem_rdata\[24\]
+port 1929 nsew
+rlabel metal3 s 130540 532916 130540 532916 4 u_riscv_top.core2_imem_rdata\[25\]
+port 1930 nsew
+rlabel metal3 s 130494 532644 130494 532644 4 u_riscv_top.core2_imem_rdata\[26\]
+port 1931 nsew
+rlabel metal3 s 130540 532372 130540 532372 4 u_riscv_top.core2_imem_rdata\[27\]
+port 1932 nsew
+rlabel metal3 s 130494 532100 130494 532100 4 u_riscv_top.core2_imem_rdata\[28\]
+port 1933 nsew
+rlabel metal3 s 130494 531828 130494 531828 4 u_riscv_top.core2_imem_rdata\[29\]
+port 1934 nsew
+rlabel metal3 s 130586 539172 130586 539172 4 u_riscv_top.core2_imem_rdata\[2\]
+port 1935 nsew
+rlabel metal3 s 130540 531556 130540 531556 4 u_riscv_top.core2_imem_rdata\[30\]
+port 1936 nsew
+rlabel metal3 s 130586 531284 130586 531284 4 u_riscv_top.core2_imem_rdata\[31\]
+port 1937 nsew
+rlabel metal3 s 130540 538900 130540 538900 4 u_riscv_top.core2_imem_rdata\[3\]
+port 1938 nsew
+rlabel metal3 s 130494 538628 130494 538628 4 u_riscv_top.core2_imem_rdata\[4\]
+port 1939 nsew
+rlabel metal3 s 130632 538356 130632 538356 4 u_riscv_top.core2_imem_rdata\[5\]
+port 1940 nsew
+rlabel metal3 s 130586 538084 130586 538084 4 u_riscv_top.core2_imem_rdata\[6\]
+port 1941 nsew
+rlabel metal3 s 130678 537812 130678 537812 4 u_riscv_top.core2_imem_rdata\[7\]
+port 1942 nsew
+rlabel metal3 s 130494 537540 130494 537540 4 u_riscv_top.core2_imem_rdata\[8\]
+port 1943 nsew
+rlabel metal3 s 130540 537268 130540 537268 4 u_riscv_top.core2_imem_rdata\[9\]
+port 1944 nsew
+rlabel metal3 s 130494 521220 130494 521220 4 u_riscv_top.core2_imem_req
+port 1945 nsew
+rlabel metal3 s 130586 520948 130586 520948 4 u_riscv_top.core2_imem_req_ack
+port 1946 nsew
+rlabel metal3 s 130540 540260 130540 540260 4 u_riscv_top.core2_imem_resp\[0\]
+port 1947 nsew
+rlabel metal3 s 130494 539988 130494 539988 4 u_riscv_top.core2_imem_resp\[1\]
+port 1948 nsew
+rlabel metal3 s 130586 626212 130586 626212 4 u_riscv_top.core2_irq_lines\[0\]
+port 1949 nsew
+rlabel metal3 s 130540 623492 130540 623492 4 u_riscv_top.core2_irq_lines\[10\]
+port 1950 nsew
+rlabel metal3 s 130494 623220 130494 623220 4 u_riscv_top.core2_irq_lines\[11\]
+port 1951 nsew
+rlabel metal3 s 130540 622948 130540 622948 4 u_riscv_top.core2_irq_lines\[12\]
+port 1952 nsew
+rlabel metal3 s 130494 622676 130494 622676 4 u_riscv_top.core2_irq_lines\[13\]
+port 1953 nsew
+rlabel metal3 s 130586 622404 130586 622404 4 u_riscv_top.core2_irq_lines\[14\]
+port 1954 nsew
+rlabel metal3 s 130586 622132 130586 622132 4 u_riscv_top.core2_irq_lines\[15\]
+port 1955 nsew
+rlabel metal3 s 130494 621860 130494 621860 4 u_riscv_top.core2_irq_lines\[16\]
+port 1956 nsew
+rlabel metal3 s 130632 621588 130632 621588 4 u_riscv_top.core2_irq_lines\[17\]
+port 1957 nsew
+rlabel metal3 s 130540 621316 130540 621316 4 u_riscv_top.core2_irq_lines\[18\]
+port 1958 nsew
+rlabel metal3 s 130678 621044 130678 621044 4 u_riscv_top.core2_irq_lines\[19\]
+port 1959 nsew
+rlabel metal3 s 130494 625940 130494 625940 4 u_riscv_top.core2_irq_lines\[1\]
+port 1960 nsew
+rlabel metal3 s 130586 620772 130586 620772 4 u_riscv_top.core2_irq_lines\[20\]
+port 1961 nsew
+rlabel metal3 s 130494 620500 130494 620500 4 u_riscv_top.core2_irq_lines\[21\]
+port 1962 nsew
+rlabel metal3 s 130494 620228 130494 620228 4 u_riscv_top.core2_irq_lines\[22\]
+port 1963 nsew
+rlabel metal3 s 130540 619956 130540 619956 4 u_riscv_top.core2_irq_lines\[23\]
+port 1964 nsew
+rlabel metal3 s 130632 619684 130632 619684 4 u_riscv_top.core2_irq_lines\[24\]
+port 1965 nsew
+rlabel metal3 s 130586 619412 130586 619412 4 u_riscv_top.core2_irq_lines\[25\]
+port 1966 nsew
+rlabel metal3 s 130540 619140 130540 619140 4 u_riscv_top.core2_irq_lines\[26\]
+port 1967 nsew
+rlabel metal3 s 130632 618868 130632 618868 4 u_riscv_top.core2_irq_lines\[27\]
+port 1968 nsew
+rlabel metal3 s 130494 618596 130494 618596 4 u_riscv_top.core2_irq_lines\[28\]
+port 1969 nsew
+rlabel metal3 s 130678 618324 130678 618324 4 u_riscv_top.core2_irq_lines\[29\]
+port 1970 nsew
+rlabel metal3 s 130540 625668 130540 625668 4 u_riscv_top.core2_irq_lines\[2\]
+port 1971 nsew
+rlabel metal3 s 130540 618052 130540 618052 4 u_riscv_top.core2_irq_lines\[30\]
+port 1972 nsew
+rlabel metal3 s 130494 617780 130494 617780 4 u_riscv_top.core2_irq_lines\[31\]
+port 1973 nsew
+rlabel metal3 s 130632 625396 130632 625396 4 u_riscv_top.core2_irq_lines\[3\]
+port 1974 nsew
+rlabel metal3 s 130494 625124 130494 625124 4 u_riscv_top.core2_irq_lines\[4\]
+port 1975 nsew
+rlabel metal3 s 130540 624852 130540 624852 4 u_riscv_top.core2_irq_lines\[5\]
+port 1976 nsew
+rlabel metal3 s 130494 624580 130494 624580 4 u_riscv_top.core2_irq_lines\[6\]
+port 1977 nsew
+rlabel metal3 s 130540 624308 130540 624308 4 u_riscv_top.core2_irq_lines\[7\]
+port 1978 nsew
+rlabel metal3 s 130586 624036 130586 624036 4 u_riscv_top.core2_irq_lines\[8\]
+port 1979 nsew
+rlabel metal3 s 130494 623764 130494 623764 4 u_riscv_top.core2_irq_lines\[9\]
+port 1980 nsew
+rlabel metal3 s 130494 626484 130494 626484 4 u_riscv_top.core2_soft_irq
+port 1981 nsew
+rlabel metal3 s 130011 600168 130011 600168 4 u_riscv_top.core2_timer_irq
+port 1982 nsew
+rlabel metal3 s 130632 617508 130632 617508 4 u_riscv_top.core2_timer_val\[0\]
+port 1983 nsew
+rlabel metal3 s 130540 614788 130540 614788 4 u_riscv_top.core2_timer_val\[10\]
+port 1984 nsew
+rlabel metal3 s 130494 614516 130494 614516 4 u_riscv_top.core2_timer_val\[11\]
+port 1985 nsew
+rlabel metal3 s 130586 614244 130586 614244 4 u_riscv_top.core2_timer_val\[12\]
+port 1986 nsew
+rlabel metal3 s 130678 613972 130678 613972 4 u_riscv_top.core2_timer_val\[13\]
+port 1987 nsew
+rlabel metal3 s 130494 613700 130494 613700 4 u_riscv_top.core2_timer_val\[14\]
+port 1988 nsew
+rlabel metal3 s 130540 613428 130540 613428 4 u_riscv_top.core2_timer_val\[15\]
+port 1989 nsew
+rlabel metal3 s 130586 613156 130586 613156 4 u_riscv_top.core2_timer_val\[16\]
+port 1990 nsew
+rlabel metal3 s 130632 612884 130632 612884 4 u_riscv_top.core2_timer_val\[17\]
+port 1991 nsew
+rlabel metal3 s 130586 612612 130586 612612 4 u_riscv_top.core2_timer_val\[18\]
+port 1992 nsew
+rlabel metal3 s 130494 612340 130494 612340 4 u_riscv_top.core2_timer_val\[19\]
+port 1993 nsew
+rlabel metal3 s 130494 617236 130494 617236 4 u_riscv_top.core2_timer_val\[1\]
+port 1994 nsew
+rlabel metal3 s 130494 612068 130494 612068 4 u_riscv_top.core2_timer_val\[20\]
+port 1995 nsew
+rlabel metal3 s 130540 611796 130540 611796 4 u_riscv_top.core2_timer_val\[21\]
+port 1996 nsew
+rlabel metal3 s 130632 611524 130632 611524 4 u_riscv_top.core2_timer_val\[22\]
+port 1997 nsew
+rlabel metal3 s 130632 611252 130632 611252 4 u_riscv_top.core2_timer_val\[23\]
+port 1998 nsew
+rlabel metal3 s 130540 610980 130540 610980 4 u_riscv_top.core2_timer_val\[24\]
+port 1999 nsew
+rlabel metal3 s 130494 610708 130494 610708 4 u_riscv_top.core2_timer_val\[25\]
+port 2000 nsew
+rlabel metal3 s 130586 610436 130586 610436 4 u_riscv_top.core2_timer_val\[26\]
+port 2001 nsew
+rlabel metal3 s 130678 610164 130678 610164 4 u_riscv_top.core2_timer_val\[27\]
+port 2002 nsew
+rlabel metal3 s 130678 609892 130678 609892 4 u_riscv_top.core2_timer_val\[28\]
+port 2003 nsew
+rlabel metal3 s 130586 609620 130586 609620 4 u_riscv_top.core2_timer_val\[29\]
+port 2004 nsew
+rlabel metal3 s 130586 616964 130586 616964 4 u_riscv_top.core2_timer_val\[2\]
+port 2005 nsew
+rlabel metal3 s 130540 609348 130540 609348 4 u_riscv_top.core2_timer_val\[30\]
+port 2006 nsew
+rlabel metal3 s 130494 609076 130494 609076 4 u_riscv_top.core2_timer_val\[31\]
+port 2007 nsew
+rlabel metal3 s 130632 608804 130632 608804 4 u_riscv_top.core2_timer_val\[32\]
+port 2008 nsew
+rlabel metal3 s 130540 608532 130540 608532 4 u_riscv_top.core2_timer_val\[33\]
+port 2009 nsew
+rlabel metal3 s 130494 608260 130494 608260 4 u_riscv_top.core2_timer_val\[34\]
+port 2010 nsew
+rlabel metal3 s 130494 607988 130494 607988 4 u_riscv_top.core2_timer_val\[35\]
+port 2011 nsew
+rlabel metal3 s 130586 607716 130586 607716 4 u_riscv_top.core2_timer_val\[36\]
+port 2012 nsew
+rlabel metal3 s 130540 607444 130540 607444 4 u_riscv_top.core2_timer_val\[37\]
+port 2013 nsew
+rlabel metal3 s 130540 607172 130540 607172 4 u_riscv_top.core2_timer_val\[38\]
+port 2014 nsew
+rlabel metal3 s 130632 606900 130632 606900 4 u_riscv_top.core2_timer_val\[39\]
+port 2015 nsew
+rlabel metal3 s 130632 616692 130632 616692 4 u_riscv_top.core2_timer_val\[3\]
+port 2016 nsew
+rlabel metal3 s 130494 606628 130494 606628 4 u_riscv_top.core2_timer_val\[40\]
+port 2017 nsew
+rlabel metal3 s 130586 606356 130586 606356 4 u_riscv_top.core2_timer_val\[41\]
+port 2018 nsew
+rlabel metal3 s 130540 606084 130540 606084 4 u_riscv_top.core2_timer_val\[42\]
+port 2019 nsew
+rlabel metal3 s 130494 605812 130494 605812 4 u_riscv_top.core2_timer_val\[43\]
+port 2020 nsew
+rlabel metal3 s 130540 605540 130540 605540 4 u_riscv_top.core2_timer_val\[44\]
+port 2021 nsew
+rlabel metal3 s 130494 605268 130494 605268 4 u_riscv_top.core2_timer_val\[45\]
+port 2022 nsew
+rlabel metal3 s 130540 604996 130540 604996 4 u_riscv_top.core2_timer_val\[46\]
+port 2023 nsew
+rlabel metal3 s 130494 604724 130494 604724 4 u_riscv_top.core2_timer_val\[47\]
+port 2024 nsew
+rlabel metal3 s 130586 604452 130586 604452 4 u_riscv_top.core2_timer_val\[48\]
+port 2025 nsew
+rlabel metal3 s 130540 604180 130540 604180 4 u_riscv_top.core2_timer_val\[49\]
+port 2026 nsew
+rlabel metal3 s 130494 616420 130494 616420 4 u_riscv_top.core2_timer_val\[4\]
+port 2027 nsew
+rlabel metal3 s 130494 603908 130494 603908 4 u_riscv_top.core2_timer_val\[50\]
+port 2028 nsew
+rlabel metal3 s 130586 603636 130586 603636 4 u_riscv_top.core2_timer_val\[51\]
+port 2029 nsew
+rlabel metal3 s 130494 603364 130494 603364 4 u_riscv_top.core2_timer_val\[52\]
+port 2030 nsew
+rlabel metal3 s 130540 603092 130540 603092 4 u_riscv_top.core2_timer_val\[53\]
+port 2031 nsew
+rlabel metal3 s 130632 602820 130632 602820 4 u_riscv_top.core2_timer_val\[54\]
+port 2032 nsew
+rlabel metal3 s 130494 602548 130494 602548 4 u_riscv_top.core2_timer_val\[55\]
+port 2033 nsew
+rlabel metal3 s 130586 602276 130586 602276 4 u_riscv_top.core2_timer_val\[56\]
+port 2034 nsew
+rlabel metal3 s 130540 602004 130540 602004 4 u_riscv_top.core2_timer_val\[57\]
+port 2035 nsew
+rlabel metal3 s 130494 601732 130494 601732 4 u_riscv_top.core2_timer_val\[58\]
+port 2036 nsew
+rlabel metal3 s 130586 601460 130586 601460 4 u_riscv_top.core2_timer_val\[59\]
+port 2037 nsew
+rlabel metal3 s 130494 616148 130494 616148 4 u_riscv_top.core2_timer_val\[5\]
+port 2038 nsew
+rlabel metal3 s 130494 601188 130494 601188 4 u_riscv_top.core2_timer_val\[60\]
+port 2039 nsew
+rlabel metal3 s 130494 600916 130494 600916 4 u_riscv_top.core2_timer_val\[61\]
+port 2040 nsew
+rlabel metal3 s 130540 600644 130540 600644 4 u_riscv_top.core2_timer_val\[62\]
+port 2041 nsew
+rlabel metal3 s 130632 600372 130632 600372 4 u_riscv_top.core2_timer_val\[63\]
+port 2042 nsew
+rlabel metal3 s 130586 615876 130586 615876 4 u_riscv_top.core2_timer_val\[6\]
+port 2043 nsew
+rlabel metal3 s 130540 615604 130540 615604 4 u_riscv_top.core2_timer_val\[7\]
+port 2044 nsew
+rlabel metal3 s 130632 615332 130632 615332 4 u_riscv_top.core2_timer_val\[8\]
+port 2045 nsew
+rlabel metal3 s 130494 615060 130494 615060 4 u_riscv_top.core2_timer_val\[9\]
+port 2046 nsew
+rlabel metal3 s 130540 520676 130540 520676 4 u_riscv_top.core2_uid\[0\]
+port 2047 nsew
+rlabel metal3 s 130494 520404 130494 520404 4 u_riscv_top.core2_uid\[1\]
+port 2048 nsew
+rlabel metal3 s 230414 520149 230414 520149 4 u_riscv_top.core3_clk
+port 2049 nsew
+rlabel metal3 s 230414 593181 230414 593181 4 u_riscv_top.core3_debug\[0\]
+port 2050 nsew
+rlabel metal3 s 230414 590461 230414 590461 4 u_riscv_top.core3_debug\[10\]
+port 2051 nsew
+rlabel metal3 s 230414 590155 230414 590155 4 u_riscv_top.core3_debug\[11\]
+port 2052 nsew
+rlabel metal3 s 230414 589883 230414 589883 4 u_riscv_top.core3_debug\[12\]
+port 2053 nsew
+rlabel metal3 s 230414 589645 230414 589645 4 u_riscv_top.core3_debug\[13\]
+port 2054 nsew
+rlabel metal3 s 230414 589339 230414 589339 4 u_riscv_top.core3_debug\[14\]
+port 2055 nsew
+rlabel metal3 s 230414 589067 230414 589067 4 u_riscv_top.core3_debug\[15\]
+port 2056 nsew
+rlabel metal3 s 230414 588795 230414 588795 4 u_riscv_top.core3_debug\[16\]
+port 2057 nsew
+rlabel metal3 s 230414 588523 230414 588523 4 u_riscv_top.core3_debug\[17\]
+port 2058 nsew
+rlabel metal3 s 230414 588285 230414 588285 4 u_riscv_top.core3_debug\[18\]
+port 2059 nsew
+rlabel metal3 s 230414 588013 230414 588013 4 u_riscv_top.core3_debug\[19\]
+port 2060 nsew
+rlabel metal3 s 230414 592875 230414 592875 4 u_riscv_top.core3_debug\[1\]
+port 2061 nsew
+rlabel metal3 s 230414 587741 230414 587741 4 u_riscv_top.core3_debug\[20\]
+port 2062 nsew
+rlabel metal3 s 230414 587435 230414 587435 4 u_riscv_top.core3_debug\[21\]
+port 2063 nsew
+rlabel metal3 s 230414 587163 230414 587163 4 u_riscv_top.core3_debug\[22\]
+port 2064 nsew
+rlabel metal3 s 230414 586891 230414 586891 4 u_riscv_top.core3_debug\[23\]
+port 2065 nsew
+rlabel metal3 s 230414 586653 230414 586653 4 u_riscv_top.core3_debug\[24\]
+port 2066 nsew
+rlabel metal3 s 230414 586381 230414 586381 4 u_riscv_top.core3_debug\[25\]
+port 2067 nsew
+rlabel metal3 s 230414 586075 230414 586075 4 u_riscv_top.core3_debug\[26\]
+port 2068 nsew
+rlabel metal3 s 230414 585837 230414 585837 4 u_riscv_top.core3_debug\[27\]
+port 2069 nsew
+rlabel metal3 s 230414 585565 230414 585565 4 u_riscv_top.core3_debug\[28\]
+port 2070 nsew
+rlabel metal3 s 230414 585293 230414 585293 4 u_riscv_top.core3_debug\[29\]
+port 2071 nsew
+rlabel metal3 s 230414 592603 230414 592603 4 u_riscv_top.core3_debug\[2\]
+port 2072 nsew
+rlabel metal3 s 230414 585021 230414 585021 4 u_riscv_top.core3_debug\[30\]
+port 2073 nsew
+rlabel metal3 s 230414 584749 230414 584749 4 u_riscv_top.core3_debug\[31\]
+port 2074 nsew
+rlabel metal3 s 230414 584477 230414 584477 4 u_riscv_top.core3_debug\[32\]
+port 2075 nsew
+rlabel metal3 s 230414 584205 230414 584205 4 u_riscv_top.core3_debug\[33\]
+port 2076 nsew
+rlabel metal3 s 230414 583933 230414 583933 4 u_riscv_top.core3_debug\[34\]
+port 2077 nsew
+rlabel metal3 s 230414 583627 230414 583627 4 u_riscv_top.core3_debug\[35\]
+port 2078 nsew
+rlabel metal3 s 230414 583355 230414 583355 4 u_riscv_top.core3_debug\[36\]
+port 2079 nsew
+rlabel metal3 s 230414 583117 230414 583117 4 u_riscv_top.core3_debug\[37\]
+port 2080 nsew
+rlabel metal3 s 230414 582845 230414 582845 4 u_riscv_top.core3_debug\[38\]
+port 2081 nsew
+rlabel metal3 s 230414 582573 230414 582573 4 u_riscv_top.core3_debug\[39\]
+port 2082 nsew
+rlabel metal3 s 230414 592365 230414 592365 4 u_riscv_top.core3_debug\[3\]
+port 2083 nsew
+rlabel metal3 s 230414 582267 230414 582267 4 u_riscv_top.core3_debug\[40\]
+port 2084 nsew
+rlabel metal3 s 230414 581995 230414 581995 4 u_riscv_top.core3_debug\[41\]
+port 2085 nsew
+rlabel metal3 s 230414 581757 230414 581757 4 u_riscv_top.core3_debug\[42\]
+port 2086 nsew
+rlabel metal3 s 230414 581485 230414 581485 4 u_riscv_top.core3_debug\[43\]
+port 2087 nsew
+rlabel metal3 s 230414 581213 230414 581213 4 u_riscv_top.core3_debug\[44\]
+port 2088 nsew
+rlabel metal3 s 230414 580907 230414 580907 4 u_riscv_top.core3_debug\[45\]
+port 2089 nsew
+rlabel metal3 s 230414 580635 230414 580635 4 u_riscv_top.core3_debug\[46\]
+port 2090 nsew
+rlabel metal3 s 230414 580397 230414 580397 4 u_riscv_top.core3_debug\[47\]
+port 2091 nsew
+rlabel metal3 s 230414 580125 230414 580125 4 u_riscv_top.core3_debug\[48\]
+port 2092 nsew
+rlabel metal3 s 230414 592059 230414 592059 4 u_riscv_top.core3_debug\[4\]
+port 2093 nsew
+rlabel metal3 s 230414 591787 230414 591787 4 u_riscv_top.core3_debug\[5\]
+port 2094 nsew
+rlabel metal3 s 230414 591515 230414 591515 4 u_riscv_top.core3_debug\[6\]
+port 2095 nsew
+rlabel metal3 s 230414 591243 230414 591243 4 u_riscv_top.core3_debug\[7\]
+port 2096 nsew
+rlabel metal3 s 230414 591005 230414 591005 4 u_riscv_top.core3_debug\[8\]
+port 2097 nsew
+rlabel metal3 s 230414 590699 230414 590699 4 u_riscv_top.core3_debug\[9\]
+port 2098 nsew
+rlabel metal3 s 230414 559963 230414 559963 4 u_riscv_top.core3_dmem_addr\[0\]
+port 2099 nsew
+rlabel metal3 s 230414 557243 230414 557243 4 u_riscv_top.core3_dmem_addr\[10\]
+port 2100 nsew
+rlabel metal3 s 230414 556971 230414 556971 4 u_riscv_top.core3_dmem_addr\[11\]
+port 2101 nsew
+rlabel metal3 s 230414 556699 230414 556699 4 u_riscv_top.core3_dmem_addr\[12\]
+port 2102 nsew
+rlabel metal3 s 230414 556427 230414 556427 4 u_riscv_top.core3_dmem_addr\[13\]
+port 2103 nsew
+rlabel metal3 s 230414 556189 230414 556189 4 u_riscv_top.core3_dmem_addr\[14\]
+port 2104 nsew
+rlabel metal3 s 230414 555883 230414 555883 4 u_riscv_top.core3_dmem_addr\[15\]
+port 2105 nsew
+rlabel metal3 s 230414 555611 230414 555611 4 u_riscv_top.core3_dmem_addr\[16\]
+port 2106 nsew
+rlabel metal3 s 230414 555339 230414 555339 4 u_riscv_top.core3_dmem_addr\[17\]
+port 2107 nsew
+rlabel metal3 s 230414 555067 230414 555067 4 u_riscv_top.core3_dmem_addr\[18\]
+port 2108 nsew
+rlabel metal3 s 230414 554795 230414 554795 4 u_riscv_top.core3_dmem_addr\[19\]
+port 2109 nsew
+rlabel metal3 s 230414 559691 230414 559691 4 u_riscv_top.core3_dmem_addr\[1\]
+port 2110 nsew
+rlabel metal3 s 230414 554523 230414 554523 4 u_riscv_top.core3_dmem_addr\[20\]
+port 2111 nsew
+rlabel metal3 s 230414 554251 230414 554251 4 u_riscv_top.core3_dmem_addr\[21\]
+port 2112 nsew
+rlabel metal3 s 230414 553979 230414 553979 4 u_riscv_top.core3_dmem_addr\[22\]
+port 2113 nsew
+rlabel metal3 s 230414 553707 230414 553707 4 u_riscv_top.core3_dmem_addr\[23\]
+port 2114 nsew
+rlabel metal3 s 230414 553435 230414 553435 4 u_riscv_top.core3_dmem_addr\[24\]
+port 2115 nsew
+rlabel metal3 s 230414 553163 230414 553163 4 u_riscv_top.core3_dmem_addr\[25\]
+port 2116 nsew
+rlabel metal3 s 230414 552891 230414 552891 4 u_riscv_top.core3_dmem_addr\[26\]
+port 2117 nsew
+rlabel metal3 s 230414 552619 230414 552619 4 u_riscv_top.core3_dmem_addr\[27\]
+port 2118 nsew
+rlabel metal3 s 230414 552347 230414 552347 4 u_riscv_top.core3_dmem_addr\[28\]
+port 2119 nsew
+rlabel metal3 s 230414 552075 230414 552075 4 u_riscv_top.core3_dmem_addr\[29\]
+port 2120 nsew
+rlabel metal3 s 230414 559419 230414 559419 4 u_riscv_top.core3_dmem_addr\[2\]
+port 2121 nsew
+rlabel metal3 s 230414 551803 230414 551803 4 u_riscv_top.core3_dmem_addr\[30\]
+port 2122 nsew
+rlabel metal3 s 230414 551531 230414 551531 4 u_riscv_top.core3_dmem_addr\[31\]
+port 2123 nsew
+rlabel metal3 s 230414 559147 230414 559147 4 u_riscv_top.core3_dmem_addr\[3\]
+port 2124 nsew
+rlabel metal3 s 230414 558875 230414 558875 4 u_riscv_top.core3_dmem_addr\[4\]
+port 2125 nsew
+rlabel metal3 s 230414 558603 230414 558603 4 u_riscv_top.core3_dmem_addr\[5\]
+port 2126 nsew
+rlabel metal3 s 230414 558331 230414 558331 4 u_riscv_top.core3_dmem_addr\[6\]
+port 2127 nsew
+rlabel metal3 s 230414 558059 230414 558059 4 u_riscv_top.core3_dmem_addr\[7\]
+port 2128 nsew
+rlabel metal3 s 230414 557787 230414 557787 4 u_riscv_top.core3_dmem_addr\[8\]
+port 2129 nsew
+rlabel metal3 s 229862 557549 229862 557549 4 u_riscv_top.core3_dmem_addr\[9\]
+port 2130 nsew
+rlabel metal2 s 230414 550681 230414 550681 4 u_riscv_top.core3_dmem_cmd
+port 2131 nsew
+rlabel metal3 s 230414 577371 230414 577371 4 u_riscv_top.core3_dmem_rdata\[0\]
+port 2132 nsew
+rlabel metal3 s 230414 574651 230414 574651 4 u_riscv_top.core3_dmem_rdata\[10\]
+port 2133 nsew
+rlabel metal3 s 230414 574379 230414 574379 4 u_riscv_top.core3_dmem_rdata\[11\]
+port 2134 nsew
+rlabel metal3 s 230414 574107 230414 574107 4 u_riscv_top.core3_dmem_rdata\[12\]
+port 2135 nsew
+rlabel metal3 s 230414 573835 230414 573835 4 u_riscv_top.core3_dmem_rdata\[13\]
+port 2136 nsew
+rlabel metal3 s 230414 573563 230414 573563 4 u_riscv_top.core3_dmem_rdata\[14\]
+port 2137 nsew
+rlabel metal3 s 230414 573291 230414 573291 4 u_riscv_top.core3_dmem_rdata\[15\]
+port 2138 nsew
+rlabel metal3 s 230414 573019 230414 573019 4 u_riscv_top.core3_dmem_rdata\[16\]
+port 2139 nsew
+rlabel metal3 s 230414 572747 230414 572747 4 u_riscv_top.core3_dmem_rdata\[17\]
+port 2140 nsew
+rlabel metal3 s 230414 572475 230414 572475 4 u_riscv_top.core3_dmem_rdata\[18\]
+port 2141 nsew
+rlabel metal3 s 230414 572203 230414 572203 4 u_riscv_top.core3_dmem_rdata\[19\]
+port 2142 nsew
+rlabel metal3 s 230414 577099 230414 577099 4 u_riscv_top.core3_dmem_rdata\[1\]
+port 2143 nsew
+rlabel metal3 s 230414 571931 230414 571931 4 u_riscv_top.core3_dmem_rdata\[20\]
+port 2144 nsew
+rlabel metal3 s 230414 571659 230414 571659 4 u_riscv_top.core3_dmem_rdata\[21\]
+port 2145 nsew
+rlabel metal3 s 230414 571387 230414 571387 4 u_riscv_top.core3_dmem_rdata\[22\]
+port 2146 nsew
+rlabel metal3 s 230414 571115 230414 571115 4 u_riscv_top.core3_dmem_rdata\[23\]
+port 2147 nsew
+rlabel metal3 s 230414 570843 230414 570843 4 u_riscv_top.core3_dmem_rdata\[24\]
+port 2148 nsew
+rlabel metal3 s 230414 570571 230414 570571 4 u_riscv_top.core3_dmem_rdata\[25\]
+port 2149 nsew
+rlabel metal3 s 230414 570299 230414 570299 4 u_riscv_top.core3_dmem_rdata\[26\]
+port 2150 nsew
+rlabel metal2 s 230414 569993 230414 569993 4 u_riscv_top.core3_dmem_rdata\[27\]
+port 2151 nsew
+rlabel metal3 s 230414 569755 230414 569755 4 u_riscv_top.core3_dmem_rdata\[28\]
+port 2152 nsew
+rlabel metal3 s 230414 569483 230414 569483 4 u_riscv_top.core3_dmem_rdata\[29\]
+port 2153 nsew
+rlabel metal3 s 229862 576861 229862 576861 4 u_riscv_top.core3_dmem_rdata\[2\]
+port 2154 nsew
+rlabel metal3 s 230414 569211 230414 569211 4 u_riscv_top.core3_dmem_rdata\[30\]
+port 2155 nsew
+rlabel metal3 s 230414 568939 230414 568939 4 u_riscv_top.core3_dmem_rdata\[31\]
+port 2156 nsew
+rlabel metal3 s 230414 576555 230414 576555 4 u_riscv_top.core3_dmem_rdata\[3\]
+port 2157 nsew
+rlabel metal3 s 230414 576283 230414 576283 4 u_riscv_top.core3_dmem_rdata\[4\]
+port 2158 nsew
+rlabel metal3 s 230414 576011 230414 576011 4 u_riscv_top.core3_dmem_rdata\[5\]
+port 2159 nsew
+rlabel metal3 s 230414 575739 230414 575739 4 u_riscv_top.core3_dmem_rdata\[6\]
+port 2160 nsew
+rlabel metal3 s 230414 575501 230414 575501 4 u_riscv_top.core3_dmem_rdata\[7\]
+port 2161 nsew
+rlabel metal3 s 230414 575195 230414 575195 4 u_riscv_top.core3_dmem_rdata\[8\]
+port 2162 nsew
+rlabel metal3 s 230414 574923 230414 574923 4 u_riscv_top.core3_dmem_rdata\[9\]
+port 2163 nsew
+rlabel metal3 s 230414 550443 230414 550443 4 u_riscv_top.core3_dmem_req
+port 2164 nsew
+rlabel metal3 s 230414 550171 230414 550171 4 u_riscv_top.core3_dmem_req_ack
+port 2165 nsew
+rlabel metal3 s 230414 577915 230414 577915 4 u_riscv_top.core3_dmem_resp\[0\]
+port 2166 nsew
+rlabel metal3 s 230414 577643 230414 577643 4 u_riscv_top.core3_dmem_resp\[1\]
+port 2167 nsew
+rlabel metal2 s 230414 568633 230414 568633 4 u_riscv_top.core3_dmem_wdata\[0\]
+port 2168 nsew
+rlabel metal3 s 230414 565947 230414 565947 4 u_riscv_top.core3_dmem_wdata\[10\]
+port 2169 nsew
+rlabel metal3 s 230414 565675 230414 565675 4 u_riscv_top.core3_dmem_wdata\[11\]
+port 2170 nsew
+rlabel metal3 s 230414 565403 230414 565403 4 u_riscv_top.core3_dmem_wdata\[12\]
+port 2171 nsew
+rlabel metal3 s 230414 565131 230414 565131 4 u_riscv_top.core3_dmem_wdata\[13\]
+port 2172 nsew
+rlabel metal3 s 230414 564859 230414 564859 4 u_riscv_top.core3_dmem_wdata\[14\]
+port 2173 nsew
+rlabel metal3 s 230414 564587 230414 564587 4 u_riscv_top.core3_dmem_wdata\[15\]
+port 2174 nsew
+rlabel metal3 s 230414 564315 230414 564315 4 u_riscv_top.core3_dmem_wdata\[16\]
+port 2175 nsew
+rlabel metal3 s 230414 564043 230414 564043 4 u_riscv_top.core3_dmem_wdata\[17\]
+port 2176 nsew
+rlabel metal3 s 230414 563771 230414 563771 4 u_riscv_top.core3_dmem_wdata\[18\]
+port 2177 nsew
+rlabel metal3 s 230414 563499 230414 563499 4 u_riscv_top.core3_dmem_wdata\[19\]
+port 2178 nsew
+rlabel metal3 s 230414 568395 230414 568395 4 u_riscv_top.core3_dmem_wdata\[1\]
+port 2179 nsew
+rlabel metal3 s 230414 563227 230414 563227 4 u_riscv_top.core3_dmem_wdata\[20\]
+port 2180 nsew
+rlabel metal3 s 230414 562955 230414 562955 4 u_riscv_top.core3_dmem_wdata\[21\]
+port 2181 nsew
+rlabel metal3 s 230414 562683 230414 562683 4 u_riscv_top.core3_dmem_wdata\[22\]
+port 2182 nsew
+rlabel metal3 s 230414 562411 230414 562411 4 u_riscv_top.core3_dmem_wdata\[23\]
+port 2183 nsew
+rlabel metal3 s 230414 562139 230414 562139 4 u_riscv_top.core3_dmem_wdata\[24\]
+port 2184 nsew
+rlabel metal3 s 230414 561867 230414 561867 4 u_riscv_top.core3_dmem_wdata\[25\]
+port 2185 nsew
+rlabel metal3 s 230414 561595 230414 561595 4 u_riscv_top.core3_dmem_wdata\[26\]
+port 2186 nsew
+rlabel metal3 s 230414 561323 230414 561323 4 u_riscv_top.core3_dmem_wdata\[27\]
+port 2187 nsew
+rlabel metal3 s 230414 561051 230414 561051 4 u_riscv_top.core3_dmem_wdata\[28\]
+port 2188 nsew
+rlabel metal3 s 230414 560779 230414 560779 4 u_riscv_top.core3_dmem_wdata\[29\]
+port 2189 nsew
+rlabel metal3 s 230414 568123 230414 568123 4 u_riscv_top.core3_dmem_wdata\[2\]
+port 2190 nsew
+rlabel metal3 s 230414 560507 230414 560507 4 u_riscv_top.core3_dmem_wdata\[30\]
+port 2191 nsew
+rlabel metal3 s 229494 560235 229494 560235 4 u_riscv_top.core3_dmem_wdata\[31\]
+port 2192 nsew
+rlabel metal3 s 230414 567851 230414 567851 4 u_riscv_top.core3_dmem_wdata\[3\]
+port 2193 nsew
+rlabel metal3 s 230414 567579 230414 567579 4 u_riscv_top.core3_dmem_wdata\[4\]
+port 2194 nsew
+rlabel metal3 s 230414 567307 230414 567307 4 u_riscv_top.core3_dmem_wdata\[5\]
+port 2195 nsew
+rlabel metal3 s 230414 567035 230414 567035 4 u_riscv_top.core3_dmem_wdata\[6\]
+port 2196 nsew
+rlabel metal3 s 230414 566763 230414 566763 4 u_riscv_top.core3_dmem_wdata\[7\]
+port 2197 nsew
+rlabel metal3 s 230414 566491 230414 566491 4 u_riscv_top.core3_dmem_wdata\[8\]
+port 2198 nsew
+rlabel metal3 s 230414 566219 230414 566219 4 u_riscv_top.core3_dmem_wdata\[9\]
+port 2199 nsew
+rlabel metal3 s 230414 551259 230414 551259 4 u_riscv_top.core3_dmem_width\[0\]
+port 2200 nsew
+rlabel metal3 s 230414 550987 230414 550987 4 u_riscv_top.core3_dmem_width\[1\]
+port 2201 nsew
+rlabel metal3 s 230414 530213 230414 530213 4 u_riscv_top.core3_imem_addr\[0\]
+port 2202 nsew
+rlabel metal3 s 230414 527493 230414 527493 4 u_riscv_top.core3_imem_addr\[10\]
+port 2203 nsew
+rlabel metal3 s 230414 527221 230414 527221 4 u_riscv_top.core3_imem_addr\[11\]
+port 2204 nsew
+rlabel metal3 s 230414 526949 230414 526949 4 u_riscv_top.core3_imem_addr\[12\]
+port 2205 nsew
+rlabel metal3 s 230414 526677 230414 526677 4 u_riscv_top.core3_imem_addr\[13\]
+port 2206 nsew
+rlabel metal3 s 230414 526405 230414 526405 4 u_riscv_top.core3_imem_addr\[14\]
+port 2207 nsew
+rlabel metal3 s 230414 526099 230414 526099 4 u_riscv_top.core3_imem_addr\[15\]
+port 2208 nsew
+rlabel metal3 s 230414 525861 230414 525861 4 u_riscv_top.core3_imem_addr\[16\]
+port 2209 nsew
+rlabel metal3 s 230414 525589 230414 525589 4 u_riscv_top.core3_imem_addr\[17\]
+port 2210 nsew
+rlabel metal3 s 230414 525317 230414 525317 4 u_riscv_top.core3_imem_addr\[18\]
+port 2211 nsew
+rlabel metal3 s 230414 525045 230414 525045 4 u_riscv_top.core3_imem_addr\[19\]
+port 2212 nsew
+rlabel metal3 s 230414 529941 230414 529941 4 u_riscv_top.core3_imem_addr\[1\]
+port 2213 nsew
+rlabel metal3 s 230414 524739 230414 524739 4 u_riscv_top.core3_imem_addr\[20\]
+port 2214 nsew
+rlabel metal3 s 230414 524501 230414 524501 4 u_riscv_top.core3_imem_addr\[21\]
+port 2215 nsew
+rlabel metal3 s 230414 524229 230414 524229 4 u_riscv_top.core3_imem_addr\[22\]
+port 2216 nsew
+rlabel metal3 s 230414 523957 230414 523957 4 u_riscv_top.core3_imem_addr\[23\]
+port 2217 nsew
+rlabel metal3 s 230414 523685 230414 523685 4 u_riscv_top.core3_imem_addr\[24\]
+port 2218 nsew
+rlabel metal3 s 230414 523379 230414 523379 4 u_riscv_top.core3_imem_addr\[25\]
+port 2219 nsew
+rlabel metal3 s 230414 523141 230414 523141 4 u_riscv_top.core3_imem_addr\[26\]
+port 2220 nsew
+rlabel metal3 s 230414 522869 230414 522869 4 u_riscv_top.core3_imem_addr\[27\]
+port 2221 nsew
+rlabel metal3 s 230414 522597 230414 522597 4 u_riscv_top.core3_imem_addr\[28\]
+port 2222 nsew
+rlabel metal3 s 230414 522325 230414 522325 4 u_riscv_top.core3_imem_addr\[29\]
+port 2223 nsew
+rlabel metal3 s 230414 529635 230414 529635 4 u_riscv_top.core3_imem_addr\[2\]
+port 2224 nsew
+rlabel metal3 s 230414 522019 230414 522019 4 u_riscv_top.core3_imem_addr\[30\]
+port 2225 nsew
+rlabel metal3 s 230414 521781 230414 521781 4 u_riscv_top.core3_imem_addr\[31\]
+port 2226 nsew
+rlabel metal3 s 230414 529363 230414 529363 4 u_riscv_top.core3_imem_addr\[3\]
+port 2227 nsew
+rlabel metal3 s 230414 529091 230414 529091 4 u_riscv_top.core3_imem_addr\[4\]
+port 2228 nsew
+rlabel metal3 s 230414 528819 230414 528819 4 u_riscv_top.core3_imem_addr\[5\]
+port 2229 nsew
+rlabel metal3 s 230414 528581 230414 528581 4 u_riscv_top.core3_imem_addr\[6\]
+port 2230 nsew
+rlabel metal3 s 230414 528275 230414 528275 4 u_riscv_top.core3_imem_addr\[7\]
+port 2231 nsew
+rlabel metal3 s 230414 528037 230414 528037 4 u_riscv_top.core3_imem_addr\[8\]
+port 2232 nsew
+rlabel metal3 s 230414 527731 230414 527731 4 u_riscv_top.core3_imem_addr\[9\]
+port 2233 nsew
+rlabel metal3 s 230414 531029 230414 531029 4 u_riscv_top.core3_imem_bl\[0\]
+port 2234 nsew
+rlabel metal3 s 230414 530723 230414 530723 4 u_riscv_top.core3_imem_bl\[1\]
+port 2235 nsew
+rlabel metal3 s 230414 530451 230414 530451 4 u_riscv_top.core3_imem_bl\[2\]
+port 2236 nsew
+rlabel metal3 s 230414 521509 230414 521509 4 u_riscv_top.core3_imem_cmd
+port 2237 nsew
+rlabel metal3 s 230414 539733 230414 539733 4 u_riscv_top.core3_imem_rdata\[0\]
+port 2238 nsew
+rlabel metal3 s 230414 537013 230414 537013 4 u_riscv_top.core3_imem_rdata\[10\]
+port 2239 nsew
+rlabel metal3 s 230414 536741 230414 536741 4 u_riscv_top.core3_imem_rdata\[11\]
+port 2240 nsew
+rlabel metal3 s 230414 536435 230414 536435 4 u_riscv_top.core3_imem_rdata\[12\]
+port 2241 nsew
+rlabel metal3 s 230414 536163 230414 536163 4 u_riscv_top.core3_imem_rdata\[13\]
+port 2242 nsew
+rlabel metal3 s 230414 535891 230414 535891 4 u_riscv_top.core3_imem_rdata\[14\]
+port 2243 nsew
+rlabel metal3 s 230414 535653 230414 535653 4 u_riscv_top.core3_imem_rdata\[15\]
+port 2244 nsew
+rlabel metal3 s 230414 535381 230414 535381 4 u_riscv_top.core3_imem_rdata\[16\]
+port 2245 nsew
+rlabel metal3 s 230414 535075 230414 535075 4 u_riscv_top.core3_imem_rdata\[17\]
+port 2246 nsew
+rlabel metal3 s 230414 534803 230414 534803 4 u_riscv_top.core3_imem_rdata\[18\]
+port 2247 nsew
+rlabel metal3 s 230414 534531 230414 534531 4 u_riscv_top.core3_imem_rdata\[19\]
+port 2248 nsew
+rlabel metal3 s 230414 539427 230414 539427 4 u_riscv_top.core3_imem_rdata\[1\]
+port 2249 nsew
+rlabel metal3 s 230414 534293 230414 534293 4 u_riscv_top.core3_imem_rdata\[20\]
+port 2250 nsew
+rlabel metal3 s 230414 534021 230414 534021 4 u_riscv_top.core3_imem_rdata\[21\]
+port 2251 nsew
+rlabel metal3 s 230414 533715 230414 533715 4 u_riscv_top.core3_imem_rdata\[22\]
+port 2252 nsew
+rlabel metal3 s 230414 533443 230414 533443 4 u_riscv_top.core3_imem_rdata\[23\]
+port 2253 nsew
+rlabel metal3 s 230414 533171 230414 533171 4 u_riscv_top.core3_imem_rdata\[24\]
+port 2254 nsew
+rlabel metal3 s 230414 532933 230414 532933 4 u_riscv_top.core3_imem_rdata\[25\]
+port 2255 nsew
+rlabel metal3 s 230414 532661 230414 532661 4 u_riscv_top.core3_imem_rdata\[26\]
+port 2256 nsew
+rlabel metal3 s 230414 532355 230414 532355 4 u_riscv_top.core3_imem_rdata\[27\]
+port 2257 nsew
+rlabel metal3 s 230414 532083 230414 532083 4 u_riscv_top.core3_imem_rdata\[28\]
+port 2258 nsew
+rlabel metal3 s 230414 531811 230414 531811 4 u_riscv_top.core3_imem_rdata\[29\]
+port 2259 nsew
+rlabel metal3 s 230414 539189 230414 539189 4 u_riscv_top.core3_imem_rdata\[2\]
+port 2260 nsew
+rlabel metal3 s 230414 531539 230414 531539 4 u_riscv_top.core3_imem_rdata\[30\]
+port 2261 nsew
+rlabel metal3 s 230414 531267 230414 531267 4 u_riscv_top.core3_imem_rdata\[31\]
+port 2262 nsew
+rlabel metal3 s 230414 538883 230414 538883 4 u_riscv_top.core3_imem_rdata\[3\]
+port 2263 nsew
+rlabel metal3 s 230414 538611 230414 538611 4 u_riscv_top.core3_imem_rdata\[4\]
+port 2264 nsew
+rlabel metal3 s 230414 538339 230414 538339 4 u_riscv_top.core3_imem_rdata\[5\]
+port 2265 nsew
+rlabel metal3 s 230414 538101 230414 538101 4 u_riscv_top.core3_imem_rdata\[6\]
+port 2266 nsew
+rlabel metal3 s 230414 537829 230414 537829 4 u_riscv_top.core3_imem_rdata\[7\]
+port 2267 nsew
+rlabel metal3 s 230414 537523 230414 537523 4 u_riscv_top.core3_imem_rdata\[8\]
+port 2268 nsew
+rlabel metal3 s 230414 537251 230414 537251 4 u_riscv_top.core3_imem_rdata\[9\]
+port 2269 nsew
+rlabel metal3 s 230414 521237 230414 521237 4 u_riscv_top.core3_imem_req
+port 2270 nsew
+rlabel metal3 s 230414 520965 230414 520965 4 u_riscv_top.core3_imem_req_ack
+port 2271 nsew
+rlabel metal3 s 230414 540243 230414 540243 4 u_riscv_top.core3_imem_resp\[0\]
+port 2272 nsew
+rlabel metal3 s 230414 540005 230414 540005 4 u_riscv_top.core3_imem_resp\[1\]
+port 2273 nsew
+rlabel metal3 s 230414 626229 230414 626229 4 u_riscv_top.core3_irq_lines\[0\]
+port 2274 nsew
+rlabel metal3 s 230414 623509 230414 623509 4 u_riscv_top.core3_irq_lines\[10\]
+port 2275 nsew
+rlabel metal3 s 230414 623237 230414 623237 4 u_riscv_top.core3_irq_lines\[11\]
+port 2276 nsew
+rlabel metal3 s 230414 622965 230414 622965 4 u_riscv_top.core3_irq_lines\[12\]
+port 2277 nsew
+rlabel metal3 s 230414 622693 230414 622693 4 u_riscv_top.core3_irq_lines\[13\]
+port 2278 nsew
+rlabel metal3 s 230414 622421 230414 622421 4 u_riscv_top.core3_irq_lines\[14\]
+port 2279 nsew
+rlabel metal3 s 230414 622149 230414 622149 4 u_riscv_top.core3_irq_lines\[15\]
+port 2280 nsew
+rlabel metal3 s 230414 621877 230414 621877 4 u_riscv_top.core3_irq_lines\[16\]
+port 2281 nsew
+rlabel metal3 s 230414 621605 230414 621605 4 u_riscv_top.core3_irq_lines\[17\]
+port 2282 nsew
+rlabel metal3 s 230414 621299 230414 621299 4 u_riscv_top.core3_irq_lines\[18\]
+port 2283 nsew
+rlabel metal3 s 230414 621027 230414 621027 4 u_riscv_top.core3_irq_lines\[19\]
+port 2284 nsew
+rlabel metal3 s 230414 625923 230414 625923 4 u_riscv_top.core3_irq_lines\[1\]
+port 2285 nsew
+rlabel metal3 s 230414 620789 230414 620789 4 u_riscv_top.core3_irq_lines\[20\]
+port 2286 nsew
+rlabel metal3 s 230414 620517 230414 620517 4 u_riscv_top.core3_irq_lines\[21\]
+port 2287 nsew
+rlabel metal3 s 230414 620245 230414 620245 4 u_riscv_top.core3_irq_lines\[22\]
+port 2288 nsew
+rlabel metal3 s 230414 619939 230414 619939 4 u_riscv_top.core3_irq_lines\[23\]
+port 2289 nsew
+rlabel metal3 s 230414 619667 230414 619667 4 u_riscv_top.core3_irq_lines\[24\]
+port 2290 nsew
+rlabel metal3 s 230414 619429 230414 619429 4 u_riscv_top.core3_irq_lines\[25\]
+port 2291 nsew
+rlabel metal3 s 230414 619157 230414 619157 4 u_riscv_top.core3_irq_lines\[26\]
+port 2292 nsew
+rlabel metal3 s 230414 618885 230414 618885 4 u_riscv_top.core3_irq_lines\[27\]
+port 2293 nsew
+rlabel metal3 s 230414 618579 230414 618579 4 u_riscv_top.core3_irq_lines\[28\]
+port 2294 nsew
+rlabel metal3 s 230414 618307 230414 618307 4 u_riscv_top.core3_irq_lines\[29\]
+port 2295 nsew
+rlabel metal3 s 230414 625685 230414 625685 4 u_riscv_top.core3_irq_lines\[2\]
+port 2296 nsew
+rlabel metal3 s 230414 618069 230414 618069 4 u_riscv_top.core3_irq_lines\[30\]
+port 2297 nsew
+rlabel metal3 s 230414 617797 230414 617797 4 u_riscv_top.core3_irq_lines\[31\]
+port 2298 nsew
+rlabel metal3 s 230414 625379 230414 625379 4 u_riscv_top.core3_irq_lines\[3\]
+port 2299 nsew
+rlabel metal3 s 230414 625107 230414 625107 4 u_riscv_top.core3_irq_lines\[4\]
+port 2300 nsew
+rlabel metal3 s 230414 624869 230414 624869 4 u_riscv_top.core3_irq_lines\[5\]
+port 2301 nsew
+rlabel metal3 s 230414 624597 230414 624597 4 u_riscv_top.core3_irq_lines\[6\]
+port 2302 nsew
+rlabel metal3 s 230414 624325 230414 624325 4 u_riscv_top.core3_irq_lines\[7\]
+port 2303 nsew
+rlabel metal3 s 230414 624053 230414 624053 4 u_riscv_top.core3_irq_lines\[8\]
+port 2304 nsew
+rlabel metal3 s 230414 623781 230414 623781 4 u_riscv_top.core3_irq_lines\[9\]
+port 2305 nsew
+rlabel metal3 s 230414 626467 230414 626467 4 u_riscv_top.core3_soft_irq
+port 2306 nsew
+rlabel metal3 s 230414 600083 230414 600083 4 u_riscv_top.core3_timer_irq
+port 2307 nsew
+rlabel metal3 s 230414 617525 230414 617525 4 u_riscv_top.core3_timer_val\[0\]
+port 2308 nsew
+rlabel metal3 s 230414 614771 230414 614771 4 u_riscv_top.core3_timer_val\[10\]
+port 2309 nsew
+rlabel metal3 s 230414 614499 230414 614499 4 u_riscv_top.core3_timer_val\[11\]
+port 2310 nsew
+rlabel metal3 s 230414 614261 230414 614261 4 u_riscv_top.core3_timer_val\[12\]
+port 2311 nsew
+rlabel metal3 s 230414 613989 230414 613989 4 u_riscv_top.core3_timer_val\[13\]
+port 2312 nsew
+rlabel metal3 s 230414 613683 230414 613683 4 u_riscv_top.core3_timer_val\[14\]
+port 2313 nsew
+rlabel metal3 s 230414 613411 230414 613411 4 u_riscv_top.core3_timer_val\[15\]
+port 2314 nsew
+rlabel metal3 s 230414 613139 230414 613139 4 u_riscv_top.core3_timer_val\[16\]
+port 2315 nsew
+rlabel metal3 s 230414 612901 230414 612901 4 u_riscv_top.core3_timer_val\[17\]
+port 2316 nsew
+rlabel metal3 s 230414 612629 230414 612629 4 u_riscv_top.core3_timer_val\[18\]
+port 2317 nsew
+rlabel metal3 s 230414 612323 230414 612323 4 u_riscv_top.core3_timer_val\[19\]
+port 2318 nsew
+rlabel metal3 s 230414 617253 230414 617253 4 u_riscv_top.core3_timer_val\[1\]
+port 2319 nsew
+rlabel metal3 s 230414 612051 230414 612051 4 u_riscv_top.core3_timer_val\[20\]
+port 2320 nsew
+rlabel metal3 s 230414 611779 230414 611779 4 u_riscv_top.core3_timer_val\[21\]
+port 2321 nsew
+rlabel metal3 s 230414 611541 230414 611541 4 u_riscv_top.core3_timer_val\[22\]
+port 2322 nsew
+rlabel metal3 s 230414 611269 230414 611269 4 u_riscv_top.core3_timer_val\[23\]
+port 2323 nsew
+rlabel metal3 s 230414 610963 230414 610963 4 u_riscv_top.core3_timer_val\[24\]
+port 2324 nsew
+rlabel metal3 s 230414 610691 230414 610691 4 u_riscv_top.core3_timer_val\[25\]
+port 2325 nsew
+rlabel metal3 s 230414 610419 230414 610419 4 u_riscv_top.core3_timer_val\[26\]
+port 2326 nsew
+rlabel metal3 s 230414 610181 230414 610181 4 u_riscv_top.core3_timer_val\[27\]
+port 2327 nsew
+rlabel metal3 s 230414 609909 230414 609909 4 u_riscv_top.core3_timer_val\[28\]
+port 2328 nsew
+rlabel metal3 s 230414 609603 230414 609603 4 u_riscv_top.core3_timer_val\[29\]
+port 2329 nsew
+rlabel metal3 s 230414 616981 230414 616981 4 u_riscv_top.core3_timer_val\[2\]
+port 2330 nsew
+rlabel metal3 s 230414 609331 230414 609331 4 u_riscv_top.core3_timer_val\[30\]
+port 2331 nsew
+rlabel metal3 s 230414 609059 230414 609059 4 u_riscv_top.core3_timer_val\[31\]
+port 2332 nsew
+rlabel metal3 s 230414 608821 230414 608821 4 u_riscv_top.core3_timer_val\[32\]
+port 2333 nsew
+rlabel metal3 s 230414 608549 230414 608549 4 u_riscv_top.core3_timer_val\[33\]
+port 2334 nsew
+rlabel metal3 s 230414 608243 230414 608243 4 u_riscv_top.core3_timer_val\[34\]
+port 2335 nsew
+rlabel metal3 s 230414 607971 230414 607971 4 u_riscv_top.core3_timer_val\[35\]
+port 2336 nsew
+rlabel metal3 s 230414 607699 230414 607699 4 u_riscv_top.core3_timer_val\[36\]
+port 2337 nsew
+rlabel metal3 s 230414 607427 230414 607427 4 u_riscv_top.core3_timer_val\[37\]
+port 2338 nsew
+rlabel metal3 s 230414 607155 230414 607155 4 u_riscv_top.core3_timer_val\[38\]
+port 2339 nsew
+rlabel metal3 s 230414 606917 230414 606917 4 u_riscv_top.core3_timer_val\[39\]
+port 2340 nsew
+rlabel metal3 s 230414 616709 230414 616709 4 u_riscv_top.core3_timer_val\[3\]
+port 2341 nsew
+rlabel metal3 s 230414 606611 230414 606611 4 u_riscv_top.core3_timer_val\[40\]
+port 2342 nsew
+rlabel metal3 s 230414 606373 230414 606373 4 u_riscv_top.core3_timer_val\[41\]
+port 2343 nsew
+rlabel metal3 s 230414 606067 230414 606067 4 u_riscv_top.core3_timer_val\[42\]
+port 2344 nsew
+rlabel metal3 s 230414 605795 230414 605795 4 u_riscv_top.core3_timer_val\[43\]
+port 2345 nsew
+rlabel metal3 s 230414 605557 230414 605557 4 u_riscv_top.core3_timer_val\[44\]
+port 2346 nsew
+rlabel metal3 s 230414 605251 230414 605251 4 u_riscv_top.core3_timer_val\[45\]
+port 2347 nsew
+rlabel metal3 s 230414 605013 230414 605013 4 u_riscv_top.core3_timer_val\[46\]
+port 2348 nsew
+rlabel metal3 s 230414 604741 230414 604741 4 u_riscv_top.core3_timer_val\[47\]
+port 2349 nsew
+rlabel metal3 s 230414 604469 230414 604469 4 u_riscv_top.core3_timer_val\[48\]
+port 2350 nsew
+rlabel metal3 s 230414 604163 230414 604163 4 u_riscv_top.core3_timer_val\[49\]
+port 2351 nsew
+rlabel metal3 s 230414 616437 230414 616437 4 u_riscv_top.core3_timer_val\[4\]
+port 2352 nsew
+rlabel metal3 s 230414 603925 230414 603925 4 u_riscv_top.core3_timer_val\[50\]
+port 2353 nsew
+rlabel metal3 s 230414 603619 230414 603619 4 u_riscv_top.core3_timer_val\[51\]
+port 2354 nsew
+rlabel metal3 s 230414 603381 230414 603381 4 u_riscv_top.core3_timer_val\[52\]
+port 2355 nsew
+rlabel metal3 s 230414 603109 230414 603109 4 u_riscv_top.core3_timer_val\[53\]
+port 2356 nsew
+rlabel metal3 s 230414 602803 230414 602803 4 u_riscv_top.core3_timer_val\[54\]
+port 2357 nsew
+rlabel metal3 s 230414 602565 230414 602565 4 u_riscv_top.core3_timer_val\[55\]
+port 2358 nsew
+rlabel metal3 s 230414 602259 230414 602259 4 u_riscv_top.core3_timer_val\[56\]
+port 2359 nsew
+rlabel metal3 s 230414 602021 230414 602021 4 u_riscv_top.core3_timer_val\[57\]
+port 2360 nsew
+rlabel metal3 s 230414 601749 230414 601749 4 u_riscv_top.core3_timer_val\[58\]
+port 2361 nsew
+rlabel metal3 s 230414 601443 230414 601443 4 u_riscv_top.core3_timer_val\[59\]
+port 2362 nsew
+rlabel metal3 s 230414 616165 230414 616165 4 u_riscv_top.core3_timer_val\[5\]
+port 2363 nsew
+rlabel metal3 s 230414 601205 230414 601205 4 u_riscv_top.core3_timer_val\[60\]
+port 2364 nsew
+rlabel metal3 s 230414 600899 230414 600899 4 u_riscv_top.core3_timer_val\[61\]
+port 2365 nsew
+rlabel metal3 s 230414 600661 230414 600661 4 u_riscv_top.core3_timer_val\[62\]
+port 2366 nsew
+rlabel metal3 s 230414 600355 230414 600355 4 u_riscv_top.core3_timer_val\[63\]
+port 2367 nsew
+rlabel metal3 s 230414 615893 230414 615893 4 u_riscv_top.core3_timer_val\[6\]
+port 2368 nsew
+rlabel metal3 s 230414 615621 230414 615621 4 u_riscv_top.core3_timer_val\[7\]
+port 2369 nsew
+rlabel metal3 s 230414 615349 230414 615349 4 u_riscv_top.core3_timer_val\[8\]
+port 2370 nsew
+rlabel metal3 s 230414 615077 230414 615077 4 u_riscv_top.core3_timer_val\[9\]
+port 2371 nsew
+rlabel metal3 s 230414 520659 230414 520659 4 u_riscv_top.core3_uid\[0\]
+port 2372 nsew
+rlabel metal3 s 230414 520387 230414 520387 4 u_riscv_top.core3_uid\[1\]
+port 2373 nsew
+rlabel metal3 s 129260 317356 129260 317356 4 u_riscv_top.core_clk_core0_skew
+port 2374 nsew
+rlabel metal3 s 240212 317356 240212 317356 4 u_riscv_top.core_clk_core1_skew
+port 2375 nsew
+rlabel metal3 s 129260 517276 129260 517276 4 u_riscv_top.core_clk_core2_skew
+port 2376 nsew
+rlabel metal3 s 240212 517276 240212 517276 4 u_riscv_top.core_clk_core3_skew
+port 2377 nsew
+rlabel metal3 s 227332 281724 227332 281724 4 u_riscv_top.core_clk_icon_skew
+port 2378 nsew
+rlabel metal2 s 346886 131529 346886 131529 4 u_riscv_top.core_clk_int\[0\]
+port 2379 nsew
+rlabel metal2 s 229402 280585 229402 280585 4 u_riscv_top.core_clk_int\[1\]
+port 2380 nsew
+rlabel metal3 s 344356 131716 344356 131716 4 u_riscv_top.core_clk_intf_skew
+port 2381 nsew
+rlabel metal1 s 210956 274482 210956 274482 4 u_riscv_top.core_dcache_addr\[0\]
+port 2382 nsew
+rlabel metal1 s 207414 273734 207414 273734 4 u_riscv_top.core_dcache_addr\[10\]
+port 2383 nsew
+rlabel metal1 s 172730 275740 172730 275740 4 u_riscv_top.core_dcache_addr\[11\]
+port 2384 nsew
+rlabel metal1 s 214360 270606 214360 270606 4 u_riscv_top.core_dcache_addr\[12\]
+port 2385 nsew
+rlabel metal1 s 200100 275162 200100 275162 4 u_riscv_top.core_dcache_addr\[13\]
+port 2386 nsew
+rlabel metal2 s 172178 278470 172178 278470 4 u_riscv_top.core_dcache_addr\[14\]
+port 2387 nsew
+rlabel metal2 s 171994 277722 171994 277722 4 u_riscv_top.core_dcache_addr\[15\]
+port 2388 nsew
+rlabel metal2 s 171810 278334 171810 278334 4 u_riscv_top.core_dcache_addr\[16\]
+port 2389 nsew
+rlabel metal2 s 199410 275383 199410 275383 4 u_riscv_top.core_dcache_addr\[17\]
+port 2390 nsew
+rlabel metal1 s 211370 269076 211370 269076 4 u_riscv_top.core_dcache_addr\[18\]
+port 2391 nsew
+rlabel metal1 s 171396 268838 171396 268838 4 u_riscv_top.core_dcache_addr\[19\]
+port 2392 nsew
+rlabel metal2 s 174340 268260 174340 268260 4 u_riscv_top.core_dcache_addr\[1\]
+port 2393 nsew
+rlabel metal1 s 170798 268294 170798 268294 4 u_riscv_top.core_dcache_addr\[20\]
+port 2394 nsew
+rlabel metal1 s 170568 268090 170568 268090 4 u_riscv_top.core_dcache_addr\[21\]
+port 2395 nsew
+rlabel metal1 s 170568 268226 170568 268226 4 u_riscv_top.core_dcache_addr\[22\]
+port 2396 nsew
+rlabel metal2 s 170568 268396 170568 268396 4 u_riscv_top.core_dcache_addr\[23\]
+port 2397 nsew
+rlabel metal2 s 170338 270208 170338 270208 4 u_riscv_top.core_dcache_addr\[24\]
+port 2398 nsew
+rlabel metal1 s 173374 275808 173374 275808 4 u_riscv_top.core_dcache_addr\[25\]
+port 2399 nsew
+rlabel metal2 s 169970 278572 169970 278572 4 u_riscv_top.core_dcache_addr\[26\]
+port 2400 nsew
+rlabel metal2 s 211738 258050 211738 258050 4 u_riscv_top.core_dcache_addr\[27\]
+port 2401 nsew
+rlabel metal2 s 211600 268396 211600 268396 4 u_riscv_top.core_dcache_addr\[28\]
+port 2402 nsew
+rlabel metal2 s 210082 275264 210082 275264 4 u_riscv_top.core_dcache_addr\[29\]
+port 2403 nsew
+rlabel metal2 s 210450 272612 210450 272612 4 u_riscv_top.core_dcache_addr\[2\]
+port 2404 nsew
+rlabel metal2 s 211094 276641 211094 276641 4 u_riscv_top.core_dcache_addr\[30\]
+port 2405 nsew
+rlabel metal2 s 169050 278708 169050 278708 4 u_riscv_top.core_dcache_addr\[31\]
+port 2406 nsew
+rlabel metal1 s 174340 268294 174340 268294 4 u_riscv_top.core_dcache_addr\[3\]
+port 2407 nsew
+rlabel metal1 s 174202 268090 174202 268090 4 u_riscv_top.core_dcache_addr\[4\]
+port 2408 nsew
+rlabel metal1 s 173420 268770 173420 268770 4 u_riscv_top.core_dcache_addr\[5\]
+port 2409 nsew
+rlabel metal1 s 173420 268226 173420 268226 4 u_riscv_top.core_dcache_addr\[6\]
+port 2410 nsew
+rlabel metal1 s 173282 268090 173282 268090 4 u_riscv_top.core_dcache_addr\[7\]
+port 2411 nsew
+rlabel metal2 s 173282 270752 173282 270752 4 u_riscv_top.core_dcache_addr\[8\]
+port 2412 nsew
+rlabel metal1 s 173236 268294 173236 268294 4 u_riscv_top.core_dcache_addr\[9\]
+port 2413 nsew
+rlabel metal2 s 168636 276420 168636 276420 4 u_riscv_top.core_dcache_cmd
+port 2414 nsew
+rlabel metal1 s 186530 272374 186530 272374 4 u_riscv_top.core_dcache_rdata\[0\]
+port 2415 nsew
+rlabel metal2 s 211186 277270 211186 277270 4 u_riscv_top.core_dcache_rdata\[10\]
+port 2416 nsew
+rlabel metal1 s 219420 276896 219420 276896 4 u_riscv_top.core_dcache_rdata\[11\]
+port 2417 nsew
+rlabel metal2 s 226274 258186 226274 258186 4 u_riscv_top.core_dcache_rdata\[12\]
+port 2418 nsew
+rlabel metal2 s 226090 258900 226090 258900 4 u_riscv_top.core_dcache_rdata\[13\]
+port 2419 nsew
+rlabel metal2 s 225814 271611 225814 271611 4 u_riscv_top.core_dcache_rdata\[14\]
+port 2420 nsew
+rlabel metal2 s 183770 278674 183770 278674 4 u_riscv_top.core_dcache_rdata\[15\]
+port 2421 nsew
+rlabel metal2 s 225538 269575 225538 269575 4 u_riscv_top.core_dcache_rdata\[16\]
+port 2422 nsew
+rlabel metal2 s 225354 259444 225354 259444 4 u_riscv_top.core_dcache_rdata\[17\]
+port 2423 nsew
+rlabel metal2 s 225170 259478 225170 259478 4 u_riscv_top.core_dcache_rdata\[18\]
+port 2424 nsew
+rlabel metal2 s 224986 259580 224986 259580 4 u_riscv_top.core_dcache_rdata\[19\]
+port 2425 nsew
+rlabel metal2 s 186438 276420 186438 276420 4 u_riscv_top.core_dcache_rdata\[1\]
+port 2426 nsew
+rlabel metal1 s 182574 267954 182574 267954 4 u_riscv_top.core_dcache_rdata\[20\]
+port 2427 nsew
+rlabel metal1 s 182528 276794 182528 276794 4 u_riscv_top.core_dcache_rdata\[21\]
+port 2428 nsew
+rlabel metal2 s 182666 268387 182666 268387 4 u_riscv_top.core_dcache_rdata\[22\]
+port 2429 nsew
+rlabel metal1 s 182528 268090 182528 268090 4 u_riscv_top.core_dcache_rdata\[23\]
+port 2430 nsew
+rlabel metal1 s 181608 268226 181608 268226 4 u_riscv_top.core_dcache_rdata\[24\]
+port 2431 nsew
+rlabel metal2 s 181194 263353 181194 263353 4 u_riscv_top.core_dcache_rdata\[25\]
+port 2432 nsew
+rlabel metal1 s 181286 268090 181286 268090 4 u_riscv_top.core_dcache_rdata\[26\]
+port 2433 nsew
+rlabel metal1 s 181286 268294 181286 268294 4 u_riscv_top.core_dcache_rdata\[27\]
+port 2434 nsew
+rlabel metal2 s 181378 277858 181378 277858 4 u_riscv_top.core_dcache_rdata\[28\]
+port 2435 nsew
+rlabel metal1 s 181056 264690 181056 264690 4 u_riscv_top.core_dcache_rdata\[29\]
+port 2436 nsew
+rlabel metal2 s 228114 260192 228114 260192 4 u_riscv_top.core_dcache_rdata\[2\]
+port 2437 nsew
+rlabel metal1 s 201940 264826 201940 264826 4 u_riscv_top.core_dcache_rdata\[30\]
+port 2438 nsew
+rlabel metal1 s 181056 268770 181056 268770 4 u_riscv_top.core_dcache_rdata\[31\]
+port 2439 nsew
+rlabel metal2 s 227930 257676 227930 257676 4 u_riscv_top.core_dcache_rdata\[3\]
+port 2440 nsew
+rlabel metal2 s 227746 260158 227746 260158 4 u_riscv_top.core_dcache_rdata\[4\]
+port 2441 nsew
+rlabel metal2 s 227562 257676 227562 257676 4 u_riscv_top.core_dcache_rdata\[5\]
+port 2442 nsew
+rlabel metal2 s 227378 260022 227378 260022 4 u_riscv_top.core_dcache_rdata\[6\]
+port 2443 nsew
+rlabel metal2 s 227194 260294 227194 260294 4 u_riscv_top.core_dcache_rdata\[7\]
+port 2444 nsew
+rlabel metal2 s 227010 260260 227010 260260 4 u_riscv_top.core_dcache_rdata\[8\]
+port 2445 nsew
+rlabel metal2 s 226826 260090 226826 260090 4 u_riscv_top.core_dcache_rdata\[9\]
+port 2446 nsew
+rlabel metal2 s 168314 279286 168314 279286 4 u_riscv_top.core_dcache_req
+port 2447 nsew
+rlabel metal2 s 167709 280092 167709 280092 4 u_riscv_top.core_dcache_req_ack
+port 2448 nsew
+rlabel metal1 s 207552 277202 207552 277202 4 u_riscv_top.core_dcache_resp\[0\]
+port 2449 nsew
+rlabel metal1 s 186530 272442 186530 272442 4 u_riscv_top.core_dcache_resp\[1\]
+port 2450 nsew
+rlabel metal2 s 180136 266084 180136 266084 4 u_riscv_top.core_dcache_wdata\[0\]
+port 2451 nsew
+rlabel metal1 s 199778 264758 199778 264758 4 u_riscv_top.core_dcache_wdata\[10\]
+port 2452 nsew
+rlabel metal1 s 199594 266322 199594 266322 4 u_riscv_top.core_dcache_wdata\[11\]
+port 2453 nsew
+rlabel metal2 s 178434 272826 178434 272826 4 u_riscv_top.core_dcache_wdata\[12\]
+port 2454 nsew
+rlabel metal2 s 210450 265268 210450 265268 4 u_riscv_top.core_dcache_wdata\[13\]
+port 2455 nsew
+rlabel metal2 s 178342 269373 178342 269373 4 u_riscv_top.core_dcache_wdata\[14\]
+port 2456 nsew
+rlabel metal1 s 198858 266118 198858 266118 4 u_riscv_top.core_dcache_wdata\[15\]
+port 2457 nsew
+rlabel metal1 s 198674 265166 198674 265166 4 u_riscv_top.core_dcache_wdata\[16\]
+port 2458 nsew
+rlabel metal1 s 198858 265302 198858 265302 4 u_riscv_top.core_dcache_wdata\[17\]
+port 2459 nsew
+rlabel metal1 s 200100 262548 200100 262548 4 u_riscv_top.core_dcache_wdata\[18\]
+port 2460 nsew
+rlabel metal2 s 217074 265421 217074 265421 4 u_riscv_top.core_dcache_wdata\[19\]
+port 2461 nsew
+rlabel metal1 s 201434 266254 201434 266254 4 u_riscv_top.core_dcache_wdata\[1\]
+port 2462 nsew
+rlabel metal1 s 177146 270266 177146 270266 4 u_riscv_top.core_dcache_wdata\[20\]
+port 2463 nsew
+rlabel metal2 s 176870 270164 176870 270164 4 u_riscv_top.core_dcache_wdata\[21\]
+port 2464 nsew
+rlabel metal2 s 176594 272996 176594 272996 4 u_riscv_top.core_dcache_wdata\[22\]
+port 2465 nsew
+rlabel metal2 s 218362 256792 218362 256792 4 u_riscv_top.core_dcache_wdata\[23\]
+port 2466 nsew
+rlabel metal1 s 175950 268226 175950 268226 4 u_riscv_top.core_dcache_wdata\[24\]
+port 2467 nsew
+rlabel metal1 s 175904 263738 175904 263738 4 u_riscv_top.core_dcache_wdata\[25\]
+port 2468 nsew
+rlabel metal2 s 175858 268644 175858 268644 4 u_riscv_top.core_dcache_wdata\[26\]
+port 2469 nsew
+rlabel metal2 s 213026 269484 213026 269484 4 u_riscv_top.core_dcache_wdata\[27\]
+port 2470 nsew
+rlabel metal1 s 175720 276658 175720 276658 4 u_riscv_top.core_dcache_wdata\[28\]
+port 2471 nsew
+rlabel metal2 s 175398 270300 175398 270300 4 u_riscv_top.core_dcache_wdata\[29\]
+port 2472 nsew
+rlabel metal2 s 215326 267036 215326 267036 4 u_riscv_top.core_dcache_wdata\[2\]
+port 2473 nsew
+rlabel metal2 s 175122 273574 175122 273574 4 u_riscv_top.core_dcache_wdata\[30\]
+port 2474 nsew
+rlabel metal2 s 174938 273676 174938 273676 4 u_riscv_top.core_dcache_wdata\[31\]
+port 2475 nsew
+rlabel metal1 s 201066 267682 201066 267682 4 u_riscv_top.core_dcache_wdata\[3\]
+port 2476 nsew
+rlabel metal1 s 200882 267614 200882 267614 4 u_riscv_top.core_dcache_wdata\[4\]
+port 2477 nsew
+rlabel metal1 s 180228 270062 180228 270062 4 u_riscv_top.core_dcache_wdata\[5\]
+port 2478 nsew
+rlabel metal1 s 180090 270402 180090 270402 4 u_riscv_top.core_dcache_wdata\[6\]
+port 2479 nsew
+rlabel metal1 s 200192 267410 200192 267410 4 u_riscv_top.core_dcache_wdata\[7\]
+port 2480 nsew
+rlabel metal1 s 200192 267138 200192 267138 4 u_riscv_top.core_dcache_wdata\[8\]
+port 2481 nsew
+rlabel metal1 s 199962 267478 199962 267478 4 u_riscv_top.core_dcache_wdata\[9\]
+port 2482 nsew
+rlabel metal2 s 198398 260168 198398 260168 4 u_riscv_top.core_dcache_width\[0\]
+port 2483 nsew
+rlabel metal2 s 169050 276318 169050 276318 4 u_riscv_top.core_dcache_width\[1\]
+port 2484 nsew
+rlabel metal1 s 197156 278630 197156 278630 4 u_riscv_top.core_dmem_addr\[0\]
+port 2485 nsew
+rlabel metal2 s 198858 277882 198858 277882 4 u_riscv_top.core_dmem_addr\[10\]
+port 2486 nsew
+rlabel metal1 s 196420 277610 196420 277610 4 u_riscv_top.core_dmem_addr\[11\]
+port 2487 nsew
+rlabel metal2 s 192694 272293 192694 272293 4 u_riscv_top.core_dmem_addr\[12\]
+port 2488 nsew
+rlabel metal2 s 192878 279524 192878 279524 4 u_riscv_top.core_dmem_addr\[13\]
+port 2489 nsew
+rlabel metal2 s 192694 279558 192694 279558 4 u_riscv_top.core_dmem_addr\[14\]
+port 2490 nsew
+rlabel metal2 s 192510 278606 192510 278606 4 u_riscv_top.core_dmem_addr\[15\]
+port 2491 nsew
+rlabel metal2 s 192326 274526 192326 274526 4 u_riscv_top.core_dmem_addr\[16\]
+port 2492 nsew
+rlabel metal2 s 192142 274492 192142 274492 4 u_riscv_top.core_dmem_addr\[17\]
+port 2493 nsew
+rlabel metal1 s 192188 272442 192188 272442 4 u_riscv_top.core_dmem_addr\[18\]
+port 2494 nsew
+rlabel metal2 s 191774 274288 191774 274288 4 u_riscv_top.core_dmem_addr\[19\]
+port 2495 nsew
+rlabel metal2 s 195086 274390 195086 274390 4 u_riscv_top.core_dmem_addr\[1\]
+port 2496 nsew
+rlabel metal2 s 191682 272973 191682 272973 4 u_riscv_top.core_dmem_addr\[20\]
+port 2497 nsew
+rlabel metal2 s 191406 274220 191406 274220 4 u_riscv_top.core_dmem_addr\[21\]
+port 2498 nsew
+rlabel metal2 s 191222 274458 191222 274458 4 u_riscv_top.core_dmem_addr\[22\]
+port 2499 nsew
+rlabel metal2 s 190946 272837 190946 272837 4 u_riscv_top.core_dmem_addr\[23\]
+port 2500 nsew
+rlabel metal2 s 190854 274424 190854 274424 4 u_riscv_top.core_dmem_addr\[24\]
+port 2501 nsew
+rlabel metal2 s 190670 279626 190670 279626 4 u_riscv_top.core_dmem_addr\[25\]
+port 2502 nsew
+rlabel metal1 s 200100 257958 200100 257958 4 u_riscv_top.core_dmem_addr\[26\]
+port 2503 nsew
+rlabel metal2 s 190302 279592 190302 279592 4 u_riscv_top.core_dmem_addr\[27\]
+port 2504 nsew
+rlabel metal1 s 189612 272442 189612 272442 4 u_riscv_top.core_dmem_addr\[28\]
+port 2505 nsew
+rlabel metal1 s 210910 276794 210910 276794 4 u_riscv_top.core_dmem_addr\[29\]
+port 2506 nsew
+rlabel metal2 s 194718 270164 194718 270164 4 u_riscv_top.core_dmem_addr\[2\]
+port 2507 nsew
+rlabel metal2 s 189750 275172 189750 275172 4 u_riscv_top.core_dmem_addr\[30\]
+port 2508 nsew
+rlabel metal2 s 231242 268925 231242 268925 4 u_riscv_top.core_dmem_addr\[31\]
+port 2509 nsew
+rlabel metal2 s 236670 256316 236670 256316 4 u_riscv_top.core_dmem_addr\[3\]
+port 2510 nsew
+rlabel metal1 s 196420 278698 196420 278698 4 u_riscv_top.core_dmem_addr\[4\]
+port 2511 nsew
+rlabel metal2 s 194534 273585 194534 273585 4 u_riscv_top.core_dmem_addr\[5\]
+port 2512 nsew
+rlabel metal2 s 194166 274968 194166 274968 4 u_riscv_top.core_dmem_addr\[6\]
+port 2513 nsew
+rlabel metal2 s 193982 275274 193982 275274 4 u_riscv_top.core_dmem_addr\[7\]
+port 2514 nsew
+rlabel metal2 s 193798 275240 193798 275240 4 u_riscv_top.core_dmem_addr\[8\]
+port 2515 nsew
+rlabel metal2 s 193614 275138 193614 275138 4 u_riscv_top.core_dmem_addr\[9\]
+port 2516 nsew
+rlabel metal2 s 230874 268823 230874 268823 4 u_riscv_top.core_dmem_bl\[0\]
+port 2517 nsew
+rlabel metal2 s 188830 275070 188830 275070 4 u_riscv_top.core_dmem_bl\[1\]
+port 2518 nsew
+rlabel metal2 s 188646 275036 188646 275036 4 u_riscv_top.core_dmem_bl\[2\]
+port 2519 nsew
+rlabel metal2 s 188462 279660 188462 279660 4 u_riscv_top.core_dmem_cmd
+port 2520 nsew
+rlabel metal2 s 248998 258118 248998 258118 4 u_riscv_top.core_dmem_rdata\[0\]
+port 2521 nsew
+rlabel metal2 s 204976 278460 204976 278460 4 u_riscv_top.core_dmem_rdata\[10\]
+port 2522 nsew
+rlabel metal2 s 213762 276828 213762 276828 4 u_riscv_top.core_dmem_rdata\[11\]
+port 2523 nsew
+rlabel metal2 s 215234 277270 215234 277270 4 u_riscv_top.core_dmem_rdata\[12\]
+port 2524 nsew
+rlabel metal2 s 204654 279014 204654 279014 4 u_riscv_top.core_dmem_rdata\[13\]
+port 2525 nsew
+rlabel metal2 s 217626 277971 217626 277971 4 u_riscv_top.core_dmem_rdata\[14\]
+port 2526 nsew
+rlabel metal3 s 205574 278307 205574 278307 4 u_riscv_top.core_dmem_rdata\[15\]
+port 2527 nsew
+rlabel metal1 s 244122 259386 244122 259386 4 u_riscv_top.core_dmem_rdata\[16\]
+port 2528 nsew
+rlabel metal2 s 209024 274108 209024 274108 4 u_riscv_top.core_dmem_rdata\[17\]
+port 2529 nsew
+rlabel metal1 s 242558 259318 242558 259318 4 u_riscv_top.core_dmem_rdata\[18\]
+port 2530 nsew
+rlabel metal1 s 244996 262990 244996 262990 4 u_riscv_top.core_dmem_rdata\[19\]
+port 2531 nsew
+rlabel metal2 s 248814 263592 248814 263592 4 u_riscv_top.core_dmem_rdata\[1\]
+port 2532 nsew
+rlabel metal2 s 203412 277380 203412 277380 4 u_riscv_top.core_dmem_rdata\[20\]
+port 2533 nsew
+rlabel metal1 s 244996 265574 244996 265574 4 u_riscv_top.core_dmem_rdata\[21\]
+port 2534 nsew
+rlabel metal2 s 244950 256979 244950 256979 4 u_riscv_top.core_dmem_rdata\[22\]
+port 2535 nsew
+rlabel metal2 s 244766 256316 244766 256316 4 u_riscv_top.core_dmem_rdata\[23\]
+port 2536 nsew
+rlabel metal2 s 244582 256248 244582 256248 4 u_riscv_top.core_dmem_rdata\[24\]
+port 2537 nsew
+rlabel metal1 s 205114 277474 205114 277474 4 u_riscv_top.core_dmem_rdata\[25\]
+port 2538 nsew
+rlabel metal1 s 224480 275910 224480 275910 4 u_riscv_top.core_dmem_rdata\[26\]
+port 2539 nsew
+rlabel metal1 s 203550 277746 203550 277746 4 u_riscv_top.core_dmem_rdata\[27\]
+port 2540 nsew
+rlabel metal2 s 243846 263796 243846 263796 4 u_riscv_top.core_dmem_rdata\[28\]
+port 2541 nsew
+rlabel metal2 s 201802 278205 201802 278205 4 u_riscv_top.core_dmem_rdata\[29\]
+port 2542 nsew
+rlabel metal2 s 248630 261042 248630 261042 4 u_riscv_top.core_dmem_rdata\[2\]
+port 2543 nsew
+rlabel metal1 s 203320 277610 203320 277610 4 u_riscv_top.core_dmem_rdata\[30\]
+port 2544 nsew
+rlabel metal2 s 201434 277380 201434 277380 4 u_riscv_top.core_dmem_rdata\[31\]
+port 2545 nsew
+rlabel metal2 s 248446 256996 248446 256996 4 u_riscv_top.core_dmem_rdata\[3\]
+port 2546 nsew
+rlabel metal2 s 248262 258832 248262 258832 4 u_riscv_top.core_dmem_rdata\[4\]
+port 2547 nsew
+rlabel metal1 s 226780 277338 226780 277338 4 u_riscv_top.core_dmem_rdata\[5\]
+port 2548 nsew
+rlabel metal2 s 247894 262266 247894 262266 4 u_riscv_top.core_dmem_rdata\[6\]
+port 2549 nsew
+rlabel metal1 s 227976 275842 227976 275842 4 u_riscv_top.core_dmem_rdata\[7\]
+port 2550 nsew
+rlabel metal2 s 205528 278732 205528 278732 4 u_riscv_top.core_dmem_rdata\[8\]
+port 2551 nsew
+rlabel metal2 s 243018 263126 243018 263126 4 u_riscv_top.core_dmem_rdata\[9\]
+port 2552 nsew
+rlabel metal2 s 229310 269639 229310 269639 4 u_riscv_top.core_dmem_req
+port 2553 nsew
+rlabel metal2 s 188094 276532 188094 276532 4 u_riscv_top.core_dmem_req_ack
+port 2554 nsew
+rlabel metal2 s 249366 257302 249366 257302 4 u_riscv_top.core_dmem_resp\[0\]
+port 2555 nsew
+rlabel metal2 s 249182 257200 249182 257200 4 u_riscv_top.core_dmem_resp\[1\]
+port 2556 nsew
+rlabel metal2 s 238050 265744 238050 265744 4 u_riscv_top.core_dmem_wdata\[0\]
+port 2557 nsew
+rlabel metal2 s 199318 278878 199318 278878 4 u_riscv_top.core_dmem_wdata\[10\]
+port 2558 nsew
+rlabel metal1 s 240764 262786 240764 262786 4 u_riscv_top.core_dmem_wdata\[11\]
+port 2559 nsew
+rlabel metal2 s 240902 264408 240902 264408 4 u_riscv_top.core_dmem_wdata\[12\]
+port 2560 nsew
+rlabel metal2 s 240626 270251 240626 270251 4 u_riscv_top.core_dmem_wdata\[13\]
+port 2561 nsew
+rlabel metal2 s 240534 264238 240534 264238 4 u_riscv_top.core_dmem_wdata\[14\]
+port 2562 nsew
+rlabel metal1 s 240672 263058 240672 263058 4 u_riscv_top.core_dmem_wdata\[15\]
+port 2563 nsew
+rlabel metal1 s 240672 262718 240672 262718 4 u_riscv_top.core_dmem_wdata\[16\]
+port 2564 nsew
+rlabel metal1 s 238142 258332 238142 258332 4 u_riscv_top.core_dmem_wdata\[17\]
+port 2565 nsew
+rlabel metal2 s 197800 277380 197800 277380 4 u_riscv_top.core_dmem_wdata\[18\]
+port 2566 nsew
+rlabel metal2 s 197478 277236 197478 277236 4 u_riscv_top.core_dmem_wdata\[19\]
+port 2567 nsew
+rlabel metal2 s 242926 257404 242926 257404 4 u_riscv_top.core_dmem_wdata\[1\]
+port 2568 nsew
+rlabel metal1 s 198720 278154 198720 278154 4 u_riscv_top.core_dmem_wdata\[20\]
+port 2569 nsew
+rlabel metal2 s 197294 277076 197294 277076 4 u_riscv_top.core_dmem_wdata\[21\]
+port 2570 nsew
+rlabel metal2 s 197110 277110 197110 277110 4 u_riscv_top.core_dmem_wdata\[22\]
+port 2571 nsew
+rlabel metal2 s 196926 277144 196926 277144 4 u_riscv_top.core_dmem_wdata\[23\]
+port 2572 nsew
+rlabel metal2 s 238694 257574 238694 257574 4 u_riscv_top.core_dmem_wdata\[24\]
+port 2573 nsew
+rlabel metal2 s 238510 257472 238510 257472 4 u_riscv_top.core_dmem_wdata\[25\]
+port 2574 nsew
+rlabel metal2 s 238326 257608 238326 257608 4 u_riscv_top.core_dmem_wdata\[26\]
+port 2575 nsew
+rlabel metal2 s 238142 257064 238142 257064 4 u_riscv_top.core_dmem_wdata\[27\]
+port 2576 nsew
+rlabel metal2 s 196006 277042 196006 277042 4 u_riscv_top.core_dmem_wdata\[28\]
+port 2577 nsew
+rlabel metal2 s 195822 276872 195822 276872 4 u_riscv_top.core_dmem_wdata\[29\]
+port 2578 nsew
+rlabel metal2 s 215050 276896 215050 276896 4 u_riscv_top.core_dmem_wdata\[2\]
+port 2579 nsew
+rlabel metal2 s 195730 274333 195730 274333 4 u_riscv_top.core_dmem_wdata\[30\]
+port 2580 nsew
+rlabel metal2 s 195500 278732 195500 278732 4 u_riscv_top.core_dmem_wdata\[31\]
+port 2581 nsew
+rlabel metal1 s 205114 278290 205114 278290 4 u_riscv_top.core_dmem_wdata\[3\]
+port 2582 nsew
+rlabel metal2 s 200376 277380 200376 277380 4 u_riscv_top.core_dmem_wdata\[4\]
+port 2583 nsew
+rlabel metal2 s 242190 257438 242190 257438 4 u_riscv_top.core_dmem_wdata\[5\]
+port 2584 nsew
+rlabel metal2 s 200054 279116 200054 279116 4 u_riscv_top.core_dmem_wdata\[6\]
+port 2585 nsew
+rlabel metal2 s 199870 279388 199870 279388 4 u_riscv_top.core_dmem_wdata\[7\]
+port 2586 nsew
+rlabel metal2 s 199686 279048 199686 279048 4 u_riscv_top.core_dmem_wdata\[8\]
+port 2587 nsew
+rlabel metal2 s 199502 277212 199502 277212 4 u_riscv_top.core_dmem_wdata\[9\]
+port 2588 nsew
+rlabel metal1 s 210220 274550 210220 274550 4 u_riscv_top.core_dmem_width\[0\]
+port 2589 nsew
+rlabel metal1 s 210174 274414 210174 274414 4 u_riscv_top.core_dmem_width\[1\]
+port 2590 nsew
+rlabel metal1 s 153824 272510 153824 272510 4 u_riscv_top.core_icache_addr\[0\]
+port 2591 nsew
+rlabel metal2 s 152582 275138 152582 275138 4 u_riscv_top.core_icache_addr\[10\]
+port 2592 nsew
+rlabel metal2 s 152398 277110 152398 277110 4 u_riscv_top.core_icache_addr\[11\]
+port 2593 nsew
+rlabel metal1 s 156538 273054 156538 273054 4 u_riscv_top.core_icache_addr\[12\]
+port 2594 nsew
+rlabel metal2 s 152030 277144 152030 277144 4 u_riscv_top.core_icache_addr\[13\]
+port 2595 nsew
+rlabel metal2 s 151846 276430 151846 276430 4 u_riscv_top.core_icache_addr\[14\]
+port 2596 nsew
+rlabel metal2 s 151662 274934 151662 274934 4 u_riscv_top.core_icache_addr\[15\]
+port 2597 nsew
+rlabel metal1 s 154008 277746 154008 277746 4 u_riscv_top.core_icache_addr\[16\]
+port 2598 nsew
+rlabel metal2 s 151294 274968 151294 274968 4 u_riscv_top.core_icache_addr\[17\]
+port 2599 nsew
+rlabel metal2 s 151110 278266 151110 278266 4 u_riscv_top.core_icache_addr\[18\]
+port 2600 nsew
+rlabel metal2 s 150926 276396 150926 276396 4 u_riscv_top.core_icache_addr\[19\]
+port 2601 nsew
+rlabel metal1 s 196604 258230 196604 258230 4 u_riscv_top.core_icache_addr\[1\]
+port 2602 nsew
+rlabel metal2 s 150742 277076 150742 277076 4 u_riscv_top.core_icache_addr\[20\]
+port 2603 nsew
+rlabel metal2 s 192234 270149 192234 270149 4 u_riscv_top.core_icache_addr\[21\]
+port 2604 nsew
+rlabel metal2 s 150374 277008 150374 277008 4 u_riscv_top.core_icache_addr\[22\]
+port 2605 nsew
+rlabel metal1 s 150420 277406 150420 277406 4 u_riscv_top.core_icache_addr\[23\]
+port 2606 nsew
+rlabel metal1 s 152720 277814 152720 277814 4 u_riscv_top.core_icache_addr\[24\]
+port 2607 nsew
+rlabel metal1 s 151248 277542 151248 277542 4 u_riscv_top.core_icache_addr\[25\]
+port 2608 nsew
+rlabel metal1 s 151064 277474 151064 277474 4 u_riscv_top.core_icache_addr\[26\]
+port 2609 nsew
+rlabel metal2 s 191130 268075 191130 268075 4 u_riscv_top.core_icache_addr\[27\]
+port 2610 nsew
+rlabel metal2 s 191222 257710 191222 257710 4 u_riscv_top.core_icache_addr\[28\]
+port 2611 nsew
+rlabel metal2 s 149086 274322 149086 274322 4 u_riscv_top.core_icache_addr\[29\]
+port 2612 nsew
+rlabel metal1 s 154560 277406 154560 277406 4 u_riscv_top.core_icache_addr\[2\]
+port 2613 nsew
+rlabel metal2 s 148902 274220 148902 274220 4 u_riscv_top.core_icache_addr\[30\]
+port 2614 nsew
+rlabel metal1 s 148258 272510 148258 272510 4 u_riscv_top.core_icache_addr\[31\]
+port 2615 nsew
+rlabel metal1 s 195362 263602 195362 263602 4 u_riscv_top.core_icache_addr\[3\]
+port 2616 nsew
+rlabel metal2 s 153686 276498 153686 276498 4 u_riscv_top.core_icache_addr\[4\]
+port 2617 nsew
+rlabel metal2 s 153502 275648 153502 275648 4 u_riscv_top.core_icache_addr\[5\]
+port 2618 nsew
+rlabel metal2 s 194994 269503 194994 269503 4 u_riscv_top.core_icache_addr\[6\]
+port 2619 nsew
+rlabel metal2 s 195914 270863 195914 270863 4 u_riscv_top.core_icache_addr\[7\]
+port 2620 nsew
+rlabel metal1 s 154284 277678 154284 277678 4 u_riscv_top.core_icache_addr\[8\]
+port 2621 nsew
+rlabel metal1 s 154008 277610 154008 277610 4 u_riscv_top.core_icache_addr\[9\]
+port 2622 nsew
+rlabel metal1 s 155894 277542 155894 277542 4 u_riscv_top.core_icache_bl\[0\]
+port 2623 nsew
+rlabel metal2 s 196742 256282 196742 256282 4 u_riscv_top.core_icache_bl\[1\]
+port 2624 nsew
+rlabel metal2 s 196558 256282 196558 256282 4 u_riscv_top.core_icache_bl\[2\]
+port 2625 nsew
+rlabel metal1 s 148212 272578 148212 272578 4 u_riscv_top.core_icache_cmd
+port 2626 nsew
+rlabel metal1 s 202032 259250 202032 259250 4 u_riscv_top.core_icache_rdata\[0\]
+port 2627 nsew
+rlabel metal2 s 201342 265190 201342 265190 4 u_riscv_top.core_icache_rdata\[10\]
+port 2628 nsew
+rlabel metal1 s 200836 262922 200836 262922 4 u_riscv_top.core_icache_rdata\[11\]
+port 2629 nsew
+rlabel metal1 s 199456 259046 199456 259046 4 u_riscv_top.core_icache_rdata\[12\]
+port 2630 nsew
+rlabel metal2 s 200790 256979 200790 256979 4 u_riscv_top.core_icache_rdata\[13\]
+port 2631 nsew
+rlabel metal1 s 159712 272646 159712 272646 4 u_riscv_top.core_icache_rdata\[14\]
+port 2632 nsew
+rlabel metal1 s 199272 258230 199272 258230 4 u_riscv_top.core_icache_rdata\[15\]
+port 2633 nsew
+rlabel metal2 s 200238 259739 200238 259739 4 u_riscv_top.core_icache_rdata\[16\]
+port 2634 nsew
+rlabel metal1 s 198352 259250 198352 259250 4 u_riscv_top.core_icache_rdata\[17\]
+port 2635 nsew
+rlabel metal1 s 160080 272306 160080 272306 4 u_riscv_top.core_icache_rdata\[18\]
+port 2636 nsew
+rlabel metal1 s 180320 271082 180320 271082 4 u_riscv_top.core_icache_rdata\[19\]
+port 2637 nsew
+rlabel metal1 s 160632 272442 160632 272442 4 u_riscv_top.core_icache_rdata\[1\]
+port 2638 nsew
+rlabel metal2 s 199502 256112 199502 256112 4 u_riscv_top.core_icache_rdata\[20\]
+port 2639 nsew
+rlabel metal2 s 199318 257268 199318 257268 4 u_riscv_top.core_icache_rdata\[21\]
+port 2640 nsew
+rlabel metal2 s 199134 257200 199134 257200 4 u_riscv_top.core_icache_rdata\[22\]
+port 2641 nsew
+rlabel metal1 s 199364 262718 199364 262718 4 u_riscv_top.core_icache_rdata\[23\]
+port 2642 nsew
+rlabel metal1 s 198996 262922 198996 262922 4 u_riscv_top.core_icache_rdata\[24\]
+port 2643 nsew
+rlabel metal1 s 156308 272510 156308 272510 4 u_riscv_top.core_icache_rdata\[25\]
+port 2644 nsew
+rlabel metal1 s 198076 258434 198076 258434 4 u_riscv_top.core_icache_rdata\[26\]
+port 2645 nsew
+rlabel metal2 s 198214 257234 198214 257234 4 u_riscv_top.core_icache_rdata\[27\]
+port 2646 nsew
+rlabel metal1 s 197754 262718 197754 262718 4 u_riscv_top.core_icache_rdata\[28\]
+port 2647 nsew
+rlabel metal2 s 197846 256282 197846 256282 4 u_riscv_top.core_icache_rdata\[29\]
+port 2648 nsew
+rlabel metal2 s 202814 259739 202814 259739 4 u_riscv_top.core_icache_rdata\[2\]
+port 2649 nsew
+rlabel metal2 s 197662 257540 197662 257540 4 u_riscv_top.core_icache_rdata\[30\]
+port 2650 nsew
+rlabel metal1 s 197984 262514 197984 262514 4 u_riscv_top.core_icache_rdata\[31\]
+port 2651 nsew
+rlabel metal1 s 160402 272510 160402 272510 4 u_riscv_top.core_icache_rdata\[3\]
+port 2652 nsew
+rlabel metal1 s 160402 272238 160402 272238 4 u_riscv_top.core_icache_rdata\[4\]
+port 2653 nsew
+rlabel metal2 s 192878 278018 192878 278018 4 u_riscv_top.core_icache_rdata\[5\]
+port 2654 nsew
+rlabel metal2 s 160264 272612 160264 272612 4 u_riscv_top.core_icache_rdata\[6\]
+port 2655 nsew
+rlabel metal2 s 194258 275502 194258 275502 4 u_riscv_top.core_icache_rdata\[7\]
+port 2656 nsew
+rlabel metal2 s 201710 257370 201710 257370 4 u_riscv_top.core_icache_rdata\[8\]
+port 2657 nsew
+rlabel metal1 s 195454 278154 195454 278154 4 u_riscv_top.core_icache_rdata\[9\]
+port 2658 nsew
+rlabel metal2 s 148258 257737 148258 257737 4 u_riscv_top.core_icache_req
+port 2659 nsew
+rlabel metal1 s 149638 272442 149638 272442 4 u_riscv_top.core_icache_req_ack
+port 2660 nsew
+rlabel metal2 s 203550 257302 203550 257302 4 u_riscv_top.core_icache_resp\[0\]
+port 2661 nsew
+rlabel metal2 s 195178 278392 195178 278392 4 u_riscv_top.core_icache_resp\[1\]
+port 2662 nsew
+rlabel metal2 s 197294 257336 197294 257336 4 u_riscv_top.core_icache_width\[0\]
+port 2663 nsew
+rlabel metal2 s 154882 271388 154882 271388 4 u_riscv_top.core_icache_width\[1\]
+port 2664 nsew
+rlabel metal1 s 133538 313310 133538 313310 4 u_riscv_top.cpu_core_rst_n\[0\]
+port 2665 nsew
+rlabel metal2 s 369150 482834 369150 482834 4 u_riscv_top.cpu_core_rst_n\[1\]
+port 2666 nsew
+rlabel metal2 s 368092 483548 368092 483548 4 u_riscv_top.cpu_core_rst_n\[2\]
+port 2667 nsew
+rlabel metal2 s 368230 484364 368230 484364 4 u_riscv_top.cpu_core_rst_n\[3\]
+port 2668 nsew
+rlabel metal2 s 229678 489209 229678 489209 4 u_riscv_top.cpu_intf_rst_n
+port 2669 nsew
+rlabel metal4 s 46086 25788 46086 25788 4 u_riscv_top.dcache_mem_addr0\[0\]
+port 2670 nsew
+rlabel metal4 s 47174 25856 47174 25856 4 u_riscv_top.dcache_mem_addr0\[1\]
+port 2671 nsew
+rlabel metal3 s 29391 54196 29391 54196 4 u_riscv_top.dcache_mem_addr0\[2\]
+port 2672 nsew
+rlabel metal3 s 29437 55964 29437 55964 4 u_riscv_top.dcache_mem_addr0\[3\]
+port 2673 nsew
+rlabel metal3 s 28655 57052 28655 57052 4 u_riscv_top.dcache_mem_addr0\[4\]
+port 2674 nsew
+rlabel metal3 s 29345 58820 29345 58820 4 u_riscv_top.dcache_mem_addr0\[5\]
+port 2675 nsew
+rlabel metal3 s 28701 59772 28701 59772 4 u_riscv_top.dcache_mem_addr0\[6\]
+port 2676 nsew
+rlabel metal3 s 29529 61948 29529 61948 4 u_riscv_top.dcache_mem_addr0\[7\]
+port 2677 nsew
+rlabel metal2 s 180642 124610 180642 124610 4 u_riscv_top.dcache_mem_addr0\[8\]
+port 2678 nsew
+rlabel metal2 s 180550 145282 180550 145282 4 u_riscv_top.dcache_mem_addr1\[0\]
+port 2679 nsew
+rlabel metal1 s 185518 172618 185518 172618 4 u_riscv_top.dcache_mem_addr1\[1\]
+port 2680 nsew
+rlabel metal2 s 176134 108358 176134 108358 4 u_riscv_top.dcache_mem_addr1\[2\]
+port 2681 nsew
+rlabel metal2 s 174846 107746 174846 107746 4 u_riscv_top.dcache_mem_addr1\[3\]
+port 2682 nsew
+rlabel metal2 s 176042 106998 176042 106998 4 u_riscv_top.dcache_mem_addr1\[4\]
+port 2683 nsew
+rlabel metal2 s 180366 106352 180366 106352 4 u_riscv_top.dcache_mem_addr1\[5\]
+port 2684 nsew
+rlabel metal3 s 166903 39638 166903 39638 4 u_riscv_top.dcache_mem_addr1\[6\]
+port 2685 nsew
+rlabel metal4 s 153254 25924 153254 25924 4 u_riscv_top.dcache_mem_addr1\[7\]
+port 2686 nsew
+rlabel metal4 s 153390 25856 153390 25856 4 u_riscv_top.dcache_mem_addr1\[8\]
+port 2687 nsew
+rlabel metal3 s 28793 34340 28793 34340 4 u_riscv_top.dcache_mem_clk0
+port 2688 nsew
+rlabel metal4 s 160870 109526 160870 109526 4 u_riscv_top.dcache_mem_clk1
+port 2689 nsew
+rlabel metal3 s 28405 34068 28405 34068 4 u_riscv_top.dcache_mem_csb0
+port 2690 nsew
+rlabel metal3 s 166903 105190 166903 105190 4 u_riscv_top.dcache_mem_csb1
+port 2691 nsew
+rlabel metal2 s 175030 79526 175030 79526 4 u_riscv_top.dcache_mem_din0\[0\]
+port 2692 nsew
+rlabel metal4 s 64582 25856 64582 25856 4 u_riscv_top.dcache_mem_din0\[10\]
+port 2693 nsew
+rlabel metal2 s 176502 80920 176502 80920 4 u_riscv_top.dcache_mem_din0\[11\]
+port 2694 nsew
+rlabel metal4 s 67030 25788 67030 25788 4 u_riscv_top.dcache_mem_din0\[12\]
+port 2695 nsew
+rlabel metal4 s 68118 25856 68118 25856 4 u_riscv_top.dcache_mem_din0\[13\]
+port 2696 nsew
+rlabel metal4 s 69478 25788 69478 25788 4 u_riscv_top.dcache_mem_din0\[14\]
+port 2697 nsew
+rlabel metal4 s 70702 25788 70702 25788 4 u_riscv_top.dcache_mem_din0\[15\]
+port 2698 nsew
+rlabel metal4 s 71790 25788 71790 25788 4 u_riscv_top.dcache_mem_din0\[16\]
+port 2699 nsew
+rlabel metal4 s 72878 25856 72878 25856 4 u_riscv_top.dcache_mem_din0\[17\]
+port 2700 nsew
+rlabel metal4 s 73966 25788 73966 25788 4 u_riscv_top.dcache_mem_din0\[18\]
+port 2701 nsew
+rlabel metal4 s 75326 25788 75326 25788 4 u_riscv_top.dcache_mem_din0\[19\]
+port 2702 nsew
+rlabel metal4 s 54246 25788 54246 25788 4 u_riscv_top.dcache_mem_din0\[1\]
+port 2703 nsew
+rlabel metal4 s 76414 25788 76414 25788 4 u_riscv_top.dcache_mem_din0\[20\]
+port 2704 nsew
+rlabel metal4 s 77638 25788 77638 25788 4 u_riscv_top.dcache_mem_din0\[21\]
+port 2705 nsew
+rlabel metal4 s 78726 25788 78726 25788 4 u_riscv_top.dcache_mem_din0\[22\]
+port 2706 nsew
+rlabel metal4 s 79814 25788 79814 25788 4 u_riscv_top.dcache_mem_din0\[23\]
+port 2707 nsew
+rlabel metal4 s 81174 25788 81174 25788 4 u_riscv_top.dcache_mem_din0\[24\]
+port 2708 nsew
+rlabel metal4 s 82262 25924 82262 25924 4 u_riscv_top.dcache_mem_din0\[25\]
+port 2709 nsew
+rlabel metal4 s 83350 25924 83350 25924 4 u_riscv_top.dcache_mem_din0\[26\]
+port 2710 nsew
+rlabel metal2 s 176226 80682 176226 80682 4 u_riscv_top.dcache_mem_din0\[27\]
+port 2711 nsew
+rlabel metal2 s 173374 81328 173374 81328 4 u_riscv_top.dcache_mem_din0\[28\]
+port 2712 nsew
+rlabel metal2 s 173466 81294 173466 81294 4 u_riscv_top.dcache_mem_din0\[29\]
+port 2713 nsew
+rlabel metal4 s 55470 25788 55470 25788 4 u_riscv_top.dcache_mem_din0\[2\]
+port 2714 nsew
+rlabel metal4 s 88110 25788 88110 25788 4 u_riscv_top.dcache_mem_din0\[30\]
+port 2715 nsew
+rlabel metal4 s 89198 25788 89198 25788 4 u_riscv_top.dcache_mem_din0\[31\]
+port 2716 nsew
+rlabel metal4 s 56558 25788 56558 25788 4 u_riscv_top.dcache_mem_din0\[3\]
+port 2717 nsew
+rlabel metal4 s 57646 25788 57646 25788 4 u_riscv_top.dcache_mem_din0\[4\]
+port 2718 nsew
+rlabel metal4 s 58734 25788 58734 25788 4 u_riscv_top.dcache_mem_din0\[5\]
+port 2719 nsew
+rlabel metal4 s 60094 25788 60094 25788 4 u_riscv_top.dcache_mem_din0\[6\]
+port 2720 nsew
+rlabel metal4 s 61318 25788 61318 25788 4 u_riscv_top.dcache_mem_din0\[7\]
+port 2721 nsew
+rlabel metal4 s 62406 25788 62406 25788 4 u_riscv_top.dcache_mem_din0\[8\]
+port 2722 nsew
+rlabel metal4 s 63494 25856 63494 25856 4 u_riscv_top.dcache_mem_din0\[9\]
+port 2723 nsew
+rlabel metal4 s 58326 25788 58326 25788 4 u_riscv_top.dcache_mem_dout0\[0\]
+port 2724 nsew
+rlabel metal4 s 83622 25788 83622 25788 4 u_riscv_top.dcache_mem_dout0\[10\]
+port 2725 nsew
+rlabel metal2 s 178802 87448 178802 87448 4 u_riscv_top.dcache_mem_dout0\[11\]
+port 2726 nsew
+rlabel metal2 s 180182 87482 180182 87482 4 u_riscv_top.dcache_mem_dout0\[12\]
+port 2727 nsew
+rlabel metal4 s 90966 25788 90966 25788 4 u_riscv_top.dcache_mem_dout0\[13\]
+port 2728 nsew
+rlabel metal2 s 180274 87414 180274 87414 4 u_riscv_top.dcache_mem_dout0\[14\]
+port 2729 nsew
+rlabel metal4 s 95998 25788 95998 25788 4 u_riscv_top.dcache_mem_dout0\[15\]
+port 2730 nsew
+rlabel metal4 s 98310 25788 98310 25788 4 u_riscv_top.dcache_mem_dout0\[16\]
+port 2731 nsew
+rlabel metal4 s 101030 25788 101030 25788 4 u_riscv_top.dcache_mem_dout0\[17\]
+port 2732 nsew
+rlabel metal4 s 103478 25788 103478 25788 4 u_riscv_top.dcache_mem_dout0\[18\]
+port 2733 nsew
+rlabel metal2 s 133630 23290 133630 23290 4 u_riscv_top.dcache_mem_dout0\[19\]
+port 2734 nsew
+rlabel metal4 s 60774 25856 60774 25856 4 u_riscv_top.dcache_mem_dout0\[1\]
+port 2735 nsew
+rlabel metal4 s 108510 25788 108510 25788 4 u_riscv_top.dcache_mem_dout0\[20\]
+port 2736 nsew
+rlabel metal2 s 174662 88808 174662 88808 4 u_riscv_top.dcache_mem_dout0\[21\]
+port 2737 nsew
+rlabel metal4 s 113542 25788 113542 25788 4 u_riscv_top.dcache_mem_dout0\[22\]
+port 2738 nsew
+rlabel metal4 s 115990 25788 115990 25788 4 u_riscv_top.dcache_mem_dout0\[23\]
+port 2739 nsew
+rlabel metal4 s 118574 25788 118574 25788 4 u_riscv_top.dcache_mem_dout0\[24\]
+port 2740 nsew
+rlabel metal4 s 121022 25788 121022 25788 4 u_riscv_top.dcache_mem_dout0\[25\]
+port 2741 nsew
+rlabel metal4 s 123470 25788 123470 25788 4 u_riscv_top.dcache_mem_dout0\[26\]
+port 2742 nsew
+rlabel metal4 s 125918 25788 125918 25788 4 u_riscv_top.dcache_mem_dout0\[27\]
+port 2743 nsew
+rlabel metal4 s 128502 25788 128502 25788 4 u_riscv_top.dcache_mem_dout0\[28\]
+port 2744 nsew
+rlabel metal4 s 130950 25924 130950 25924 4 u_riscv_top.dcache_mem_dout0\[29\]
+port 2745 nsew
+rlabel metal4 s 63630 25788 63630 25788 4 u_riscv_top.dcache_mem_dout0\[2\]
+port 2746 nsew
+rlabel metal4 s 133398 25788 133398 25788 4 u_riscv_top.dcache_mem_dout0\[30\]
+port 2747 nsew
+rlabel metal4 s 135982 25788 135982 25788 4 u_riscv_top.dcache_mem_dout0\[31\]
+port 2748 nsew
+rlabel metal4 s 66078 25856 66078 25856 4 u_riscv_top.dcache_mem_dout0\[3\]
+port 2749 nsew
+rlabel metal4 s 68526 25788 68526 25788 4 u_riscv_top.dcache_mem_dout0\[4\]
+port 2750 nsew
+rlabel metal4 s 180044 86836 180044 86836 4 u_riscv_top.dcache_mem_dout0\[5\]
+port 2751 nsew
+rlabel metal2 s 174754 87329 174754 87329 4 u_riscv_top.dcache_mem_dout0\[6\]
+port 2752 nsew
+rlabel metal4 s 76006 25788 76006 25788 4 u_riscv_top.dcache_mem_dout0\[7\]
+port 2753 nsew
+rlabel metal4 s 78318 25788 78318 25788 4 u_riscv_top.dcache_mem_dout0\[8\]
+port 2754 nsew
+rlabel metal4 s 81038 25788 81038 25788 4 u_riscv_top.dcache_mem_dout0\[9\]
+port 2755 nsew
+rlabel metal4 s 58734 109526 58734 109526 4 u_riscv_top.dcache_mem_dout1\[0\]
+port 2756 nsew
+rlabel metal4 s 83622 109526 83622 109526 4 u_riscv_top.dcache_mem_dout1\[10\]
+port 2757 nsew
+rlabel metal2 s 176594 150076 176594 150076 4 u_riscv_top.dcache_mem_dout1\[11\]
+port 2758 nsew
+rlabel metal2 s 177514 162554 177514 162554 4 u_riscv_top.dcache_mem_dout1\[12\]
+port 2759 nsew
+rlabel metal4 s 90966 109526 90966 109526 4 u_riscv_top.dcache_mem_dout1\[13\]
+port 2760 nsew
+rlabel metal4 s 93686 109526 93686 109526 4 u_riscv_top.dcache_mem_dout1\[14\]
+port 2761 nsew
+rlabel metal4 s 96134 109526 96134 109526 4 u_riscv_top.dcache_mem_dout1\[15\]
+port 2762 nsew
+rlabel metal4 s 98582 109526 98582 109526 4 u_riscv_top.dcache_mem_dout1\[16\]
+port 2763 nsew
+rlabel metal4 s 101030 109526 101030 109526 4 u_riscv_top.dcache_mem_dout1\[17\]
+port 2764 nsew
+rlabel metal2 s 174938 165274 174938 165274 4 u_riscv_top.dcache_mem_dout1\[18\]
+port 2765 nsew
+rlabel metal1 s 138552 120734 138552 120734 4 u_riscv_top.dcache_mem_dout1\[19\]
+port 2766 nsew
+rlabel metal4 s 61046 109526 61046 109526 4 u_riscv_top.dcache_mem_dout1\[1\]
+port 2767 nsew
+rlabel metal2 s 180642 160514 180642 160514 4 u_riscv_top.dcache_mem_dout1\[20\]
+port 2768 nsew
+rlabel metal2 s 177606 161194 177606 161194 4 u_riscv_top.dcache_mem_dout1\[21\]
+port 2769 nsew
+rlabel metal4 s 113542 109526 113542 109526 4 u_riscv_top.dcache_mem_dout1\[22\]
+port 2770 nsew
+rlabel metal4 s 115990 109526 115990 109526 4 u_riscv_top.dcache_mem_dout1\[23\]
+port 2771 nsew
+rlabel metal4 s 118438 109526 118438 109526 4 u_riscv_top.dcache_mem_dout1\[24\]
+port 2772 nsew
+rlabel metal4 s 121022 109526 121022 109526 4 u_riscv_top.dcache_mem_dout1\[25\]
+port 2773 nsew
+rlabel metal4 s 123606 109526 123606 109526 4 u_riscv_top.dcache_mem_dout1\[26\]
+port 2774 nsew
+rlabel metal4 s 126054 109526 126054 109526 4 u_riscv_top.dcache_mem_dout1\[27\]
+port 2775 nsew
+rlabel metal2 s 172362 158440 172362 158440 4 u_riscv_top.dcache_mem_dout1\[28\]
+port 2776 nsew
+rlabel metal2 s 180458 168028 180458 168028 4 u_riscv_top.dcache_mem_dout1\[29\]
+port 2777 nsew
+rlabel metal4 s 63494 109526 63494 109526 4 u_riscv_top.dcache_mem_dout1\[2\]
+port 2778 nsew
+rlabel metal4 s 133398 109526 133398 109526 4 u_riscv_top.dcache_mem_dout1\[30\]
+port 2779 nsew
+rlabel metal4 s 136118 109526 136118 109526 4 u_riscv_top.dcache_mem_dout1\[31\]
+port 2780 nsew
+rlabel metal1 s 118496 115294 118496 115294 4 u_riscv_top.dcache_mem_dout1\[3\]
+port 2781 nsew
+rlabel metal4 s 68526 109526 68526 109526 4 u_riscv_top.dcache_mem_dout1\[4\]
+port 2782 nsew
+rlabel metal2 s 172086 147390 172086 147390 4 u_riscv_top.dcache_mem_dout1\[5\]
+port 2783 nsew
+rlabel metal4 s 73558 109526 73558 109526 4 u_riscv_top.dcache_mem_dout1\[6\]
+port 2784 nsew
+rlabel metal4 s 76142 109526 76142 109526 4 u_riscv_top.dcache_mem_dout1\[7\]
+port 2785 nsew
+rlabel metal4 s 78590 109526 78590 109526 4 u_riscv_top.dcache_mem_dout1\[8\]
+port 2786 nsew
+rlabel metal4 s 81174 109526 81174 109526 4 u_riscv_top.dcache_mem_dout1\[9\]
+port 2787 nsew
+rlabel metal3 s 29483 35972 29483 35972 4 u_riscv_top.dcache_mem_web0
+port 2788 nsew
+rlabel metal2 s 171994 78336 171994 78336 4 u_riscv_top.dcache_mem_wmask0\[0\]
+port 2789 nsew
+rlabel metal2 s 98670 23868 98670 23868 4 u_riscv_top.dcache_mem_wmask0\[1\]
+port 2790 nsew
+rlabel metal2 s 171902 79441 171902 79441 4 u_riscv_top.dcache_mem_wmask0\[2\]
+port 2791 nsew
+rlabel metal4 s 51798 25788 51798 25788 4 u_riscv_top.dcache_mem_wmask0\[3\]
+port 2792 nsew
+rlabel metal2 s 190670 128700 190670 128700 4 u_riscv_top.icache_mem_addr0\[0\]
+port 2793 nsew
+rlabel metal2 s 190946 116779 190946 116779 4 u_riscv_top.icache_mem_addr0\[1\]
+port 2794 nsew
+rlabel metal2 s 191038 120710 191038 120710 4 u_riscv_top.icache_mem_addr0\[2\]
+port 2795 nsew
+rlabel metal2 s 191222 120948 191222 120948 4 u_riscv_top.icache_mem_addr0\[3\]
+port 2796 nsew
+rlabel metal2 s 191406 120540 191406 120540 4 u_riscv_top.icache_mem_addr0\[4\]
+port 2797 nsew
+rlabel metal2 s 191590 121662 191590 121662 4 u_riscv_top.icache_mem_addr0\[5\]
+port 2798 nsew
+rlabel metal2 s 191774 128802 191774 128802 4 u_riscv_top.icache_mem_addr0\[6\]
+port 2799 nsew
+rlabel metal2 s 191958 128292 191958 128292 4 u_riscv_top.icache_mem_addr0\[7\]
+port 2800 nsew
+rlabel metal2 s 192142 128632 192142 128632 4 u_riscv_top.icache_mem_addr0\[8\]
+port 2801 nsew
+rlabel metal2 s 213946 126667 213946 126667 4 u_riscv_top.icache_mem_addr1\[0\]
+port 2802 nsew
+rlabel metal2 s 215234 126208 215234 126208 4 u_riscv_top.icache_mem_addr1\[1\]
+port 2803 nsew
+rlabel metal3 s 326991 45356 326991 45356 4 u_riscv_top.icache_mem_addr1\[2\]
+port 2804 nsew
+rlabel metal3 s 326914 43718 326914 43718 4 u_riscv_top.icache_mem_addr1\[3\]
+port 2805 nsew
+rlabel metal3 s 326945 42364 326945 42364 4 u_riscv_top.icache_mem_addr1\[4\]
+port 2806 nsew
+rlabel metal3 s 327589 40868 327589 40868 4 u_riscv_top.icache_mem_addr1\[5\]
+port 2807 nsew
+rlabel metal3 s 327037 39644 327037 39644 4 u_riscv_top.icache_mem_addr1\[6\]
+port 2808 nsew
+rlabel metal4 s 313254 25788 313254 25788 4 u_riscv_top.icache_mem_addr1\[7\]
+port 2809 nsew
+rlabel metal4 s 313390 25788 313390 25788 4 u_riscv_top.icache_mem_addr1\[8\]
+port 2810 nsew
+rlabel metal3 s 189735 34334 189735 34334 4 u_riscv_top.icache_mem_clk0
+port 2811 nsew
+rlabel metal2 s 210358 128197 210358 128197 4 u_riscv_top.icache_mem_clk1
+port 2812 nsew
+rlabel metal3 s 189735 34062 189735 34062 4 u_riscv_top.icache_mem_csb0
+port 2813 nsew
+rlabel metal2 s 210450 127476 210450 127476 4 u_riscv_top.icache_mem_csb1
+port 2814 nsew
+rlabel metal4 s 213158 25788 213158 25788 4 u_riscv_top.icache_mem_din0\[0\]
+port 2815 nsew
+rlabel metal1 s 195040 123114 195040 123114 4 u_riscv_top.icache_mem_din0\[10\]
+port 2816 nsew
+rlabel metal2 s 195086 120880 195086 120880 4 u_riscv_top.icache_mem_din0\[11\]
+port 2817 nsew
+rlabel metal2 s 195270 120812 195270 120812 4 u_riscv_top.icache_mem_din0\[12\]
+port 2818 nsew
+rlabel metal2 s 195454 129040 195454 129040 4 u_riscv_top.icache_mem_din0\[13\]
+port 2819 nsew
+rlabel metal4 s 229478 25788 229478 25788 4 u_riscv_top.icache_mem_din0\[14\]
+port 2820 nsew
+rlabel metal4 s 230702 25788 230702 25788 4 u_riscv_top.icache_mem_din0\[15\]
+port 2821 nsew
+rlabel metal4 s 231790 25788 231790 25788 4 u_riscv_top.icache_mem_din0\[16\]
+port 2822 nsew
+rlabel metal4 s 232878 25788 232878 25788 4 u_riscv_top.icache_mem_din0\[17\]
+port 2823 nsew
+rlabel metal4 s 233966 25788 233966 25788 4 u_riscv_top.icache_mem_din0\[18\]
+port 2824 nsew
+rlabel metal4 s 235326 25788 235326 25788 4 u_riscv_top.icache_mem_din0\[19\]
+port 2825 nsew
+rlabel metal4 s 214246 25924 214246 25924 4 u_riscv_top.icache_mem_din0\[1\]
+port 2826 nsew
+rlabel metal4 s 236414 25924 236414 25924 4 u_riscv_top.icache_mem_din0\[20\]
+port 2827 nsew
+rlabel metal4 s 237638 25856 237638 25856 4 u_riscv_top.icache_mem_din0\[21\]
+port 2828 nsew
+rlabel metal4 s 238726 25788 238726 25788 4 u_riscv_top.icache_mem_din0\[22\]
+port 2829 nsew
+rlabel metal2 s 197294 120761 197294 120761 4 u_riscv_top.icache_mem_din0\[23\]
+port 2830 nsew
+rlabel metal2 s 197478 129006 197478 129006 4 u_riscv_top.icache_mem_din0\[24\]
+port 2831 nsew
+rlabel metal2 s 180550 68051 180550 68051 4 u_riscv_top.icache_mem_din0\[25\]
+port 2832 nsew
+rlabel metal2 s 197846 120693 197846 120693 4 u_riscv_top.icache_mem_din0\[26\]
+port 2833 nsew
+rlabel metal2 s 198030 120829 198030 120829 4 u_riscv_top.icache_mem_din0\[27\]
+port 2834 nsew
+rlabel metal2 s 179998 68068 179998 68068 4 u_riscv_top.icache_mem_din0\[28\]
+port 2835 nsew
+rlabel metal2 s 198398 120897 198398 120897 4 u_riscv_top.icache_mem_din0\[29\]
+port 2836 nsew
+rlabel metal4 s 215470 25924 215470 25924 4 u_riscv_top.icache_mem_din0\[2\]
+port 2837 nsew
+rlabel metal2 s 180734 75922 180734 75922 4 u_riscv_top.icache_mem_din0\[30\]
+port 2838 nsew
+rlabel metal4 s 249198 25788 249198 25788 4 u_riscv_top.icache_mem_din0\[31\]
+port 2839 nsew
+rlabel metal4 s 216558 25788 216558 25788 4 u_riscv_top.icache_mem_din0\[3\]
+port 2840 nsew
+rlabel metal4 s 217646 25788 217646 25788 4 u_riscv_top.icache_mem_din0\[4\]
+port 2841 nsew
+rlabel metal4 s 218734 25788 218734 25788 4 u_riscv_top.icache_mem_din0\[5\]
+port 2842 nsew
+rlabel metal2 s 177790 69292 177790 69292 4 u_riscv_top.icache_mem_din0\[6\]
+port 2843 nsew
+rlabel metal2 s 179262 69360 179262 69360 4 u_riscv_top.icache_mem_din0\[7\]
+port 2844 nsew
+rlabel metal2 s 175214 69122 175214 69122 4 u_riscv_top.icache_mem_din0\[8\]
+port 2845 nsew
+rlabel metal2 s 176594 68442 176594 68442 4 u_riscv_top.icache_mem_din0\[9\]
+port 2846 nsew
+rlabel metal4 s 218734 109526 218734 109526 4 u_riscv_top.icache_mem_dout1\[0\]
+port 2847 nsew
+rlabel metal1 s 232438 119578 232438 119578 4 u_riscv_top.icache_mem_dout1\[10\]
+port 2848 nsew
+rlabel metal2 s 222226 126089 222226 126089 4 u_riscv_top.icache_mem_dout1\[11\]
+port 2849 nsew
+rlabel metal4 s 248518 109526 248518 109526 4 u_riscv_top.icache_mem_dout1\[12\]
+port 2850 nsew
+rlabel metal4 s 250966 109526 250966 109526 4 u_riscv_top.icache_mem_dout1\[13\]
+port 2851 nsew
+rlabel metal4 s 253686 109526 253686 109526 4 u_riscv_top.icache_mem_dout1\[14\]
+port 2852 nsew
+rlabel metal4 s 256134 109526 256134 109526 4 u_riscv_top.icache_mem_dout1\[15\]
+port 2853 nsew
+rlabel metal1 s 240580 122230 240580 122230 4 u_riscv_top.icache_mem_dout1\[16\]
+port 2854 nsew
+rlabel metal1 s 242052 119510 242052 119510 4 u_riscv_top.icache_mem_dout1\[17\]
+port 2855 nsew
+rlabel metal1 s 243524 120802 243524 120802 4 u_riscv_top.icache_mem_dout1\[18\]
+port 2856 nsew
+rlabel metal1 s 245364 117946 245364 117946 4 u_riscv_top.icache_mem_dout1\[19\]
+port 2857 nsew
+rlabel metal4 s 221046 109526 221046 109526 4 u_riscv_top.icache_mem_dout1\[1\]
+port 2858 nsew
+rlabel metal4 s 268646 109526 268646 109526 4 u_riscv_top.icache_mem_dout1\[20\]
+port 2859 nsew
+rlabel metal4 s 271094 109526 271094 109526 4 u_riscv_top.icache_mem_dout1\[21\]
+port 2860 nsew
+rlabel metal2 s 238050 120428 238050 120428 4 u_riscv_top.icache_mem_dout1\[22\]
+port 2861 nsew
+rlabel metal4 s 275990 109526 275990 109526 4 u_riscv_top.icache_mem_dout1\[23\]
+port 2862 nsew
+rlabel metal2 s 224526 129040 224526 129040 4 u_riscv_top.icache_mem_dout1\[24\]
+port 2863 nsew
+rlabel metal2 s 224710 127544 224710 127544 4 u_riscv_top.icache_mem_dout1\[25\]
+port 2864 nsew
+rlabel metal2 s 224894 129006 224894 129006 4 u_riscv_top.icache_mem_dout1\[26\]
+port 2865 nsew
+rlabel metal2 s 225078 128972 225078 128972 4 u_riscv_top.icache_mem_dout1\[27\]
+port 2866 nsew
+rlabel metal4 s 288502 109526 288502 109526 4 u_riscv_top.icache_mem_dout1\[28\]
+port 2867 nsew
+rlabel metal2 s 249090 120428 249090 120428 4 u_riscv_top.icache_mem_dout1\[29\]
+port 2868 nsew
+rlabel metal4 s 223494 109526 223494 109526 4 u_riscv_top.icache_mem_dout1\[2\]
+port 2869 nsew
+rlabel metal4 s 293398 109526 293398 109526 4 u_riscv_top.icache_mem_dout1\[30\]
+port 2870 nsew
+rlabel metal2 s 250470 120428 250470 120428 4 u_riscv_top.icache_mem_dout1\[31\]
+port 2871 nsew
+rlabel metal4 s 226214 109526 226214 109526 4 u_riscv_top.icache_mem_dout1\[3\]
+port 2872 nsew
+rlabel metal4 s 228526 109526 228526 109526 4 u_riscv_top.icache_mem_dout1\[4\]
+port 2873 nsew
+rlabel metal4 s 231110 109526 231110 109526 4 u_riscv_top.icache_mem_dout1\[5\]
+port 2874 nsew
+rlabel metal4 s 233558 109526 233558 109526 4 u_riscv_top.icache_mem_dout1\[6\]
+port 2875 nsew
+rlabel metal4 s 236142 109526 236142 109526 4 u_riscv_top.icache_mem_dout1\[7\]
+port 2876 nsew
+rlabel metal4 s 238590 109526 238590 109526 4 u_riscv_top.icache_mem_dout1\[8\]
+port 2877 nsew
+rlabel metal2 s 221766 121594 221766 121594 4 u_riscv_top.icache_mem_dout1\[9\]
+port 2878 nsew
+rlabel metal2 s 190486 128836 190486 128836 4 u_riscv_top.icache_mem_web0
+port 2879 nsew
+rlabel metal2 s 180642 69904 180642 69904 4 u_riscv_top.icache_mem_wmask0\[0\]
+port 2880 nsew
+rlabel metal2 s 192510 121730 192510 121730 4 u_riscv_top.icache_mem_wmask0\[1\]
+port 2881 nsew
+rlabel metal4 s 210574 25788 210574 25788 4 u_riscv_top.icache_mem_wmask0\[2\]
+port 2882 nsew
+rlabel metal4 s 211798 25788 211798 25788 4 u_riscv_top.icache_mem_wmask0\[3\]
+port 2883 nsew
+rlabel metal3 s 230414 488597 230414 488597 4 u_riscv_top.irq_lines\[0\]
+port 2884 nsew
+rlabel metal3 s 230322 485877 230322 485877 4 u_riscv_top.irq_lines\[10\]
+port 2885 nsew
+rlabel metal2 s 229494 485333 229494 485333 4 u_riscv_top.irq_lines\[11\]
+port 2886 nsew
+rlabel metal3 s 229862 485299 229862 485299 4 u_riscv_top.irq_lines\[12\]
+port 2887 nsew
+rlabel metal2 s 229862 484721 229862 484721 4 u_riscv_top.irq_lines\[13\]
+port 2888 nsew
+rlabel metal3 s 230046 484755 230046 484755 4 u_riscv_top.irq_lines\[14\]
+port 2889 nsew
+rlabel metal2 s 230322 480675 230322 480675 4 u_riscv_top.irq_lines\[15\]
+port 2890 nsew
+rlabel metal2 s 229494 483667 229494 483667 4 u_riscv_top.irq_lines\[16\]
+port 2891 nsew
+rlabel metal2 s 229678 483497 229678 483497 4 u_riscv_top.irq_lines\[17\]
+port 2892 nsew
+rlabel metal2 s 230046 479587 230046 479587 4 u_riscv_top.irq_lines\[18\]
+port 2893 nsew
+rlabel metal3 s 230414 483395 230414 483395 4 u_riscv_top.irq_lines\[19\]
+port 2894 nsew
+rlabel metal2 s 229678 488087 229678 488087 4 u_riscv_top.irq_lines\[1\]
+port 2895 nsew
+rlabel metal2 s 230230 479349 230230 479349 4 u_riscv_top.irq_lines\[20\]
+port 2896 nsew
+rlabel metal2 s 229494 482273 229494 482273 4 u_riscv_top.irq_lines\[21\]
+port 2897 nsew
+rlabel metal3 s 229678 482579 229678 482579 4 u_riscv_top.irq_lines\[22\]
+port 2898 nsew
+rlabel metal2 s 229770 481984 229770 481984 4 u_riscv_top.irq_lines\[23\]
+port 2899 nsew
+rlabel metal2 s 229862 481933 229862 481933 4 u_riscv_top.irq_lines\[24\]
+port 2900 nsew
+rlabel metal2 s 229218 480709 229218 480709 4 u_riscv_top.irq_lines\[25\]
+port 2901 nsew
+rlabel metal2 s 229954 481185 229954 481185 4 u_riscv_top.irq_lines\[26\]
+port 2902 nsew
+rlabel metal2 s 229494 480369 229494 480369 4 u_riscv_top.irq_lines\[27\]
+port 2903 nsew
+rlabel metal2 s 229770 480845 229770 480845 4 u_riscv_top.irq_lines\[28\]
+port 2904 nsew
+rlabel metal3 s 230414 480675 230414 480675 4 u_riscv_top.irq_lines\[29\]
+port 2905 nsew
+rlabel metal2 s 229586 487781 229586 487781 4 u_riscv_top.irq_lines\[2\]
+port 2906 nsew
+rlabel metal2 s 367126 450891 367126 450891 4 u_riscv_top.irq_lines\[30\]
+port 2907 nsew
+rlabel metal2 s 367218 450789 367218 450789 4 u_riscv_top.irq_lines\[31\]
+port 2908 nsew
+rlabel metal3 s 229678 487747 229678 487747 4 u_riscv_top.irq_lines\[3\]
+port 2909 nsew
+rlabel metal2 s 229402 484075 229402 484075 4 u_riscv_top.irq_lines\[4\]
+port 2910 nsew
+rlabel metal3 s 230414 487203 230414 487203 4 u_riscv_top.irq_lines\[5\]
+port 2911 nsew
+rlabel metal2 s 230414 486387 230414 486387 4 u_riscv_top.irq_lines\[6\]
+port 2912 nsew
+rlabel metal2 s 229586 483458 229586 483458 4 u_riscv_top.irq_lines\[7\]
+port 2913 nsew
+rlabel metal2 s 229862 486183 229862 486183 4 u_riscv_top.irq_lines\[8\]
+port 2914 nsew
+rlabel metal2 s 230138 482205 230138 482205 4 u_riscv_top.irq_lines\[9\]
+port 2915 nsew
+rlabel metal1 s 134550 619446 134550 619446 4 u_riscv_top.pwrup_rst_n
+port 2916 nsew
+rlabel metal4 s 347875 3060 347875 3060 4 u_riscv_top.riscv_debug\[0\]
+port 2917 nsew
+rlabel metal2 s 210496 275196 210496 275196 4 u_riscv_top.riscv_debug\[10\]
+port 2918 nsew
+rlabel metal1 s 210358 275298 210358 275298 4 u_riscv_top.riscv_debug\[11\]
+port 2919 nsew
+rlabel metal3 s 367609 18292 367609 18292 4 u_riscv_top.riscv_debug\[12\]
+port 2920 nsew
+rlabel metal3 s 367609 18428 367609 18428 4 u_riscv_top.riscv_debug\[13\]
+port 2921 nsew
+rlabel metal3 s 350313 17612 350313 17612 4 u_riscv_top.riscv_debug\[14\]
+port 2922 nsew
+rlabel metal2 s 211278 279116 211278 279116 4 u_riscv_top.riscv_debug\[15\]
+port 2923 nsew
+rlabel metal4 s 364872 21420 364872 21420 4 u_riscv_top.riscv_debug\[16\]
+port 2924 nsew
+rlabel metal2 s 211600 277380 211600 277380 4 u_riscv_top.riscv_debug\[17\]
+port 2925 nsew
+rlabel metal2 s 218546 278120 218546 278120 4 u_riscv_top.riscv_debug\[18\]
+port 2926 nsew
+rlabel metal3 s 368897 18292 368897 18292 4 u_riscv_top.riscv_debug\[19\]
+port 2927 nsew
+rlabel metal4 s 367724 136884 367724 136884 4 u_riscv_top.riscv_debug\[1\]
+port 2928 nsew
+rlabel metal3 s 212313 278460 212313 278460 4 u_riscv_top.riscv_debug\[20\]
+port 2929 nsew
+rlabel metal3 s 350290 17068 350290 17068 4 u_riscv_top.riscv_debug\[21\]
+port 2930 nsew
+rlabel metal2 s 212566 279133 212566 279133 4 u_riscv_top.riscv_debug\[22\]
+port 2931 nsew
+rlabel metal3 s 362411 18564 362411 18564 4 u_riscv_top.riscv_debug\[23\]
+port 2932 nsew
+rlabel metal3 s 218316 278392 218316 278392 4 u_riscv_top.riscv_debug\[24\]
+port 2933 nsew
+rlabel metal3 s 368943 18428 368943 18428 4 u_riscv_top.riscv_debug\[25\]
+port 2934 nsew
+rlabel metal2 s 213302 279065 213302 279065 4 u_riscv_top.riscv_debug\[26\]
+port 2935 nsew
+rlabel metal2 s 349922 136493 349922 136493 4 u_riscv_top.riscv_debug\[27\]
+port 2936 nsew
+rlabel metal4 s 213693 278596 213693 278596 4 u_riscv_top.riscv_debug\[28\]
+port 2937 nsew
+rlabel metal2 s 347070 256088 347070 256088 4 u_riscv_top.riscv_debug\[29\]
+port 2938 nsew
+rlabel metal4 s 365056 20740 365056 20740 4 u_riscv_top.riscv_debug\[2\]
+port 2939 nsew
+rlabel metal4 s 348427 3060 348427 3060 4 u_riscv_top.riscv_debug\[30\]
+port 2940 nsew
+rlabel metal2 s 214222 279150 214222 279150 4 u_riscv_top.riscv_debug\[31\]
+port 2941 nsew
+rlabel metal3 s 367609 18156 367609 18156 4 u_riscv_top.riscv_debug\[32\]
+port 2942 nsew
+rlabel metal2 s 348542 138839 348542 138839 4 u_riscv_top.riscv_debug\[33\]
+port 2943 nsew
+rlabel metal2 s 214774 279184 214774 279184 4 u_riscv_top.riscv_debug\[34\]
+port 2944 nsew
+rlabel metal2 s 351946 256139 351946 256139 4 u_riscv_top.riscv_debug\[35\]
+port 2945 nsew
+rlabel metal2 s 215142 279218 215142 279218 4 u_riscv_top.riscv_debug\[36\]
+port 2946 nsew
+rlabel metal3 s 218132 278528 218132 278528 4 u_riscv_top.riscv_debug\[37\]
+port 2947 nsew
+rlabel metal4 s 366597 18428 366597 18428 4 u_riscv_top.riscv_debug\[38\]
+port 2948 nsew
+rlabel metal3 s 366321 18428 366321 18428 4 u_riscv_top.riscv_debug\[39\]
+port 2949 nsew
+rlabel metal2 s 348634 140216 348634 140216 4 u_riscv_top.riscv_debug\[3\]
+port 2950 nsew
+rlabel metal3 s 347047 3060 347047 3060 4 u_riscv_top.riscv_debug\[40\]
+port 2951 nsew
+rlabel metal2 s 216062 279252 216062 279252 4 u_riscv_top.riscv_debug\[41\]
+port 2952 nsew
+rlabel metal2 s 348726 138091 348726 138091 4 u_riscv_top.riscv_debug\[42\]
+port 2953 nsew
+rlabel metal3 s 407146 2363 407146 2363 4 u_riscv_top.riscv_debug\[43\]
+port 2954 nsew
+rlabel metal3 s 216545 278596 216545 278596 4 u_riscv_top.riscv_debug\[44\]
+port 2955 nsew
+rlabel metal2 s 216844 277380 216844 277380 4 u_riscv_top.riscv_debug\[45\]
+port 2956 nsew
+rlabel metal2 s 368138 183345 368138 183345 4 u_riscv_top.riscv_debug\[46\]
+port 2957 nsew
+rlabel metal2 s 367770 185232 367770 185232 4 u_riscv_top.riscv_debug\[47\]
+port 2958 nsew
+rlabel metal3 s 217649 278596 217649 278596 4 u_riscv_top.riscv_debug\[48\]
+port 2959 nsew
+rlabel metal2 s 217534 279048 217534 279048 4 u_riscv_top.riscv_debug\[49\]
+port 2960 nsew
+rlabel metal2 s 365010 184756 365010 184756 4 u_riscv_top.riscv_debug\[4\]
+port 2961 nsew
+rlabel metal2 s 217718 279422 217718 279422 4 u_riscv_top.riscv_debug\[50\]
+port 2962 nsew
+rlabel metal2 s 217902 279456 217902 279456 4 u_riscv_top.riscv_debug\[51\]
+port 2963 nsew
+rlabel metal3 s 376257 19788 376257 19788 4 u_riscv_top.riscv_debug\[52\]
+port 2964 nsew
+rlabel metal2 s 218224 277380 218224 277380 4 u_riscv_top.riscv_debug\[53\]
+port 2965 nsew
+rlabel metal3 s 371887 19788 371887 19788 4 u_riscv_top.riscv_debug\[54\]
+port 2966 nsew
+rlabel metal2 s 365378 185215 365378 185215 4 u_riscv_top.riscv_debug\[55\]
+port 2967 nsew
+rlabel metal2 s 218776 277380 218776 277380 4 u_riscv_top.riscv_debug\[56\]
+port 2968 nsew
+rlabel metal2 s 359582 186660 359582 186660 4 u_riscv_top.riscv_debug\[57\]
+port 2969 nsew
+rlabel metal2 s 219190 279082 219190 279082 4 u_riscv_top.riscv_debug\[58\]
+port 2970 nsew
+rlabel metal2 s 219236 277380 219236 277380 4 u_riscv_top.riscv_debug\[59\]
+port 2971 nsew
+rlabel metal2 s 344310 141423 344310 141423 4 u_riscv_top.riscv_debug\[5\]
+port 2972 nsew
+rlabel metal1 s 422526 14117 422526 14117 4 u_riscv_top.riscv_debug\[60\]
+port 2973 nsew
+rlabel metal1 s 423062 14117 423062 14117 4 u_riscv_top.riscv_debug\[61\]
+port 2974 nsew
+rlabel metal1 s 423614 14151 423614 14151 4 u_riscv_top.riscv_debug\[62\]
+port 2975 nsew
+rlabel metal1 s 424166 14151 424166 14151 4 u_riscv_top.riscv_debug\[63\]
+port 2976 nsew
+rlabel metal3 s 343965 2924 343965 2924 4 u_riscv_top.riscv_debug\[6\]
+port 2977 nsew
+rlabel metal1 s 210036 278766 210036 278766 4 u_riscv_top.riscv_debug\[7\]
+port 2978 nsew
+rlabel metal3 s 348795 19516 348795 19516 4 u_riscv_top.riscv_debug\[8\]
+port 2979 nsew
+rlabel metal2 s 210174 279490 210174 279490 4 u_riscv_top.riscv_debug\[9\]
+port 2980 nsew
+rlabel metal2 s 229862 488903 229862 488903 4 u_riscv_top.rtc_clk
+port 2981 nsew
+rlabel metal2 s 230046 488699 230046 488699 4 u_riscv_top.soft_irq
+port 2982 nsew
+rlabel metal2 s 28842 212619 28842 212619 4 u_riscv_top.sram0_addr0\[0\]
+port 2983 nsew
+rlabel metal2 s 28566 213367 28566 213367 4 u_riscv_top.sram0_addr0\[1\]
+port 2984 nsew
+rlabel metal3 s 28083 178228 28083 178228 4 u_riscv_top.sram0_addr0\[2\]
+port 2985 nsew
+rlabel metal2 s 140070 261188 140070 261188 4 u_riscv_top.sram0_addr0\[3\]
+port 2986 nsew
+rlabel metal3 s 28221 181084 28221 181084 4 u_riscv_top.sram0_addr0\[4\]
+port 2987 nsew
+rlabel metal3 s 28129 182852 28129 182852 4 u_riscv_top.sram0_addr0\[5\]
+port 2988 nsew
+rlabel metal2 s 138690 260474 138690 260474 4 u_riscv_top.sram0_addr0\[6\]
+port 2989 nsew
+rlabel metal2 s 136206 277134 136206 277134 4 u_riscv_top.sram0_addr0\[7\]
+port 2990 nsew
+rlabel metal2 s 133722 276386 133722 276386 4 u_riscv_top.sram0_addr0\[8\]
+port 2991 nsew
+rlabel metal3 s 149569 235212 149569 235212 4 u_riscv_top.sram0_addr1\[0\]
+port 2992 nsew
+rlabel metal3 s 147683 235892 147683 235892 4 u_riscv_top.sram0_addr1\[1\]
+port 2993 nsew
+rlabel metal3 s 147668 304300 147668 304300 4 u_riscv_top.sram0_addr1\[2\]
+port 2994 nsew
+rlabel metal1 s 158010 235314 158010 235314 4 u_riscv_top.sram0_addr1\[3\]
+port 2995 nsew
+rlabel metal1 s 158286 236674 158286 236674 4 u_riscv_top.sram0_addr1\[4\]
+port 2996 nsew
+rlabel metal1 s 157780 238034 157780 238034 4 u_riscv_top.sram0_addr1\[5\]
+port 2997 nsew
+rlabel metal1 s 158056 253198 158056 253198 4 u_riscv_top.sram0_addr1\[6\]
+port 2998 nsew
+rlabel metal4 s 153254 149804 153254 149804 4 u_riscv_top.sram0_addr1\[7\]
+port 2999 nsew
+rlabel metal4 s 153390 149668 153390 149668 4 u_riscv_top.sram0_addr1\[8\]
+port 3000 nsew
+rlabel metal4 s 140300 263228 140300 263228 4 u_riscv_top.sram0_clk0
+port 3001 nsew
+rlabel metal3 s 160793 235892 160793 235892 4 u_riscv_top.sram0_clk1
+port 3002 nsew
+rlabel metal3 s 28451 158100 28451 158100 4 u_riscv_top.sram0_csb0
+port 3003 nsew
+rlabel metal3 s 166903 229190 166903 229190 4 u_riscv_top.sram0_csb1
+port 3004 nsew
+rlabel metal3 s 147645 293012 147645 293012 4 u_riscv_top.sram0_din0\[0\]
+port 3005 nsew
+rlabel metal4 s 64699 147628 64699 147628 4 u_riscv_top.sram0_din0\[10\]
+port 3006 nsew
+rlabel metal3 s 146357 290020 146357 290020 4 u_riscv_top.sram0_din0\[11\]
+port 3007 nsew
+rlabel metal3 s 146794 289748 146794 289748 4 u_riscv_top.sram0_din0\[12\]
+port 3008 nsew
+rlabel metal3 s 147737 289476 147737 289476 4 u_riscv_top.sram0_din0\[13\]
+port 3009 nsew
+rlabel metal3 s 146334 289204 146334 289204 4 u_riscv_top.sram0_din0\[14\]
+port 3010 nsew
+rlabel metal1 s 144026 288490 144026 288490 4 u_riscv_top.sram0_din0\[15\]
+port 3011 nsew
+rlabel metal1 s 144164 288422 144164 288422 4 u_riscv_top.sram0_din0\[16\]
+port 3012 nsew
+rlabel metal3 s 146472 288388 146472 288388 4 u_riscv_top.sram0_din0\[17\]
+port 3013 nsew
+rlabel metal2 s 140714 281248 140714 281248 4 u_riscv_top.sram0_din0\[18\]
+port 3014 nsew
+rlabel metal3 s 146426 287844 146426 287844 4 u_riscv_top.sram0_din0\[19\]
+port 3015 nsew
+rlabel metal2 s 140254 285464 140254 285464 4 u_riscv_top.sram0_din0\[1\]
+port 3016 nsew
+rlabel metal3 s 147921 287572 147921 287572 4 u_riscv_top.sram0_din0\[20\]
+port 3017 nsew
+rlabel metal4 s 78315 147628 78315 147628 4 u_riscv_top.sram0_din0\[21\]
+port 3018 nsew
+rlabel metal1 s 144072 285702 144072 285702 4 u_riscv_top.sram0_din0\[22\]
+port 3019 nsew
+rlabel metal2 s 141726 280789 141726 280789 4 u_riscv_top.sram0_din0\[23\]
+port 3020 nsew
+rlabel metal4 s 81174 149668 81174 149668 4 u_riscv_top.sram0_din0\[24\]
+port 3021 nsew
+rlabel metal4 s 82262 149668 82262 149668 4 u_riscv_top.sram0_din0\[25\]
+port 3022 nsew
+rlabel metal4 s 83350 149668 83350 149668 4 u_riscv_top.sram0_din0\[26\]
+port 3023 nsew
+rlabel metal4 s 84438 149668 84438 149668 4 u_riscv_top.sram0_din0\[27\]
+port 3024 nsew
+rlabel metal4 s 85798 149804 85798 149804 4 u_riscv_top.sram0_din0\[28\]
+port 3025 nsew
+rlabel metal4 s 87022 149668 87022 149668 4 u_riscv_top.sram0_din0\[29\]
+port 3026 nsew
+rlabel metal2 s 137494 284954 137494 284954 4 u_riscv_top.sram0_din0\[2\]
+port 3027 nsew
+rlabel metal4 s 88110 149804 88110 149804 4 u_riscv_top.sram0_din0\[30\]
+port 3028 nsew
+rlabel metal4 s 89198 149668 89198 149668 4 u_riscv_top.sram0_din0\[31\]
+port 3029 nsew
+rlabel metal2 s 137678 284988 137678 284988 4 u_riscv_top.sram0_din0\[3\]
+port 3030 nsew
+rlabel metal2 s 135102 284580 135102 284580 4 u_riscv_top.sram0_din0\[4\]
+port 3031 nsew
+rlabel metal4 s 58765 147628 58765 147628 4 u_riscv_top.sram0_din0\[5\]
+port 3032 nsew
+rlabel metal2 s 135194 284580 135194 284580 4 u_riscv_top.sram0_din0\[6\]
+port 3033 nsew
+rlabel metal2 s 139058 284104 139058 284104 4 u_riscv_top.sram0_din0\[7\]
+port 3034 nsew
+rlabel metal3 s 146610 290836 146610 290836 4 u_riscv_top.sram0_din0\[8\]
+port 3035 nsew
+rlabel metal3 s 146932 290564 146932 290564 4 u_riscv_top.sram0_din0\[9\]
+port 3036 nsew
+rlabel metal2 s 138966 289612 138966 289612 4 u_riscv_top.sram0_dout0\[0\]
+port 3037 nsew
+rlabel metal4 s 83622 149872 83622 149872 4 u_riscv_top.sram0_dout0\[10\]
+port 3038 nsew
+rlabel metal2 s 140438 286790 140438 286790 4 u_riscv_top.sram0_dout0\[11\]
+port 3039 nsew
+rlabel metal2 s 141634 285379 141634 285379 4 u_riscv_top.sram0_dout0\[12\]
+port 3040 nsew
+rlabel metal1 s 145728 294746 145728 294746 4 u_riscv_top.sram0_dout0\[13\]
+port 3041 nsew
+rlabel metal1 s 144486 297262 144486 297262 4 u_riscv_top.sram0_dout0\[14\]
+port 3042 nsew
+rlabel metal2 s 141818 288252 141818 288252 4 u_riscv_top.sram0_dout0\[15\]
+port 3043 nsew
+rlabel metal2 s 145682 291924 145682 291924 4 u_riscv_top.sram0_dout0\[16\]
+port 3044 nsew
+rlabel metal4 s 101030 149804 101030 149804 4 u_riscv_top.sram0_dout0\[17\]
+port 3045 nsew
+rlabel metal4 s 103478 149668 103478 149668 4 u_riscv_top.sram0_dout0\[18\]
+port 3046 nsew
+rlabel metal2 s 139150 284274 139150 284274 4 u_riscv_top.sram0_dout0\[19\]
+port 3047 nsew
+rlabel metal4 s 60789 147628 60789 147628 4 u_riscv_top.sram0_dout0\[1\]
+port 3048 nsew
+rlabel metal1 s 144072 295494 144072 295494 4 u_riscv_top.sram0_dout0\[20\]
+port 3049 nsew
+rlabel metal1 s 144210 295358 144210 295358 4 u_riscv_top.sram0_dout0\[21\]
+port 3050 nsew
+rlabel metal4 s 113542 149668 113542 149668 4 u_riscv_top.sram0_dout0\[22\]
+port 3051 nsew
+rlabel metal4 s 115990 149668 115990 149668 4 u_riscv_top.sram0_dout0\[23\]
+port 3052 nsew
+rlabel metal4 s 118574 149668 118574 149668 4 u_riscv_top.sram0_dout0\[24\]
+port 3053 nsew
+rlabel metal4 s 121022 149668 121022 149668 4 u_riscv_top.sram0_dout0\[25\]
+port 3054 nsew
+rlabel metal2 s 140530 281996 140530 281996 4 u_riscv_top.sram0_dout0\[26\]
+port 3055 nsew
+rlabel metal2 s 140346 286960 140346 286960 4 u_riscv_top.sram0_dout0\[27\]
+port 3056 nsew
+rlabel metal2 s 142002 283628 142002 283628 4 u_riscv_top.sram0_dout0\[28\]
+port 3057 nsew
+rlabel metal1 s 144302 292638 144302 292638 4 u_riscv_top.sram0_dout0\[29\]
+port 3058 nsew
+rlabel metal2 s 137402 288116 137402 288116 4 u_riscv_top.sram0_dout0\[2\]
+port 3059 nsew
+rlabel metal4 s 133398 149668 133398 149668 4 u_riscv_top.sram0_dout0\[30\]
+port 3060 nsew
+rlabel metal4 s 135982 149668 135982 149668 4 u_riscv_top.sram0_dout0\[31\]
+port 3061 nsew
+rlabel metal3 s 146725 300900 146725 300900 4 u_riscv_top.sram0_dout0\[3\]
+port 3062 nsew
+rlabel metal1 s 153295 270470 153295 270470 4 u_riscv_top.sram0_dout0\[4\]
+port 3063 nsew
+rlabel metal1 s 145774 292060 145774 292060 4 u_riscv_top.sram0_dout0\[5\]
+port 3064 nsew
+rlabel metal3 s 155733 273020 155733 273020 4 u_riscv_top.sram0_dout0\[6\]
+port 3065 nsew
+rlabel metal2 s 139978 281928 139978 281928 4 u_riscv_top.sram0_dout0\[7\]
+port 3066 nsew
+rlabel metal2 s 139334 284886 139334 284886 4 u_riscv_top.sram0_dout0\[8\]
+port 3067 nsew
+rlabel metal4 s 81038 149668 81038 149668 4 u_riscv_top.sram0_dout0\[9\]
+port 3068 nsew
+rlabel metal3 s 59041 235892 59041 235892 4 u_riscv_top.sram0_dout1\[0\]
+port 3069 nsew
+rlabel metal3 s 83881 235892 83881 235892 4 u_riscv_top.sram0_dout1\[10\]
+port 3070 nsew
+rlabel metal2 s 86894 236623 86894 236623 4 u_riscv_top.sram0_dout1\[11\]
+port 3071 nsew
+rlabel metal3 s 89125 235892 89125 235892 4 u_riscv_top.sram0_dout1\[12\]
+port 3072 nsew
+rlabel metal4 s 91011 235892 91011 235892 4 u_riscv_top.sram0_dout1\[13\]
+port 3073 nsew
+rlabel metal2 s 93794 235977 93794 235977 4 u_riscv_top.sram0_dout1\[14\]
+port 3074 nsew
+rlabel metal3 s 96347 235892 96347 235892 4 u_riscv_top.sram0_dout1\[15\]
+port 3075 nsew
+rlabel metal2 s 99314 235535 99314 235535 4 u_riscv_top.sram0_dout1\[16\]
+port 3076 nsew
+rlabel metal3 s 101591 235892 101591 235892 4 u_riscv_top.sram0_dout1\[17\]
+port 3077 nsew
+rlabel metal2 s 133446 287470 133446 287470 4 u_riscv_top.sram0_dout1\[18\]
+port 3078 nsew
+rlabel metal2 s 133354 283968 133354 283968 4 u_riscv_top.sram0_dout1\[19\]
+port 3079 nsew
+rlabel metal3 s 61525 235212 61525 235212 4 u_riscv_top.sram0_dout1\[1\]
+port 3080 nsew
+rlabel metal2 s 133538 288116 133538 288116 4 u_riscv_top.sram0_dout1\[20\]
+port 3081 nsew
+rlabel metal2 s 136114 292366 136114 292366 4 u_riscv_top.sram0_dout1\[21\]
+port 3082 nsew
+rlabel metal3 s 114057 235212 114057 235212 4 u_riscv_top.sram0_dout1\[22\]
+port 3083 nsew
+rlabel metal3 s 116633 235892 116633 235892 4 u_riscv_top.sram0_dout1\[23\]
+port 3084 nsew
+rlabel metal3 s 118519 235212 118519 235212 4 u_riscv_top.sram0_dout1\[24\]
+port 3085 nsew
+rlabel metal3 s 121187 235892 121187 235892 4 u_riscv_top.sram0_dout1\[25\]
+port 3086 nsew
+rlabel metal2 s 135010 291006 135010 291006 4 u_riscv_top.sram0_dout1\[26\]
+port 3087 nsew
+rlabel metal3 s 126523 235212 126523 235212 4 u_riscv_top.sram0_dout1\[27\]
+port 3088 nsew
+rlabel metal3 s 129099 235892 129099 235892 4 u_riscv_top.sram0_dout1\[28\]
+port 3089 nsew
+rlabel metal3 s 131767 235892 131767 235892 4 u_riscv_top.sram0_dout1\[29\]
+port 3090 nsew
+rlabel metal3 s 64193 235892 64193 235892 4 u_riscv_top.sram0_dout1\[2\]
+port 3091 nsew
+rlabel metal3 s 133653 235212 133653 235212 4 u_riscv_top.sram0_dout1\[30\]
+port 3092 nsew
+rlabel metal3 s 136321 235892 136321 235892 4 u_riscv_top.sram0_dout1\[31\]
+port 3093 nsew
+rlabel metal4 s 66171 235212 66171 235212 4 u_riscv_top.sram0_dout1\[3\]
+port 3094 nsew
+rlabel metal2 s 133170 277882 133170 277882 4 u_riscv_top.sram0_dout1\[4\]
+port 3095 nsew
+rlabel metal2 s 134642 277134 134642 277134 4 u_riscv_top.sram0_dout1\[5\]
+port 3096 nsew
+rlabel metal2 s 134734 282574 134734 282574 4 u_riscv_top.sram0_dout1\[6\]
+port 3097 nsew
+rlabel metal3 s 76383 235892 76383 235892 4 u_riscv_top.sram0_dout1\[7\]
+port 3098 nsew
+rlabel metal3 s 78614 235909 78614 235909 4 u_riscv_top.sram0_dout1\[8\]
+port 3099 nsew
+rlabel metal2 s 81374 236283 81374 236283 4 u_riscv_top.sram0_dout1\[9\]
+port 3100 nsew
+rlabel metal3 s 28405 160004 28405 160004 4 u_riscv_top.sram0_web0
+port 3101 nsew
+rlabel metal2 s 137218 281316 137218 281316 4 u_riscv_top.sram0_wmask0\[0\]
+port 3102 nsew
+rlabel metal2 s 24702 213350 24702 213350 4 u_riscv_top.sram0_wmask0\[1\]
+port 3103 nsew
+rlabel metal2 s 24610 211242 24610 211242 4 u_riscv_top.sram0_wmask0\[2\]
+port 3104 nsew
+rlabel metal2 s 24794 213282 24794 213282 4 u_riscv_top.sram0_wmask0\[3\]
+port 3105 nsew
+rlabel metal3 s 344356 141644 344356 141644 4 u_riscv_top.wb_clk
+port 3106 nsew
+rlabel metal2 s 346518 221391 346518 221391 4 u_riscv_top.wb_dcache_ack_i
+port 3107 nsew
+rlabel metal3 s 347714 199461 347714 199461 4 u_riscv_top.wb_dcache_adr_o\[0\]
+port 3108 nsew
+rlabel metal2 s 347714 196673 347714 196673 4 u_riscv_top.wb_dcache_adr_o\[10\]
+port 3109 nsew
+rlabel metal2 s 346702 196673 346702 196673 4 u_riscv_top.wb_dcache_adr_o\[11\]
+port 3110 nsew
+rlabel metal2 s 346610 196503 346610 196503 4 u_riscv_top.wb_dcache_adr_o\[12\]
+port 3111 nsew
+rlabel metal2 s 347622 195687 347622 195687 4 u_riscv_top.wb_dcache_adr_o\[13\]
+port 3112 nsew
+rlabel metal2 s 347162 195483 347162 195483 4 u_riscv_top.wb_dcache_adr_o\[14\]
+port 3113 nsew
+rlabel metal2 s 347714 195449 347714 195449 4 u_riscv_top.wb_dcache_adr_o\[15\]
+port 3114 nsew
+rlabel metal2 s 347346 195245 347346 195245 4 u_riscv_top.wb_dcache_adr_o\[16\]
+port 3115 nsew
+rlabel metal2 s 346886 195041 346886 195041 4 u_riscv_top.wb_dcache_adr_o\[17\]
+port 3116 nsew
+rlabel metal2 s 346886 194327 346886 194327 4 u_riscv_top.wb_dcache_adr_o\[18\]
+port 3117 nsew
+rlabel metal2 s 347714 194123 347714 194123 4 u_riscv_top.wb_dcache_adr_o\[19\]
+port 3118 nsew
+rlabel metal2 s 347622 199291 347622 199291 4 u_riscv_top.wb_dcache_adr_o\[1\]
+port 3119 nsew
+rlabel metal2 s 347622 193953 347622 193953 4 u_riscv_top.wb_dcache_adr_o\[20\]
+port 3120 nsew
+rlabel metal2 s 347714 193783 347714 193783 4 u_riscv_top.wb_dcache_adr_o\[21\]
+port 3121 nsew
+rlabel metal2 s 346702 193749 346702 193749 4 u_riscv_top.wb_dcache_adr_o\[22\]
+port 3122 nsew
+rlabel metal2 s 346886 192967 346886 192967 4 u_riscv_top.wb_dcache_adr_o\[23\]
+port 3123 nsew
+rlabel metal2 s 347346 192729 347346 192729 4 u_riscv_top.wb_dcache_adr_o\[24\]
+port 3124 nsew
+rlabel metal3 s 347714 192627 347714 192627 4 u_riscv_top.wb_dcache_adr_o\[25\]
+port 3125 nsew
+rlabel metal2 s 347622 192525 347622 192525 4 u_riscv_top.wb_dcache_adr_o\[26\]
+port 3126 nsew
+rlabel metal2 s 347714 192287 347714 192287 4 u_riscv_top.wb_dcache_adr_o\[27\]
+port 3127 nsew
+rlabel metal2 s 347162 192321 347162 192321 4 u_riscv_top.wb_dcache_adr_o\[28\]
+port 3128 nsew
+rlabel metal2 s 346702 191335 346702 191335 4 u_riscv_top.wb_dcache_adr_o\[29\]
+port 3129 nsew
+rlabel metal2 s 346794 199223 346794 199223 4 u_riscv_top.wb_dcache_adr_o\[2\]
+port 3130 nsew
+rlabel metal3 s 347714 191267 347714 191267 4 u_riscv_top.wb_dcache_adr_o\[30\]
+port 3131 nsew
+rlabel metal2 s 347622 191097 347622 191097 4 u_riscv_top.wb_dcache_adr_o\[31\]
+port 3132 nsew
+rlabel metal2 s 347714 198441 347714 198441 4 u_riscv_top.wb_dcache_adr_o\[3\]
+port 3133 nsew
+rlabel metal2 s 347622 198169 347622 198169 4 u_riscv_top.wb_dcache_adr_o\[4\]
+port 3134 nsew
+rlabel metal3 s 347714 198067 347714 198067 4 u_riscv_top.wb_dcache_adr_o\[5\]
+port 3135 nsew
+rlabel metal2 s 346610 197999 346610 197999 4 u_riscv_top.wb_dcache_adr_o\[6\]
+port 3136 nsew
+rlabel metal2 s 346886 197829 346886 197829 4 u_riscv_top.wb_dcache_adr_o\[7\]
+port 3137 nsew
+rlabel metal2 s 347346 196979 347346 196979 4 u_riscv_top.wb_dcache_adr_o\[8\]
+port 3138 nsew
+rlabel metal2 s 347622 196877 347622 196877 4 u_riscv_top.wb_dcache_adr_o\[9\]
+port 3139 nsew
+rlabel metal2 s 347346 203439 347346 203439 4 u_riscv_top.wb_dcache_bl_o\[0\]
+port 3140 nsew
+rlabel metal2 s 346794 203371 346794 203371 4 u_riscv_top.wb_dcache_bl_o\[1\]
+port 3141 nsew
+rlabel metal2 s 346794 202521 346794 202521 4 u_riscv_top.wb_dcache_bl_o\[2\]
+port 3142 nsew
+rlabel metal2 s 347622 202317 347622 202317 4 u_riscv_top.wb_dcache_bl_o\[3\]
+port 3143 nsew
+rlabel metal3 s 347714 202147 347714 202147 4 u_riscv_top.wb_dcache_bl_o\[4\]
+port 3144 nsew
+rlabel metal2 s 347346 202079 347346 202079 4 u_riscv_top.wb_dcache_bl_o\[5\]
+port 3145 nsew
+rlabel metal2 s 347162 202011 347162 202011 4 u_riscv_top.wb_dcache_bl_o\[6\]
+port 3146 nsew
+rlabel metal2 s 346610 201161 346610 201161 4 u_riscv_top.wb_dcache_bl_o\[7\]
+port 3147 nsew
+rlabel metal2 s 347346 200923 347346 200923 4 u_riscv_top.wb_dcache_bl_o\[8\]
+port 3148 nsew
+rlabel metal2 s 347714 200855 347714 200855 4 u_riscv_top.wb_dcache_bl_o\[9\]
+port 3149 nsew
+rlabel metal3 s 347714 203541 347714 203541 4 u_riscv_top.wb_dcache_bry_o
+port 3150 nsew
+rlabel metal2 s 346886 221289 346886 221289 4 u_riscv_top.wb_dcache_dat_i\[0\]
+port 3151 nsew
+rlabel metal2 s 346886 218501 346886 218501 4 u_riscv_top.wb_dcache_dat_i\[10\]
+port 3152 nsew
+rlabel metal2 s 346702 217651 346702 217651 4 u_riscv_top.wb_dcache_dat_i\[11\]
+port 3153 nsew
+rlabel metal2 s 347346 217481 347346 217481 4 u_riscv_top.wb_dcache_dat_i\[12\]
+port 3154 nsew
+rlabel metal3 s 347714 217413 347714 217413 4 u_riscv_top.wb_dcache_dat_i\[13\]
+port 3155 nsew
+rlabel metal2 s 347622 217311 347622 217311 4 u_riscv_top.wb_dcache_dat_i\[14\]
+port 3156 nsew
+rlabel metal2 s 347162 217209 347162 217209 4 u_riscv_top.wb_dcache_dat_i\[15\]
+port 3157 nsew
+rlabel metal2 s 347714 216393 347714 216393 4 u_riscv_top.wb_dcache_dat_i\[16\]
+port 3158 nsew
+rlabel metal2 s 347622 216155 347622 216155 4 u_riscv_top.wb_dcache_dat_i\[17\]
+port 3159 nsew
+rlabel metal3 s 347714 216053 347714 216053 4 u_riscv_top.wb_dcache_dat_i\[18\]
+port 3160 nsew
+rlabel metal2 s 347714 215849 347714 215849 4 u_riscv_top.wb_dcache_dat_i\[19\]
+port 3161 nsew
+rlabel metal2 s 347622 220439 347622 220439 4 u_riscv_top.wb_dcache_dat_i\[1\]
+port 3162 nsew
+rlabel metal2 s 346794 215815 346794 215815 4 u_riscv_top.wb_dcache_dat_i\[20\]
+port 3163 nsew
+rlabel metal2 s 346702 214897 346702 214897 4 u_riscv_top.wb_dcache_dat_i\[21\]
+port 3164 nsew
+rlabel metal2 s 347346 214829 347346 214829 4 u_riscv_top.wb_dcache_dat_i\[22\]
+port 3165 nsew
+rlabel metal2 s 347714 214727 347714 214727 4 u_riscv_top.wb_dcache_dat_i\[23\]
+port 3166 nsew
+rlabel metal2 s 347622 214523 347622 214523 4 u_riscv_top.wb_dcache_dat_i\[24\]
+port 3167 nsew
+rlabel metal2 s 347162 214489 347162 214489 4 u_riscv_top.wb_dcache_dat_i\[25\]
+port 3168 nsew
+rlabel metal2 s 346702 213571 346702 213571 4 u_riscv_top.wb_dcache_dat_i\[26\]
+port 3169 nsew
+rlabel metal2 s 347346 213401 347346 213401 4 u_riscv_top.wb_dcache_dat_i\[27\]
+port 3170 nsew
+rlabel metal2 s 347714 213401 347714 213401 4 u_riscv_top.wb_dcache_dat_i\[28\]
+port 3171 nsew
+rlabel metal2 s 347622 213197 347622 213197 4 u_riscv_top.wb_dcache_dat_i\[29\]
+port 3172 nsew
+rlabel metal2 s 346978 220235 346978 220235 4 u_riscv_top.wb_dcache_dat_i\[2\]
+port 3173 nsew
+rlabel metal2 s 346610 213095 346610 213095 4 u_riscv_top.wb_dcache_dat_i\[30\]
+port 3174 nsew
+rlabel metal2 s 347714 212313 347714 212313 4 u_riscv_top.wb_dcache_dat_i\[31\]
+port 3175 nsew
+rlabel metal2 s 347714 220235 347714 220235 4 u_riscv_top.wb_dcache_dat_i\[3\]
+port 3176 nsew
+rlabel metal2 s 347162 220065 347162 220065 4 u_riscv_top.wb_dcache_dat_i\[4\]
+port 3177 nsew
+rlabel metal2 s 347346 219861 347346 219861 4 u_riscv_top.wb_dcache_dat_i\[5\]
+port 3178 nsew
+rlabel metal2 s 346702 219011 346702 219011 4 u_riscv_top.wb_dcache_dat_i\[6\]
+port 3179 nsew
+rlabel metal3 s 347714 219011 347714 219011 4 u_riscv_top.wb_dcache_dat_i\[7\]
+port 3180 nsew
+rlabel metal2 s 347714 218807 347714 218807 4 u_riscv_top.wb_dcache_dat_i\[8\]
+port 3181 nsew
+rlabel metal2 s 347622 218705 347622 218705 4 u_riscv_top.wb_dcache_dat_i\[9\]
+port 3182 nsew
+rlabel metal2 s 347622 212109 347622 212109 4 u_riscv_top.wb_dcache_dat_o\[0\]
+port 3183 nsew
+rlabel metal2 s 347622 209355 347622 209355 4 u_riscv_top.wb_dcache_dat_o\[10\]
+port 3184 nsew
+rlabel metal2 s 347714 209185 347714 209185 4 u_riscv_top.wb_dcache_dat_o\[11\]
+port 3185 nsew
+rlabel metal2 s 347346 209117 347346 209117 4 u_riscv_top.wb_dcache_dat_o\[12\]
+port 3186 nsew
+rlabel metal2 s 346610 208879 346610 208879 4 u_riscv_top.wb_dcache_dat_o\[13\]
+port 3187 nsew
+rlabel metal2 s 346886 208879 346886 208879 4 u_riscv_top.wb_dcache_dat_o\[14\]
+port 3188 nsew
+rlabel metal2 s 347622 207927 347622 207927 4 u_riscv_top.wb_dcache_dat_o\[15\]
+port 3189 nsew
+rlabel metal3 s 347714 207859 347714 207859 4 u_riscv_top.wb_dcache_dat_o\[16\]
+port 3190 nsew
+rlabel metal3 s 347714 207621 347714 207621 4 u_riscv_top.wb_dcache_dat_o\[17\]
+port 3191 nsew
+rlabel metal2 s 346702 207621 346702 207621 4 u_riscv_top.wb_dcache_dat_o\[18\]
+port 3192 nsew
+rlabel metal2 s 346886 207417 346886 207417 4 u_riscv_top.wb_dcache_dat_o\[19\]
+port 3193 nsew
+rlabel metal2 s 347714 211871 347714 211871 4 u_riscv_top.wb_dcache_dat_o\[1\]
+port 3194 nsew
+rlabel metal2 s 347346 206601 347346 206601 4 u_riscv_top.wb_dcache_dat_o\[20\]
+port 3195 nsew
+rlabel metal2 s 347714 206397 347714 206397 4 u_riscv_top.wb_dcache_dat_o\[21\]
+port 3196 nsew
+rlabel metal2 s 347622 206363 347622 206363 4 u_riscv_top.wb_dcache_dat_o\[22\]
+port 3197 nsew
+rlabel metal2 s 346794 206159 346794 206159 4 u_riscv_top.wb_dcache_dat_o\[23\]
+port 3198 nsew
+rlabel metal2 s 347162 206125 347162 206125 4 u_riscv_top.wb_dcache_dat_o\[24\]
+port 3199 nsew
+rlabel metal2 s 347714 205309 347714 205309 4 u_riscv_top.wb_dcache_dat_o\[25\]
+port 3200 nsew
+rlabel metal2 s 347622 205071 347622 205071 4 u_riscv_top.wb_dcache_dat_o\[26\]
+port 3201 nsew
+rlabel metal2 s 347346 205003 347346 205003 4 u_riscv_top.wb_dcache_dat_o\[27\]
+port 3202 nsew
+rlabel metal2 s 347162 204833 347162 204833 4 u_riscv_top.wb_dcache_dat_o\[28\]
+port 3203 nsew
+rlabel metal2 s 347714 204629 347714 204629 4 u_riscv_top.wb_dcache_dat_o\[29\]
+port 3204 nsew
+rlabel metal2 s 347346 211803 347346 211803 4 u_riscv_top.wb_dcache_dat_o\[2\]
+port 3205 nsew
+rlabel metal2 s 347714 203949 347714 203949 4 u_riscv_top.wb_dcache_dat_o\[30\]
+port 3206 nsew
+rlabel metal2 s 347622 203745 347622 203745 4 u_riscv_top.wb_dcache_dat_o\[31\]
+port 3207 nsew
+rlabel metal2 s 347162 211735 347162 211735 4 u_riscv_top.wb_dcache_dat_o\[3\]
+port 3208 nsew
+rlabel metal2 s 346886 211497 346886 211497 4 u_riscv_top.wb_dcache_dat_o\[4\]
+port 3209 nsew
+rlabel metal2 s 347714 210783 347714 210783 4 u_riscv_top.wb_dcache_dat_o\[5\]
+port 3210 nsew
+rlabel metal2 s 347714 210511 347714 210511 4 u_riscv_top.wb_dcache_dat_o\[6\]
+port 3211 nsew
+rlabel metal2 s 346518 210477 346518 210477 4 u_riscv_top.wb_dcache_dat_o\[7\]
+port 3212 nsew
+rlabel metal2 s 347622 210273 347622 210273 4 u_riscv_top.wb_dcache_dat_o\[8\]
+port 3213 nsew
+rlabel metal2 s 346886 210171 346886 210171 4 u_riscv_top.wb_dcache_dat_o\[9\]
+port 3214 nsew
+rlabel metal2 s 347622 221629 347622 221629 4 u_riscv_top.wb_dcache_err_i
+port 3215 nsew
+rlabel metal3 s 347714 221459 347714 221459 4 u_riscv_top.wb_dcache_lack_i
+port 3216 nsew
+rlabel metal2 s 347622 200685 347622 200685 4 u_riscv_top.wb_dcache_sel_o\[0\]
+port 3217 nsew
+rlabel metal2 s 346794 200651 346794 200651 4 u_riscv_top.wb_dcache_sel_o\[1\]
+port 3218 nsew
+rlabel metal2 s 347622 199835 347622 199835 4 u_riscv_top.wb_dcache_sel_o\[2\]
+port 3219 nsew
+rlabel metal2 s 347714 199665 347714 199665 4 u_riscv_top.wb_dcache_sel_o\[3\]
+port 3220 nsew
+rlabel metal2 s 346886 189975 346886 189975 4 u_riscv_top.wb_dcache_stb_o
+port 3221 nsew
+rlabel metal2 s 347346 191029 347346 191029 4 u_riscv_top.wb_dcache_we_o
+port 3222 nsew
+rlabel metal2 s 347530 252161 347530 252161 4 u_riscv_top.wb_icache_ack_i
+port 3223 nsew
+rlabel metal2 s 347622 239547 347622 239547 4 u_riscv_top.wb_icache_adr_o\[0\]
+port 3224 nsew
+rlabel metal3 s 347714 236691 347714 236691 4 u_riscv_top.wb_icache_adr_o\[10\]
+port 3225 nsew
+rlabel metal2 s 346518 236623 346518 236623 4 u_riscv_top.wb_icache_adr_o\[11\]
+port 3226 nsew
+rlabel metal2 s 346886 236521 346886 236521 4 u_riscv_top.wb_icache_adr_o\[12\]
+port 3227 nsew
+rlabel metal2 s 347714 235671 347714 235671 4 u_riscv_top.wb_icache_adr_o\[13\]
+port 3228 nsew
+rlabel metal2 s 347622 235501 347622 235501 4 u_riscv_top.wb_icache_adr_o\[14\]
+port 3229 nsew
+rlabel metal3 s 347714 235331 347714 235331 4 u_riscv_top.wb_icache_adr_o\[15\]
+port 3230 nsew
+rlabel metal2 s 347346 235297 347346 235297 4 u_riscv_top.wb_icache_adr_o\[16\]
+port 3231 nsew
+rlabel metal2 s 347622 235025 347622 235025 4 u_riscv_top.wb_icache_adr_o\[17\]
+port 3232 nsew
+rlabel metal2 s 347622 234311 347622 234311 4 u_riscv_top.wb_icache_adr_o\[18\]
+port 3233 nsew
+rlabel metal2 s 347714 234209 347714 234209 4 u_riscv_top.wb_icache_adr_o\[19\]
+port 3234 nsew
+rlabel metal2 s 347714 239275 347714 239275 4 u_riscv_top.wb_icache_adr_o\[1\]
+port 3235 nsew
+rlabel metal3 s 347714 233971 347714 233971 4 u_riscv_top.wb_icache_adr_o\[20\]
+port 3236 nsew
+rlabel metal2 s 347346 233869 347346 233869 4 u_riscv_top.wb_icache_adr_o\[21\]
+port 3237 nsew
+rlabel metal2 s 347622 233665 347622 233665 4 u_riscv_top.wb_icache_adr_o\[22\]
+port 3238 nsew
+rlabel metal2 s 347346 232883 347346 232883 4 u_riscv_top.wb_icache_adr_o\[23\]
+port 3239 nsew
+rlabel metal2 s 346518 232713 346518 232713 4 u_riscv_top.wb_icache_adr_o\[24\]
+port 3240 nsew
+rlabel metal2 s 347714 232679 347714 232679 4 u_riscv_top.wb_icache_adr_o\[25\]
+port 3241 nsew
+rlabel metal2 s 347622 232509 347622 232509 4 u_riscv_top.wb_icache_adr_o\[26\]
+port 3242 nsew
+rlabel metal2 s 347162 232441 347162 232441 4 u_riscv_top.wb_icache_adr_o\[27\]
+port 3243 nsew
+rlabel metal2 s 346702 231489 346702 231489 4 u_riscv_top.wb_icache_adr_o\[28\]
+port 3244 nsew
+rlabel metal2 s 347622 231387 347622 231387 4 u_riscv_top.wb_icache_adr_o\[29\]
+port 3245 nsew
+rlabel metal2 s 347162 239241 347162 239241 4 u_riscv_top.wb_icache_adr_o\[2\]
+port 3246 nsew
+rlabel metal2 s 347714 231183 347714 231183 4 u_riscv_top.wb_icache_adr_o\[30\]
+port 3247 nsew
+rlabel metal2 s 347346 231149 347346 231149 4 u_riscv_top.wb_icache_adr_o\[31\]
+port 3248 nsew
+rlabel metal2 s 347622 238459 347622 238459 4 u_riscv_top.wb_icache_adr_o\[3\]
+port 3249 nsew
+rlabel metal2 s 347714 238289 347714 238289 4 u_riscv_top.wb_icache_adr_o\[4\]
+port 3250 nsew
+rlabel metal3 s 347714 238085 347714 238085 4 u_riscv_top.wb_icache_adr_o\[5\]
+port 3251 nsew
+rlabel metal2 s 347622 237915 347622 237915 4 u_riscv_top.wb_icache_adr_o\[6\]
+port 3252 nsew
+rlabel metal2 s 346794 237847 346794 237847 4 u_riscv_top.wb_icache_adr_o\[7\]
+port 3253 nsew
+rlabel metal2 s 346702 237099 346702 237099 4 u_riscv_top.wb_icache_adr_o\[8\]
+port 3254 nsew
+rlabel metal2 s 347622 236861 347622 236861 4 u_riscv_top.wb_icache_adr_o\[9\]
+port 3255 nsew
+rlabel metal2 s 347162 243491 347162 243491 4 u_riscv_top.wb_icache_bl_o\[0\]
+port 3256 nsew
+rlabel metal2 s 347622 243253 347622 243253 4 u_riscv_top.wb_icache_bl_o\[1\]
+port 3257 nsew
+rlabel metal2 s 347714 242573 347714 242573 4 u_riscv_top.wb_icache_bl_o\[2\]
+port 3258 nsew
+rlabel metal2 s 347622 242335 347622 242335 4 u_riscv_top.wb_icache_bl_o\[3\]
+port 3259 nsew
+rlabel metal2 s 347346 242267 347346 242267 4 u_riscv_top.wb_icache_bl_o\[4\]
+port 3260 nsew
+rlabel metal2 s 346518 242097 346518 242097 4 u_riscv_top.wb_icache_bl_o\[5\]
+port 3261 nsew
+rlabel metal2 s 347714 241893 347714 241893 4 u_riscv_top.wb_icache_bl_o\[6\]
+port 3262 nsew
+rlabel metal2 s 347346 241077 347346 241077 4 u_riscv_top.wb_icache_bl_o\[7\]
+port 3263 nsew
+rlabel metal3 s 347714 241043 347714 241043 4 u_riscv_top.wb_icache_bl_o\[8\]
+port 3264 nsew
+rlabel metal2 s 347714 240839 347714 240839 4 u_riscv_top.wb_icache_bl_o\[9\]
+port 3265 nsew
+rlabel metal2 s 347714 243593 347714 243593 4 u_riscv_top.wb_icache_bry_o
+port 3266 nsew
+rlabel metal2 s 347714 252161 347714 252161 4 u_riscv_top.wb_icache_dat_i\[0\]
+port 3267 nsew
+rlabel metal2 s 346886 249271 346886 249271 4 u_riscv_top.wb_icache_dat_i\[10\]
+port 3268 nsew
+rlabel metal2 s 347714 249271 347714 249271 4 u_riscv_top.wb_icache_dat_i\[11\]
+port 3269 nsew
+rlabel metal2 s 347622 249101 347622 249101 4 u_riscv_top.wb_icache_dat_i\[12\]
+port 3270 nsew
+rlabel metal2 s 347438 249033 347438 249033 4 u_riscv_top.wb_icache_dat_i\[13\]
+port 3271 nsew
+rlabel metal2 s 347714 248761 347714 248761 4 u_riscv_top.wb_icache_dat_i\[14\]
+port 3272 nsew
+rlabel metal2 s 347714 248013 347714 248013 4 u_riscv_top.wb_icache_dat_i\[15\]
+port 3273 nsew
+rlabel metal2 s 347622 247775 347622 247775 4 u_riscv_top.wb_icache_dat_i\[16\]
+port 3274 nsew
+rlabel metal2 s 347346 247707 347346 247707 4 u_riscv_top.wb_icache_dat_i\[17\]
+port 3275 nsew
+rlabel metal2 s 346702 247639 346702 247639 4 u_riscv_top.wb_icache_dat_i\[18\]
+port 3276 nsew
+rlabel metal2 s 347714 247401 347714 247401 4 u_riscv_top.wb_icache_dat_i\[19\]
+port 3277 nsew
+rlabel metal3 s 347714 251923 347714 251923 4 u_riscv_top.wb_icache_dat_i\[1\]
+port 3278 nsew
+rlabel metal2 s 347622 246653 347622 246653 4 u_riscv_top.wb_icache_dat_i\[20\]
+port 3279 nsew
+rlabel metal2 s 347714 246449 347714 246449 4 u_riscv_top.wb_icache_dat_i\[21\]
+port 3280 nsew
+rlabel metal2 s 347346 246415 347346 246415 4 u_riscv_top.wb_icache_dat_i\[22\]
+port 3281 nsew
+rlabel metal2 s 346610 246143 346610 246143 4 u_riscv_top.wb_icache_dat_i\[23\]
+port 3282 nsew
+rlabel metal2 s 346886 246075 346886 246075 4 u_riscv_top.wb_icache_dat_i\[24\]
+port 3283 nsew
+rlabel metal2 s 346610 245225 346610 245225 4 u_riscv_top.wb_icache_dat_i\[25\]
+port 3284 nsew
+rlabel metal2 s 347714 245055 347714 245055 4 u_riscv_top.wb_icache_dat_i\[26\]
+port 3285 nsew
+rlabel metal2 s 347162 245021 347162 245021 4 u_riscv_top.wb_icache_dat_i\[27\]
+port 3286 nsew
+rlabel metal2 s 347346 244851 347346 244851 4 u_riscv_top.wb_icache_dat_i\[28\]
+port 3287 nsew
+rlabel metal2 s 347622 244613 347622 244613 4 u_riscv_top.wb_icache_dat_i\[29\]
+port 3288 nsew
+rlabel metal2 s 346886 251855 346886 251855 4 u_riscv_top.wb_icache_dat_i\[2\]
+port 3289 nsew
+rlabel metal2 s 347346 243831 347346 243831 4 u_riscv_top.wb_icache_dat_i\[30\]
+port 3290 nsew
+rlabel metal3 s 347714 243797 347714 243797 4 u_riscv_top.wb_icache_dat_i\[31\]
+port 3291 nsew
+rlabel metal2 s 347622 251685 347622 251685 4 u_riscv_top.wb_icache_dat_i\[3\]
+port 3292 nsew
+rlabel metal2 s 347438 250801 347438 250801 4 u_riscv_top.wb_icache_dat_i\[4\]
+port 3293 nsew
+rlabel metal2 s 347714 250801 347714 250801 4 u_riscv_top.wb_icache_dat_i\[5\]
+port 3294 nsew
+rlabel metal2 s 347622 250631 347622 250631 4 u_riscv_top.wb_icache_dat_i\[6\]
+port 3295 nsew
+rlabel metal2 s 347530 250461 347530 250461 4 u_riscv_top.wb_icache_dat_i\[7\]
+port 3296 nsew
+rlabel metal2 s 347714 250291 347714 250291 4 u_riscv_top.wb_icache_dat_i\[8\]
+port 3297 nsew
+rlabel metal2 s 347530 249475 347530 249475 4 u_riscv_top.wb_icache_dat_i\[9\]
+port 3298 nsew
+rlabel metal2 s 347714 253147 347714 253147 4 u_riscv_top.wb_icache_err_i
+port 3299 nsew
+rlabel metal2 s 347070 252977 347070 252977 4 u_riscv_top.wb_icache_lack_i
+port 3300 nsew
+rlabel metal2 s 347622 240737 347622 240737 4 u_riscv_top.wb_icache_sel_o\[0\]
+port 3301 nsew
+rlabel metal2 s 346794 240499 346794 240499 4 u_riscv_top.wb_icache_sel_o\[1\]
+port 3302 nsew
+rlabel metal2 s 347714 239751 347714 239751 4 u_riscv_top.wb_icache_sel_o\[2\]
+port 3303 nsew
+rlabel metal2 s 347346 239581 347346 239581 4 u_riscv_top.wb_icache_sel_o\[3\]
+port 3304 nsew
+rlabel metal2 s 346886 229959 346886 229959 4 u_riscv_top.wb_icache_stb_o
+port 3305 nsew
+rlabel metal2 s 346610 231047 346610 231047 4 u_riscv_top.wb_icache_we_o
+port 3306 nsew
+rlabel metal2 s 347714 141321 347714 141321 4 u_riscv_top.wbd_clk_int
+port 3307 nsew
+rlabel metal2 s 346886 179877 346886 179877 4 u_riscv_top.wbd_dmem_ack_i
+port 3308 nsew
+rlabel metal2 s 347714 159511 347714 159511 4 u_riscv_top.wbd_dmem_adr_o\[0\]
+port 3309 nsew
+rlabel metal3 s 347714 156757 347714 156757 4 u_riscv_top.wbd_dmem_adr_o\[10\]
+port 3310 nsew
+rlabel metal2 s 347714 156553 347714 156553 4 u_riscv_top.wbd_dmem_adr_o\[11\]
+port 3311 nsew
+rlabel metal2 s 346886 156553 346886 156553 4 u_riscv_top.wbd_dmem_adr_o\[12\]
+port 3312 nsew
+rlabel metal2 s 347346 155567 347346 155567 4 u_riscv_top.wbd_dmem_adr_o\[13\]
+port 3313 nsew
+rlabel metal2 s 346518 155465 346518 155465 4 u_riscv_top.wbd_dmem_adr_o\[14\]
+port 3314 nsew
+rlabel metal3 s 347714 155397 347714 155397 4 u_riscv_top.wbd_dmem_adr_o\[15\]
+port 3315 nsew
+rlabel metal2 s 347622 155227 347622 155227 4 u_riscv_top.wbd_dmem_adr_o\[16\]
+port 3316 nsew
+rlabel metal2 s 346794 155159 346794 155159 4 u_riscv_top.wbd_dmem_adr_o\[17\]
+port 3317 nsew
+rlabel metal2 s 347162 155057 347162 155057 4 u_riscv_top.wbd_dmem_adr_o\[18\]
+port 3318 nsew
+rlabel metal2 s 347714 154173 347714 154173 4 u_riscv_top.wbd_dmem_adr_o\[19\]
+port 3319 nsew
+rlabel metal2 s 347622 159341 347622 159341 4 u_riscv_top.wbd_dmem_adr_o\[1\]
+port 3320 nsew
+rlabel metal2 s 347622 153935 347622 153935 4 u_riscv_top.wbd_dmem_adr_o\[20\]
+port 3321 nsew
+rlabel metal2 s 347346 153867 347346 153867 4 u_riscv_top.wbd_dmem_adr_o\[21\]
+port 3322 nsew
+rlabel metal2 s 346702 153697 346702 153697 4 u_riscv_top.wbd_dmem_adr_o\[22\]
+port 3323 nsew
+rlabel metal2 s 347162 153663 347162 153663 4 u_riscv_top.wbd_dmem_adr_o\[23\]
+port 3324 nsew
+rlabel metal2 s 346518 152745 346518 152745 4 u_riscv_top.wbd_dmem_adr_o\[24\]
+port 3325 nsew
+rlabel metal2 s 347714 152711 347714 152711 4 u_riscv_top.wbd_dmem_adr_o\[25\]
+port 3326 nsew
+rlabel metal2 s 347622 152541 347622 152541 4 u_riscv_top.wbd_dmem_adr_o\[26\]
+port 3327 nsew
+rlabel metal2 s 347714 152303 347714 152303 4 u_riscv_top.wbd_dmem_adr_o\[27\]
+port 3328 nsew
+rlabel metal2 s 346886 152235 346886 152235 4 u_riscv_top.wbd_dmem_adr_o\[28\]
+port 3329 nsew
+rlabel metal2 s 347162 151317 347162 151317 4 u_riscv_top.wbd_dmem_adr_o\[29\]
+port 3330 nsew
+rlabel metal2 s 347162 159273 347162 159273 4 u_riscv_top.wbd_dmem_adr_o\[2\]
+port 3331 nsew
+rlabel metal2 s 347714 151215 347714 151215 4 u_riscv_top.wbd_dmem_adr_o\[30\]
+port 3332 nsew
+rlabel metal2 s 347622 151147 347622 151147 4 u_riscv_top.wbd_dmem_adr_o\[31\]
+port 3333 nsew
+rlabel metal2 s 346702 158389 346702 158389 4 u_riscv_top.wbd_dmem_adr_o\[3\]
+port 3334 nsew
+rlabel metal2 s 347714 158287 347714 158287 4 u_riscv_top.wbd_dmem_adr_o\[4\]
+port 3335 nsew
+rlabel metal2 s 347714 158049 347714 158049 4 u_riscv_top.wbd_dmem_adr_o\[5\]
+port 3336 nsew
+rlabel metal2 s 347622 157947 347622 157947 4 u_riscv_top.wbd_dmem_adr_o\[6\]
+port 3337 nsew
+rlabel metal2 s 346886 157913 346886 157913 4 u_riscv_top.wbd_dmem_adr_o\[7\]
+port 3338 nsew
+rlabel metal2 s 347622 157063 347622 157063 4 u_riscv_top.wbd_dmem_adr_o\[8\]
+port 3339 nsew
+rlabel metal2 s 346518 156859 346518 156859 4 u_riscv_top.wbd_dmem_adr_o\[9\]
+port 3340 nsew
+rlabel metal2 s 347622 161143 347622 161143 4 u_riscv_top.wbd_dmem_bl_o\[0\]
+port 3341 nsew
+rlabel metal2 s 347162 160939 347162 160939 4 u_riscv_top.wbd_dmem_bl_o\[1\]
+port 3342 nsew
+rlabel metal2 s 347714 160905 347714 160905 4 u_riscv_top.wbd_dmem_bl_o\[2\]
+port 3343 nsew
+rlabel metal2 s 347622 161925 347622 161925 4 u_riscv_top.wbd_dmem_bry_o
+port 3344 nsew
+rlabel metal2 s 347622 178925 347622 178925 4 u_riscv_top.wbd_dmem_dat_i\[0\]
+port 3345 nsew
+rlabel metal2 s 346518 176137 346518 176137 4 u_riscv_top.wbd_dmem_dat_i\[10\]
+port 3346 nsew
+rlabel metal2 s 347714 176103 347714 176103 4 u_riscv_top.wbd_dmem_dat_i\[11\]
+port 3347 nsew
+rlabel metal2 s 347622 175933 347622 175933 4 u_riscv_top.wbd_dmem_dat_i\[12\]
+port 3348 nsew
+rlabel metal2 s 347162 175865 347162 175865 4 u_riscv_top.wbd_dmem_dat_i\[13\]
+port 3349 nsew
+rlabel metal2 s 346886 174947 346886 174947 4 u_riscv_top.wbd_dmem_dat_i\[14\]
+port 3350 nsew
+rlabel metal2 s 346610 174777 346610 174777 4 u_riscv_top.wbd_dmem_dat_i\[15\]
+port 3351 nsew
+rlabel metal3 s 347714 174709 347714 174709 4 u_riscv_top.wbd_dmem_dat_i\[16\]
+port 3352 nsew
+rlabel metal2 s 347714 174471 347714 174471 4 u_riscv_top.wbd_dmem_dat_i\[17\]
+port 3353 nsew
+rlabel metal2 s 346794 174471 346794 174471 4 u_riscv_top.wbd_dmem_dat_i\[18\]
+port 3354 nsew
+rlabel metal2 s 347346 173655 347346 173655 4 u_riscv_top.wbd_dmem_dat_i\[19\]
+port 3355 nsew
+rlabel metal3 s 347714 178755 347714 178755 4 u_riscv_top.wbd_dmem_dat_i\[1\]
+port 3356 nsew
+rlabel metal2 s 347622 173485 347622 173485 4 u_riscv_top.wbd_dmem_dat_i\[20\]
+port 3357 nsew
+rlabel metal2 s 347714 173417 347714 173417 4 u_riscv_top.wbd_dmem_dat_i\[21\]
+port 3358 nsew
+rlabel metal2 s 347714 173111 347714 173111 4 u_riscv_top.wbd_dmem_dat_i\[22\]
+port 3359 nsew
+rlabel metal2 s 347622 173009 347622 173009 4 u_riscv_top.wbd_dmem_dat_i\[23\]
+port 3360 nsew
+rlabel metal2 s 346886 172907 346886 172907 4 u_riscv_top.wbd_dmem_dat_i\[24\]
+port 3361 nsew
+rlabel metal2 s 347346 172091 347346 172091 4 u_riscv_top.wbd_dmem_dat_i\[25\]
+port 3362 nsew
+rlabel metal2 s 347714 172023 347714 172023 4 u_riscv_top.wbd_dmem_dat_i\[26\]
+port 3363 nsew
+rlabel metal2 s 347714 171751 347714 171751 4 u_riscv_top.wbd_dmem_dat_i\[27\]
+port 3364 nsew
+rlabel metal2 s 347622 171649 347622 171649 4 u_riscv_top.wbd_dmem_dat_i\[28\]
+port 3365 nsew
+rlabel metal2 s 347162 171581 347162 171581 4 u_riscv_top.wbd_dmem_dat_i\[29\]
+port 3366 nsew
+rlabel metal2 s 346518 178687 346518 178687 4 u_riscv_top.wbd_dmem_dat_i\[2\]
+port 3367 nsew
+rlabel metal2 s 347346 170663 347346 170663 4 u_riscv_top.wbd_dmem_dat_i\[30\]
+port 3368 nsew
+rlabel metal3 s 347714 170629 347714 170629 4 u_riscv_top.wbd_dmem_dat_i\[31\]
+port 3369 nsew
+rlabel metal2 s 347346 178585 347346 178585 4 u_riscv_top.wbd_dmem_dat_i\[3\]
+port 3370 nsew
+rlabel metal2 s 346702 177633 346702 177633 4 u_riscv_top.wbd_dmem_dat_i\[4\]
+port 3371 nsew
+rlabel metal2 s 347346 177531 347346 177531 4 u_riscv_top.wbd_dmem_dat_i\[5\]
+port 3372 nsew
+rlabel metal2 s 347714 177463 347714 177463 4 u_riscv_top.wbd_dmem_dat_i\[6\]
+port 3373 nsew
+rlabel metal2 s 347622 177293 347622 177293 4 u_riscv_top.wbd_dmem_dat_i\[7\]
+port 3374 nsew
+rlabel metal2 s 347162 177225 347162 177225 4 u_riscv_top.wbd_dmem_dat_i\[8\]
+port 3375 nsew
+rlabel metal2 s 347346 176307 347346 176307 4 u_riscv_top.wbd_dmem_dat_i\[9\]
+port 3376 nsew
+rlabel metal2 s 347622 170459 347622 170459 4 u_riscv_top.wbd_dmem_dat_o\[0\]
+port 3377 nsew
+rlabel metal2 s 347714 167671 347714 167671 4 u_riscv_top.wbd_dmem_dat_o\[10\]
+port 3378 nsew
+rlabel metal2 s 347346 167637 347346 167637 4 u_riscv_top.wbd_dmem_dat_o\[11\]
+port 3379 nsew
+rlabel metal2 s 346886 167433 346886 167433 4 u_riscv_top.wbd_dmem_dat_o\[12\]
+port 3380 nsew
+rlabel metal2 s 347622 166685 347622 166685 4 u_riscv_top.wbd_dmem_dat_o\[13\]
+port 3381 nsew
+rlabel metal3 s 347714 166515 347714 166515 4 u_riscv_top.wbd_dmem_dat_o\[14\]
+port 3382 nsew
+rlabel metal2 s 347714 166311 347714 166311 4 u_riscv_top.wbd_dmem_dat_o\[15\]
+port 3383 nsew
+rlabel metal2 s 347622 166141 347622 166141 4 u_riscv_top.wbd_dmem_dat_o\[16\]
+port 3384 nsew
+rlabel metal2 s 346886 166073 346886 166073 4 u_riscv_top.wbd_dmem_dat_o\[17\]
+port 3385 nsew
+rlabel metal2 s 347346 165223 347346 165223 4 u_riscv_top.wbd_dmem_dat_o\[18\]
+port 3386 nsew
+rlabel metal2 s 347714 165121 347714 165121 4 u_riscv_top.wbd_dmem_dat_o\[19\]
+port 3387 nsew
+rlabel metal2 s 347714 170221 347714 170221 4 u_riscv_top.wbd_dmem_dat_o\[1\]
+port 3388 nsew
+rlabel metal3 s 347714 164883 347714 164883 4 u_riscv_top.wbd_dmem_dat_o\[20\]
+port 3389 nsew
+rlabel metal2 s 347622 164781 347622 164781 4 u_riscv_top.wbd_dmem_dat_o\[21\]
+port 3390 nsew
+rlabel metal2 s 346794 164747 346794 164747 4 u_riscv_top.wbd_dmem_dat_o\[22\]
+port 3391 nsew
+rlabel metal2 s 347622 163931 347622 163931 4 u_riscv_top.wbd_dmem_dat_o\[23\]
+port 3392 nsew
+rlabel metal2 s 347714 163761 347714 163761 4 u_riscv_top.wbd_dmem_dat_o\[24\]
+port 3393 nsew
+rlabel metal2 s 347622 163591 347622 163591 4 u_riscv_top.wbd_dmem_dat_o\[25\]
+port 3394 nsew
+rlabel metal2 s 347714 163387 347714 163387 4 u_riscv_top.wbd_dmem_dat_o\[26\]
+port 3395 nsew
+rlabel metal2 s 347346 163285 347346 163285 4 u_riscv_top.wbd_dmem_dat_o\[27\]
+port 3396 nsew
+rlabel metal2 s 346610 162537 346610 162537 4 u_riscv_top.wbd_dmem_dat_o\[28\]
+port 3397 nsew
+rlabel metal2 s 347346 162299 347346 162299 4 u_riscv_top.wbd_dmem_dat_o\[29\]
+port 3398 nsew
+rlabel metal2 s 347162 170153 347162 170153 4 u_riscv_top.wbd_dmem_dat_o\[2\]
+port 3399 nsew
+rlabel metal2 s 347714 162231 347714 162231 4 u_riscv_top.wbd_dmem_dat_o\[30\]
+port 3400 nsew
+rlabel metal2 s 346518 162163 346518 162163 4 u_riscv_top.wbd_dmem_dat_o\[31\]
+port 3401 nsew
+rlabel metal2 s 346610 169337 346610 169337 4 u_riscv_top.wbd_dmem_dat_o\[3\]
+port 3402 nsew
+rlabel metal3 s 347714 169235 347714 169235 4 u_riscv_top.wbd_dmem_dat_o\[4\]
+port 3403 nsew
+rlabel metal3 s 347714 168997 347714 168997 4 u_riscv_top.wbd_dmem_dat_o\[5\]
+port 3404 nsew
+rlabel metal2 s 347346 168997 347346 168997 4 u_riscv_top.wbd_dmem_dat_o\[6\]
+port 3405 nsew
+rlabel metal2 s 347622 168759 347622 168759 4 u_riscv_top.wbd_dmem_dat_o\[7\]
+port 3406 nsew
+rlabel metal2 s 347714 168011 347714 168011 4 u_riscv_top.wbd_dmem_dat_o\[8\]
+port 3407 nsew
+rlabel metal2 s 347622 167773 347622 167773 4 u_riscv_top.wbd_dmem_dat_o\[9\]
+port 3408 nsew
+rlabel metal2 s 347714 179979 347714 179979 4 u_riscv_top.wbd_dmem_err_i
+port 3409 nsew
+rlabel metal2 s 346794 178993 346794 178993 4 u_riscv_top.wbd_dmem_lack_i
+port 3410 nsew
+rlabel metal2 s 347346 160701 347346 160701 4 u_riscv_top.wbd_dmem_sel_o\[0\]
+port 3411 nsew
+rlabel metal2 s 346886 160497 346886 160497 4 u_riscv_top.wbd_dmem_sel_o\[1\]
+port 3412 nsew
+rlabel metal2 s 347346 159715 347346 159715 4 u_riscv_top.wbd_dmem_sel_o\[2\]
+port 3413 nsew
+rlabel metal2 s 346518 159545 346518 159545 4 u_riscv_top.wbd_dmem_sel_o\[3\]
+port 3414 nsew
+rlabel metal2 s 347714 149957 347714 149957 4 u_riscv_top.wbd_dmem_stb_o
+port 3415 nsew
+rlabel metal2 s 347346 150977 347346 150977 4 u_riscv_top.wbd_dmem_we_o
+port 3416 nsew
+rlabel metal3 s 449926 200260 449926 200260 4 uart_rst_n\[0\]
+port 3417 nsew
+rlabel metal3 s 449926 200532 449926 200532 4 uart_rst_n\[1\]
+port 3418 nsew
+rlabel metal2 s 451214 361206 451214 361206 4 uart_rxd\[0\]
+port 3419 nsew
+rlabel metal2 s 451582 360934 451582 360934 4 uart_rxd\[1\]
+port 3420 nsew
+rlabel metal2 s 451398 360832 451398 360832 4 uart_txd\[0\]
+port 3421 nsew
+rlabel metal2 s 451766 360900 451766 360900 4 uart_txd\[1\]
+port 3422 nsew
+rlabel metal2 s 446430 229500 446430 229500 4 uartm_rxd
+port 3423 nsew
+rlabel metal2 s 443670 229024 443670 229024 4 uartm_txd
+port 3424 nsew
+rlabel metal2 s 450057 200668 450057 200668 4 usb_clk
+port 3425 nsew
+rlabel metal2 s 452134 360866 452134 360866 4 usb_dn_i
+port 3426 nsew
+rlabel metal2 s 452502 360798 452502 360798 4 usb_dn_o
+port 3427 nsew
+rlabel metal2 s 451950 361070 451950 361070 4 usb_dp_i
+port 3428 nsew
+rlabel metal2 s 452318 361002 452318 361002 4 usb_dp_o
+port 3429 nsew
+rlabel metal2 s 453054 361138 453054 361138 4 usb_intr_o
+port 3430 nsew
+rlabel metal2 s 452686 361240 452686 361240 4 usb_oen
+port 3431 nsew
+rlabel metal3 s 450386 200668 450386 200668 4 usb_rst_n
+port 3432 nsew
+rlabel metal2 s 520214 2924 520214 2924 4 user_clock2
+port 3433 nsew
+rlabel metal2 s 581026 1962 581026 1962 4 user_irq[0]
+port 3434 nsew
+rlabel metal2 s 582222 1894 582222 1894 4 user_irq[1]
+port 3435 nsew
+rlabel metal2 s 559590 193817 559590 193817 4 user_irq[2]
+port 3436 nsew
+rlabel metal2 s 598 1588 598 1588 4 wb_clk_i
+port 3437 nsew
+rlabel metal2 s 1702 1690 1702 1690 4 wb_rst_i
+port 3438 nsew
+rlabel metal2 s 383870 130009 383870 130009 4 wbd_clk_int
+port 3439 nsew
+rlabel metal3 s 438112 580788 438112 580788 4 wbd_clk_peri_rp
+port 3440 nsew
+rlabel metal3 s 439170 580516 439170 580516 4 wbd_clk_peri_skew
+port 3441 nsew
+rlabel metal2 s 447350 430117 447350 430117 4 wbd_clk_pinmux_rp
+port 3442 nsew
+rlabel metal3 s 449236 430644 449236 430644 4 wbd_clk_pinmux_skew
+port 3443 nsew
+rlabel metal2 s 447350 132107 447350 132107 4 wbd_clk_qspi_rp
+port 3444 nsew
+rlabel metal3 s 450156 132804 450156 132804 4 wbd_clk_spi
+port 3445 nsew
+rlabel metal2 s 447166 261409 447166 261409 4 wbd_clk_uart_rp
+port 3446 nsew
+rlabel metal3 s 450156 261732 450156 261732 4 wbd_clk_uart_skew
+port 3447 nsew
+rlabel metal2 s 383640 105815 383640 105815 4 wbd_clk_wh
+port 3448 nsew
+rlabel metal2 s 384376 130009 384376 130009 4 wbd_clk_wi_skew
+port 3449 nsew
+rlabel metal2 s 447166 454427 447166 454427 4 wbd_glbl_ack_i
+port 3450 nsew
+rlabel metal3 s 447166 435387 447166 435387 4 wbd_glbl_adr_o\[0\]
+port 3451 nsew
+rlabel metal2 s 447166 432633 447166 432633 4 wbd_glbl_adr_o\[10\]
+port 3452 nsew
+rlabel metal2 s 447350 435387 447350 435387 4 wbd_glbl_adr_o\[1\]
+port 3453 nsew
+rlabel metal2 s 447442 435217 447442 435217 4 wbd_glbl_adr_o\[2\]
+port 3454 nsew
+rlabel metal2 s 447442 434333 447442 434333 4 wbd_glbl_adr_o\[3\]
+port 3455 nsew
+rlabel metal3 s 447166 434299 447166 434299 4 wbd_glbl_adr_o\[4\]
+port 3456 nsew
+rlabel metal2 s 447166 434095 447166 434095 4 wbd_glbl_adr_o\[5\]
+port 3457 nsew
+rlabel metal2 s 447350 433993 447350 433993 4 wbd_glbl_adr_o\[6\]
+port 3458 nsew
+rlabel metal2 s 447258 433755 447258 433755 4 wbd_glbl_adr_o\[7\]
+port 3459 nsew
+rlabel metal2 s 447258 433007 447258 433007 4 wbd_glbl_adr_o\[8\]
+port 3460 nsew
+rlabel metal2 s 447166 432905 447166 432905 4 wbd_glbl_adr_o\[9\]
+port 3461 nsew
+rlabel metal2 s 447442 453645 447442 453645 4 wbd_glbl_dat_i\[0\]
+port 3462 nsew
+rlabel metal2 s 447166 450959 447166 450959 4 wbd_glbl_dat_i\[10\]
+port 3463 nsew
+rlabel metal2 s 447350 450721 447350 450721 4 wbd_glbl_dat_i\[11\]
+port 3464 nsew
+rlabel metal3 s 447166 450619 447166 450619 4 wbd_glbl_dat_i\[12\]
+port 3465 nsew
+rlabel metal2 s 447258 450517 447258 450517 4 wbd_glbl_dat_i\[13\]
+port 3466 nsew
+rlabel metal2 s 447442 450449 447442 450449 4 wbd_glbl_dat_i\[14\]
+port 3467 nsew
+rlabel metal2 s 447442 449497 447442 449497 4 wbd_glbl_dat_i\[15\]
+port 3468 nsew
+rlabel metal2 s 447258 449395 447258 449395 4 wbd_glbl_dat_i\[16\]
+port 3469 nsew
+rlabel metal3 s 447166 449293 447166 449293 4 wbd_glbl_dat_i\[17\]
+port 3470 nsew
+rlabel metal2 s 447350 449191 447350 449191 4 wbd_glbl_dat_i\[18\]
+port 3471 nsew
+rlabel metal2 s 447534 449089 447534 449089 4 wbd_glbl_dat_i\[19\]
+port 3472 nsew
+rlabel metal2 s 447166 453577 447166 453577 4 wbd_glbl_dat_i\[1\]
+port 3473 nsew
+rlabel metal2 s 447442 448137 447442 448137 4 wbd_glbl_dat_i\[20\]
+port 3474 nsew
+rlabel metal2 s 447166 448137 447166 448137 4 wbd_glbl_dat_i\[21\]
+port 3475 nsew
+rlabel metal2 s 447258 447967 447258 447967 4 wbd_glbl_dat_i\[22\]
+port 3476 nsew
+rlabel metal2 s 447350 447797 447350 447797 4 wbd_glbl_dat_i\[23\]
+port 3477 nsew
+rlabel metal2 s 447166 447627 447166 447627 4 wbd_glbl_dat_i\[24\]
+port 3478 nsew
+rlabel metal2 s 447626 446743 447626 446743 4 wbd_glbl_dat_i\[25\]
+port 3479 nsew
+rlabel metal2 s 447258 446641 447258 446641 4 wbd_glbl_dat_i\[26\]
+port 3480 nsew
+rlabel metal3 s 447166 446539 447166 446539 4 wbd_glbl_dat_i\[27\]
+port 3481 nsew
+rlabel metal2 s 447350 446505 447350 446505 4 wbd_glbl_dat_i\[28\]
+port 3482 nsew
+rlabel metal2 s 447442 446335 447442 446335 4 wbd_glbl_dat_i\[29\]
+port 3483 nsew
+rlabel metal2 s 447258 453475 447258 453475 4 wbd_glbl_dat_i\[2\]
+port 3484 nsew
+rlabel metal2 s 447534 446165 447534 446165 4 wbd_glbl_dat_i\[30\]
+port 3485 nsew
+rlabel metal2 s 447258 445349 447258 445349 4 wbd_glbl_dat_i\[31\]
+port 3486 nsew
+rlabel metal2 s 447350 453271 447350 453271 4 wbd_glbl_dat_i\[3\]
+port 3487 nsew
+rlabel metal2 s 447166 453067 447166 453067 4 wbd_glbl_dat_i\[4\]
+port 3488 nsew
+rlabel metal2 s 447258 452319 447258 452319 4 wbd_glbl_dat_i\[5\]
+port 3489 nsew
+rlabel metal2 s 447350 452081 447350 452081 4 wbd_glbl_dat_i\[6\]
+port 3490 nsew
+rlabel metal3 s 447166 452013 447166 452013 4 wbd_glbl_dat_i\[7\]
+port 3491 nsew
+rlabel metal2 s 447258 451843 447258 451843 4 wbd_glbl_dat_i\[8\]
+port 3492 nsew
+rlabel metal2 s 447442 451809 447442 451809 4 wbd_glbl_dat_i\[9\]
+port 3493 nsew
+rlabel metal2 s 447166 445247 447166 445247 4 wbd_glbl_dat_o\[0\]
+port 3494 nsew
+rlabel metal2 s 447258 442357 447258 442357 4 wbd_glbl_dat_o\[10\]
+port 3495 nsew
+rlabel metal2 s 447350 442323 447350 442323 4 wbd_glbl_dat_o\[11\]
+port 3496 nsew
+rlabel metal2 s 447166 442119 447166 442119 4 wbd_glbl_dat_o\[12\]
+port 3497 nsew
+rlabel metal2 s 447442 442017 447442 442017 4 wbd_glbl_dat_o\[13\]
+port 3498 nsew
+rlabel metal2 s 447166 441269 447166 441269 4 wbd_glbl_dat_o\[14\]
+port 3499 nsew
+rlabel metal2 s 447258 441065 447258 441065 4 wbd_glbl_dat_o\[15\]
+port 3500 nsew
+rlabel metal2 s 447350 440963 447350 440963 4 wbd_glbl_dat_o\[16\]
+port 3501 nsew
+rlabel metal2 s 447166 440725 447166 440725 4 wbd_glbl_dat_o\[17\]
+port 3502 nsew
+rlabel metal2 s 447442 440623 447442 440623 4 wbd_glbl_dat_o\[18\]
+port 3503 nsew
+rlabel metal2 s 447350 439807 447350 439807 4 wbd_glbl_dat_o\[19\]
+port 3504 nsew
+rlabel metal2 s 447166 445009 447166 445009 4 wbd_glbl_dat_o\[1\]
+port 3505 nsew
+rlabel metal2 s 447166 439705 447166 439705 4 wbd_glbl_dat_o\[20\]
+port 3506 nsew
+rlabel metal2 s 447258 439603 447258 439603 4 wbd_glbl_dat_o\[21\]
+port 3507 nsew
+rlabel metal2 s 447166 439365 447166 439365 4 wbd_glbl_dat_o\[22\]
+port 3508 nsew
+rlabel metal2 s 447442 439365 447442 439365 4 wbd_glbl_dat_o\[23\]
+port 3509 nsew
+rlabel metal2 s 447258 438549 447258 438549 4 wbd_glbl_dat_o\[24\]
+port 3510 nsew
+rlabel metal3 s 447166 438379 447166 438379 4 wbd_glbl_dat_o\[25\]
+port 3511 nsew
+rlabel metal2 s 447258 438209 447258 438209 4 wbd_glbl_dat_o\[26\]
+port 3512 nsew
+rlabel metal2 s 447166 438005 447166 438005 4 wbd_glbl_dat_o\[27\]
+port 3513 nsew
+rlabel metal2 s 447350 437903 447350 437903 4 wbd_glbl_dat_o\[28\]
+port 3514 nsew
+rlabel metal2 s 447350 437121 447350 437121 4 wbd_glbl_dat_o\[29\]
+port 3515 nsew
+rlabel metal2 s 447350 444907 447350 444907 4 wbd_glbl_dat_o\[2\]
+port 3516 nsew
+rlabel metal3 s 447166 437019 447166 437019 4 wbd_glbl_dat_o\[30\]
+port 3517 nsew
+rlabel metal2 s 447258 436815 447258 436815 4 wbd_glbl_dat_o\[31\]
+port 3518 nsew
+rlabel metal2 s 447258 444703 447258 444703 4 wbd_glbl_dat_o\[3\]
+port 3519 nsew
+rlabel metal2 s 447442 443887 447442 443887 4 wbd_glbl_dat_o\[4\]
+port 3520 nsew
+rlabel metal3 s 447166 443819 447166 443819 4 wbd_glbl_dat_o\[5\]
+port 3521 nsew
+rlabel metal2 s 447350 443717 447350 443717 4 wbd_glbl_dat_o\[6\]
+port 3522 nsew
+rlabel metal2 s 447258 443513 447258 443513 4 wbd_glbl_dat_o\[7\]
+port 3523 nsew
+rlabel metal2 s 447534 443479 447534 443479 4 wbd_glbl_dat_o\[8\]
+port 3524 nsew
+rlabel metal2 s 447166 442629 447166 442629 4 wbd_glbl_dat_o\[9\]
+port 3525 nsew
+rlabel metal2 s 447166 436611 447166 436611 4 wbd_glbl_sel_o\[0\]
+port 3526 nsew
+rlabel metal2 s 447350 436509 447350 436509 4 wbd_glbl_sel_o\[1\]
+port 3527 nsew
+rlabel metal2 s 447258 435693 447258 435693 4 wbd_glbl_sel_o\[2\]
+port 3528 nsew
+rlabel metal2 s 447166 435591 447166 435591 4 wbd_glbl_sel_o\[3\]
+port 3529 nsew
+rlabel metal2 s 447350 432429 447350 432429 4 wbd_glbl_stb_o
+port 3530 nsew
+rlabel metal2 s 447258 432531 447258 432531 4 wbd_glbl_we_o
+port 3531 nsew
+rlabel metal2 s 408848 105883 408848 105883 4 wbd_int_ack_o
+port 3532 nsew
+rlabel metal2 s 396152 105883 396152 105883 4 wbd_int_adr_i\[0\]
+port 3533 nsew
+rlabel metal2 s 394312 105883 394312 105883 4 wbd_int_adr_i\[10\]
+port 3534 nsew
+rlabel metal2 s 394128 105883 394128 105883 4 wbd_int_adr_i\[11\]
+port 3535 nsew
+rlabel metal2 s 393944 105883 393944 105883 4 wbd_int_adr_i\[12\]
+port 3536 nsew
+rlabel metal2 s 393760 105866 393760 105866 4 wbd_int_adr_i\[13\]
+port 3537 nsew
+rlabel metal2 s 393576 105883 393576 105883 4 wbd_int_adr_i\[14\]
+port 3538 nsew
+rlabel metal2 s 393392 105883 393392 105883 4 wbd_int_adr_i\[15\]
+port 3539 nsew
+rlabel metal2 s 393208 105883 393208 105883 4 wbd_int_adr_i\[16\]
+port 3540 nsew
+rlabel metal2 s 393024 105883 393024 105883 4 wbd_int_adr_i\[17\]
+port 3541 nsew
+rlabel metal2 s 392840 105883 392840 105883 4 wbd_int_adr_i\[18\]
+port 3542 nsew
+rlabel metal2 s 392656 105883 392656 105883 4 wbd_int_adr_i\[19\]
+port 3543 nsew
+rlabel metal2 s 395968 105883 395968 105883 4 wbd_int_adr_i\[1\]
+port 3544 nsew
+rlabel metal2 s 392472 105883 392472 105883 4 wbd_int_adr_i\[20\]
+port 3545 nsew
+rlabel metal2 s 392288 105883 392288 105883 4 wbd_int_adr_i\[21\]
+port 3546 nsew
+rlabel metal2 s 392104 105866 392104 105866 4 wbd_int_adr_i\[22\]
+port 3547 nsew
+rlabel metal2 s 391920 105883 391920 105883 4 wbd_int_adr_i\[23\]
+port 3548 nsew
+rlabel metal2 s 391736 105883 391736 105883 4 wbd_int_adr_i\[24\]
+port 3549 nsew
+rlabel metal2 s 391552 105883 391552 105883 4 wbd_int_adr_i\[25\]
+port 3550 nsew
+rlabel metal2 s 391368 105883 391368 105883 4 wbd_int_adr_i\[26\]
+port 3551 nsew
+rlabel metal2 s 391184 105883 391184 105883 4 wbd_int_adr_i\[27\]
+port 3552 nsew
+rlabel metal2 s 391000 105883 391000 105883 4 wbd_int_adr_i\[28\]
+port 3553 nsew
+rlabel metal2 s 390816 105883 390816 105883 4 wbd_int_adr_i\[29\]
+port 3554 nsew
+rlabel metal2 s 395784 105883 395784 105883 4 wbd_int_adr_i\[2\]
+port 3555 nsew
+rlabel metal2 s 390632 105883 390632 105883 4 wbd_int_adr_i\[30\]
+port 3556 nsew
+rlabel metal2 s 390448 105883 390448 105883 4 wbd_int_adr_i\[31\]
+port 3557 nsew
+rlabel metal2 s 395600 105883 395600 105883 4 wbd_int_adr_i\[3\]
+port 3558 nsew
+rlabel metal2 s 395416 105883 395416 105883 4 wbd_int_adr_i\[4\]
+port 3559 nsew
+rlabel metal2 s 395232 105866 395232 105866 4 wbd_int_adr_i\[5\]
+port 3560 nsew
+rlabel metal2 s 395048 105866 395048 105866 4 wbd_int_adr_i\[6\]
+port 3561 nsew
+rlabel metal2 s 394864 105883 394864 105883 4 wbd_int_adr_i\[7\]
+port 3562 nsew
+rlabel metal2 s 394680 105883 394680 105883 4 wbd_int_adr_i\[8\]
+port 3563 nsew
+rlabel metal2 s 394496 105883 394496 105883 4 wbd_int_adr_i\[9\]
+port 3564 nsew
+rlabel metal2 s 409292 105740 409292 105740 4 wbd_int_cyc_i
+port 3565 nsew
+rlabel metal2 s 402776 105883 402776 105883 4 wbd_int_dat_i\[0\]
+port 3566 nsew
+rlabel metal2 s 400936 105883 400936 105883 4 wbd_int_dat_i\[10\]
+port 3567 nsew
+rlabel metal2 s 400752 105883 400752 105883 4 wbd_int_dat_i\[11\]
+port 3568 nsew
+rlabel metal2 s 400568 105883 400568 105883 4 wbd_int_dat_i\[12\]
+port 3569 nsew
+rlabel metal2 s 400384 105883 400384 105883 4 wbd_int_dat_i\[13\]
+port 3570 nsew
+rlabel metal2 s 400200 105883 400200 105883 4 wbd_int_dat_i\[14\]
+port 3571 nsew
+rlabel metal2 s 400016 105883 400016 105883 4 wbd_int_dat_i\[15\]
+port 3572 nsew
+rlabel metal2 s 399832 105883 399832 105883 4 wbd_int_dat_i\[16\]
+port 3573 nsew
+rlabel metal2 s 399648 105883 399648 105883 4 wbd_int_dat_i\[17\]
+port 3574 nsew
+rlabel metal2 s 399464 105883 399464 105883 4 wbd_int_dat_i\[18\]
+port 3575 nsew
+rlabel metal2 s 399280 105866 399280 105866 4 wbd_int_dat_i\[19\]
+port 3576 nsew
+rlabel metal2 s 402592 105883 402592 105883 4 wbd_int_dat_i\[1\]
+port 3577 nsew
+rlabel metal2 s 399096 105883 399096 105883 4 wbd_int_dat_i\[20\]
+port 3578 nsew
+rlabel metal2 s 398912 105883 398912 105883 4 wbd_int_dat_i\[21\]
+port 3579 nsew
+rlabel metal2 s 398728 105883 398728 105883 4 wbd_int_dat_i\[22\]
+port 3580 nsew
+rlabel metal2 s 398544 105883 398544 105883 4 wbd_int_dat_i\[23\]
+port 3581 nsew
+rlabel metal2 s 398360 105883 398360 105883 4 wbd_int_dat_i\[24\]
+port 3582 nsew
+rlabel metal2 s 398176 105883 398176 105883 4 wbd_int_dat_i\[25\]
+port 3583 nsew
+rlabel metal2 s 397992 105866 397992 105866 4 wbd_int_dat_i\[26\]
+port 3584 nsew
+rlabel metal2 s 397808 105883 397808 105883 4 wbd_int_dat_i\[27\]
+port 3585 nsew
+rlabel metal2 s 397624 105883 397624 105883 4 wbd_int_dat_i\[28\]
+port 3586 nsew
+rlabel metal2 s 397440 105883 397440 105883 4 wbd_int_dat_i\[29\]
+port 3587 nsew
+rlabel metal2 s 402408 105883 402408 105883 4 wbd_int_dat_i\[2\]
+port 3588 nsew
+rlabel metal2 s 397256 105883 397256 105883 4 wbd_int_dat_i\[30\]
+port 3589 nsew
+rlabel metal2 s 397072 105883 397072 105883 4 wbd_int_dat_i\[31\]
+port 3590 nsew
+rlabel metal2 s 402224 105883 402224 105883 4 wbd_int_dat_i\[3\]
+port 3591 nsew
+rlabel metal2 s 402040 105866 402040 105866 4 wbd_int_dat_i\[4\]
+port 3592 nsew
+rlabel metal2 s 401856 105883 401856 105883 4 wbd_int_dat_i\[5\]
+port 3593 nsew
+rlabel metal2 s 401672 105883 401672 105883 4 wbd_int_dat_i\[6\]
+port 3594 nsew
+rlabel metal2 s 401488 105883 401488 105883 4 wbd_int_dat_i\[7\]
+port 3595 nsew
+rlabel metal2 s 401304 105883 401304 105883 4 wbd_int_dat_i\[8\]
+port 3596 nsew
+rlabel metal2 s 401120 105883 401120 105883 4 wbd_int_dat_i\[9\]
+port 3597 nsew
+rlabel metal2 s 408664 105883 408664 105883 4 wbd_int_dat_o\[0\]
+port 3598 nsew
+rlabel metal2 s 406824 105883 406824 105883 4 wbd_int_dat_o\[10\]
+port 3599 nsew
+rlabel metal2 s 406640 105883 406640 105883 4 wbd_int_dat_o\[11\]
+port 3600 nsew
+rlabel metal2 s 406456 105883 406456 105883 4 wbd_int_dat_o\[12\]
+port 3601 nsew
+rlabel metal2 s 406272 105866 406272 105866 4 wbd_int_dat_o\[13\]
+port 3602 nsew
+rlabel metal2 s 406088 105815 406088 105815 4 wbd_int_dat_o\[14\]
+port 3603 nsew
+rlabel metal2 s 405904 105883 405904 105883 4 wbd_int_dat_o\[15\]
+port 3604 nsew
+rlabel metal2 s 405720 105883 405720 105883 4 wbd_int_dat_o\[16\]
+port 3605 nsew
+rlabel metal2 s 405536 105883 405536 105883 4 wbd_int_dat_o\[17\]
+port 3606 nsew
+rlabel metal2 s 405352 105883 405352 105883 4 wbd_int_dat_o\[18\]
+port 3607 nsew
+rlabel metal2 s 405168 105883 405168 105883 4 wbd_int_dat_o\[19\]
+port 3608 nsew
+rlabel metal2 s 408480 105883 408480 105883 4 wbd_int_dat_o\[1\]
+port 3609 nsew
+rlabel metal2 s 404984 105883 404984 105883 4 wbd_int_dat_o\[20\]
+port 3610 nsew
+rlabel metal2 s 404800 105883 404800 105883 4 wbd_int_dat_o\[21\]
+port 3611 nsew
+rlabel metal2 s 404616 105883 404616 105883 4 wbd_int_dat_o\[22\]
+port 3612 nsew
+rlabel metal2 s 404432 105883 404432 105883 4 wbd_int_dat_o\[23\]
+port 3613 nsew
+rlabel metal2 s 404248 105883 404248 105883 4 wbd_int_dat_o\[24\]
+port 3614 nsew
+rlabel metal2 s 404064 105883 404064 105883 4 wbd_int_dat_o\[25\]
+port 3615 nsew
+rlabel metal2 s 403880 105883 403880 105883 4 wbd_int_dat_o\[26\]
+port 3616 nsew
+rlabel metal2 s 403696 105883 403696 105883 4 wbd_int_dat_o\[27\]
+port 3617 nsew
+rlabel metal2 s 403512 105866 403512 105866 4 wbd_int_dat_o\[28\]
+port 3618 nsew
+rlabel metal2 s 403328 105883 403328 105883 4 wbd_int_dat_o\[29\]
+port 3619 nsew
+rlabel metal2 s 408296 105883 408296 105883 4 wbd_int_dat_o\[2\]
+port 3620 nsew
+rlabel metal2 s 403144 105883 403144 105883 4 wbd_int_dat_o\[30\]
+port 3621 nsew
+rlabel metal2 s 402960 105883 402960 105883 4 wbd_int_dat_o\[31\]
+port 3622 nsew
+rlabel metal2 s 408112 105883 408112 105883 4 wbd_int_dat_o\[3\]
+port 3623 nsew
+rlabel metal2 s 407928 105883 407928 105883 4 wbd_int_dat_o\[4\]
+port 3624 nsew
+rlabel metal2 s 407744 105866 407744 105866 4 wbd_int_dat_o\[5\]
+port 3625 nsew
+rlabel metal2 s 407560 105883 407560 105883 4 wbd_int_dat_o\[6\]
+port 3626 nsew
+rlabel metal2 s 407376 105815 407376 105815 4 wbd_int_dat_o\[7\]
+port 3627 nsew
+rlabel metal2 s 407192 105883 407192 105883 4 wbd_int_dat_o\[8\]
+port 3628 nsew
+rlabel metal2 s 407008 105883 407008 105883 4 wbd_int_dat_o\[9\]
+port 3629 nsew
+rlabel metal2 s 409032 105883 409032 105883 4 wbd_int_err_o
+port 3630 nsew
+rlabel metal2 s 396888 105883 396888 105883 4 wbd_int_sel_i\[0\]
+port 3631 nsew
+rlabel metal2 s 396704 105883 396704 105883 4 wbd_int_sel_i\[1\]
+port 3632 nsew
+rlabel metal2 s 396520 105866 396520 105866 4 wbd_int_sel_i\[2\]
+port 3633 nsew
+rlabel metal2 s 396336 105883 396336 105883 4 wbd_int_sel_i\[3\]
+port 3634 nsew
+rlabel metal2 s 390080 105883 390080 105883 4 wbd_int_stb_i
+port 3635 nsew
+rlabel metal2 s 390264 105883 390264 105883 4 wbd_int_we_i
+port 3636 nsew
+rlabel metal2 s 449190 525062 449190 525062 4 wbd_pll_rst_n
+port 3637 nsew
+rlabel metal2 s 447166 170731 447166 170731 4 wbd_spim_ack_i
+port 3638 nsew
+rlabel metal2 s 447442 149515 447442 149515 4 wbd_spim_adr_o\[0\]
+port 3639 nsew
+rlabel metal2 s 447350 146761 447350 146761 4 wbd_spim_adr_o\[10\]
+port 3640 nsew
+rlabel metal2 s 447258 145911 447258 145911 4 wbd_spim_adr_o\[11\]
+port 3641 nsew
+rlabel metal2 s 447350 145707 447350 145707 4 wbd_spim_adr_o\[12\]
+port 3642 nsew
+rlabel metal3 s 447166 145605 447166 145605 4 wbd_spim_adr_o\[13\]
+port 3643 nsew
+rlabel metal2 s 447442 145571 447442 145571 4 wbd_spim_adr_o\[14\]
+port 3644 nsew
+rlabel metal2 s 447534 145401 447534 145401 4 wbd_spim_adr_o\[15\]
+port 3645 nsew
+rlabel metal2 s 447166 144585 447166 144585 4 wbd_spim_adr_o\[16\]
+port 3646 nsew
+rlabel metal2 s 447258 144415 447258 144415 4 wbd_spim_adr_o\[17\]
+port 3647 nsew
+rlabel metal3 s 447166 144245 447166 144245 4 wbd_spim_adr_o\[18\]
+port 3648 nsew
+rlabel metal2 s 447258 144075 447258 144075 4 wbd_spim_adr_o\[19\]
+port 3649 nsew
+rlabel metal2 s 447166 148733 447166 148733 4 wbd_spim_adr_o\[1\]
+port 3650 nsew
+rlabel metal2 s 447350 144075 447350 144075 4 wbd_spim_adr_o\[20\]
+port 3651 nsew
+rlabel metal2 s 447258 143157 447258 143157 4 wbd_spim_adr_o\[21\]
+port 3652 nsew
+rlabel metal2 s 447350 142987 447350 142987 4 wbd_spim_adr_o\[22\]
+port 3653 nsew
+rlabel metal2 s 447166 142919 447166 142919 4 wbd_spim_adr_o\[23\]
+port 3654 nsew
+rlabel metal2 s 447442 142851 447442 142851 4 wbd_spim_adr_o\[24\]
+port 3655 nsew
+rlabel metal2 s 447534 142681 447534 142681 4 wbd_spim_adr_o\[25\]
+port 3656 nsew
+rlabel metal2 s 447258 141831 447258 141831 4 wbd_spim_adr_o\[26\]
+port 3657 nsew
+rlabel metal2 s 447350 141593 447350 141593 4 wbd_spim_adr_o\[27\]
+port 3658 nsew
+rlabel metal3 s 447166 141525 447166 141525 4 wbd_spim_adr_o\[28\]
+port 3659 nsew
+rlabel metal2 s 447258 141355 447258 141355 4 wbd_spim_adr_o\[29\]
+port 3660 nsew
+rlabel metal2 s 447258 148529 447258 148529 4 wbd_spim_adr_o\[2\]
+port 3661 nsew
+rlabel metal2 s 447442 141321 447442 141321 4 wbd_spim_adr_o\[30\]
+port 3662 nsew
+rlabel metal2 s 447350 140403 447350 140403 4 wbd_spim_adr_o\[31\]
+port 3663 nsew
+rlabel metal2 s 447350 148427 447350 148427 4 wbd_spim_adr_o\[3\]
+port 3664 nsew
+rlabel metal2 s 447166 148223 447166 148223 4 wbd_spim_adr_o\[4\]
+port 3665 nsew
+rlabel metal2 s 447258 148053 447258 148053 4 wbd_spim_adr_o\[5\]
+port 3666 nsew
+rlabel metal2 s 447258 147271 447258 147271 4 wbd_spim_adr_o\[6\]
+port 3667 nsew
+rlabel metal3 s 447166 147203 447166 147203 4 wbd_spim_adr_o\[7\]
+port 3668 nsew
+rlabel metal3 s 447166 146965 447166 146965 4 wbd_spim_adr_o\[8\]
+port 3669 nsew
+rlabel metal2 s 447258 146795 447258 146795 4 wbd_spim_adr_o\[9\]
+port 3670 nsew
+rlabel metal2 s 447258 152745 447258 152745 4 wbd_spim_bl_o\[0\]
+port 3671 nsew
+rlabel metal3 s 447166 152677 447166 152677 4 wbd_spim_bl_o\[1\]
+port 3672 nsew
+rlabel metal2 s 447442 152575 447442 152575 4 wbd_spim_bl_o\[2\]
+port 3673 nsew
+rlabel metal2 s 447166 152303 447166 152303 4 wbd_spim_bl_o\[3\]
+port 3674 nsew
+rlabel metal2 s 447350 152235 447350 152235 4 wbd_spim_bl_o\[4\]
+port 3675 nsew
+rlabel metal2 s 447166 151453 447166 151453 4 wbd_spim_bl_o\[5\]
+port 3676 nsew
+rlabel metal2 s 447258 151249 447258 151249 4 wbd_spim_bl_o\[6\]
+port 3677 nsew
+rlabel metal3 s 447166 151045 447166 151045 4 wbd_spim_bl_o\[7\]
+port 3678 nsew
+rlabel metal2 s 447350 150943 447350 150943 4 wbd_spim_bl_o\[8\]
+port 3679 nsew
+rlabel metal2 s 447442 150875 447442 150875 4 wbd_spim_bl_o\[9\]
+port 3680 nsew
+rlabel metal2 s 447442 153629 447442 153629 4 wbd_spim_bry_o
+port 3681 nsew
+rlabel metal2 s 447258 170493 447258 170493 4 wbd_spim_dat_i\[0\]
+port 3682 nsew
+rlabel metal2 s 447258 167807 447258 167807 4 wbd_spim_dat_i\[10\]
+port 3683 nsew
+rlabel metal3 s 447166 167637 447166 167637 4 wbd_spim_dat_i\[11\]
+port 3684 nsew
+rlabel metal2 s 447442 167637 447442 167637 4 wbd_spim_dat_i\[12\]
+port 3685 nsew
+rlabel metal2 s 447350 167433 447350 167433 4 wbd_spim_dat_i\[13\]
+port 3686 nsew
+rlabel metal2 s 447166 166685 447166 166685 4 wbd_spim_dat_i\[14\]
+port 3687 nsew
+rlabel metal2 s 447258 166447 447258 166447 4 wbd_spim_dat_i\[15\]
+port 3688 nsew
+rlabel metal2 s 447350 166345 447350 166345 4 wbd_spim_dat_i\[16\]
+port 3689 nsew
+rlabel metal2 s 447166 166141 447166 166141 4 wbd_spim_dat_i\[17\]
+port 3690 nsew
+rlabel metal2 s 447442 166107 447442 166107 4 wbd_spim_dat_i\[18\]
+port 3691 nsew
+rlabel metal2 s 447350 165257 447350 165257 4 wbd_spim_dat_i\[19\]
+port 3692 nsew
+rlabel metal2 s 447166 170391 447166 170391 4 wbd_spim_dat_i\[1\]
+port 3693 nsew
+rlabel metal3 s 447166 165155 447166 165155 4 wbd_spim_dat_i\[20\]
+port 3694 nsew
+rlabel metal2 s 447258 164951 447258 164951 4 wbd_spim_dat_i\[21\]
+port 3695 nsew
+rlabel metal2 s 447166 164747 447166 164747 4 wbd_spim_dat_i\[22\]
+port 3696 nsew
+rlabel metal2 s 447350 164645 447350 164645 4 wbd_spim_dat_i\[23\]
+port 3697 nsew
+rlabel metal2 s 447534 163795 447534 163795 4 wbd_spim_dat_i\[24\]
+port 3698 nsew
+rlabel metal2 s 447258 163693 447258 163693 4 wbd_spim_dat_i\[25\]
+port 3699 nsew
+rlabel metal2 s 447166 163591 447166 163591 4 wbd_spim_dat_i\[26\]
+port 3700 nsew
+rlabel metal2 s 447350 163523 447350 163523 4 wbd_spim_dat_i\[27\]
+port 3701 nsew
+rlabel metal2 s 447442 163353 447442 163353 4 wbd_spim_dat_i\[28\]
+port 3702 nsew
+rlabel metal2 s 447258 162503 447258 162503 4 wbd_spim_dat_i\[29\]
+port 3703 nsew
+rlabel metal2 s 447442 170357 447442 170357 4 wbd_spim_dat_i\[2\]
+port 3704 nsew
+rlabel metal2 s 447442 162299 447442 162299 4 wbd_spim_dat_i\[30\]
+port 3705 nsew
+rlabel metal3 s 447166 162197 447166 162197 4 wbd_spim_dat_i\[31\]
+port 3706 nsew
+rlabel metal2 s 447350 170153 447350 170153 4 wbd_spim_dat_i\[3\]
+port 3707 nsew
+rlabel metal2 s 447350 169303 447350 169303 4 wbd_spim_dat_i\[4\]
+port 3708 nsew
+rlabel metal2 s 447166 169133 447166 169133 4 wbd_spim_dat_i\[5\]
+port 3709 nsew
+rlabel metal2 s 447442 169133 447442 169133 4 wbd_spim_dat_i\[6\]
+port 3710 nsew
+rlabel metal2 s 447258 168929 447258 168929 4 wbd_spim_dat_i\[7\]
+port 3711 nsew
+rlabel metal2 s 447534 168827 447534 168827 4 wbd_spim_dat_i\[8\]
+port 3712 nsew
+rlabel metal2 s 447166 168011 447166 168011 4 wbd_spim_dat_i\[9\]
+port 3713 nsew
+rlabel metal2 s 447350 162129 447350 162129 4 wbd_spim_dat_o\[0\]
+port 3714 nsew
+rlabel metal2 s 447258 159307 447258 159307 4 wbd_spim_dat_o\[10\]
+port 3715 nsew
+rlabel metal2 s 447442 159273 447442 159273 4 wbd_spim_dat_o\[11\]
+port 3716 nsew
+rlabel metal2 s 447350 158389 447350 158389 4 wbd_spim_dat_o\[12\]
+port 3717 nsew
+rlabel metal2 s 447534 158185 447534 158185 4 wbd_spim_dat_o\[13\]
+port 3718 nsew
+rlabel metal2 s 447166 158185 447166 158185 4 wbd_spim_dat_o\[14\]
+port 3719 nsew
+rlabel metal2 s 447442 158015 447442 158015 4 wbd_spim_dat_o\[15\]
+port 3720 nsew
+rlabel metal2 s 447258 157811 447258 157811 4 wbd_spim_dat_o\[16\]
+port 3721 nsew
+rlabel metal2 s 447258 157063 447258 157063 4 wbd_spim_dat_o\[17\]
+port 3722 nsew
+rlabel metal2 s 447442 156825 447442 156825 4 wbd_spim_dat_o\[18\]
+port 3723 nsew
+rlabel metal2 s 447166 156825 447166 156825 4 wbd_spim_dat_o\[19\]
+port 3724 nsew
+rlabel metal2 s 447534 162027 447534 162027 4 wbd_spim_dat_o\[1\]
+port 3725 nsew
+rlabel metal2 s 447350 156621 447350 156621 4 wbd_spim_dat_o\[20\]
+port 3726 nsew
+rlabel metal2 s 447258 156451 447258 156451 4 wbd_spim_dat_o\[21\]
+port 3727 nsew
+rlabel metal2 s 447350 155669 447350 155669 4 wbd_spim_dat_o\[22\]
+port 3728 nsew
+rlabel metal2 s 447166 155601 447166 155601 4 wbd_spim_dat_o\[23\]
+port 3729 nsew
+rlabel metal2 s 447258 155431 447258 155431 4 wbd_spim_dat_o\[24\]
+port 3730 nsew
+rlabel metal2 s 447166 155193 447166 155193 4 wbd_spim_dat_o\[25\]
+port 3731 nsew
+rlabel metal2 s 447258 155023 447258 155023 4 wbd_spim_dat_o\[26\]
+port 3732 nsew
+rlabel metal2 s 447442 154955 447442 154955 4 wbd_spim_dat_o\[27\]
+port 3733 nsew
+rlabel metal2 s 447166 154139 447166 154139 4 wbd_spim_dat_o\[28\]
+port 3734 nsew
+rlabel metal2 s 447258 153969 447258 153969 4 wbd_spim_dat_o\[29\]
+port 3735 nsew
+rlabel metal2 s 447442 161041 447442 161041 4 wbd_spim_dat_o\[2\]
+port 3736 nsew
+rlabel metal2 s 447166 153799 447166 153799 4 wbd_spim_dat_o\[30\]
+port 3737 nsew
+rlabel metal2 s 447350 153799 447350 153799 4 wbd_spim_dat_o\[31\]
+port 3738 nsew
+rlabel metal2 s 447258 161007 447258 161007 4 wbd_spim_dat_o\[3\]
+port 3739 nsew
+rlabel metal3 s 447166 160837 447166 160837 4 wbd_spim_dat_o\[4\]
+port 3740 nsew
+rlabel metal2 s 447350 160769 447350 160769 4 wbd_spim_dat_o\[5\]
+port 3741 nsew
+rlabel metal2 s 447258 160531 447258 160531 4 wbd_spim_dat_o\[6\]
+port 3742 nsew
+rlabel metal2 s 447350 159749 447350 159749 4 wbd_spim_dat_o\[7\]
+port 3743 nsew
+rlabel metal2 s 447166 159647 447166 159647 4 wbd_spim_dat_o\[8\]
+port 3744 nsew
+rlabel metal2 s 447166 159409 447166 159409 4 wbd_spim_dat_o\[9\]
+port 3745 nsew
+rlabel metal2 s 447166 171479 447166 171479 4 wbd_spim_lack_i
+port 3746 nsew
+rlabel metal2 s 447350 150025 447350 150025 4 wbd_spim_sel_o\[0\]
+port 3747 nsew
+rlabel metal3 s 447166 149957 447166 149957 4 wbd_spim_sel_o\[1\]
+port 3748 nsew
+rlabel metal3 s 447166 149685 447166 149685 4 wbd_spim_sel_o\[2\]
+port 3749 nsew
+rlabel metal2 s 447258 149583 447258 149583 4 wbd_spim_sel_o\[3\]
+port 3750 nsew
+rlabel metal3 s 447166 140165 447166 140165 4 wbd_spim_stb_o
+port 3751 nsew
+rlabel metal2 s 447258 140233 447258 140233 4 wbd_spim_we_o
+port 3752 nsew
+rlabel metal2 s 447258 301597 447258 301597 4 wbd_uart_ack_i
+port 3753 nsew
+rlabel metal1 s 445694 282880 445694 282880 4 wbd_uart_adr_o\[0\]
+port 3754 nsew
+rlabel metal2 s 447166 282489 447166 282489 4 wbd_uart_adr_o\[1\]
+port 3755 nsew
+rlabel metal2 s 447258 282319 447258 282319 4 wbd_uart_adr_o\[2\]
+port 3756 nsew
+rlabel metal3 s 447166 282149 447166 282149 4 wbd_uart_adr_o\[3\]
+port 3757 nsew
+rlabel metal2 s 447350 282115 447350 282115 4 wbd_uart_adr_o\[4\]
+port 3758 nsew
+rlabel metal1 s 445694 281520 445694 281520 4 wbd_uart_adr_o\[5\]
+port 3759 nsew
+rlabel metal2 s 447258 281095 447258 281095 4 wbd_uart_adr_o\[6\]
+port 3760 nsew
+rlabel metal2 s 447166 280993 447166 280993 4 wbd_uart_adr_o\[7\]
+port 3761 nsew
+rlabel metal3 s 447166 280789 447166 280789 4 wbd_uart_adr_o\[8\]
+port 3762 nsew
+rlabel metal2 s 447166 301495 447166 301495 4 wbd_uart_dat_i\[0\]
+port 3763 nsew
+rlabel metal3 s 447166 298741 447166 298741 4 wbd_uart_dat_i\[10\]
+port 3764 nsew
+rlabel metal2 s 447350 298673 447350 298673 4 wbd_uart_dat_i\[11\]
+port 3765 nsew
+rlabel metal1 s 445694 298112 445694 298112 4 wbd_uart_dat_i\[12\]
+port 3766 nsew
+rlabel metal2 s 447166 297755 447166 297755 4 wbd_uart_dat_i\[13\]
+port 3767 nsew
+rlabel metal2 s 447350 297517 447350 297517 4 wbd_uart_dat_i\[14\]
+port 3768 nsew
+rlabel metal2 s 447258 297449 447258 297449 4 wbd_uart_dat_i\[15\]
+port 3769 nsew
+rlabel metal2 s 447166 297279 447166 297279 4 wbd_uart_dat_i\[16\]
+port 3770 nsew
+rlabel metal1 s 445809 296718 445809 296718 4 wbd_uart_dat_i\[17\]
+port 3771 nsew
+rlabel metal2 s 447350 296361 447350 296361 4 wbd_uart_dat_i\[18\]
+port 3772 nsew
+rlabel metal3 s 447166 296259 447166 296259 4 wbd_uart_dat_i\[19\]
+port 3773 nsew
+rlabel metal2 s 447350 301393 447350 301393 4 wbd_uart_dat_i\[1\]
+port 3774 nsew
+rlabel metal2 s 447258 296055 447258 296055 4 wbd_uart_dat_i\[20\]
+port 3775 nsew
+rlabel metal2 s 447166 295851 447166 295851 4 wbd_uart_dat_i\[21\]
+port 3776 nsew
+rlabel metal2 s 447350 295749 447350 295749 4 wbd_uart_dat_i\[22\]
+port 3777 nsew
+rlabel metal2 s 447166 295001 447166 295001 4 wbd_uart_dat_i\[23\]
+port 3778 nsew
+rlabel metal2 s 447258 294831 447258 294831 4 wbd_uart_dat_i\[24\]
+port 3779 nsew
+rlabel metal3 s 447166 294661 447166 294661 4 wbd_uart_dat_i\[25\]
+port 3780 nsew
+rlabel metal2 s 447258 294491 447258 294491 4 wbd_uart_dat_i\[26\]
+port 3781 nsew
+rlabel metal2 s 447350 294491 447350 294491 4 wbd_uart_dat_i\[27\]
+port 3782 nsew
+rlabel metal2 s 447258 293573 447258 293573 4 wbd_uart_dat_i\[28\]
+port 3783 nsew
+rlabel metal2 s 447166 293471 447166 293471 4 wbd_uart_dat_i\[29\]
+port 3784 nsew
+rlabel metal1 s 445694 300832 445694 300832 4 wbd_uart_dat_i\[2\]
+port 3785 nsew
+rlabel metal3 s 447166 293267 447166 293267 4 wbd_uart_dat_i\[30\]
+port 3786 nsew
+rlabel metal2 s 447350 293267 447350 293267 4 wbd_uart_dat_i\[31\]
+port 3787 nsew
+rlabel metal2 s 447442 300373 447442 300373 4 wbd_uart_dat_i\[3\]
+port 3788 nsew
+rlabel metal2 s 447166 300271 447166 300271 4 wbd_uart_dat_i\[4\]
+port 3789 nsew
+rlabel metal2 s 447258 300203 447258 300203 4 wbd_uart_dat_i\[5\]
+port 3790 nsew
+rlabel metal2 s 447350 300033 447350 300033 4 wbd_uart_dat_i\[6\]
+port 3791 nsew
+rlabel metal1 s 445694 299472 445694 299472 4 wbd_uart_dat_i\[7\]
+port 3792 nsew
+rlabel metal2 s 447166 299115 447166 299115 4 wbd_uart_dat_i\[8\]
+port 3793 nsew
+rlabel metal2 s 447258 298911 447258 298911 4 wbd_uart_dat_i\[9\]
+port 3794 nsew
+rlabel metal2 s 447442 293097 447442 293097 4 wbd_uart_dat_o\[0\]
+port 3795 nsew
+rlabel metal2 s 447258 290309 447258 290309 4 wbd_uart_dat_o\[10\]
+port 3796 nsew
+rlabel metal2 s 447534 289425 447534 289425 4 wbd_uart_dat_o\[11\]
+port 3797 nsew
+rlabel metal2 s 447258 289357 447258 289357 4 wbd_uart_dat_o\[12\]
+port 3798 nsew
+rlabel metal3 s 447166 289187 447166 289187 4 wbd_uart_dat_o\[13\]
+port 3799 nsew
+rlabel metal2 s 447350 289153 447350 289153 4 wbd_uart_dat_o\[14\]
+port 3800 nsew
+rlabel metal2 s 447442 288983 447442 288983 4 wbd_uart_dat_o\[15\]
+port 3801 nsew
+rlabel metal2 s 447166 288167 447166 288167 4 wbd_uart_dat_o\[16\]
+port 3802 nsew
+rlabel metal2 s 447350 287929 447350 287929 4 wbd_uart_dat_o\[17\]
+port 3803 nsew
+rlabel metal2 s 447166 287759 447166 287759 4 wbd_uart_dat_o\[18\]
+port 3804 nsew
+rlabel metal2 s 447258 287691 447258 287691 4 wbd_uart_dat_o\[19\]
+port 3805 nsew
+rlabel metal2 s 447442 292145 447442 292145 4 wbd_uart_dat_o\[1\]
+port 3806 nsew
+rlabel metal2 s 447442 287589 447442 287589 4 wbd_uart_dat_o\[20\]
+port 3807 nsew
+rlabel metal2 s 447534 286705 447534 286705 4 wbd_uart_dat_o\[21\]
+port 3808 nsew
+rlabel metal2 s 447350 286535 447350 286535 4 wbd_uart_dat_o\[22\]
+port 3809 nsew
+rlabel metal3 s 447166 286467 447166 286467 4 wbd_uart_dat_o\[23\]
+port 3810 nsew
+rlabel metal2 s 447258 286399 447258 286399 4 wbd_uart_dat_o\[24\]
+port 3811 nsew
+rlabel metal2 s 447442 286229 447442 286229 4 wbd_uart_dat_o\[25\]
+port 3812 nsew
+rlabel metal1 s 445694 285668 445694 285668 4 wbd_uart_dat_o\[26\]
+port 3813 nsew
+rlabel metal2 s 447258 285243 447258 285243 4 wbd_uart_dat_o\[27\]
+port 3814 nsew
+rlabel metal3 s 447166 285141 447166 285141 4 wbd_uart_dat_o\[28\]
+port 3815 nsew
+rlabel metal2 s 447166 284903 447166 284903 4 wbd_uart_dat_o\[29\]
+port 3816 nsew
+rlabel metal2 s 447166 292145 447166 292145 4 wbd_uart_dat_o\[2\]
+port 3817 nsew
+rlabel metal2 s 447350 284801 447350 284801 4 wbd_uart_dat_o\[30\]
+port 3818 nsew
+rlabel metal1 s 445694 284308 445694 284308 4 wbd_uart_dat_o\[31\]
+port 3819 nsew
+rlabel metal2 s 447258 291975 447258 291975 4 wbd_uart_dat_o\[3\]
+port 3820 nsew
+rlabel metal2 s 447166 291771 447166 291771 4 wbd_uart_dat_o\[4\]
+port 3821 nsew
+rlabel metal2 s 447350 291669 447350 291669 4 wbd_uart_dat_o\[5\]
+port 3822 nsew
+rlabel metal2 s 447166 290887 447166 290887 4 wbd_uart_dat_o\[6\]
+port 3823 nsew
+rlabel metal2 s 447350 290649 447350 290649 4 wbd_uart_dat_o\[7\]
+port 3824 nsew
+rlabel metal3 s 447166 290547 447166 290547 4 wbd_uart_dat_o\[8\]
+port 3825 nsew
+rlabel metal2 s 447442 290513 447442 290513 4 wbd_uart_dat_o\[9\]
+port 3826 nsew
+rlabel metal2 s 447258 283883 447258 283883 4 wbd_uart_sel_o\[0\]
+port 3827 nsew
+rlabel metal2 s 447166 283713 447166 283713 4 wbd_uart_sel_o\[1\]
+port 3828 nsew
+rlabel metal2 s 447350 283645 447350 283645 4 wbd_uart_sel_o\[2\]
+port 3829 nsew
+rlabel metal2 s 447258 283407 447258 283407 4 wbd_uart_sel_o\[3\]
+port 3830 nsew
+rlabel metal1 s 445694 280160 445694 280160 4 wbd_uart_stb_o
+port 3831 nsew
+rlabel metal2 s 447350 280755 447350 280755 4 wbd_uart_we_o
+port 3832 nsew
+rlabel metal2 s 350865 18972 350865 18972 4 wbs_ack_int_o
+port 3833 nsew
+rlabel metal2 s 2898 2098 2898 2098 4 wbs_ack_o
+port 3834 nsew
+rlabel metal2 s 17802 2856 17802 2856 4 wbs_adr_i[0]
+port 3835 nsew
+rlabel metal2 s 47886 1928 47886 1928 4 wbs_adr_i[10]
+port 3836 nsew
+rlabel metal2 s 51382 1962 51382 1962 4 wbs_adr_i[11]
+port 3837 nsew
+rlabel metal2 s 54970 1928 54970 1928 4 wbs_adr_i[12]
+port 3838 nsew
+rlabel metal2 s 58466 1724 58466 1724 4 wbs_adr_i[13]
+port 3839 nsew
+rlabel metal2 s 74934 3434 74934 3434 4 wbs_adr_i[14]
+port 3840 nsew
+rlabel metal1 s 79948 3869 79948 3869 4 wbs_adr_i[15]
+port 3841 nsew
+rlabel metal2 s 81190 3502 81190 3502 4 wbs_adr_i[16]
+port 3842 nsew
+rlabel metal2 s 72634 1724 72634 1724 4 wbs_adr_i[17]
+port 3843 nsew
+rlabel metal2 s 76222 1928 76222 1928 4 wbs_adr_i[18]
+port 3844 nsew
+rlabel metal2 s 79718 1690 79718 1690 4 wbs_adr_i[19]
+port 3845 nsew
+rlabel metal2 s 12374 2030 12374 2030 4 wbs_adr_i[1]
+port 3846 nsew
+rlabel metal2 s 83306 1962 83306 1962 4 wbs_adr_i[20]
+port 3847 nsew
+rlabel metal2 s 99406 3536 99406 3536 4 wbs_adr_i[21]
+port 3848 nsew
+rlabel metal1 s 99498 3196 99498 3196 4 wbs_adr_i[22]
+port 3849 nsew
+rlabel metal2 s 94169 340 94169 340 4 wbs_adr_i[23]
+port 3850 nsew
+rlabel metal2 s 97474 1622 97474 1622 4 wbs_adr_i[24]
+port 3851 nsew
+rlabel metal2 s 101062 1656 101062 1656 4 wbs_adr_i[25]
+port 3852 nsew
+rlabel metal2 s 114310 3230 114310 3230 4 wbs_adr_i[26]
+port 3853 nsew
+rlabel metal1 s 114402 2754 114402 2754 4 wbs_adr_i[27]
+port 3854 nsew
+rlabel metal2 s 117714 3468 117714 3468 4 wbs_adr_i[28]
+port 3855 nsew
+rlabel metal2 s 115230 1622 115230 1622 4 wbs_adr_i[29]
+port 3856 nsew
+rlabel metal2 s 17066 1792 17066 1792 4 wbs_adr_i[2]
+port 3857 nsew
+rlabel metal2 s 118818 1724 118818 1724 4 wbs_adr_i[30]
+port 3858 nsew
+rlabel metal2 s 122314 1792 122314 1792 4 wbs_adr_i[31]
+port 3859 nsew
+rlabel metal2 s 21850 1656 21850 1656 4 wbs_adr_i[3]
+port 3860 nsew
+rlabel metal2 s 36202 3094 36202 3094 4 wbs_adr_i[4]
+port 3861 nsew
+rlabel metal1 s 37490 2856 37490 2856 4 wbs_adr_i[5]
+port 3862 nsew
+rlabel metal1 s 40774 3502 40774 3502 4 wbs_adr_i[6]
+port 3863 nsew
+rlabel metal1 s 37950 3570 37950 3570 4 wbs_adr_i[7]
+port 3864 nsew
+rlabel metal2 s 57086 3434 57086 3434 4 wbs_adr_i[8]
+port 3865 nsew
+rlabel metal2 s 44298 1622 44298 1622 4 wbs_adr_i[9]
+port 3866 nsew
+rlabel metal2 s 4094 1622 4094 1622 4 wbs_cyc_i
+port 3867 nsew
+rlabel metal2 s 8786 1928 8786 1928 4 wbs_dat_i[0]
+port 3868 nsew
+rlabel metal1 s 59386 2958 59386 2958 4 wbs_dat_i[10]
+port 3869 nsew
+rlabel metal2 s 52578 1826 52578 1826 4 wbs_dat_i[11]
+port 3870 nsew
+rlabel metal2 s 56074 1792 56074 1792 4 wbs_dat_i[12]
+port 3871 nsew
+rlabel metal2 s 59662 1656 59662 1656 4 wbs_dat_i[13]
+port 3872 nsew
+rlabel metal2 s 76038 3570 76038 3570 4 wbs_dat_i[14]
+port 3873 nsew
+rlabel metal2 s 80086 3672 80086 3672 4 wbs_dat_i[15]
+port 3874 nsew
+rlabel metal2 s 82938 3502 82938 3502 4 wbs_dat_i[16]
+port 3875 nsew
+rlabel metal2 s 73830 1996 73830 1996 4 wbs_dat_i[17]
+port 3876 nsew
+rlabel metal2 s 77418 1622 77418 1622 4 wbs_dat_i[18]
+port 3877 nsew
+rlabel metal2 s 80914 1860 80914 1860 4 wbs_dat_i[19]
+port 3878 nsew
+rlabel metal2 s 13570 1894 13570 1894 4 wbs_dat_i[1]
+port 3879 nsew
+rlabel metal2 s 96646 3366 96646 3366 4 wbs_dat_i[20]
+port 3880 nsew
+rlabel metal2 s 100602 3230 100602 3230 4 wbs_dat_i[21]
+port 3881 nsew
+rlabel metal2 s 98670 3604 98670 3604 4 wbs_dat_i[22]
+port 3882 nsew
+rlabel metal2 s 95174 1928 95174 1928 4 wbs_dat_i[23]
+port 3883 nsew
+rlabel metal2 s 98670 1588 98670 1588 4 wbs_dat_i[24]
+port 3884 nsew
+rlabel metal2 s 102258 1962 102258 1962 4 wbs_dat_i[25]
+port 3885 nsew
+rlabel metal2 s 115966 3196 115966 3196 4 wbs_dat_i[26]
+port 3886 nsew
+rlabel metal2 s 116702 3434 116702 3434 4 wbs_dat_i[27]
+port 3887 nsew
+rlabel metal2 s 112838 1928 112838 1928 4 wbs_dat_i[28]
+port 3888 nsew
+rlabel metal2 s 116426 1656 116426 1656 4 wbs_dat_i[29]
+port 3889 nsew
+rlabel metal2 s 18262 1724 18262 1724 4 wbs_dat_i[2]
+port 3890 nsew
+rlabel metal2 s 119922 1690 119922 1690 4 wbs_dat_i[30]
+port 3891 nsew
+rlabel metal2 s 123510 1826 123510 1826 4 wbs_dat_i[31]
+port 3892 nsew
+rlabel metal2 s 23046 1622 23046 1622 4 wbs_dat_i[3]
+port 3893 nsew
+rlabel metal2 s 36294 3604 36294 3604 4 wbs_dat_i[4]
+port 3894 nsew
+rlabel metal2 s 45218 2924 45218 2924 4 wbs_dat_i[5]
+port 3895 nsew
+rlabel metal2 s 51658 3536 51658 3536 4 wbs_dat_i[6]
+port 3896 nsew
+rlabel metal1 s 40664 2890 40664 2890 4 wbs_dat_i[7]
+port 3897 nsew
+rlabel metal2 s 41906 1792 41906 1792 4 wbs_dat_i[8]
+port 3898 nsew
+rlabel metal2 s 45494 1588 45494 1588 4 wbs_dat_i[9]
+port 3899 nsew
+rlabel metal2 s 351992 19169 351992 19169 4 wbs_dat_int_o\[0\]
+port 3900 nsew
+rlabel metal1 s 358248 19244 358248 19244 4 wbs_dat_int_o\[10\]
+port 3901 nsew
+rlabel metal2 s 358754 18581 358754 18581 4 wbs_dat_int_o\[11\]
+port 3902 nsew
+rlabel metal2 s 349554 19754 349554 19754 4 wbs_dat_int_o\[12\]
+port 3903 nsew
+rlabel metal2 s 358846 3655 358846 3655 4 wbs_dat_int_o\[13\]
+port 3904 nsew
+rlabel metal4 s 248883 14076 248883 14076 4 wbs_dat_int_o\[14\]
+port 3905 nsew
+rlabel metal1 s 251098 14185 251098 14185 4 wbs_dat_int_o\[15\]
+port 3906 nsew
+rlabel metal4 s 252747 14076 252747 14076 4 wbs_dat_int_o\[16\]
+port 3907 nsew
+rlabel metal2 s 361606 3723 361606 3723 4 wbs_dat_int_o\[17\]
+port 3908 nsew
+rlabel metal3 s 354844 3808 354844 3808 4 wbs_dat_int_o\[18\]
+port 3909 nsew
+rlabel metal3 s 362986 3723 362986 3723 4 wbs_dat_int_o\[19\]
+port 3910 nsew
+rlabel metal4 s 275011 3196 275011 3196 4 wbs_dat_int_o\[1\]
+port 3911 nsew
+rlabel metal3 s 307372 2516 307372 2516 4 wbs_dat_int_o\[20\]
+port 3912 nsew
+rlabel metal2 s 364366 19091 364366 19091 4 wbs_dat_int_o\[21\]
+port 3913 nsew
+rlabel metal2 s 349002 19975 349002 19975 4 wbs_dat_int_o\[22\]
+port 3914 nsew
+rlabel metal2 s 365401 18972 365401 18972 4 wbs_dat_int_o\[23\]
+port 3915 nsew
+rlabel metal2 s 365953 18972 365953 18972 4 wbs_dat_int_o\[24\]
+port 3916 nsew
+rlabel metal3 s 366367 17340 366367 17340 4 wbs_dat_int_o\[25\]
+port 3917 nsew
+rlabel metal2 s 367057 18972 367057 18972 4 wbs_dat_int_o\[26\]
+port 3918 nsew
+rlabel metal2 s 367609 18972 367609 18972 4 wbs_dat_int_o\[27\]
+port 3919 nsew
+rlabel metal2 s 368161 18972 368161 18972 4 wbs_dat_int_o\[28\]
+port 3920 nsew
+rlabel metal2 s 368713 18972 368713 18972 4 wbs_dat_int_o\[29\]
+port 3921 nsew
+rlabel metal2 s 349186 18632 349186 18632 4 wbs_dat_int_o\[2\]
+port 3922 nsew
+rlabel metal2 s 369219 18972 369219 18972 4 wbs_dat_int_o\[30\]
+port 3923 nsew
+rlabel metal2 s 369817 18972 369817 18972 4 wbs_dat_int_o\[31\]
+port 3924 nsew
+rlabel metal2 s 354246 17952 354246 17952 4 wbs_dat_int_o\[3\]
+port 3925 nsew
+rlabel metal2 s 348358 19788 348358 19788 4 wbs_dat_int_o\[4\]
+port 3926 nsew
+rlabel metal1 s 234784 14151 234784 14151 4 wbs_dat_int_o\[5\]
+port 3927 nsew
+rlabel metal1 s 236410 14151 236410 14151 4 wbs_dat_int_o\[6\]
+port 3928 nsew
+rlabel metal1 s 238050 14117 238050 14117 4 wbs_dat_int_o\[7\]
+port 3929 nsew
+rlabel metal2 s 357121 18972 357121 18972 4 wbs_dat_int_o\[8\]
+port 3930 nsew
+rlabel metal2 s 357673 18972 357673 18972 4 wbs_dat_int_o\[9\]
+port 3931 nsew
+rlabel metal2 s 21390 3060 21390 3060 4 wbs_dat_o[0]
+port 3932 nsew
+rlabel metal2 s 50186 1894 50186 1894 4 wbs_dat_o[10]
+port 3933 nsew
+rlabel metal2 s 53774 1996 53774 1996 4 wbs_dat_o[11]
+port 3934 nsew
+rlabel metal2 s 57270 1724 57270 1724 4 wbs_dat_o[12]
+port 3935 nsew
+rlabel metal2 s 75578 3230 75578 3230 4 wbs_dat_o[13]
+port 3936 nsew
+rlabel metal2 s 78706 3264 78706 3264 4 wbs_dat_o[14]
+port 3937 nsew
+rlabel metal2 s 81466 3264 81466 3264 4 wbs_dat_o[15]
+port 3938 nsew
+rlabel metal2 s 82846 3502 82846 3502 4 wbs_dat_o[16]
+port 3939 nsew
+rlabel metal2 s 75026 1894 75026 1894 4 wbs_dat_o[17]
+port 3940 nsew
+rlabel metal2 s 78614 1588 78614 1588 4 wbs_dat_o[18]
+port 3941 nsew
+rlabel metal2 s 82110 1758 82110 1758 4 wbs_dat_o[19]
+port 3942 nsew
+rlabel metal2 s 23506 2992 23506 2992 4 wbs_dat_o[1]
+port 3943 nsew
+rlabel metal2 s 98026 3264 98026 3264 4 wbs_dat_o[20]
+port 3944 nsew
+rlabel metal2 s 96554 2890 96554 2890 4 wbs_dat_o[21]
+port 3945 nsew
+rlabel metal2 s 99406 2890 99406 2890 4 wbs_dat_o[22]
+port 3946 nsew
+rlabel metal2 s 96278 1860 96278 1860 4 wbs_dat_o[23]
+port 3947 nsew
+rlabel metal2 s 99866 1758 99866 1758 4 wbs_dat_o[24]
+port 3948 nsew
+rlabel metal2 s 103362 1792 103362 1792 4 wbs_dat_o[25]
+port 3949 nsew
+rlabel metal1 s 114494 2856 114494 2856 4 wbs_dat_o[26]
+port 3950 nsew
+rlabel metal1 s 117254 3128 117254 3128 4 wbs_dat_o[27]
+port 3951 nsew
+rlabel metal2 s 114034 1860 114034 1860 4 wbs_dat_o[28]
+port 3952 nsew
+rlabel metal2 s 117622 1588 117622 1588 4 wbs_dat_o[29]
+port 3953 nsew
+rlabel metal2 s 19458 1758 19458 1758 4 wbs_dat_o[2]
+port 3954 nsew
+rlabel metal2 s 121118 1758 121118 1758 4 wbs_dat_o[30]
+port 3955 nsew
+rlabel metal2 s 124706 1928 124706 1928 4 wbs_dat_o[31]
+port 3956 nsew
+rlabel metal2 s 24242 1690 24242 1690 4 wbs_dat_o[3]
+port 3957 nsew
+rlabel metal2 s 28934 1826 28934 1826 4 wbs_dat_o[4]
+port 3958 nsew
+rlabel metal2 s 48346 3434 48346 3434 4 wbs_dat_o[5]
+port 3959 nsew
+rlabel metal1 s 48898 3060 48898 3060 4 wbs_dat_o[6]
+port 3960 nsew
+rlabel metal1 s 41216 2822 41216 2822 4 wbs_dat_o[7]
+port 3961 nsew
+rlabel metal2 s 43102 1860 43102 1860 4 wbs_dat_o[8]
+port 3962 nsew
+rlabel metal2 s 46690 1486 46690 1486 4 wbs_dat_o[9]
+port 3963 nsew
+rlabel metal2 s 11178 1996 11178 1996 4 wbs_sel_i[0]
+port 3964 nsew
+rlabel metal2 s 16153 340 16153 340 4 wbs_sel_i[1]
+port 3965 nsew
+rlabel metal2 s 20654 1962 20654 1962 4 wbs_sel_i[2]
+port 3966 nsew
+rlabel metal2 s 25537 340 25537 340 4 wbs_sel_i[3]
+port 3967 nsew
+rlabel metal2 s 5290 1656 5290 1656 4 wbs_stb_i
+port 3968 nsew
+rlabel metal2 s 6486 1792 6486 1792 4 wbs_we_i
+port 3969 nsew
+rlabel metal2 s 430192 105815 430192 105815 4 xtal_clk
+port 3970 nsew
+flabel metal3 s 583520 285276 584960 285516 0 FreeSans 1200 0 0 0 analog_io[0]
+port 3971 nsew
+flabel metal2 s 446098 703520 446210 704960 0 FreeSans 560 90 0 0 analog_io[10]
+port 3972 nsew
+flabel metal2 s 381146 703520 381258 704960 0 FreeSans 560 90 0 0 analog_io[11]
+port 3973 nsew
+flabel metal2 s 316286 703520 316398 704960 0 FreeSans 560 90 0 0 analog_io[12]
+port 3974 nsew
+flabel metal2 s 251426 703520 251538 704960 0 FreeSans 560 90 0 0 analog_io[13]
+port 3975 nsew
+flabel metal2 s 186474 703520 186586 704960 0 FreeSans 560 90 0 0 analog_io[14]
+port 3976 nsew
+flabel metal2 s 121614 703520 121726 704960 0 FreeSans 560 90 0 0 analog_io[15]
+port 9 nsew
+flabel metal2 s 56754 703520 56866 704960 0 FreeSans 560 90 0 0 analog_io[16]
+port 10 nsew
+flabel metal3 s -960 697220 480 697460 0 FreeSans 1200 0 0 0 analog_io[17]
+port 11 nsew
+flabel metal3 s -960 644996 480 645236 0 FreeSans 1200 0 0 0 analog_io[18]
+port 12 nsew
+flabel metal3 s -960 592908 480 593148 0 FreeSans 1200 0 0 0 analog_io[19]
+port 3977 nsew
+flabel metal3 s 583520 338452 584960 338692 0 FreeSans 1200 0 0 0 analog_io[1]
+port 3978 nsew
+flabel metal3 s -960 540684 480 540924 0 FreeSans 1200 0 0 0 analog_io[20]
+port 3979 nsew
+flabel metal3 s -960 488596 480 488836 0 FreeSans 1200 0 0 0 analog_io[21]
+port 3980 nsew
+flabel metal3 s -960 436508 480 436748 0 FreeSans 1200 0 0 0 analog_io[22]
+port 3981 nsew
+flabel metal3 s -960 384284 480 384524 0 FreeSans 1200 0 0 0 analog_io[23]
+port 13 nsew
+flabel metal3 s -960 332196 480 332436 0 FreeSans 1200 0 0 0 analog_io[24]
+port 3982 nsew
+flabel metal3 s -960 279972 480 280212 0 FreeSans 1200 0 0 0 analog_io[25]
+port 3983 nsew
+flabel metal3 s -960 227884 480 228124 0 FreeSans 1200 0 0 0 analog_io[26]
+port 3984 nsew
+flabel metal3 s -960 175796 480 176036 0 FreeSans 1200 0 0 0 analog_io[27]
+port 3985 nsew
+flabel metal3 s -960 123572 480 123812 0 FreeSans 1200 0 0 0 analog_io[28]
+port 3986 nsew
+flabel metal3 s 583520 391628 584960 391868 0 FreeSans 1200 0 0 0 analog_io[2]
+port 3987 nsew
+flabel metal3 s 583520 444668 584960 444908 0 FreeSans 1200 0 0 0 analog_io[3]
+port 3988 nsew
+flabel metal3 s 583520 497844 584960 498084 0 FreeSans 1200 0 0 0 analog_io[4]
+port 3989 nsew
+flabel metal3 s 583520 551020 584960 551260 0 FreeSans 1200 0 0 0 analog_io[5]
+port 3990 nsew
+flabel metal3 s 583520 604060 584960 604300 0 FreeSans 1200 0 0 0 analog_io[6]
+port 3991 nsew
+flabel metal3 s 583520 657236 584960 657476 0 FreeSans 1200 0 0 0 analog_io[7]
+port 3992 nsew
+flabel metal2 s 575818 703520 575930 704960 0 FreeSans 560 90 0 0 analog_io[8]
+port 3993 nsew
+flabel metal2 s 510958 703520 511070 704960 0 FreeSans 560 90 0 0 analog_io[9]
+port 3994 nsew
+flabel metal3 s 583520 6476 584960 6716 0 FreeSans 1200 0 0 0 io_in[0]
+port 360 nsew
+flabel metal3 s 583520 457996 584960 458236 0 FreeSans 1200 0 0 0 io_in[10]
+port 361 nsew
+flabel metal3 s 583520 511172 584960 511412 0 FreeSans 1200 0 0 0 io_in[11]
+port 362 nsew
+flabel metal3 s 583520 564212 584960 564452 0 FreeSans 1200 0 0 0 io_in[12]
+port 363 nsew
+flabel metal3 s 583520 617388 584960 617628 0 FreeSans 1200 0 0 0 io_in[13]
+port 364 nsew
+flabel metal3 s 583520 670564 584960 670804 0 FreeSans 1200 0 0 0 io_in[14]
+port 365 nsew
+flabel metal2 s 559626 703520 559738 704960 0 FreeSans 560 90 0 0 io_in[15]
+port 366 nsew
+flabel metal2 s 494766 703520 494878 704960 0 FreeSans 560 90 0 0 io_in[16]
+port 367 nsew
+flabel metal2 s 429814 703520 429926 704960 0 FreeSans 560 90 0 0 io_in[17]
+port 368 nsew
+flabel metal2 s 364954 703520 365066 704960 0 FreeSans 560 90 0 0 io_in[18]
+port 369 nsew
+flabel metal2 s 300094 703520 300206 704960 0 FreeSans 560 90 0 0 io_in[19]
+port 370 nsew
+flabel metal3 s 583520 46188 584960 46428 0 FreeSans 1200 0 0 0 io_in[1]
+port 371 nsew
+flabel metal2 s 235142 703520 235254 704960 0 FreeSans 560 90 0 0 io_in[20]
+port 372 nsew
+flabel metal2 s 170282 703520 170394 704960 0 FreeSans 560 90 0 0 io_in[21]
+port 373 nsew
+flabel metal2 s 105422 703520 105534 704960 0 FreeSans 560 90 0 0 io_in[22]
+port 374 nsew
+flabel metal2 s 40470 703520 40582 704960 0 FreeSans 560 90 0 0 io_in[23]
+port 375 nsew
+flabel metal3 s -960 684164 480 684404 0 FreeSans 1200 0 0 0 io_in[24]
+port 376 nsew
+flabel metal3 s -960 631940 480 632180 0 FreeSans 1200 0 0 0 io_in[25]
+port 377 nsew
+flabel metal3 s -960 579852 480 580092 0 FreeSans 1200 0 0 0 io_in[26]
+port 378 nsew
+flabel metal3 s -960 527764 480 528004 0 FreeSans 1200 0 0 0 io_in[27]
+port 379 nsew
+flabel metal3 s -960 475540 480 475780 0 FreeSans 1200 0 0 0 io_in[28]
+port 380 nsew
+flabel metal3 s -960 423452 480 423692 0 FreeSans 1200 0 0 0 io_in[29]
+port 381 nsew
+flabel metal3 s 583520 86036 584960 86276 0 FreeSans 1200 0 0 0 io_in[2]
+port 382 nsew
+flabel metal3 s -960 371228 480 371468 0 FreeSans 1200 0 0 0 io_in[30]
+port 383 nsew
+flabel metal3 s -960 319140 480 319380 0 FreeSans 1200 0 0 0 io_in[31]
+port 384 nsew
+flabel metal3 s -960 267052 480 267292 0 FreeSans 1200 0 0 0 io_in[32]
+port 385 nsew
+flabel metal3 s -960 214828 480 215068 0 FreeSans 1200 0 0 0 io_in[33]
+port 386 nsew
+flabel metal3 s -960 162740 480 162980 0 FreeSans 1200 0 0 0 io_in[34]
+port 387 nsew
+flabel metal3 s -960 110516 480 110756 0 FreeSans 1200 0 0 0 io_in[35]
+port 388 nsew
+flabel metal3 s -960 71484 480 71724 0 FreeSans 1200 0 0 0 io_in[36]
+port 389 nsew
+flabel metal3 s -960 32316 480 32556 0 FreeSans 1200 0 0 0 io_in[37]
+port 390 nsew
+flabel metal3 s 583520 125884 584960 126124 0 FreeSans 1200 0 0 0 io_in[3]
+port 391 nsew
+flabel metal3 s 583520 165732 584960 165972 0 FreeSans 1200 0 0 0 io_in[4]
+port 392 nsew
+flabel metal3 s 583520 205580 584960 205820 0 FreeSans 1200 0 0 0 io_in[5]
+port 393 nsew
+flabel metal3 s 583520 245428 584960 245668 0 FreeSans 1200 0 0 0 io_in[6]
+port 394 nsew
+flabel metal3 s 583520 298604 584960 298844 0 FreeSans 1200 0 0 0 io_in[7]
+port 395 nsew
+flabel metal3 s 583520 351780 584960 352020 0 FreeSans 1200 0 0 0 io_in[8]
+port 396 nsew
+flabel metal3 s 583520 404820 584960 405060 0 FreeSans 1200 0 0 0 io_in[9]
+port 397 nsew
+flabel metal3 s 583520 32996 584960 33236 0 FreeSans 1200 0 0 0 io_oeb[0]
+port 398 nsew
+flabel metal3 s 583520 484516 584960 484756 0 FreeSans 1200 0 0 0 io_oeb[10]
+port 399 nsew
+flabel metal3 s 583520 537692 584960 537932 0 FreeSans 1200 0 0 0 io_oeb[11]
+port 400 nsew
+flabel metal3 s 583520 590868 584960 591108 0 FreeSans 1200 0 0 0 io_oeb[12]
+port 401 nsew
+flabel metal3 s 583520 643908 584960 644148 0 FreeSans 1200 0 0 0 io_oeb[13]
+port 402 nsew
+flabel metal3 s 583520 697084 584960 697324 0 FreeSans 1200 0 0 0 io_oeb[14]
+port 403 nsew
+flabel metal2 s 527150 703520 527262 704960 0 FreeSans 560 90 0 0 io_oeb[15]
+port 404 nsew
+flabel metal2 s 462290 703520 462402 704960 0 FreeSans 560 90 0 0 io_oeb[16]
+port 405 nsew
+flabel metal2 s 397430 703520 397542 704960 0 FreeSans 560 90 0 0 io_oeb[17]
+port 406 nsew
+flabel metal2 s 332478 703520 332590 704960 0 FreeSans 560 90 0 0 io_oeb[18]
+port 407 nsew
+flabel metal2 s 267618 703520 267730 704960 0 FreeSans 560 90 0 0 io_oeb[19]
+port 408 nsew
+flabel metal3 s 583520 72844 584960 73084 0 FreeSans 1200 0 0 0 io_oeb[1]
+port 409 nsew
+flabel metal2 s 202758 703520 202870 704960 0 FreeSans 560 90 0 0 io_oeb[20]
+port 410 nsew
+flabel metal2 s 137806 703520 137918 704960 0 FreeSans 560 90 0 0 io_oeb[21]
+port 411 nsew
+flabel metal2 s 72946 703520 73058 704960 0 FreeSans 560 90 0 0 io_oeb[22]
+port 412 nsew
+flabel metal2 s 8086 703520 8198 704960 0 FreeSans 560 90 0 0 io_oeb[23]
+port 413 nsew
+flabel metal3 s -960 658052 480 658292 0 FreeSans 1200 0 0 0 io_oeb[24]
+port 414 nsew
+flabel metal3 s -960 605964 480 606204 0 FreeSans 1200 0 0 0 io_oeb[25]
+port 415 nsew
+flabel metal3 s -960 553740 480 553980 0 FreeSans 1200 0 0 0 io_oeb[26]
+port 416 nsew
+flabel metal3 s -960 501652 480 501892 0 FreeSans 1200 0 0 0 io_oeb[27]
+port 417 nsew
+flabel metal3 s -960 449428 480 449668 0 FreeSans 1200 0 0 0 io_oeb[28]
+port 418 nsew
+flabel metal3 s -960 397340 480 397580 0 FreeSans 1200 0 0 0 io_oeb[29]
+port 419 nsew
+flabel metal3 s 583520 112692 584960 112932 0 FreeSans 1200 0 0 0 io_oeb[2]
+port 420 nsew
+flabel metal3 s -960 345252 480 345492 0 FreeSans 1200 0 0 0 io_oeb[30]
+port 421 nsew
+flabel metal3 s -960 293028 480 293268 0 FreeSans 1200 0 0 0 io_oeb[31]
+port 422 nsew
+flabel metal3 s -960 240940 480 241180 0 FreeSans 1200 0 0 0 io_oeb[32]
+port 423 nsew
+flabel metal3 s -960 188716 480 188956 0 FreeSans 1200 0 0 0 io_oeb[33]
+port 424 nsew
+flabel metal3 s -960 136628 480 136868 0 FreeSans 1200 0 0 0 io_oeb[34]
+port 425 nsew
+flabel metal3 s -960 84540 480 84780 0 FreeSans 1200 0 0 0 io_oeb[35]
+port 426 nsew
+flabel metal3 s -960 45372 480 45612 0 FreeSans 1200 0 0 0 io_oeb[36]
+port 427 nsew
+flabel metal3 s -960 6340 480 6580 0 FreeSans 1200 0 0 0 io_oeb[37]
+port 428 nsew
+flabel metal3 s 583520 152540 584960 152780 0 FreeSans 1200 0 0 0 io_oeb[3]
+port 429 nsew
+flabel metal3 s 583520 192388 584960 192628 0 FreeSans 1200 0 0 0 io_oeb[4]
+port 430 nsew
+flabel metal3 s 583520 232236 584960 232476 0 FreeSans 1200 0 0 0 io_oeb[5]
+port 431 nsew
+flabel metal3 s 583520 272084 584960 272324 0 FreeSans 1200 0 0 0 io_oeb[6]
+port 432 nsew
+flabel metal3 s 583520 325124 584960 325364 0 FreeSans 1200 0 0 0 io_oeb[7]
+port 433 nsew
+flabel metal3 s 583520 378300 584960 378540 0 FreeSans 1200 0 0 0 io_oeb[8]
+port 434 nsew
+flabel metal3 s 583520 431476 584960 431716 0 FreeSans 1200 0 0 0 io_oeb[9]
+port 435 nsew
+flabel metal3 s 583520 19668 584960 19908 0 FreeSans 1200 0 0 0 io_out[0]
+port 474 nsew
+flabel metal3 s 583520 471324 584960 471564 0 FreeSans 1200 0 0 0 io_out[10]
+port 475 nsew
+flabel metal3 s 583520 524364 584960 524604 0 FreeSans 1200 0 0 0 io_out[11]
+port 476 nsew
+flabel metal3 s 583520 577540 584960 577780 0 FreeSans 1200 0 0 0 io_out[12]
+port 477 nsew
+flabel metal3 s 583520 630716 584960 630956 0 FreeSans 1200 0 0 0 io_out[13]
+port 478 nsew
+flabel metal3 s 583520 683756 584960 683996 0 FreeSans 1200 0 0 0 io_out[14]
+port 479 nsew
+flabel metal2 s 543434 703520 543546 704960 0 FreeSans 560 90 0 0 io_out[15]
+port 480 nsew
+flabel metal2 s 478482 703520 478594 704960 0 FreeSans 560 90 0 0 io_out[16]
+port 481 nsew
+flabel metal2 s 413622 703520 413734 704960 0 FreeSans 560 90 0 0 io_out[17]
+port 482 nsew
+flabel metal2 s 348762 703520 348874 704960 0 FreeSans 560 90 0 0 io_out[18]
+port 483 nsew
+flabel metal2 s 283810 703520 283922 704960 0 FreeSans 560 90 0 0 io_out[19]
+port 484 nsew
+flabel metal3 s 583520 59516 584960 59756 0 FreeSans 1200 0 0 0 io_out[1]
+port 485 nsew
+flabel metal2 s 218950 703520 219062 704960 0 FreeSans 560 90 0 0 io_out[20]
+port 486 nsew
+flabel metal2 s 154090 703520 154202 704960 0 FreeSans 560 90 0 0 io_out[21]
+port 487 nsew
+flabel metal2 s 89138 703520 89250 704960 0 FreeSans 560 90 0 0 io_out[22]
+port 488 nsew
+flabel metal2 s 24278 703520 24390 704960 0 FreeSans 560 90 0 0 io_out[23]
+port 489 nsew
+flabel metal3 s -960 671108 480 671348 0 FreeSans 1200 0 0 0 io_out[24]
+port 490 nsew
+flabel metal3 s -960 619020 480 619260 0 FreeSans 1200 0 0 0 io_out[25]
+port 491 nsew
+flabel metal3 s -960 566796 480 567036 0 FreeSans 1200 0 0 0 io_out[26]
+port 492 nsew
+flabel metal3 s -960 514708 480 514948 0 FreeSans 1200 0 0 0 io_out[27]
+port 493 nsew
+flabel metal3 s -960 462484 480 462724 0 FreeSans 1200 0 0 0 io_out[28]
+port 494 nsew
+flabel metal3 s -960 410396 480 410636 0 FreeSans 1200 0 0 0 io_out[29]
+port 495 nsew
+flabel metal3 s 583520 99364 584960 99604 0 FreeSans 1200 0 0 0 io_out[2]
+port 496 nsew
+flabel metal3 s -960 358308 480 358548 0 FreeSans 1200 0 0 0 io_out[30]
+port 497 nsew
+flabel metal3 s -960 306084 480 306324 0 FreeSans 1200 0 0 0 io_out[31]
+port 498 nsew
+flabel metal3 s -960 253996 480 254236 0 FreeSans 1200 0 0 0 io_out[32]
+port 499 nsew
+flabel metal3 s -960 201772 480 202012 0 FreeSans 1200 0 0 0 io_out[33]
+port 500 nsew
+flabel metal3 s -960 149684 480 149924 0 FreeSans 1200 0 0 0 io_out[34]
+port 501 nsew
+flabel metal3 s -960 97460 480 97700 0 FreeSans 1200 0 0 0 io_out[35]
+port 502 nsew
+flabel metal3 s -960 58428 480 58668 0 FreeSans 1200 0 0 0 io_out[36]
+port 503 nsew
+flabel metal3 s -960 19260 480 19500 0 FreeSans 1200 0 0 0 io_out[37]
+port 504 nsew
+flabel metal3 s 583520 139212 584960 139452 0 FreeSans 1200 0 0 0 io_out[3]
+port 505 nsew
+flabel metal3 s 583520 179060 584960 179300 0 FreeSans 1200 0 0 0 io_out[4]
+port 506 nsew
+flabel metal3 s 583520 218908 584960 219148 0 FreeSans 1200 0 0 0 io_out[5]
+port 507 nsew
+flabel metal3 s 583520 258756 584960 258996 0 FreeSans 1200 0 0 0 io_out[6]
+port 508 nsew
+flabel metal3 s 583520 311932 584960 312172 0 FreeSans 1200 0 0 0 io_out[7]
+port 509 nsew
+flabel metal3 s 583520 364972 584960 365212 0 FreeSans 1200 0 0 0 io_out[8]
+port 510 nsew
+flabel metal3 s 583520 418148 584960 418388 0 FreeSans 1200 0 0 0 io_out[9]
+port 511 nsew
+flabel metal2 s 125846 -960 125958 480 0 FreeSans 560 90 0 0 la_data_in[0]
+port 585 nsew
+flabel metal2 s 480506 -960 480618 480 0 FreeSans 560 90 0 0 la_data_in[100]
+port 3995 nsew
+flabel metal2 s 484002 -960 484114 480 0 FreeSans 560 90 0 0 la_data_in[101]
+port 3996 nsew
+flabel metal2 s 487590 -960 487702 480 0 FreeSans 560 90 0 0 la_data_in[102]
+port 3997 nsew
+flabel metal2 s 491086 -960 491198 480 0 FreeSans 560 90 0 0 la_data_in[103]
+port 3998 nsew
+flabel metal2 s 494674 -960 494786 480 0 FreeSans 560 90 0 0 la_data_in[104]
+port 3999 nsew
+flabel metal2 s 498170 -960 498282 480 0 FreeSans 560 90 0 0 la_data_in[105]
+port 4000 nsew
+flabel metal2 s 501758 -960 501870 480 0 FreeSans 560 90 0 0 la_data_in[106]
+port 4001 nsew
+flabel metal2 s 505346 -960 505458 480 0 FreeSans 560 90 0 0 la_data_in[107]
+port 4002 nsew
+flabel metal2 s 508842 -960 508954 480 0 FreeSans 560 90 0 0 la_data_in[108]
+port 4003 nsew
+flabel metal2 s 512430 -960 512542 480 0 FreeSans 560 90 0 0 la_data_in[109]
+port 4004 nsew
+flabel metal2 s 161266 -960 161378 480 0 FreeSans 560 90 0 0 la_data_in[10]
+port 586 nsew
+flabel metal2 s 515926 -960 516038 480 0 FreeSans 560 90 0 0 la_data_in[110]
+port 4005 nsew
+flabel metal2 s 519514 -960 519626 480 0 FreeSans 560 90 0 0 la_data_in[111]
+port 4006 nsew
+flabel metal2 s 523010 -960 523122 480 0 FreeSans 560 90 0 0 la_data_in[112]
+port 4007 nsew
+flabel metal2 s 526598 -960 526710 480 0 FreeSans 560 90 0 0 la_data_in[113]
+port 4008 nsew
+flabel metal2 s 530094 -960 530206 480 0 FreeSans 560 90 0 0 la_data_in[114]
+port 4009 nsew
+flabel metal2 s 533682 -960 533794 480 0 FreeSans 560 90 0 0 la_data_in[115]
+port 4010 nsew
+flabel metal2 s 537178 -960 537290 480 0 FreeSans 560 90 0 0 la_data_in[116]
+port 4011 nsew
+flabel metal2 s 540766 -960 540878 480 0 FreeSans 560 90 0 0 la_data_in[117]
+port 4012 nsew
+flabel metal2 s 544354 -960 544466 480 0 FreeSans 560 90 0 0 la_data_in[118]
+port 4013 nsew
+flabel metal2 s 547850 -960 547962 480 0 FreeSans 560 90 0 0 la_data_in[119]
+port 4014 nsew
+flabel metal2 s 164854 -960 164966 480 0 FreeSans 560 90 0 0 la_data_in[11]
+port 587 nsew
+flabel metal2 s 551438 -960 551550 480 0 FreeSans 560 90 0 0 la_data_in[120]
+port 4015 nsew
+flabel metal2 s 554934 -960 555046 480 0 FreeSans 560 90 0 0 la_data_in[121]
+port 4016 nsew
+flabel metal2 s 558522 -960 558634 480 0 FreeSans 560 90 0 0 la_data_in[122]
+port 4017 nsew
+flabel metal2 s 562018 -960 562130 480 0 FreeSans 560 90 0 0 la_data_in[123]
+port 4018 nsew
+flabel metal2 s 565606 -960 565718 480 0 FreeSans 560 90 0 0 la_data_in[124]
+port 4019 nsew
+flabel metal2 s 569102 -960 569214 480 0 FreeSans 560 90 0 0 la_data_in[125]
+port 4020 nsew
+flabel metal2 s 572690 -960 572802 480 0 FreeSans 560 90 0 0 la_data_in[126]
+port 4021 nsew
+flabel metal2 s 576278 -960 576390 480 0 FreeSans 560 90 0 0 la_data_in[127]
+port 4022 nsew
+flabel metal2 s 168350 -960 168462 480 0 FreeSans 560 90 0 0 la_data_in[12]
+port 588 nsew
+flabel metal2 s 171938 -960 172050 480 0 FreeSans 560 90 0 0 la_data_in[13]
+port 589 nsew
+flabel metal2 s 175434 -960 175546 480 0 FreeSans 560 90 0 0 la_data_in[14]
+port 590 nsew
+flabel metal2 s 179022 -960 179134 480 0 FreeSans 560 90 0 0 la_data_in[15]
+port 591 nsew
+flabel metal2 s 182518 -960 182630 480 0 FreeSans 560 90 0 0 la_data_in[16]
+port 592 nsew
+flabel metal2 s 186106 -960 186218 480 0 FreeSans 560 90 0 0 la_data_in[17]
+port 593 nsew
+flabel metal2 s 189694 -960 189806 480 0 FreeSans 560 90 0 0 la_data_in[18]
+port 4023 nsew
+flabel metal2 s 193190 -960 193302 480 0 FreeSans 560 90 0 0 la_data_in[19]
+port 4024 nsew
+flabel metal2 s 129342 -960 129454 480 0 FreeSans 560 90 0 0 la_data_in[1]
+port 594 nsew
+flabel metal2 s 196778 -960 196890 480 0 FreeSans 560 90 0 0 la_data_in[20]
+port 4025 nsew
+flabel metal2 s 200274 -960 200386 480 0 FreeSans 560 90 0 0 la_data_in[21]
+port 4026 nsew
+flabel metal2 s 203862 -960 203974 480 0 FreeSans 560 90 0 0 la_data_in[22]
+port 4027 nsew
+flabel metal2 s 207358 -960 207470 480 0 FreeSans 560 90 0 0 la_data_in[23]
+port 4028 nsew
+flabel metal2 s 210946 -960 211058 480 0 FreeSans 560 90 0 0 la_data_in[24]
+port 4029 nsew
+flabel metal2 s 214442 -960 214554 480 0 FreeSans 560 90 0 0 la_data_in[25]
+port 4030 nsew
+flabel metal2 s 218030 -960 218142 480 0 FreeSans 560 90 0 0 la_data_in[26]
+port 4031 nsew
+flabel metal2 s 221526 -960 221638 480 0 FreeSans 560 90 0 0 la_data_in[27]
+port 4032 nsew
+flabel metal2 s 225114 -960 225226 480 0 FreeSans 560 90 0 0 la_data_in[28]
+port 4033 nsew
+flabel metal2 s 228702 -960 228814 480 0 FreeSans 560 90 0 0 la_data_in[29]
+port 4034 nsew
+flabel metal2 s 132930 -960 133042 480 0 FreeSans 560 90 0 0 la_data_in[2]
+port 595 nsew
+flabel metal2 s 232198 -960 232310 480 0 FreeSans 560 90 0 0 la_data_in[30]
+port 4035 nsew
+flabel metal2 s 235786 -960 235898 480 0 FreeSans 560 90 0 0 la_data_in[31]
+port 4036 nsew
+flabel metal2 s 239282 -960 239394 480 0 FreeSans 560 90 0 0 la_data_in[32]
+port 4037 nsew
+flabel metal2 s 242870 -960 242982 480 0 FreeSans 560 90 0 0 la_data_in[33]
+port 4038 nsew
+flabel metal2 s 246366 -960 246478 480 0 FreeSans 560 90 0 0 la_data_in[34]
+port 4039 nsew
+flabel metal2 s 249954 -960 250066 480 0 FreeSans 560 90 0 0 la_data_in[35]
+port 4040 nsew
+flabel metal2 s 253450 -960 253562 480 0 FreeSans 560 90 0 0 la_data_in[36]
+port 4041 nsew
+flabel metal2 s 257038 -960 257150 480 0 FreeSans 560 90 0 0 la_data_in[37]
+port 4042 nsew
+flabel metal2 s 260626 -960 260738 480 0 FreeSans 560 90 0 0 la_data_in[38]
+port 4043 nsew
+flabel metal2 s 264122 -960 264234 480 0 FreeSans 560 90 0 0 la_data_in[39]
+port 4044 nsew
+flabel metal2 s 136426 -960 136538 480 0 FreeSans 560 90 0 0 la_data_in[3]
+port 596 nsew
+flabel metal2 s 267710 -960 267822 480 0 FreeSans 560 90 0 0 la_data_in[40]
+port 4045 nsew
+flabel metal2 s 271206 -960 271318 480 0 FreeSans 560 90 0 0 la_data_in[41]
+port 4046 nsew
+flabel metal2 s 274794 -960 274906 480 0 FreeSans 560 90 0 0 la_data_in[42]
+port 4047 nsew
+flabel metal2 s 278290 -960 278402 480 0 FreeSans 560 90 0 0 la_data_in[43]
+port 4048 nsew
+flabel metal2 s 281878 -960 281990 480 0 FreeSans 560 90 0 0 la_data_in[44]
+port 4049 nsew
+flabel metal2 s 285374 -960 285486 480 0 FreeSans 560 90 0 0 la_data_in[45]
+port 4050 nsew
+flabel metal2 s 288962 -960 289074 480 0 FreeSans 560 90 0 0 la_data_in[46]
+port 4051 nsew
+flabel metal2 s 292550 -960 292662 480 0 FreeSans 560 90 0 0 la_data_in[47]
+port 4052 nsew
+flabel metal2 s 296046 -960 296158 480 0 FreeSans 560 90 0 0 la_data_in[48]
+port 4053 nsew
+flabel metal2 s 299634 -960 299746 480 0 FreeSans 560 90 0 0 la_data_in[49]
+port 4054 nsew
+flabel metal2 s 140014 -960 140126 480 0 FreeSans 560 90 0 0 la_data_in[4]
+port 597 nsew
+flabel metal2 s 303130 -960 303242 480 0 FreeSans 560 90 0 0 la_data_in[50]
+port 4055 nsew
+flabel metal2 s 306718 -960 306830 480 0 FreeSans 560 90 0 0 la_data_in[51]
+port 4056 nsew
+flabel metal2 s 310214 -960 310326 480 0 FreeSans 560 90 0 0 la_data_in[52]
+port 4057 nsew
+flabel metal2 s 313802 -960 313914 480 0 FreeSans 560 90 0 0 la_data_in[53]
+port 4058 nsew
+flabel metal2 s 317298 -960 317410 480 0 FreeSans 560 90 0 0 la_data_in[54]
+port 4059 nsew
+flabel metal2 s 320886 -960 320998 480 0 FreeSans 560 90 0 0 la_data_in[55]
+port 4060 nsew
+flabel metal2 s 324382 -960 324494 480 0 FreeSans 560 90 0 0 la_data_in[56]
+port 4061 nsew
+flabel metal2 s 327970 -960 328082 480 0 FreeSans 560 90 0 0 la_data_in[57]
+port 4062 nsew
+flabel metal2 s 331558 -960 331670 480 0 FreeSans 560 90 0 0 la_data_in[58]
+port 4063 nsew
+flabel metal2 s 335054 -960 335166 480 0 FreeSans 560 90 0 0 la_data_in[59]
+port 4064 nsew
+flabel metal2 s 143510 -960 143622 480 0 FreeSans 560 90 0 0 la_data_in[5]
+port 598 nsew
+flabel metal2 s 338642 -960 338754 480 0 FreeSans 560 90 0 0 la_data_in[60]
+port 4065 nsew
+flabel metal2 s 342138 -960 342250 480 0 FreeSans 560 90 0 0 la_data_in[61]
+port 4066 nsew
+flabel metal2 s 345726 -960 345838 480 0 FreeSans 560 90 0 0 la_data_in[62]
+port 4067 nsew
+flabel metal2 s 349222 -960 349334 480 0 FreeSans 560 90 0 0 la_data_in[63]
+port 4068 nsew
+flabel metal2 s 352810 -960 352922 480 0 FreeSans 560 90 0 0 la_data_in[64]
+port 4069 nsew
+flabel metal2 s 356306 -960 356418 480 0 FreeSans 560 90 0 0 la_data_in[65]
+port 4070 nsew
+flabel metal2 s 359894 -960 360006 480 0 FreeSans 560 90 0 0 la_data_in[66]
+port 4071 nsew
+flabel metal2 s 363482 -960 363594 480 0 FreeSans 560 90 0 0 la_data_in[67]
+port 4072 nsew
+flabel metal2 s 366978 -960 367090 480 0 FreeSans 560 90 0 0 la_data_in[68]
+port 4073 nsew
+flabel metal2 s 370566 -960 370678 480 0 FreeSans 560 90 0 0 la_data_in[69]
+port 4074 nsew
+flabel metal2 s 147098 -960 147210 480 0 FreeSans 560 90 0 0 la_data_in[6]
+port 599 nsew
+flabel metal2 s 374062 -960 374174 480 0 FreeSans 560 90 0 0 la_data_in[70]
+port 4075 nsew
+flabel metal2 s 377650 -960 377762 480 0 FreeSans 560 90 0 0 la_data_in[71]
+port 4076 nsew
+flabel metal2 s 381146 -960 381258 480 0 FreeSans 560 90 0 0 la_data_in[72]
+port 4077 nsew
+flabel metal2 s 384734 -960 384846 480 0 FreeSans 560 90 0 0 la_data_in[73]
+port 4078 nsew
+flabel metal2 s 388230 -960 388342 480 0 FreeSans 560 90 0 0 la_data_in[74]
+port 4079 nsew
+flabel metal2 s 391818 -960 391930 480 0 FreeSans 560 90 0 0 la_data_in[75]
+port 4080 nsew
+flabel metal2 s 395314 -960 395426 480 0 FreeSans 560 90 0 0 la_data_in[76]
+port 4081 nsew
+flabel metal2 s 398902 -960 399014 480 0 FreeSans 560 90 0 0 la_data_in[77]
+port 4082 nsew
+flabel metal2 s 402490 -960 402602 480 0 FreeSans 560 90 0 0 la_data_in[78]
+port 4083 nsew
+flabel metal2 s 405986 -960 406098 480 0 FreeSans 560 90 0 0 la_data_in[79]
+port 4084 nsew
+flabel metal2 s 150594 -960 150706 480 0 FreeSans 560 90 0 0 la_data_in[7]
+port 600 nsew
+flabel metal2 s 409574 -960 409686 480 0 FreeSans 560 90 0 0 la_data_in[80]
+port 4085 nsew
+flabel metal2 s 413070 -960 413182 480 0 FreeSans 560 90 0 0 la_data_in[81]
+port 4086 nsew
+flabel metal2 s 416658 -960 416770 480 0 FreeSans 560 90 0 0 la_data_in[82]
+port 4087 nsew
+flabel metal2 s 420154 -960 420266 480 0 FreeSans 560 90 0 0 la_data_in[83]
+port 4088 nsew
+flabel metal2 s 423742 -960 423854 480 0 FreeSans 560 90 0 0 la_data_in[84]
+port 4089 nsew
+flabel metal2 s 427238 -960 427350 480 0 FreeSans 560 90 0 0 la_data_in[85]
+port 4090 nsew
+flabel metal2 s 430826 -960 430938 480 0 FreeSans 560 90 0 0 la_data_in[86]
+port 4091 nsew
+flabel metal2 s 434414 -960 434526 480 0 FreeSans 560 90 0 0 la_data_in[87]
+port 4092 nsew
+flabel metal2 s 437910 -960 438022 480 0 FreeSans 560 90 0 0 la_data_in[88]
+port 4093 nsew
+flabel metal2 s 441498 -960 441610 480 0 FreeSans 560 90 0 0 la_data_in[89]
+port 4094 nsew
+flabel metal2 s 154182 -960 154294 480 0 FreeSans 560 90 0 0 la_data_in[8]
+port 601 nsew
+flabel metal2 s 444994 -960 445106 480 0 FreeSans 560 90 0 0 la_data_in[90]
+port 4095 nsew
+flabel metal2 s 448582 -960 448694 480 0 FreeSans 560 90 0 0 la_data_in[91]
+port 4096 nsew
+flabel metal2 s 452078 -960 452190 480 0 FreeSans 560 90 0 0 la_data_in[92]
+port 4097 nsew
+flabel metal2 s 455666 -960 455778 480 0 FreeSans 560 90 0 0 la_data_in[93]
+port 4098 nsew
+flabel metal2 s 459162 -960 459274 480 0 FreeSans 560 90 0 0 la_data_in[94]
+port 4099 nsew
+flabel metal2 s 462750 -960 462862 480 0 FreeSans 560 90 0 0 la_data_in[95]
+port 4100 nsew
+flabel metal2 s 466246 -960 466358 480 0 FreeSans 560 90 0 0 la_data_in[96]
+port 4101 nsew
+flabel metal2 s 469834 -960 469946 480 0 FreeSans 560 90 0 0 la_data_in[97]
+port 4102 nsew
+flabel metal2 s 473422 -960 473534 480 0 FreeSans 560 90 0 0 la_data_in[98]
+port 4103 nsew
+flabel metal2 s 476918 -960 477030 480 0 FreeSans 560 90 0 0 la_data_in[99]
+port 4104 nsew
+flabel metal2 s 157770 -960 157882 480 0 FreeSans 560 90 0 0 la_data_in[9]
+port 602 nsew
+flabel metal2 s 126950 -960 127062 480 0 FreeSans 560 90 0 0 la_data_out[0]
+port 603 nsew
+flabel metal2 s 481702 -960 481814 480 0 FreeSans 560 90 0 0 la_data_out[100]
+port 604 nsew
+flabel metal2 s 485198 -960 485310 480 0 FreeSans 560 90 0 0 la_data_out[101]
+port 605 nsew
+flabel metal2 s 488786 -960 488898 480 0 FreeSans 560 90 0 0 la_data_out[102]
+port 606 nsew
+flabel metal2 s 492282 -960 492394 480 0 FreeSans 560 90 0 0 la_data_out[103]
+port 607 nsew
+flabel metal2 s 495870 -960 495982 480 0 FreeSans 560 90 0 0 la_data_out[104]
+port 608 nsew
+flabel metal2 s 499366 -960 499478 480 0 FreeSans 560 90 0 0 la_data_out[105]
+port 609 nsew
+flabel metal2 s 502954 -960 503066 480 0 FreeSans 560 90 0 0 la_data_out[106]
+port 610 nsew
+flabel metal2 s 506450 -960 506562 480 0 FreeSans 560 90 0 0 la_data_out[107]
+port 611 nsew
+flabel metal2 s 510038 -960 510150 480 0 FreeSans 560 90 0 0 la_data_out[108]
+port 612 nsew
+flabel metal2 s 513534 -960 513646 480 0 FreeSans 560 90 0 0 la_data_out[109]
+port 613 nsew
+flabel metal2 s 162462 -960 162574 480 0 FreeSans 560 90 0 0 la_data_out[10]
+port 614 nsew
+flabel metal2 s 517122 -960 517234 480 0 FreeSans 560 90 0 0 la_data_out[110]
+port 615 nsew
+flabel metal2 s 520710 -960 520822 480 0 FreeSans 560 90 0 0 la_data_out[111]
+port 616 nsew
+flabel metal2 s 524206 -960 524318 480 0 FreeSans 560 90 0 0 la_data_out[112]
+port 617 nsew
+flabel metal2 s 527794 -960 527906 480 0 FreeSans 560 90 0 0 la_data_out[113]
+port 618 nsew
+flabel metal2 s 531290 -960 531402 480 0 FreeSans 560 90 0 0 la_data_out[114]
+port 619 nsew
+flabel metal2 s 534878 -960 534990 480 0 FreeSans 560 90 0 0 la_data_out[115]
+port 620 nsew
+flabel metal2 s 538374 -960 538486 480 0 FreeSans 560 90 0 0 la_data_out[116]
+port 621 nsew
+flabel metal2 s 541962 -960 542074 480 0 FreeSans 560 90 0 0 la_data_out[117]
+port 622 nsew
+flabel metal2 s 545458 -960 545570 480 0 FreeSans 560 90 0 0 la_data_out[118]
+port 623 nsew
+flabel metal2 s 549046 -960 549158 480 0 FreeSans 560 90 0 0 la_data_out[119]
+port 624 nsew
+flabel metal2 s 166050 -960 166162 480 0 FreeSans 560 90 0 0 la_data_out[11]
+port 625 nsew
+flabel metal2 s 552634 -960 552746 480 0 FreeSans 560 90 0 0 la_data_out[120]
+port 626 nsew
+flabel metal2 s 556130 -960 556242 480 0 FreeSans 560 90 0 0 la_data_out[121]
+port 627 nsew
+flabel metal2 s 559718 -960 559830 480 0 FreeSans 560 90 0 0 la_data_out[122]
+port 628 nsew
+flabel metal2 s 563214 -960 563326 480 0 FreeSans 560 90 0 0 la_data_out[123]
+port 629 nsew
+flabel metal2 s 566802 -960 566914 480 0 FreeSans 560 90 0 0 la_data_out[124]
+port 630 nsew
+flabel metal2 s 570298 -960 570410 480 0 FreeSans 560 90 0 0 la_data_out[125]
+port 631 nsew
+flabel metal2 s 573886 -960 573998 480 0 FreeSans 560 90 0 0 la_data_out[126]
+port 632 nsew
+flabel metal2 s 577382 -960 577494 480 0 FreeSans 560 90 0 0 la_data_out[127]
+port 633 nsew
+flabel metal2 s 169546 -960 169658 480 0 FreeSans 560 90 0 0 la_data_out[12]
+port 634 nsew
+flabel metal2 s 173134 -960 173246 480 0 FreeSans 560 90 0 0 la_data_out[13]
+port 635 nsew
+flabel metal2 s 176630 -960 176742 480 0 FreeSans 560 90 0 0 la_data_out[14]
+port 636 nsew
+flabel metal2 s 180218 -960 180330 480 0 FreeSans 560 90 0 0 la_data_out[15]
+port 637 nsew
+flabel metal2 s 183714 -960 183826 480 0 FreeSans 560 90 0 0 la_data_out[16]
+port 638 nsew
+flabel metal2 s 187302 -960 187414 480 0 FreeSans 560 90 0 0 la_data_out[17]
+port 639 nsew
+flabel metal2 s 190798 -960 190910 480 0 FreeSans 560 90 0 0 la_data_out[18]
+port 640 nsew
+flabel metal2 s 194386 -960 194498 480 0 FreeSans 560 90 0 0 la_data_out[19]
+port 641 nsew
+flabel metal2 s 130538 -960 130650 480 0 FreeSans 560 90 0 0 la_data_out[1]
+port 642 nsew
+flabel metal2 s 197882 -960 197994 480 0 FreeSans 560 90 0 0 la_data_out[20]
+port 643 nsew
+flabel metal2 s 201470 -960 201582 480 0 FreeSans 560 90 0 0 la_data_out[21]
+port 644 nsew
+flabel metal2 s 205058 -960 205170 480 0 FreeSans 560 90 0 0 la_data_out[22]
+port 645 nsew
+flabel metal2 s 208554 -960 208666 480 0 FreeSans 560 90 0 0 la_data_out[23]
+port 646 nsew
+flabel metal2 s 212142 -960 212254 480 0 FreeSans 560 90 0 0 la_data_out[24]
+port 647 nsew
+flabel metal2 s 215638 -960 215750 480 0 FreeSans 560 90 0 0 la_data_out[25]
+port 648 nsew
+flabel metal2 s 219226 -960 219338 480 0 FreeSans 560 90 0 0 la_data_out[26]
+port 649 nsew
+flabel metal2 s 222722 -960 222834 480 0 FreeSans 560 90 0 0 la_data_out[27]
+port 650 nsew
+flabel metal2 s 226310 -960 226422 480 0 FreeSans 560 90 0 0 la_data_out[28]
+port 651 nsew
+flabel metal2 s 229806 -960 229918 480 0 FreeSans 560 90 0 0 la_data_out[29]
+port 652 nsew
+flabel metal2 s 134126 -960 134238 480 0 FreeSans 560 90 0 0 la_data_out[2]
+port 653 nsew
+flabel metal2 s 233394 -960 233506 480 0 FreeSans 560 90 0 0 la_data_out[30]
+port 654 nsew
+flabel metal2 s 236982 -960 237094 480 0 FreeSans 560 90 0 0 la_data_out[31]
+port 655 nsew
+flabel metal2 s 240478 -960 240590 480 0 FreeSans 560 90 0 0 la_data_out[32]
+port 656 nsew
+flabel metal2 s 244066 -960 244178 480 0 FreeSans 560 90 0 0 la_data_out[33]
+port 657 nsew
+flabel metal2 s 247562 -960 247674 480 0 FreeSans 560 90 0 0 la_data_out[34]
+port 658 nsew
+flabel metal2 s 251150 -960 251262 480 0 FreeSans 560 90 0 0 la_data_out[35]
+port 659 nsew
+flabel metal2 s 254646 -960 254758 480 0 FreeSans 560 90 0 0 la_data_out[36]
+port 660 nsew
+flabel metal2 s 258234 -960 258346 480 0 FreeSans 560 90 0 0 la_data_out[37]
+port 661 nsew
+flabel metal2 s 261730 -960 261842 480 0 FreeSans 560 90 0 0 la_data_out[38]
+port 662 nsew
+flabel metal2 s 265318 -960 265430 480 0 FreeSans 560 90 0 0 la_data_out[39]
+port 663 nsew
+flabel metal2 s 137622 -960 137734 480 0 FreeSans 560 90 0 0 la_data_out[3]
+port 664 nsew
+flabel metal2 s 268814 -960 268926 480 0 FreeSans 560 90 0 0 la_data_out[40]
+port 665 nsew
+flabel metal2 s 272402 -960 272514 480 0 FreeSans 560 90 0 0 la_data_out[41]
+port 666 nsew
+flabel metal2 s 275990 -960 276102 480 0 FreeSans 560 90 0 0 la_data_out[42]
+port 667 nsew
+flabel metal2 s 279486 -960 279598 480 0 FreeSans 560 90 0 0 la_data_out[43]
+port 668 nsew
+flabel metal2 s 283074 -960 283186 480 0 FreeSans 560 90 0 0 la_data_out[44]
+port 669 nsew
+flabel metal2 s 286570 -960 286682 480 0 FreeSans 560 90 0 0 la_data_out[45]
+port 670 nsew
+flabel metal2 s 290158 -960 290270 480 0 FreeSans 560 90 0 0 la_data_out[46]
+port 671 nsew
+flabel metal2 s 293654 -960 293766 480 0 FreeSans 560 90 0 0 la_data_out[47]
+port 672 nsew
+flabel metal2 s 297242 -960 297354 480 0 FreeSans 560 90 0 0 la_data_out[48]
+port 673 nsew
+flabel metal2 s 300738 -960 300850 480 0 FreeSans 560 90 0 0 la_data_out[49]
+port 674 nsew
+flabel metal2 s 141210 -960 141322 480 0 FreeSans 560 90 0 0 la_data_out[4]
+port 675 nsew
+flabel metal2 s 304326 -960 304438 480 0 FreeSans 560 90 0 0 la_data_out[50]
+port 676 nsew
+flabel metal2 s 307914 -960 308026 480 0 FreeSans 560 90 0 0 la_data_out[51]
+port 677 nsew
+flabel metal2 s 311410 -960 311522 480 0 FreeSans 560 90 0 0 la_data_out[52]
+port 678 nsew
+flabel metal2 s 314998 -960 315110 480 0 FreeSans 560 90 0 0 la_data_out[53]
+port 679 nsew
+flabel metal2 s 318494 -960 318606 480 0 FreeSans 560 90 0 0 la_data_out[54]
+port 680 nsew
+flabel metal2 s 322082 -960 322194 480 0 FreeSans 560 90 0 0 la_data_out[55]
+port 681 nsew
+flabel metal2 s 325578 -960 325690 480 0 FreeSans 560 90 0 0 la_data_out[56]
+port 682 nsew
+flabel metal2 s 329166 -960 329278 480 0 FreeSans 560 90 0 0 la_data_out[57]
+port 683 nsew
+flabel metal2 s 332662 -960 332774 480 0 FreeSans 560 90 0 0 la_data_out[58]
+port 684 nsew
+flabel metal2 s 336250 -960 336362 480 0 FreeSans 560 90 0 0 la_data_out[59]
+port 685 nsew
+flabel metal2 s 144706 -960 144818 480 0 FreeSans 560 90 0 0 la_data_out[5]
+port 686 nsew
+flabel metal2 s 339838 -960 339950 480 0 FreeSans 560 90 0 0 la_data_out[60]
+port 687 nsew
+flabel metal2 s 343334 -960 343446 480 0 FreeSans 560 90 0 0 la_data_out[61]
+port 688 nsew
+flabel metal2 s 346922 -960 347034 480 0 FreeSans 560 90 0 0 la_data_out[62]
+port 689 nsew
+flabel metal2 s 350418 -960 350530 480 0 FreeSans 560 90 0 0 la_data_out[63]
+port 690 nsew
+flabel metal2 s 354006 -960 354118 480 0 FreeSans 560 90 0 0 la_data_out[64]
+port 691 nsew
+flabel metal2 s 357502 -960 357614 480 0 FreeSans 560 90 0 0 la_data_out[65]
+port 692 nsew
+flabel metal2 s 361090 -960 361202 480 0 FreeSans 560 90 0 0 la_data_out[66]
+port 693 nsew
+flabel metal2 s 364586 -960 364698 480 0 FreeSans 560 90 0 0 la_data_out[67]
+port 694 nsew
+flabel metal2 s 368174 -960 368286 480 0 FreeSans 560 90 0 0 la_data_out[68]
+port 695 nsew
+flabel metal2 s 371670 -960 371782 480 0 FreeSans 560 90 0 0 la_data_out[69]
+port 696 nsew
+flabel metal2 s 148294 -960 148406 480 0 FreeSans 560 90 0 0 la_data_out[6]
+port 697 nsew
+flabel metal2 s 375258 -960 375370 480 0 FreeSans 560 90 0 0 la_data_out[70]
+port 698 nsew
+flabel metal2 s 378846 -960 378958 480 0 FreeSans 560 90 0 0 la_data_out[71]
+port 699 nsew
+flabel metal2 s 382342 -960 382454 480 0 FreeSans 560 90 0 0 la_data_out[72]
+port 700 nsew
+flabel metal2 s 385930 -960 386042 480 0 FreeSans 560 90 0 0 la_data_out[73]
+port 701 nsew
+flabel metal2 s 389426 -960 389538 480 0 FreeSans 560 90 0 0 la_data_out[74]
+port 702 nsew
+flabel metal2 s 393014 -960 393126 480 0 FreeSans 560 90 0 0 la_data_out[75]
+port 703 nsew
+flabel metal2 s 396510 -960 396622 480 0 FreeSans 560 90 0 0 la_data_out[76]
+port 704 nsew
+flabel metal2 s 400098 -960 400210 480 0 FreeSans 560 90 0 0 la_data_out[77]
+port 705 nsew
+flabel metal2 s 403594 -960 403706 480 0 FreeSans 560 90 0 0 la_data_out[78]
+port 706 nsew
+flabel metal2 s 407182 -960 407294 480 0 FreeSans 560 90 0 0 la_data_out[79]
+port 707 nsew
+flabel metal2 s 151790 -960 151902 480 0 FreeSans 560 90 0 0 la_data_out[7]
+port 708 nsew
+flabel metal2 s 410770 -960 410882 480 0 FreeSans 560 90 0 0 la_data_out[80]
+port 709 nsew
+flabel metal2 s 414266 -960 414378 480 0 FreeSans 560 90 0 0 la_data_out[81]
+port 710 nsew
+flabel metal2 s 417854 -960 417966 480 0 FreeSans 560 90 0 0 la_data_out[82]
+port 711 nsew
+flabel metal2 s 421350 -960 421462 480 0 FreeSans 560 90 0 0 la_data_out[83]
+port 712 nsew
+flabel metal2 s 424938 -960 425050 480 0 FreeSans 560 90 0 0 la_data_out[84]
+port 713 nsew
+flabel metal2 s 428434 -960 428546 480 0 FreeSans 560 90 0 0 la_data_out[85]
+port 714 nsew
+flabel metal2 s 432022 -960 432134 480 0 FreeSans 560 90 0 0 la_data_out[86]
+port 715 nsew
+flabel metal2 s 435518 -960 435630 480 0 FreeSans 560 90 0 0 la_data_out[87]
+port 716 nsew
+flabel metal2 s 439106 -960 439218 480 0 FreeSans 560 90 0 0 la_data_out[88]
+port 717 nsew
+flabel metal2 s 442602 -960 442714 480 0 FreeSans 560 90 0 0 la_data_out[89]
+port 718 nsew
+flabel metal2 s 155378 -960 155490 480 0 FreeSans 560 90 0 0 la_data_out[8]
+port 719 nsew
+flabel metal2 s 446190 -960 446302 480 0 FreeSans 560 90 0 0 la_data_out[90]
+port 720 nsew
+flabel metal2 s 449778 -960 449890 480 0 FreeSans 560 90 0 0 la_data_out[91]
+port 721 nsew
+flabel metal2 s 453274 -960 453386 480 0 FreeSans 560 90 0 0 la_data_out[92]
+port 722 nsew
+flabel metal2 s 456862 -960 456974 480 0 FreeSans 560 90 0 0 la_data_out[93]
+port 723 nsew
+flabel metal2 s 460358 -960 460470 480 0 FreeSans 560 90 0 0 la_data_out[94]
+port 724 nsew
+flabel metal2 s 463946 -960 464058 480 0 FreeSans 560 90 0 0 la_data_out[95]
+port 725 nsew
+flabel metal2 s 467442 -960 467554 480 0 FreeSans 560 90 0 0 la_data_out[96]
+port 726 nsew
+flabel metal2 s 471030 -960 471142 480 0 FreeSans 560 90 0 0 la_data_out[97]
+port 727 nsew
+flabel metal2 s 474526 -960 474638 480 0 FreeSans 560 90 0 0 la_data_out[98]
+port 728 nsew
+flabel metal2 s 478114 -960 478226 480 0 FreeSans 560 90 0 0 la_data_out[99]
+port 729 nsew
+flabel metal2 s 158874 -960 158986 480 0 FreeSans 560 90 0 0 la_data_out[9]
+port 730 nsew
+flabel metal2 s 128146 -960 128258 480 0 FreeSans 560 90 0 0 la_oenb[0]
+port 4105 nsew
+flabel metal2 s 482806 -960 482918 480 0 FreeSans 560 90 0 0 la_oenb[100]
+port 4106 nsew
+flabel metal2 s 486394 -960 486506 480 0 FreeSans 560 90 0 0 la_oenb[101]
+port 4107 nsew
+flabel metal2 s 489890 -960 490002 480 0 FreeSans 560 90 0 0 la_oenb[102]
+port 4108 nsew
+flabel metal2 s 493478 -960 493590 480 0 FreeSans 560 90 0 0 la_oenb[103]
+port 4109 nsew
+flabel metal2 s 497066 -960 497178 480 0 FreeSans 560 90 0 0 la_oenb[104]
+port 4110 nsew
+flabel metal2 s 500562 -960 500674 480 0 FreeSans 560 90 0 0 la_oenb[105]
+port 4111 nsew
+flabel metal2 s 504150 -960 504262 480 0 FreeSans 560 90 0 0 la_oenb[106]
+port 4112 nsew
+flabel metal2 s 507646 -960 507758 480 0 FreeSans 560 90 0 0 la_oenb[107]
+port 4113 nsew
+flabel metal2 s 511234 -960 511346 480 0 FreeSans 560 90 0 0 la_oenb[108]
+port 4114 nsew
+flabel metal2 s 514730 -960 514842 480 0 FreeSans 560 90 0 0 la_oenb[109]
+port 4115 nsew
+flabel metal2 s 163658 -960 163770 480 0 FreeSans 560 90 0 0 la_oenb[10]
+port 4116 nsew
+flabel metal2 s 518318 -960 518430 480 0 FreeSans 560 90 0 0 la_oenb[110]
+port 4117 nsew
+flabel metal2 s 521814 -960 521926 480 0 FreeSans 560 90 0 0 la_oenb[111]
+port 4118 nsew
+flabel metal2 s 525402 -960 525514 480 0 FreeSans 560 90 0 0 la_oenb[112]
+port 4119 nsew
+flabel metal2 s 528990 -960 529102 480 0 FreeSans 560 90 0 0 la_oenb[113]
+port 4120 nsew
+flabel metal2 s 532486 -960 532598 480 0 FreeSans 560 90 0 0 la_oenb[114]
+port 4121 nsew
+flabel metal2 s 536074 -960 536186 480 0 FreeSans 560 90 0 0 la_oenb[115]
+port 4122 nsew
+flabel metal2 s 539570 -960 539682 480 0 FreeSans 560 90 0 0 la_oenb[116]
+port 4123 nsew
+flabel metal2 s 543158 -960 543270 480 0 FreeSans 560 90 0 0 la_oenb[117]
+port 4124 nsew
+flabel metal2 s 546654 -960 546766 480 0 FreeSans 560 90 0 0 la_oenb[118]
+port 4125 nsew
+flabel metal2 s 550242 -960 550354 480 0 FreeSans 560 90 0 0 la_oenb[119]
+port 4126 nsew
+flabel metal2 s 167154 -960 167266 480 0 FreeSans 560 90 0 0 la_oenb[11]
+port 4127 nsew
+flabel metal2 s 553738 -960 553850 480 0 FreeSans 560 90 0 0 la_oenb[120]
+port 4128 nsew
+flabel metal2 s 557326 -960 557438 480 0 FreeSans 560 90 0 0 la_oenb[121]
+port 4129 nsew
+flabel metal2 s 560822 -960 560934 480 0 FreeSans 560 90 0 0 la_oenb[122]
+port 4130 nsew
+flabel metal2 s 564410 -960 564522 480 0 FreeSans 560 90 0 0 la_oenb[123]
+port 4131 nsew
+flabel metal2 s 567998 -960 568110 480 0 FreeSans 560 90 0 0 la_oenb[124]
+port 4132 nsew
+flabel metal2 s 571494 -960 571606 480 0 FreeSans 560 90 0 0 la_oenb[125]
+port 4133 nsew
+flabel metal2 s 575082 -960 575194 480 0 FreeSans 560 90 0 0 la_oenb[126]
+port 4134 nsew
+flabel metal2 s 578578 -960 578690 480 0 FreeSans 560 90 0 0 la_oenb[127]
+port 4135 nsew
+flabel metal2 s 170742 -960 170854 480 0 FreeSans 560 90 0 0 la_oenb[12]
+port 4136 nsew
+flabel metal2 s 174238 -960 174350 480 0 FreeSans 560 90 0 0 la_oenb[13]
+port 4137 nsew
+flabel metal2 s 177826 -960 177938 480 0 FreeSans 560 90 0 0 la_oenb[14]
+port 4138 nsew
+flabel metal2 s 181414 -960 181526 480 0 FreeSans 560 90 0 0 la_oenb[15]
+port 4139 nsew
+flabel metal2 s 184910 -960 185022 480 0 FreeSans 560 90 0 0 la_oenb[16]
+port 4140 nsew
+flabel metal2 s 188498 -960 188610 480 0 FreeSans 560 90 0 0 la_oenb[17]
+port 4141 nsew
+flabel metal2 s 191994 -960 192106 480 0 FreeSans 560 90 0 0 la_oenb[18]
+port 4142 nsew
+flabel metal2 s 195582 -960 195694 480 0 FreeSans 560 90 0 0 la_oenb[19]
+port 4143 nsew
+flabel metal2 s 131734 -960 131846 480 0 FreeSans 560 90 0 0 la_oenb[1]
+port 4144 nsew
+flabel metal2 s 199078 -960 199190 480 0 FreeSans 560 90 0 0 la_oenb[20]
+port 4145 nsew
+flabel metal2 s 202666 -960 202778 480 0 FreeSans 560 90 0 0 la_oenb[21]
+port 4146 nsew
+flabel metal2 s 206162 -960 206274 480 0 FreeSans 560 90 0 0 la_oenb[22]
+port 4147 nsew
+flabel metal2 s 209750 -960 209862 480 0 FreeSans 560 90 0 0 la_oenb[23]
+port 4148 nsew
+flabel metal2 s 213338 -960 213450 480 0 FreeSans 560 90 0 0 la_oenb[24]
+port 4149 nsew
+flabel metal2 s 216834 -960 216946 480 0 FreeSans 560 90 0 0 la_oenb[25]
+port 4150 nsew
+flabel metal2 s 220422 -960 220534 480 0 FreeSans 560 90 0 0 la_oenb[26]
+port 4151 nsew
+flabel metal2 s 223918 -960 224030 480 0 FreeSans 560 90 0 0 la_oenb[27]
+port 4152 nsew
+flabel metal2 s 227506 -960 227618 480 0 FreeSans 560 90 0 0 la_oenb[28]
+port 4153 nsew
+flabel metal2 s 231002 -960 231114 480 0 FreeSans 560 90 0 0 la_oenb[29]
+port 4154 nsew
+flabel metal2 s 135230 -960 135342 480 0 FreeSans 560 90 0 0 la_oenb[2]
+port 4155 nsew
+flabel metal2 s 234590 -960 234702 480 0 FreeSans 560 90 0 0 la_oenb[30]
+port 4156 nsew
+flabel metal2 s 238086 -960 238198 480 0 FreeSans 560 90 0 0 la_oenb[31]
+port 4157 nsew
+flabel metal2 s 241674 -960 241786 480 0 FreeSans 560 90 0 0 la_oenb[32]
+port 4158 nsew
+flabel metal2 s 245170 -960 245282 480 0 FreeSans 560 90 0 0 la_oenb[33]
+port 4159 nsew
+flabel metal2 s 248758 -960 248870 480 0 FreeSans 560 90 0 0 la_oenb[34]
+port 4160 nsew
+flabel metal2 s 252346 -960 252458 480 0 FreeSans 560 90 0 0 la_oenb[35]
+port 4161 nsew
+flabel metal2 s 255842 -960 255954 480 0 FreeSans 560 90 0 0 la_oenb[36]
+port 4162 nsew
+flabel metal2 s 259430 -960 259542 480 0 FreeSans 560 90 0 0 la_oenb[37]
+port 4163 nsew
+flabel metal2 s 262926 -960 263038 480 0 FreeSans 560 90 0 0 la_oenb[38]
+port 4164 nsew
+flabel metal2 s 266514 -960 266626 480 0 FreeSans 560 90 0 0 la_oenb[39]
+port 4165 nsew
+flabel metal2 s 138818 -960 138930 480 0 FreeSans 560 90 0 0 la_oenb[3]
+port 4166 nsew
+flabel metal2 s 270010 -960 270122 480 0 FreeSans 560 90 0 0 la_oenb[40]
+port 4167 nsew
+flabel metal2 s 273598 -960 273710 480 0 FreeSans 560 90 0 0 la_oenb[41]
+port 4168 nsew
+flabel metal2 s 277094 -960 277206 480 0 FreeSans 560 90 0 0 la_oenb[42]
+port 4169 nsew
+flabel metal2 s 280682 -960 280794 480 0 FreeSans 560 90 0 0 la_oenb[43]
+port 4170 nsew
+flabel metal2 s 284270 -960 284382 480 0 FreeSans 560 90 0 0 la_oenb[44]
+port 4171 nsew
+flabel metal2 s 287766 -960 287878 480 0 FreeSans 560 90 0 0 la_oenb[45]
+port 4172 nsew
+flabel metal2 s 291354 -960 291466 480 0 FreeSans 560 90 0 0 la_oenb[46]
+port 4173 nsew
+flabel metal2 s 294850 -960 294962 480 0 FreeSans 560 90 0 0 la_oenb[47]
+port 4174 nsew
+flabel metal2 s 298438 -960 298550 480 0 FreeSans 560 90 0 0 la_oenb[48]
+port 4175 nsew
+flabel metal2 s 301934 -960 302046 480 0 FreeSans 560 90 0 0 la_oenb[49]
+port 4176 nsew
+flabel metal2 s 142406 -960 142518 480 0 FreeSans 560 90 0 0 la_oenb[4]
+port 4177 nsew
+flabel metal2 s 305522 -960 305634 480 0 FreeSans 560 90 0 0 la_oenb[50]
+port 4178 nsew
+flabel metal2 s 309018 -960 309130 480 0 FreeSans 560 90 0 0 la_oenb[51]
+port 4179 nsew
+flabel metal2 s 312606 -960 312718 480 0 FreeSans 560 90 0 0 la_oenb[52]
+port 4180 nsew
+flabel metal2 s 316194 -960 316306 480 0 FreeSans 560 90 0 0 la_oenb[53]
+port 4181 nsew
+flabel metal2 s 319690 -960 319802 480 0 FreeSans 560 90 0 0 la_oenb[54]
+port 4182 nsew
+flabel metal2 s 323278 -960 323390 480 0 FreeSans 560 90 0 0 la_oenb[55]
+port 4183 nsew
+flabel metal2 s 326774 -960 326886 480 0 FreeSans 560 90 0 0 la_oenb[56]
+port 4184 nsew
+flabel metal2 s 330362 -960 330474 480 0 FreeSans 560 90 0 0 la_oenb[57]
+port 4185 nsew
+flabel metal2 s 333858 -960 333970 480 0 FreeSans 560 90 0 0 la_oenb[58]
+port 4186 nsew
+flabel metal2 s 337446 -960 337558 480 0 FreeSans 560 90 0 0 la_oenb[59]
+port 4187 nsew
+flabel metal2 s 145902 -960 146014 480 0 FreeSans 560 90 0 0 la_oenb[5]
+port 4188 nsew
+flabel metal2 s 340942 -960 341054 480 0 FreeSans 560 90 0 0 la_oenb[60]
+port 4189 nsew
+flabel metal2 s 344530 -960 344642 480 0 FreeSans 560 90 0 0 la_oenb[61]
+port 4190 nsew
+flabel metal2 s 348026 -960 348138 480 0 FreeSans 560 90 0 0 la_oenb[62]
+port 4191 nsew
+flabel metal2 s 351614 -960 351726 480 0 FreeSans 560 90 0 0 la_oenb[63]
+port 4192 nsew
+flabel metal2 s 355202 -960 355314 480 0 FreeSans 560 90 0 0 la_oenb[64]
+port 4193 nsew
+flabel metal2 s 358698 -960 358810 480 0 FreeSans 560 90 0 0 la_oenb[65]
+port 4194 nsew
+flabel metal2 s 362286 -960 362398 480 0 FreeSans 560 90 0 0 la_oenb[66]
+port 4195 nsew
+flabel metal2 s 365782 -960 365894 480 0 FreeSans 560 90 0 0 la_oenb[67]
+port 4196 nsew
+flabel metal2 s 369370 -960 369482 480 0 FreeSans 560 90 0 0 la_oenb[68]
+port 4197 nsew
+flabel metal2 s 372866 -960 372978 480 0 FreeSans 560 90 0 0 la_oenb[69]
+port 4198 nsew
+flabel metal2 s 149490 -960 149602 480 0 FreeSans 560 90 0 0 la_oenb[6]
+port 4199 nsew
+flabel metal2 s 376454 -960 376566 480 0 FreeSans 560 90 0 0 la_oenb[70]
+port 4200 nsew
+flabel metal2 s 379950 -960 380062 480 0 FreeSans 560 90 0 0 la_oenb[71]
+port 4201 nsew
+flabel metal2 s 383538 -960 383650 480 0 FreeSans 560 90 0 0 la_oenb[72]
+port 4202 nsew
+flabel metal2 s 387126 -960 387238 480 0 FreeSans 560 90 0 0 la_oenb[73]
+port 4203 nsew
+flabel metal2 s 390622 -960 390734 480 0 FreeSans 560 90 0 0 la_oenb[74]
+port 4204 nsew
+flabel metal2 s 394210 -960 394322 480 0 FreeSans 560 90 0 0 la_oenb[75]
+port 4205 nsew
+flabel metal2 s 397706 -960 397818 480 0 FreeSans 560 90 0 0 la_oenb[76]
+port 4206 nsew
+flabel metal2 s 401294 -960 401406 480 0 FreeSans 560 90 0 0 la_oenb[77]
+port 4207 nsew
+flabel metal2 s 404790 -960 404902 480 0 FreeSans 560 90 0 0 la_oenb[78]
+port 4208 nsew
+flabel metal2 s 408378 -960 408490 480 0 FreeSans 560 90 0 0 la_oenb[79]
+port 4209 nsew
+flabel metal2 s 152986 -960 153098 480 0 FreeSans 560 90 0 0 la_oenb[7]
+port 4210 nsew
+flabel metal2 s 411874 -960 411986 480 0 FreeSans 560 90 0 0 la_oenb[80]
+port 4211 nsew
+flabel metal2 s 415462 -960 415574 480 0 FreeSans 560 90 0 0 la_oenb[81]
+port 4212 nsew
+flabel metal2 s 418958 -960 419070 480 0 FreeSans 560 90 0 0 la_oenb[82]
+port 4213 nsew
+flabel metal2 s 422546 -960 422658 480 0 FreeSans 560 90 0 0 la_oenb[83]
+port 4214 nsew
+flabel metal2 s 426134 -960 426246 480 0 FreeSans 560 90 0 0 la_oenb[84]
+port 4215 nsew
+flabel metal2 s 429630 -960 429742 480 0 FreeSans 560 90 0 0 la_oenb[85]
+port 4216 nsew
+flabel metal2 s 433218 -960 433330 480 0 FreeSans 560 90 0 0 la_oenb[86]
+port 4217 nsew
+flabel metal2 s 436714 -960 436826 480 0 FreeSans 560 90 0 0 la_oenb[87]
+port 4218 nsew
+flabel metal2 s 440302 -960 440414 480 0 FreeSans 560 90 0 0 la_oenb[88]
+port 4219 nsew
+flabel metal2 s 443798 -960 443910 480 0 FreeSans 560 90 0 0 la_oenb[89]
+port 4220 nsew
+flabel metal2 s 156574 -960 156686 480 0 FreeSans 560 90 0 0 la_oenb[8]
+port 4221 nsew
+flabel metal2 s 447386 -960 447498 480 0 FreeSans 560 90 0 0 la_oenb[90]
+port 4222 nsew
+flabel metal2 s 450882 -960 450994 480 0 FreeSans 560 90 0 0 la_oenb[91]
+port 4223 nsew
+flabel metal2 s 454470 -960 454582 480 0 FreeSans 560 90 0 0 la_oenb[92]
+port 4224 nsew
+flabel metal2 s 458058 -960 458170 480 0 FreeSans 560 90 0 0 la_oenb[93]
+port 4225 nsew
+flabel metal2 s 461554 -960 461666 480 0 FreeSans 560 90 0 0 la_oenb[94]
+port 4226 nsew
+flabel metal2 s 465142 -960 465254 480 0 FreeSans 560 90 0 0 la_oenb[95]
+port 4227 nsew
+flabel metal2 s 468638 -960 468750 480 0 FreeSans 560 90 0 0 la_oenb[96]
+port 4228 nsew
+flabel metal2 s 472226 -960 472338 480 0 FreeSans 560 90 0 0 la_oenb[97]
+port 4229 nsew
+flabel metal2 s 475722 -960 475834 480 0 FreeSans 560 90 0 0 la_oenb[98]
+port 4230 nsew
+flabel metal2 s 479310 -960 479422 480 0 FreeSans 560 90 0 0 la_oenb[99]
+port 4231 nsew
+flabel metal2 s 160070 -960 160182 480 0 FreeSans 560 90 0 0 la_oenb[9]
+port 4232 nsew
+flabel metal2 s 579774 -960 579886 480 0 FreeSans 560 90 0 0 user_clock2
+port 3433 nsew
+flabel metal2 s 580970 -960 581082 480 0 FreeSans 560 90 0 0 user_irq[0]
+port 3434 nsew
+flabel metal2 s 582166 -960 582278 480 0 FreeSans 560 90 0 0 user_irq[1]
+port 3435 nsew
+flabel metal2 s 583362 -960 583474 480 0 FreeSans 560 90 0 0 user_irq[2]
+port 3436 nsew
+flabel metal4 s -2006 -934 -1386 704870 0 FreeSans 4800 90 0 0 vccd1
+port 1 nsew
+flabel metal5 s -2006 -934 585930 -314 0 FreeSans 3200 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -2006 704250 585930 704870 0 FreeSans 3200 0 0 0 vccd1
+port 1 nsew
+flabel metal4 s 585310 -934 585930 704870 0 FreeSans 4800 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 1584 -7654 2624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 17584 -7654 18624 18000 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 17584 672000 18624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33584 -7654 34624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33584 111244 34624 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33584 235244 34624 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 33584 664912 34624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49584 -7654 50624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49584 111244 50624 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49584 235244 50624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 49584 662905 50624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65584 -7654 66624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65584 111368 66624 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65584 235368 66624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 65584 662905 66624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81584 -7654 82624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81584 111244 82624 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81584 235244 82624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 81584 662905 82624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97584 -7654 98624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97584 111368 98624 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97584 235368 98624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 97584 662905 98624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113584 -7654 114624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113584 111368 114624 147940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113584 235368 114624 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 113584 664912 114624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129584 -7654 130624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129584 111244 130624 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129584 235244 130624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 129584 662905 130624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145584 -7654 146624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145584 111244 146624 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145584 235244 146624 278383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 145584 650993 146624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161584 -7654 162624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161584 111244 162624 148064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161584 235244 162624 278383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 161584 659664 162624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 177584 -7654 178624 278383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 177584 650993 178624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 193584 -7654 194624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 193584 256329 194624 278383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 193584 650993 194624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 209584 -7654 210624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 209584 256329 210624 278383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 209584 650993 210624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 225584 -7654 226624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 225584 256329 226624 278383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 225584 650993 226624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 241584 -7654 242624 23940 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 241584 256329 242624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 241584 662905 242624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 257584 -7654 258624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 257584 256329 258624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 257584 662905 258624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 273584 -7654 274624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 273584 256329 274624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 273584 662905 274624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 289584 -7654 290624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 289584 256329 290624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 289584 662905 290624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 305584 -7654 306624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 305584 256329 306624 280048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 305584 664912 306624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 321584 -7654 322624 24064 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 321584 256329 322624 280967 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 321584 662905 322624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 337584 -7654 338624 128383 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 337584 256329 338624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 353584 -7654 354624 20048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 353584 104816 354624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 369584 -7654 370624 130423 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 369584 460601 370624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 385584 -7654 386624 130423 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 385584 460601 386624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 401584 -7654 402624 130423 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 401584 460601 402624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 417584 -7654 418624 130423 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 417584 460601 418624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 433584 -7654 434624 68839 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 433584 105121 434624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 449584 -7654 450624 70559 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 449584 179465 450624 202599 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 449584 651385 450624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 465584 -7654 466624 70559 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 465584 179465 466624 202599 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 465584 651385 466624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 481584 -7654 482624 70559 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 481584 179465 482624 202599 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 481584 651385 482624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 497584 -7654 498624 70559 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 497584 179465 498624 202599 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 497584 651385 498624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 513584 -7654 514624 70048 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 513584 659920 514624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 529584 -7654 530624 202599 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 529584 559913 530624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 545584 -7654 546624 202599 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 545584 559913 546624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 561584 -7654 562624 8000 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal4 s 577584 -7654 578624 711590 0 FreeSans 9600 90 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 2656 592650 3696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 18656 592650 19696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 34656 592650 35696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 50656 592650 51696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 66656 592650 67696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 82656 592650 83696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 98656 592650 99696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 114656 592650 115696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 130656 592650 131696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 146656 592650 147696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 162656 592650 163696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 178656 592650 179696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 194656 592650 195696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 210656 592650 211696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 226656 592650 227696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 242656 592650 243696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 258656 592650 259696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 274656 592650 275696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 290656 592650 291696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 306656 592650 307696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 322656 592650 323696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 338656 592650 339696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 354656 592650 355696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 370656 592650 371696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 386656 592650 387696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 402656 592650 403696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 418656 592650 419696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 434656 592650 435696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 450656 592650 451696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 466656 592650 467696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 482656 592650 483696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 498656 592650 499696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 514656 592650 515696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
+flabel metal5 s -8726 530656 592650 531696 0 FreeSans 6400 0 0 0 vccd1
+port 1 nsew
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+port 1 nsew
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+flabel metal5 s -8726 58256 592650 59296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 74256 592650 75296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 90256 592650 91296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 106256 592650 107296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 122256 592650 123296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 138256 592650 139296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 154256 592650 155296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 170256 592650 171296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 186256 592650 187296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 202256 592650 203296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 218256 592650 219296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 234256 592650 235296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 250256 592650 251296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 266256 592650 267296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 282256 592650 283296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 298256 592650 299296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 314256 592650 315296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 330256 592650 331296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 346256 592650 347296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 362256 592650 363296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 378256 592650 379296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 394256 592650 395296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 410256 592650 411296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 426256 592650 427296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 442256 592650 443296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 458256 592650 459296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 474256 592650 475296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 490256 592650 491296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 506256 592650 507296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 522256 592650 523296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 538256 592650 539296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 554256 592650 555296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 570256 592650 571296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 586256 592650 587296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 602256 592650 603296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 618256 592650 619296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 634256 592650 635296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 650256 592650 651296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s 291962 666776 291962 666776 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 682256 592650 683296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal5 s -8726 698256 592650 699296 0 FreeSans 6400 0 0 0 vssd1
+port 7 nsew
+flabel metal4 s -4886 -3814 -4266 707750 0 FreeSans 4800 90 0 0 vssd2
+port 8 nsew
+flabel metal5 s -4886 -3814 588810 -3194 0 FreeSans 3200 0 0 0 vssd2
+port 8 nsew
+flabel metal5 s -4886 707130 588810 707750 0 FreeSans 3200 0 0 0 vssd2
+port 8 nsew
+flabel metal4 s 588500 351968 588500 351968 0 FreeSans 4800 90 0 0 vssd2
+port 8 nsew
+flabel metal2 s 542 -960 654 480 0 FreeSans 560 90 0 0 wb_clk_i
+port 3437 nsew
+flabel metal2 s 1646 -960 1758 480 0 FreeSans 560 90 0 0 wb_rst_i
+port 3438 nsew
+flabel metal2 s 2842 -960 2954 480 0 FreeSans 560 90 0 0 wbs_ack_o
+port 3834 nsew
+flabel metal2 s 7626 -960 7738 480 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 3835 nsew
+flabel metal2 s 47830 -960 47942 480 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 3836 nsew
+flabel metal2 s 51326 -960 51438 480 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 3837 nsew
+flabel metal2 s 54914 -960 55026 480 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 3838 nsew
+flabel metal2 s 58410 -960 58522 480 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 3839 nsew
+flabel metal2 s 61998 -960 62110 480 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 3840 nsew
+flabel metal2 s 65494 -960 65606 480 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 3841 nsew
+flabel metal2 s 69082 -960 69194 480 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 3842 nsew
+flabel metal2 s 72578 -960 72690 480 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 3843 nsew
+flabel metal2 s 76166 -960 76278 480 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 3844 nsew
+flabel metal2 s 79662 -960 79774 480 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 3845 nsew
+flabel metal2 s 12318 -960 12430 480 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 3846 nsew
+flabel metal2 s 83250 -960 83362 480 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 3847 nsew
+flabel metal2 s 86838 -960 86950 480 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 3848 nsew
+flabel metal2 s 90334 -960 90446 480 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 3849 nsew
+flabel metal2 s 93922 -960 94034 480 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 3850 nsew
+flabel metal2 s 97418 -960 97530 480 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 3851 nsew
+flabel metal2 s 101006 -960 101118 480 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 3852 nsew
+flabel metal2 s 104502 -960 104614 480 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 3853 nsew
+flabel metal2 s 108090 -960 108202 480 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 3854 nsew
+flabel metal2 s 111586 -960 111698 480 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 3855 nsew
+flabel metal2 s 115174 -960 115286 480 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 3856 nsew
+flabel metal2 s 17010 -960 17122 480 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 3857 nsew
+flabel metal2 s 118762 -960 118874 480 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 3858 nsew
+flabel metal2 s 122258 -960 122370 480 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 3859 nsew
+flabel metal2 s 21794 -960 21906 480 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 3860 nsew
+flabel metal2 s 26486 -960 26598 480 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 3861 nsew
+flabel metal2 s 30074 -960 30186 480 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 3862 nsew
+flabel metal2 s 33570 -960 33682 480 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 3863 nsew
+flabel metal2 s 37158 -960 37270 480 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 3864 nsew
+flabel metal2 s 40654 -960 40766 480 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 3865 nsew
+flabel metal2 s 44242 -960 44354 480 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 3866 nsew
+flabel metal2 s 4038 -960 4150 480 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 3867 nsew
+flabel metal2 s 8730 -960 8842 480 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 3868 nsew
+flabel metal2 s 48934 -960 49046 480 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 3869 nsew
+flabel metal2 s 52522 -960 52634 480 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 3870 nsew
+flabel metal2 s 56018 -960 56130 480 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 3871 nsew
+flabel metal2 s 59606 -960 59718 480 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 3872 nsew
+flabel metal2 s 63194 -960 63306 480 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 3873 nsew
+flabel metal2 s 66690 -960 66802 480 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 3874 nsew
+flabel metal2 s 70278 -960 70390 480 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 3875 nsew
+flabel metal2 s 73774 -960 73886 480 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 3876 nsew
+flabel metal2 s 77362 -960 77474 480 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 3877 nsew
+flabel metal2 s 80858 -960 80970 480 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 3878 nsew
+flabel metal2 s 13514 -960 13626 480 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 3879 nsew
+flabel metal2 s 84446 -960 84558 480 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 3880 nsew
+flabel metal2 s 87942 -960 88054 480 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 3881 nsew
+flabel metal2 s 91530 -960 91642 480 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 3882 nsew
+flabel metal2 s 95118 -960 95230 480 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 3883 nsew
+flabel metal2 s 98614 -960 98726 480 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 3884 nsew
+flabel metal2 s 102202 -960 102314 480 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 3885 nsew
+flabel metal2 s 105698 -960 105810 480 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 3886 nsew
+flabel metal2 s 109286 -960 109398 480 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 3887 nsew
+flabel metal2 s 112782 -960 112894 480 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 3888 nsew
+flabel metal2 s 116370 -960 116482 480 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 3889 nsew
+flabel metal2 s 18206 -960 18318 480 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 3890 nsew
+flabel metal2 s 119866 -960 119978 480 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 3891 nsew
+flabel metal2 s 123454 -960 123566 480 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 3892 nsew
+flabel metal2 s 22990 -960 23102 480 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 3893 nsew
+flabel metal2 s 27682 -960 27794 480 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 3894 nsew
+flabel metal2 s 31270 -960 31382 480 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 3895 nsew
+flabel metal2 s 34766 -960 34878 480 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 3896 nsew
+flabel metal2 s 38354 -960 38466 480 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 3897 nsew
+flabel metal2 s 41850 -960 41962 480 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 3898 nsew
+flabel metal2 s 45438 -960 45550 480 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 3899 nsew
+flabel metal2 s 9926 -960 10038 480 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 3932 nsew
+flabel metal2 s 50130 -960 50242 480 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 3933 nsew
+flabel metal2 s 53718 -960 53830 480 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 3934 nsew
+flabel metal2 s 57214 -960 57326 480 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 3935 nsew
+flabel metal2 s 60802 -960 60914 480 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 3936 nsew
+flabel metal2 s 64298 -960 64410 480 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 3937 nsew
+flabel metal2 s 67886 -960 67998 480 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 3938 nsew
+flabel metal2 s 71474 -960 71586 480 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 3939 nsew
+flabel metal2 s 74970 -960 75082 480 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 3940 nsew
+flabel metal2 s 78558 -960 78670 480 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 3941 nsew
+flabel metal2 s 82054 -960 82166 480 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 3942 nsew
+flabel metal2 s 14710 -960 14822 480 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 3943 nsew
+flabel metal2 s 85642 -960 85754 480 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 3944 nsew
+flabel metal2 s 89138 -960 89250 480 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 3945 nsew
+flabel metal2 s 92726 -960 92838 480 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 3946 nsew
+flabel metal2 s 96222 -960 96334 480 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 3947 nsew
+flabel metal2 s 99810 -960 99922 480 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 3948 nsew
+flabel metal2 s 103306 -960 103418 480 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 3949 nsew
+flabel metal2 s 106894 -960 107006 480 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 3950 nsew
+flabel metal2 s 110482 -960 110594 480 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 3951 nsew
+flabel metal2 s 113978 -960 114090 480 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 3952 nsew
+flabel metal2 s 117566 -960 117678 480 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 3953 nsew
+flabel metal2 s 19402 -960 19514 480 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 3954 nsew
+flabel metal2 s 121062 -960 121174 480 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 3955 nsew
+flabel metal2 s 124650 -960 124762 480 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 3956 nsew
+flabel metal2 s 24186 -960 24298 480 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 3957 nsew
+flabel metal2 s 28878 -960 28990 480 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 3958 nsew
+flabel metal2 s 32374 -960 32486 480 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 3959 nsew
+flabel metal2 s 35962 -960 36074 480 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 3960 nsew
+flabel metal2 s 39550 -960 39662 480 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 3961 nsew
+flabel metal2 s 43046 -960 43158 480 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 3962 nsew
+flabel metal2 s 46634 -960 46746 480 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 3963 nsew
+flabel metal2 s 11122 -960 11234 480 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 3964 nsew
+flabel metal2 s 15906 -960 16018 480 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 3965 nsew
+flabel metal2 s 20598 -960 20710 480 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 3966 nsew
+flabel metal2 s 25290 -960 25402 480 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 3967 nsew
+flabel metal2 s 5234 -960 5346 480 0 FreeSans 560 90 0 0 wbs_stb_i
+port 3968 nsew
+flabel metal2 s 6430 -960 6542 480 0 FreeSans 560 90 0 0 wbs_we_i
+port 3969 nsew
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mpw_precheck/outputs/user_project_wrapper.xor.gds b/mpw_precheck/outputs/user_project_wrapper.xor.gds
new file mode 100644
index 0000000..0e8d5af
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.xor.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..9894d73
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_erased.gds b/mpw_precheck/outputs/user_project_wrapper_erased.gds
new file mode 100644
index 0000000..9894d73
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz b/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz
new file mode 100644
index 0000000..6190333
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz
Binary files differ
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/signoff/assigned_slot b/signoff/assigned_slot
new file mode 100644
index 0000000..0c294ed
--- /dev/null
+++ b/signoff/assigned_slot
@@ -0,0 +1 @@
+007
diff --git a/signoff/caravel_layout.png b/signoff/caravel_layout.png
new file mode 100644
index 0000000..3b1da1d
--- /dev/null
+++ b/signoff/caravel_layout.png
Binary files differ
diff --git a/tapeout/logs/compose.log b/tapeout/logs/compose.log
new file mode 100644
index 0000000..e67f576
--- /dev/null
+++ b/tapeout/logs/compose.log
@@ -0,0 +1,1902 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/compose.tcl" from command line.
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+caravel
+Scaled magic input cell advSeal_6um_gen geometry by factor of 2
+Writing final GDS. . . 
+Scaled magic input cell seal_ring_corner_abstract geometry by factor of 2
+Scaled magic input cell caravel_motto geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 24
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_49 geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_68 geometry by factor of 24
+Scaled magic input cell font_54 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_69 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_56 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_35 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_4F geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+Scaled magic input cell user_id_textblock geometry by factor of 2
+Scaled magic input cell alpha_0 geometry by factor of 2
+caravel_clocking: 10000 rects
+caravel_clocking: 20000 rects
+caravel_clocking: 30000 rects
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+housekeeping: 360000 rects
+housekeeping: 370000 rects
+housekeeping: 380000 rects
+housekeeping: 390000 rects
+housekeeping: 400000 rects
+housekeeping: 410000 rects
+housekeeping: 420000 rects
+housekeeping: 430000 rects
+housekeeping: 440000 rects
+housekeeping: 450000 rects
+housekeeping: 460000 rects
+housekeeping: 470000 rects
+housekeeping: 480000 rects
+housekeeping: 490000 rects
+housekeeping: 500000 rects
+housekeeping: 510000 rects
+housekeeping: 520000 rects
+digital_pll: 10000 rects
+digital_pll: 20000 rects
+Scaled magic input cell sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__nfet_g5v0d10v5_PKVMTM geometry by factor of 2
+mgmt_protect: 10000 rects
+mgmt_protect: 20000 rects
+mgmt_protect: 30000 rects
+mgmt_protect: 40000 rects
+mgmt_protect: 50000 rects
+mgmt_protect: 60000 rects
+mgmt_protect: 70000 rects
+mgmt_protect: 80000 rects
+mgmt_protect: 90000 rects
+mgmt_protect: 100000 rects
+mgmt_protect: 110000 rects
+mgmt_protect: 120000 rects
+mgmt_protect: 130000 rects
+mgmt_protect: 140000 rects
+mgmt_protect: 150000 rects
+mgmt_protect: 160000 rects
+mgmt_protect: 170000 rects
+mgmt_protect: 180000 rects
+mgmt_protect: 190000 rects
+mgmt_protect: 200000 rects
+mgmt_protect: 210000 rects
+mgmt_protect: 220000 rects
+mgmt_protect: 230000 rects
+mgmt_protect: 240000 rects
+mgmt_protect: 250000 rects
+mgmt_protect: 260000 rects
+mgmt_protect: 270000 rects
+mgmt_protect: 280000 rects
+mgmt_protect: 290000 rects
+mgmt_protect: 300000 rects
+mgmt_protect: 310000 rects
+mgmt_protect: 320000 rects
+mgmt_protect: 330000 rects
+mgmt_protect: 340000 rects
+mgmt_protect: 350000 rects
+mgmt_protect: 360000 rects
+mgmt_protect: 370000 rects
+mgmt_protect: 380000 rects
+mgmt_protect: 390000 rects
+mgmt_protect: 400000 rects
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+Processing timestamp mismatches: sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__buf_8, sky130_ef_sc_hd__decap_12, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__corner_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped3_pad, gpio_control_power_routing, gpio_control_power_routing_right, gpio_control_power_routing_top, sky130_fd_sc_hd__inv_12, mprj2_logic_high, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__decap_6, mprj_logic_high, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hvl__conb_1, mgmt_protect_hv, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hd__bufbuf_8, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__and3b_4, sky130_fd_sc_hd__and3b_2, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__and2b_4, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, sky130_fd_sc_hvl__buf_8, sky130_fd_sc_hvl__fill_4, sky130_fd_sc_hvl__inv_8, sky130_fd_sc_hvl__schmittbuf_1, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__o21ba_2, sky130_fd_sc_hd__nand4b_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__xor2_2, sky130_fd_sc_hd__a21boi_2, sky130_fd_sc_hd__nand3b_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__clkinv_1, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__nand3_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__nand2b_2, sky130_fd_sc_hd__a211o_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__and2b_2, sky130_fd_sc_hd__xnor2_2, sky130_fd_sc_hd__and4b_2, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__a21o_4, sky130_fd_sc_hd__a21oi_4, sky130_fd_sc_hd__a221o_4, sky130_fd_sc_hd__a221oi_1, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o31a_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__xor2_1, sky130_fd_sc_hd__o21a_4, sky130_fd_sc_hd__nand3b_4, sky130_fd_sc_hd__and4b_4, sky130_fd_sc_hd__a31oi_4, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__a2111oi_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__o41a_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nand4b_1, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__a21boi_1, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__nand2b_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_4, sky130_fd_sc_hd__a2111o_4, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__and4bb_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__dlygate4sd3_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o31ai_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__nand2b_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__mux2_4, gpio_defaults_block, sky130_fd_sc_hd__and2_0, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or2_0, sky130_fd_sc_hd__dfbbn_2, sky130_fd_sc_hd__macro_sparecell, sky130_fd_sc_hd__buf_16, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__a41oi_1, sky130_fd_sc_hd__o2bb2ai_1, sky130_fd_sc_hd__o31ai_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__decap_8, seal_ring_corner_abstract.
+   Generating output for cell advSeal_6um_gen
+Reading "sealring_slots".
+Reading "seal_ring_slots_array".
+Reading "sr_polygon00011".
+Reading "sr_polygon00039".
+Reading "sr_polygon00035".
+Reading "sr_polygon00015".
+Reading "sr_polygon00007".
+Reading "sr_polygon00001".
+Reading "sr_polygon00002".
+Reading "sr_polygon00003".
+Reading "sr_polygon00004".
+Reading "sr_polygon00005".
+Reading "sr_polygon00006".
+Reading "nikon_sealring_shape".
+Reading "sr_polygon00019".
+Reading "sr_polygon00023".
+Reading "sr_polygon00027".
+Reading "sr_polygon00031".
+Reading "sr_polygon00036".
+Reading "sr_polygon00032".
+Reading "sr_polygon00016".
+Reading "sr_polygon00020".
+Reading "sr_polygon00024".
+Reading "sr_polygon00028".
+Reading "seal_ring_corner".
+Reading "advSeal_6um_gen".
+   Generating output for cell caravel_000710d6_fill_pattern
+Reading "caravel_000710d6_fill_pattern_0_0".
+Reading "caravel_000710d6_fill_pattern_1_0".
+Reading "caravel_000710d6_fill_pattern_0_1".
+Reading "caravel_000710d6_fill_pattern_1_1".
+Reading "caravel_000710d6_fill_pattern_2_0".
+Reading "caravel_000710d6_fill_pattern_2_1".
+Reading "caravel_000710d6_fill_pattern_3_0".
+Reading "caravel_000710d6_fill_pattern_3_1".
+Reading "caravel_000710d6_fill_pattern_4_0".
+Reading "caravel_000710d6_fill_pattern_4_1".
+Reading "caravel_000710d6_fill_pattern_5_0".
+Reading "caravel_000710d6_fill_pattern_5_1".
+Reading "caravel_000710d6_fill_pattern_0_2".
+Reading "caravel_000710d6_fill_pattern_1_2".
+Reading "caravel_000710d6_fill_pattern_2_2".
+Reading "caravel_000710d6_fill_pattern_3_2".
+Reading "caravel_000710d6_fill_pattern_4_2".
+Reading "caravel_000710d6_fill_pattern_5_2".
+Reading "caravel_000710d6_fill_pattern_0_3".
+Reading "caravel_000710d6_fill_pattern_1_3".
+Reading "caravel_000710d6_fill_pattern_2_3".
+Reading "caravel_000710d6_fill_pattern_3_3".
+Reading "caravel_000710d6_fill_pattern_4_3".
+Reading "caravel_000710d6_fill_pattern_5_3".
+Reading "caravel_000710d6_fill_pattern_0_4".
+Reading "caravel_000710d6_fill_pattern_1_4".
+Reading "caravel_000710d6_fill_pattern_2_4".
+Reading "caravel_000710d6_fill_pattern_3_4".
+Reading "caravel_000710d6_fill_pattern_4_4".
+Reading "caravel_000710d6_fill_pattern_5_4".
+Reading "caravel_000710d6_fill_pattern_0_5".
+Reading "caravel_000710d6_fill_pattern_1_5".
+Reading "caravel_000710d6_fill_pattern_2_5".
+Reading "caravel_000710d6_fill_pattern_3_5".
+Reading "caravel_000710d6_fill_pattern_4_5".
+Reading "caravel_000710d6_fill_pattern_5_5".
+Reading "caravel_000710d6_fill_pattern_0_6".
+Reading "caravel_000710d6_fill_pattern_1_6".
+Reading "caravel_000710d6_fill_pattern_2_6".
+Reading "caravel_000710d6_fill_pattern_3_6".
+Reading "caravel_000710d6_fill_pattern_4_6".
+Reading "caravel_000710d6_fill_pattern_5_6".
+Reading "caravel_000710d6_fill_pattern_0_7".
+Reading "caravel_000710d6_fill_pattern_1_7".
+Reading "caravel_000710d6_fill_pattern_2_7".
+Reading "caravel_000710d6_fill_pattern_3_7".
+Reading "caravel_000710d6_fill_pattern_4_7".
+Reading "caravel_000710d6_fill_pattern_5_7".
+Reading "caravel_000710d6_fill_pattern".
+   Generating output for cell caravel
+Reading "caravel_logo".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "font_79".
+Reading "font_76".
+Reading "font_74".
+Reading "font_72".
+Reading "font_70".
+Reading "font_66".
+Reading "font_63".
+Reading "font_62".
+Reading "font_57".
+Reading "font_56".
+Reading "font_50".
+Reading "font_47".
+Reading "font_44".
+Reading "font_35".
+Reading "font_32".
+Reading "font_30".
+Reading "font_29".
+Reading "font_28".
+Reading "font_20".
+Reading "font_6F".
+Reading "font_6B".
+Reading "font_4F".
+Reading "font_4B".
+Reading "font_2D".
+Reading "copyright_block".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "alpha_7".
+Reading "alpha_1".
+Reading "alpha_D".
+Reading "alpha_6".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "gpio_defaults_block_1803".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "buff_flash_clkrst".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__macro_sparecell".
+Reading "sky130_fd_sc_hd__dfbbn_2".
+Reading "sky130_fd_sc_hd__or2_0".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__and2_0".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "housekeeping".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "digital_pll".
+Reading "user_id_programming".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "WG_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "WG_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "WG_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "WG_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "WG_sky130_fd_sc_hvl__buf_8".
+Reading "WG_sky130_fd_sc_hvl__inv_8".
+Reading "WG_sky130_fd_sc_hvl__fill_4".
+Reading "WG_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "WG_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "WG_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+Reading "WJ_sky130_fd_sc_hd__decap_3".
+Reading "WJ_sky130_ef_sc_hd__decap_12".
+Reading "WJ_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "WJ_sky130_fd_sc_hd__fill_1".
+Reading "WJ_sky130_fd_sc_hd__decap_4".
+Reading "WJ_sky130_fd_sc_hd__decap_6".
+Reading "WJ_sky130_fd_sc_hd__fill_2".
+Reading "WJ_sky130_fd_sc_hd__decap_8".
+Reading "WJ_sky130_fd_sc_hd__diode_2".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_16".
+Reading "WJ_sky130_fd_sc_hd__o211a_1".
+Reading "WJ_sky130_fd_sc_hd__dfxtp_2".
+Reading "WJ_sky130_fd_sc_hd__o21a_1".
+Reading "WJ_sky130_fd_sc_hd__mux2_1".
+Reading "WJ_sky130_fd_sc_hd__or2_1".
+Reading "WJ_sky130_fd_sc_hd__dfxtp_1".
+Reading "WJ_sky130_fd_sc_hd__a22o_1".
+Reading "WJ_sky130_fd_sc_hd__a21o_2".
+Reading "WJ_sky130_fd_sc_hd__a21o_1".
+Reading "WJ_sky130_fd_sc_hd__a22o_4".
+Reading "WJ_sky130_fd_sc_hd__buf_8".
+Reading "WJ_sky130_fd_sc_hd__o21a_2".
+Reading "WJ_sky130_fd_sc_hd__mux2_2".
+Reading "WJ_sky130_fd_sc_hd__buf_4".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_8".
+Reading "WJ_sky130_fd_sc_hd__buf_6".
+Reading "WJ_sky130_fd_sc_hd__dfxtp_4".
+Reading "WJ_sky130_fd_sc_hd__buf_2".
+Reading "WJ_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "WJ_sky130_fd_sc_hd__o21ai_1".
+Reading "WJ_sky130_fd_sc_hd__mux4_1".
+Reading "WJ_sky130_fd_sc_hd__buf_12".
+Reading "WJ_sky130_fd_sc_hd__mux4_2".
+Reading "WJ_sky130_fd_sc_hd__inv_2".
+Reading "WJ_sky130_fd_sc_hd__and3_2".
+Reading "WJ_sky130_fd_sc_hd__nand2_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2o_1".
+Reading "WJ_sky130_fd_sc_hd__or3b_1".
+Reading "WJ_sky130_fd_sc_hd__o32a_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2o_2".
+Reading "WJ_sky130_fd_sc_hd__o311a_1".
+Reading "WJ_sky130_fd_sc_hd__o221a_1".
+Reading "WJ_sky130_fd_sc_hd__o31a_1".
+Reading "WJ_sky130_fd_sc_hd__o211a_2".
+Reading "WJ_sky130_fd_sc_hd__and3_1".
+Reading "WJ_sky130_fd_sc_hd__a211oi_1".
+Reading "WJ_sky130_fd_sc_hd__and4_4".
+Reading "WJ_sky130_fd_sc_hd__and4_1".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_4".
+Reading "WJ_sky130_fd_sc_hd__and3b_1".
+Reading "WJ_sky130_fd_sc_hd__a211o_4".
+Reading "WJ_sky130_fd_sc_hd__a211o_1".
+Reading "WJ_sky130_fd_sc_hd__o21ba_1".
+Reading "WJ_sky130_fd_sc_hd__a21oi_1".
+Reading "WJ_sky130_fd_sc_hd__nor2_1".
+Reading "WJ_sky130_fd_sc_hd__nand2_8".
+Reading "WJ_sky130_fd_sc_hd__a311o_1".
+Reading "WJ_sky130_fd_sc_hd__nor2_2".
+Reading "WJ_sky130_fd_sc_hd__a41o_1".
+Reading "WJ_sky130_fd_sc_hd__nor3_2".
+Reading "WJ_sky130_fd_sc_hd__or4bb_4".
+Reading "WJ_sky130_fd_sc_hd__nor3_1".
+Reading "WJ_sky130_fd_sc_hd__or4b_4".
+Reading "WJ_sky130_fd_sc_hd__or3b_4".
+Reading "WJ_sky130_fd_sc_hd__a31o_1".
+Reading "WJ_sky130_fd_sc_hd__a211o_2".
+Reading "WJ_sky130_fd_sc_hd__or2_2".
+Reading "WJ_sky130_fd_sc_hd__a31o_2".
+Reading "WJ_sky130_fd_sc_hd__a221o_1".
+Reading "WJ_sky130_fd_sc_hd__and4b_4".
+Reading "WJ_sky130_fd_sc_hd__and3_4".
+Reading "WJ_sky130_fd_sc_hd__mux2_8".
+Reading "WJ_sky130_fd_sc_hd__o21ai_2".
+Reading "WJ_sky130_fd_sc_hd__and4b_1".
+Reading "WJ_sky130_fd_sc_hd__or4b_1".
+Reading "WJ_sky130_fd_sc_hd__o211a_4".
+Reading "WJ_sky130_fd_sc_hd__a32o_1".
+Reading "WJ_sky130_fd_sc_hd__a21boi_1".
+Reading "WJ_sky130_fd_sc_hd__o41ai_4".
+Reading "WJ_sky130_fd_sc_hd__o31a_2".
+Reading "WJ_sky130_fd_sc_hd__nand2_4".
+Reading "WJ_sky130_fd_sc_hd__a31oi_4".
+Reading "WJ_sky130_fd_sc_hd__and4_2".
+Reading "WJ_sky130_fd_sc_hd__nand3_4".
+Reading "WJ_sky130_fd_sc_hd__and4b_2".
+Reading "WJ_sky130_fd_sc_hd__o41a_4".
+Reading "WJ_sky130_fd_sc_hd__and4bb_2".
+Reading "WJ_sky130_fd_sc_hd__clkinv_2".
+Reading "WJ_sky130_fd_sc_hd__and2b_2".
+Reading "WJ_sky130_fd_sc_hd__or4bb_1".
+Reading "WJ_sky130_fd_sc_hd__a21oi_2".
+Reading "WJ_sky130_fd_sc_hd__a221oi_1".
+Reading "WJ_sky130_fd_sc_hd__a31oi_1".
+Reading "WJ_sky130_fd_sc_hd__xor2_4".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_1".
+Reading "WJ_sky130_fd_sc_hd__nand3b_4".
+Reading "WJ_sky130_fd_sc_hd__nand2_2".
+Reading "WJ_sky130_fd_sc_hd__xnor2_1".
+Reading "WJ_sky130_fd_sc_hd__and2_1".
+Reading "WJ_sky130_fd_sc_hd__nor2_4".
+Reading "WJ_sky130_fd_sc_hd__nand4_4".
+Reading "WJ_sky130_fd_sc_hd__a32o_2".
+Reading "WJ_sky130_fd_sc_hd__nor4_1".
+Reading "WJ_sky130_fd_sc_hd__nand4_1".
+Reading "WJ_sky130_fd_sc_hd__xor2_1".
+Reading "WJ_sky130_fd_sc_hd__and4bb_4".
+Reading "WJ_sky130_fd_sc_hd__a41o_2".
+Reading "WJ_sky130_fd_sc_hd__o2bb2a_1".
+Reading "WJ_sky130_fd_sc_hd__xnor2_2".
+Reading "WJ_sky130_fd_sc_hd__xor2_2".
+Reading "WJ_sky130_fd_sc_hd__or2_4".
+Reading "WJ_sky130_fd_sc_hd__a2111oi_2".
+Reading "WJ_sky130_fd_sc_hd__nor4_4".
+Reading "WJ_sky130_fd_sc_hd__mux2_4".
+Reading "WJ_sky130_fd_sc_hd__and2b_1".
+Reading "WJ_sky130_fd_sc_hd__and2_2".
+Reading "WJ_sky130_fd_sc_hd__nor4b_1".
+Reading "WJ_sky130_fd_sc_hd__o2111ai_4".
+Reading "WJ_sky130_fd_sc_hd__nor4_2".
+Reading "WJ_sky130_fd_sc_hd__nand3b_2".
+Reading "WJ_sky130_fd_sc_hd__nand3_1".
+Reading "WJ_sky130_fd_sc_hd__nand2b_2".
+Reading "WJ_sky130_fd_sc_hd__o31ai_1".
+Reading "WJ_sky130_fd_sc_hd__o41a_1".
+Reading "WJ_sky130_fd_sc_hd__a21bo_1".
+Reading "WJ_sky130_fd_sc_hd__o41ai_1".
+Reading "WJ_sky130_fd_sc_hd__nand3b_1".
+Reading "WJ_sky130_fd_sc_hd__o2111a_1".
+Reading "WJ_sky130_fd_sc_hd__o21a_4".
+Reading "WJ_sky130_fd_sc_hd__o22a_1".
+Reading "WJ_sky130_fd_sc_hd__or3b_2".
+Reading "WJ_sky130_fd_sc_hd__nand2b_1".
+Reading "WJ_sky130_fd_sc_hd__nor4b_4".
+Reading "WJ_sky130_fd_sc_hd__o21bai_1".
+Reading "WJ_sky130_fd_sc_hd__nor3_4".
+Reading "WJ_sky130_fd_sc_hd__o41a_2".
+Reading "WJ_sky130_fd_sc_hd__or4b_2".
+Reading "WJ_sky130_fd_sc_hd__a221o_4".
+Reading "WJ_sky130_fd_sc_hd__a2111oi_1".
+Reading "WJ_sky130_fd_sc_hd__o31a_4".
+Reading "WJ_sky130_fd_sc_hd__nor2_8".
+Reading "WJ_sky130_fd_sc_hd__clkinv_4".
+Reading "WJ_sky130_fd_sc_hd__a221o_2".
+Reading "WJ_sky130_fd_sc_hd__o21ai_4".
+Reading "WJ_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_2".
+Reading "WJ_sky130_fd_sc_hd__a31o_4".
+Reading "WJ_sky130_fd_sc_hd__ebufn_4".
+Reading "WJ_sky130_fd_sc_hd__dlxtp_1".
+Reading "WJ_sky130_fd_sc_hd__dlclkp_1".
+Reading "WJ_sky130_fd_sc_hd__conb_1".
+Reading "WJ_sky130_fd_sc_hd__inv_1".
+Reading "WJ_sky130_fd_sc_hd__nor4b_2".
+Reading "WJ_sky130_fd_sc_hd__and3b_2".
+Reading "WJ_sky130_fd_sc_hd__nor3b_2".
+Reading "WJ_RAM256".
+Reading "WJ_sky130_fd_sc_hd__a21o_4".
+Reading "WJ_sky130_fd_sc_hd__o2111a_4".
+Reading "WJ_sky130_fd_sc_hd__a22o_2".
+Reading "WJ_sky130_fd_sc_hd__o211ai_4".
+Reading "WJ_sky130_fd_sc_hd__o22ai_4".
+Reading "WJ_sky130_fd_sc_hd__a221oi_4".
+Reading "WJ_sky130_fd_sc_hd__and2b_4".
+Reading "WJ_sky130_fd_sc_hd__and3b_4".
+Reading "WJ_sky130_fd_sc_hd__and4bb_1".
+Reading "WJ_sky130_fd_sc_hd__a21oi_4".
+Reading "WJ_sky130_fd_sc_hd__o22ai_1".
+Reading "WJ_sky130_fd_sc_hd__inv_4".
+Reading "WJ_sky130_fd_sc_hd__a311o_2".
+Reading "WJ_sky130_fd_sc_hd__a2111o_1".
+Reading "WJ_sky130_fd_sc_hd__o311a_4".
+Reading "WJ_sky130_fd_sc_hd__o2111ai_1".
+Reading "WJ_sky130_fd_sc_hd__clkinv_8".
+Reading "WJ_sky130_fd_sc_hd__nand3_2".
+Reading "WJ_sky130_fd_sc_hd__a22oi_1".
+Reading "WJ_sky130_fd_sc_hd__nand4b_4".
+Reading "WJ_sky130_fd_sc_hd__o221ai_4".
+Reading "WJ_sky130_fd_sc_hd__nand4_2".
+Reading "WJ_sky130_fd_sc_hd__inv_6".
+Reading "WJ_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "WJ_sky130_fd_sc_hd__a311oi_4".
+Reading "WJ_sky130_fd_sc_hd__o32ai_4".
+Reading "WJ_sky130_fd_sc_hd__o211ai_1".
+Reading "WJ_sky130_fd_sc_hd__nand4b_1".
+Reading "WJ_sky130_fd_sc_hd__o211ai_2".
+Reading "WJ_sky130_fd_sc_hd__a22oi_4".
+Reading "WJ_sky130_fd_sc_hd__and2_4".
+Reading "WJ_sky130_fd_sc_hd__a211oi_4".
+Reading "WJ_sky130_fd_sc_hd__nor3b_4".
+Reading "WJ_sky130_fd_sc_hd__o22a_2".
+Reading "WJ_sky130_fd_sc_hd__a2111oi_4".
+Reading "WJ_sky130_fd_sc_hd__nand2b_4".
+Reading "WJ_sky130_fd_sc_hd__a2bb2o_4".
+Reading "WJ_sky130_fd_sc_hd__o2bb2a_2".
+Reading "WJ_sky130_fd_sc_hd__o2111ai_2".
+Reading "WJ_sky130_fd_sc_hd__a22oi_2".
+Reading "WJ_sky130_fd_sc_hd__nor3b_1".
+Reading "WJ_sky130_fd_sc_hd__o2bb2a_4".
+Reading "WJ_sky130_fd_sc_hd__o21bai_4".
+Reading "WJ_sky130_fd_sc_hd__o311ai_1".
+Reading "WJ_sky130_fd_sc_hd__a32oi_2".
+Reading "WJ_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "WJ_sky130_fd_sc_hd__o311ai_4".
+Reading "WJ_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "WJ_sky130_fd_sc_hd__o31ai_4".
+Reading "WJ_sky130_fd_sc_hd__o221a_2".
+Reading "WJ_sky130_fd_sc_hd__o2111a_2".
+Reading "WJ_sky130_fd_sc_hd__a31oi_2".
+Reading "WJ_sky130_fd_sc_hd__o311a_2".
+Reading "WJ_sky130_fd_sc_hd__o22a_4".
+Reading "WJ_sky130_fd_sc_hd__a32oi_4".
+Reading "WJ_sky130_fd_sc_hd__a211oi_2".
+Reading "WJ_sky130_fd_sc_hd__o31ai_2".
+Reading "WJ_sky130_fd_sc_hd__o221ai_1".
+Reading "WJ_sky130_fd_sc_hd__clkinv_16".
+Reading "WJ_sky130_fd_sc_hd__or4bb_2".
+Reading "WJ_sky130_fd_sc_hd__a221oi_2".
+Reading "WJ_sky130_fd_sc_hd__inv_8".
+Reading "WJ_sky130_fd_sc_hd__a311oi_2".
+Reading "WJ_sky130_fd_sc_hd__a311oi_1".
+Reading "WJ_sky130_fd_sc_hd__o311ai_2".
+Reading "WJ_sky130_fd_sc_hd__a32oi_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "WJ_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "WJ_sky130_fd_sc_hd__xnor2_4".
+Reading "WJ_sky130_fd_sc_hd__inv_12".
+Reading "WJ_sky130_fd_sc_hd__a2111o_4".
+Reading "WJ_sky130_fd_sc_hd__a32o_4".
+Reading "WJ_sky130_fd_sc_hd__o21ba_2".
+Reading "WJ_sky130_fd_sc_hd__a41oi_2".
+Reading "WJ_sky130_fd_sc_hd__o22ai_2".
+Reading "WJ_sky130_fd_sc_hd__o21bai_2".
+Reading "WJ_sky130_fd_sc_hd__a41oi_4".
+Reading "WJ_sky130_fd_sc_hd__a41o_4".
+Reading "WJ_sky130_fd_sc_hd__a311o_4".
+Reading "WJ_sky130_fd_sc_hd__o32ai_1".
+Reading "WJ_sky130_fd_sc_hd__a21boi_4".
+Reading "WJ_sky130_fd_sc_hd__o32ai_2".
+Reading "WJ_sky130_fd_sc_hd__a21bo_2".
+Reading "WJ_RAM128".
+Reading "mgmt_core_wrapper".
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "mgmt_protect".
+Reading "gpio_defaults_block_0801".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "QN_sky130_fd_sc_hd__nor4_1".
+Reading "QN_sky130_fd_sc_hd__a221oi_1".
+Reading "QN_sky130_fd_sc_hd__or4b_2".
+Reading "QN_sky130_fd_sc_hd__a2111o_2".
+Reading "QN_sky130_fd_sc_hd__a22oi_1".
+Reading "QN_sky130_fd_sc_hd__o2111ai_1".
+Reading "QN_sky130_fd_sc_hd__a211oi_1".
+Reading "QN_sky130_fd_sc_hd__o31ai_1".
+Reading "QN_sky130_fd_sc_hd__a22oi_2".
+Reading "QN_sky130_fd_sc_hd__o2111a_1".
+Reading "QN_sky130_fd_sc_hd__mux4_1".
+Reading "QN_sky130_fd_sc_hd__a21boi_1".
+Reading "QN_sky130_fd_sc_hd__dfxtp_1".
+Reading "QN_sky130_fd_sc_hd__a41o_1".
+Reading "QN_sky130_fd_sc_hd__and4b_2".
+Reading "QN_sky130_fd_sc_hd__o221a_2".
+Reading "QN_sky130_fd_sc_hd__dfrtp_4".
+Reading "QN_sky130_fd_sc_hd__mux2_2".
+Reading "QN_sky130_fd_sc_hd__or4_2".
+Reading "QN_sky130_fd_sc_hd__clkinv_2".
+Reading "QN_sky130_fd_sc_hd__nand3b_1".
+Reading "QN_sky130_fd_sc_hd__o31ai_2".
+Reading "QN_sky130_fd_sc_hd__a2bb2o_1".
+Reading "QN_sky130_fd_sc_hd__o21bai_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_8".
+Reading "QN_sky130_fd_sc_hd__o32ai_4".
+Reading "QN_sky130_fd_sc_hd__o221ai_1".
+Reading "QN_sky130_fd_sc_hd__o22ai_1".
+Reading "QN_sky130_fd_sc_hd__nand3_1".
+Reading "QN_sky130_fd_sc_hd__o2bb2a_1".
+Reading "QN_sky130_fd_sc_hd__nand4_1".
+Reading "QN_sky130_fd_sc_hd__dfstp_2".
+Reading "QN_sky130_fd_sc_hd__dfstp_1".
+Reading "QN_sky130_ef_sc_hd__decap_12".
+Reading "QN_sky130_fd_sc_hd__o221a_1".
+Reading "QN_sky130_fd_sc_hd__o211a_1".
+Reading "QN_sky130_fd_sc_hd__o31a_1".
+Reading "QN_sky130_fd_sc_hd__nand2_2".
+Reading "QN_sky130_fd_sc_hd__or4_1".
+Reading "QN_sky130_fd_sc_hd__or4b_1".
+Reading "QN_sky130_fd_sc_hd__o21ai_2".
+Reading "QN_sky130_fd_sc_hd__a211o_1".
+Reading "QN_sky130_fd_sc_hd__o211ai_1".
+Reading "QN_sky130_fd_sc_hd__and4_1".
+Reading "QN_sky130_fd_sc_hd__a211oi_2".
+Reading "QN_sky130_fd_sc_hd__and3b_2".
+Reading "QN_sky130_fd_sc_hd__or4bb_1".
+Reading "QN_sky130_fd_sc_hd__and3b_4".
+Reading "QN_sky130_fd_sc_hd__o21ba_1".
+Reading "QN_sky130_fd_sc_hd__dfrtp_2".
+Reading "QN_sky130_fd_sc_hd__and4b_1".
+Reading "QN_sky130_fd_sc_hd__a21oi_2".
+Reading "QN_sky130_fd_sc_hd__o22a_1".
+Reading "QN_sky130_fd_sc_hd__a311o_1".
+Reading "QN_sky130_fd_sc_hd__xnor2_2".
+Reading "QN_sky130_fd_sc_hd__nor3_1".
+Reading "QN_sky130_fd_sc_hd__a21oi_1".
+Reading "QN_sky130_fd_sc_hd__o311a_1".
+Reading "QN_sky130_fd_sc_hd__or3b_4".
+Reading "QN_sky130_fd_sc_hd__and2_1".
+Reading "QN_sky130_fd_sc_hd__nor3b_1".
+Reading "QN_sky130_fd_sc_hd__a21bo_1".
+Reading "QN_sky130_fd_sc_hd__o32a_1".
+Reading "QN_sky130_fd_sc_hd__xor2_1".
+Reading "QN_sky130_fd_sc_hd__nand4_4".
+Reading "QN_sky130_fd_sc_hd__a31o_1".
+Reading "QN_sky130_fd_sc_hd__nand2_1".
+Reading "QN_sky130_fd_sc_hd__xnor2_1".
+Reading "QN_sky130_fd_sc_hd__and2b_1".
+Reading "QN_sky130_fd_sc_hd__nor2_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_16".
+Reading "QN_sky130_fd_sc_hd__and3_1".
+Reading "QN_sky130_fd_sc_hd__o21ai_1".
+Reading "QN_sky130_fd_sc_hd__nand2b_1".
+Reading "QN_sky130_fd_sc_hd__a32o_1".
+Reading "QN_sky130_fd_sc_hd__and3b_1".
+Reading "QN_sky130_fd_sc_hd__buf_4".
+Reading "QN_sky130_fd_sc_hd__conb_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_4".
+Reading "QN_sky130_fd_sc_hd__a22o_1".
+Reading "QN_sky130_fd_sc_hd__or4b_4".
+Reading "QN_sky130_fd_sc_hd__and4bb_1".
+Reading "QN_sky130_fd_sc_hd__buf_6".
+Reading "QN_sky130_fd_sc_hd__or3b_1".
+Reading "QN_sky130_fd_sc_hd__a221o_1".
+Reading "QN_sky130_fd_sc_hd__a21o_1".
+Reading "QN_sky130_fd_sc_hd__inv_2".
+Reading "QN_sky130_fd_sc_hd__or2_1".
+Reading "QN_sky130_fd_sc_hd__o21a_1".
+Reading "QN_sky130_fd_sc_hd__or3_1".
+Reading "QN_sky130_fd_sc_hd__diode_2".
+Reading "QN_sky130_fd_sc_hd__clkbuf_1".
+Reading "QN_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_2".
+Reading "QN_sky130_fd_sc_hd__buf_2".
+Reading "QN_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "QN_sky130_fd_sc_hd__decap_8".
+Reading "QN_sky130_fd_sc_hd__dfrtp_1".
+Reading "QN_sky130_fd_sc_hd__decap_4".
+Reading "QN_sky130_fd_sc_hd__decap_6".
+Reading "QN_sky130_fd_sc_hd__fill_1".
+Reading "QN_sky130_fd_sc_hd__fill_2".
+Reading "QN_sky130_fd_sc_hd__decap_3".
+Reading "QN_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "QN_sky130_fd_sc_hd__mux2_1".
+Reading "QN_sky130_fd_sc_hd__buf_8".
+Reading "QN_sky130_fd_sc_hd__buf_12".
+Reading "QN_sky130_fd_sc_hd__o2bb2a_2".
+Reading "QN_sky130_fd_sc_hd__nand4_2".
+Reading "QN_sky130_fd_sc_hd__a221o_2".
+Reading "QN_sky130_fd_sc_hd__a31oi_2".
+Reading "QN_sky130_fd_sc_hd__or3b_2".
+Reading "QN_sky130_fd_sc_hd__or3_2".
+Reading "QN_sky130_fd_sc_hd__and2b_2".
+Reading "QN_sky130_fd_sc_hd__a31o_2".
+Reading "QN_sky130_fd_sc_hd__xor2_2".
+Reading "QN_sky130_fd_sc_hd__nor2_2".
+Reading "QN_sky130_fd_sc_hd__a22o_2".
+Reading "QN_sky130_fd_sc_hd__o21a_2".
+Reading "QN_sky130_fd_sc_hd__nand2b_2".
+Reading "QN_sky130_fd_sc_hd__o211a_2".
+Reading "QN_sky130_fd_sc_hd__a21o_2".
+Reading "QN_sky130_fd_sc_hd__o22a_2".
+Reading "QN_sky130_fd_sc_hd__nand3b_2".
+Reading "QN_sky130_fd_sc_hd__and4_2".
+Reading "QN_sky130_fd_sc_hd__a311o_2".
+Reading "QN_sky130_fd_sc_hd__a211o_2".
+Reading "QN_sky130_fd_sc_hd__nand3_2".
+Reading "QN_sky130_fd_sc_hd__and3_2".
+Reading "QN_sky130_fd_sc_hd__a32o_2".
+Reading "QN_sky130_fd_sc_hd__a21boi_2".
+Reading "QN_sky130_fd_sc_hd__and2_2".
+Reading "QN_sky130_fd_sc_hd__a2111oi_2".
+Reading "QN_sky130_fd_sc_hd__or2_2".
+Reading "QN_sky130_fd_sc_hd__and4_4".
+Reading "QN_sky130_fd_sc_hd__a2bb2o_2".
+Reading "QN_sky130_fd_sc_hd__and4bb_4".
+Reading "QN_sky130_fd_sc_hd__o31ai_4".
+Reading "QN_sky130_fd_sc_hd__o21ba_4".
+Reading "QN_sky130_fd_sc_hd__nand2_4".
+Reading "QN_sky130_fd_sc_hd__a31oi_1".
+Reading "QN_sky130_fd_sc_hd__o31a_2".
+Reading "QN_sky130_fd_sc_hd__a2111o_1".
+Reading "QN_sky130_fd_sc_hd__or3_4".
+Reading "QN_sky130_fd_sc_hd__o311a_4".
+Reading "QN_sky130_fd_sc_hd__nor2_8".
+Reading "QN_sky130_fd_sc_hd__and3_4".
+Reading "QN_sky130_fd_sc_hd__and2_4".
+Reading "QN_sky130_fd_sc_hd__a21bo_4".
+Reading "QN_sky130_fd_sc_hd__nor2_4".
+Reading "QN_sky130_fd_sc_hd__o22ai_4".
+Reading "QN_sky130_fd_sc_hd__a22oi_4".
+Reading "QN_sky130_fd_sc_hd__a21oi_4".
+Reading "QN_sky130_fd_sc_hd__a211oi_4".
+Reading "QN_sky130_fd_sc_hd__o21ai_4".
+Reading "QN_sky130_fd_sc_hd__or4_4".
+Reading "QN_sky130_fd_sc_hd__or2_4".
+Reading "QN_sky130_fd_sc_hd__nand2_8".
+Reading "QN_sky130_fd_sc_hd__xor2_4".
+Reading "QN_sky130_fd_sc_hd__dfxtp_2".
+Reading "QN_sky130_fd_sc_hd__a211o_4".
+Reading "QN_sky130_fd_sc_hd__a31o_4".
+Reading "QN_sky130_fd_sc_hd__a22o_4".
+Reading "QN_sky130_fd_sc_hd__o31a_4".
+Reading "QN_sky130_fd_sc_hd__xnor2_4".
+Reading "QN_sky130_fd_sc_hd__mux2_4".
+Reading "QN_sky130_fd_sc_hd__mux2_8".
+Reading "QN_sky130_fd_sc_hd__mux4_2".
+Reading "QN_sky130_fd_sc_hd__dfxtp_4".
+Reading "QN_sky130_fd_sc_hd__a221o_4".
+Reading "QN_sky130_fd_sc_hd__nand2b_4".
+Reading "QN_sky130_fd_sc_hd__clkinv_4".
+Reading "QN_sky130_fd_sc_hd__o221ai_4".
+Reading "QN_sky130_fd_sc_hd__nand3_4".
+Reading "QN_sky130_fd_sc_hd__o41a_1".
+Reading "QN_sky130_fd_sc_hd__nor3_2".
+Reading "QN_sky130_fd_sc_hd__nor4_4".
+Reading "QN_sky130_fd_sc_hd__a2111oi_4".
+Reading "QN_sky130_fd_sc_hd__a2111o_4".
+Reading "QN_sky130_fd_sc_hd__a31oi_4".
+Reading "QN_sky130_fd_sc_hd__o22ai_2".
+Reading "QN_sky130_fd_sc_hd__a32oi_4".
+Reading "QN_sky130_fd_sc_hd__a221oi_4".
+Reading "QN_sky130_fd_sc_hd__nor4b_1".
+Reading "QN_sky130_fd_sc_hd__nor3b_4".
+Reading "QN_sky130_fd_sc_hd__and4bb_2".
+Reading "QN_sky130_fd_sc_hd__a311o_4".
+Reading "QN_sky130_fd_sc_hd__o311ai_2".
+Reading "QN_sky130_fd_sc_hd__nor3_4".
+Reading "QN_sky130_fd_sc_hd__a311oi_4".
+Reading "QN_sky130_fd_sc_hd__o2111ai_2".
+Reading "QN_sky130_fd_sc_hd__o211ai_4".
+Reading "QN_sky130_fd_sc_hd__inv_4".
+Reading "QN_sky130_fd_sc_hd__o21bai_2".
+Reading "QN_sky130_fd_sc_hd__o22a_4".
+Reading "QN_sky130_fd_sc_hd__a2bb2o_4".
+Reading "QN_sky130_fd_sc_hd__o211a_4".
+Reading "QN_sky130_fd_sc_hd__o211ai_2".
+Reading "QN_sky130_fd_sc_hd__o21ba_2".
+Reading "QN_sky130_fd_sc_hd__o2111a_2".
+Reading "QN_sky130_fd_sc_hd__dfstp_4".
+Reading "QN_sky130_fd_sc_hd__o221ai_2".
+Reading "QN_sky130_fd_sc_hd__a21bo_2".
+Reading "QN_sky130_fd_sc_hd__o21a_4".
+Reading "QN_sky130_fd_sc_hd__and2b_4".
+Reading "QN_sky130_fd_sc_hd__nand3b_4".
+Reading "QN_sky130_fd_sc_hd__o32a_4".
+Reading "QN_sky130_fd_sc_hd__and4b_4".
+Reading "QN_ycr_core_top".
+Reading "QN_sky130_fd_sc_hd__clkinv_8".
+Reading "QN_sky130_fd_sc_hd__or2b_1".
+Reading "QN_sky130_fd_sc_hd__o2111ai_4".
+Reading "QN_sky130_fd_sc_hd__or4bb_2".
+Reading "QN_sky130_fd_sc_hd__inv_6".
+Reading "QN_sky130_fd_sc_hd__a21o_4".
+Reading "QN_sky130_fd_sc_hd__o311a_2".
+Reading "QN_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "QN_sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "QN_sky130_fd_sc_hd__nor4_2".
+Reading "QN_sky130_fd_sc_hd__or2b_2".
+Reading "QN_sky130_fd_sc_hd__buf_1".
+Reading "QN_ycr4_iconnect".
+Reading "QN_bus_rep_west".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "QN_sky130_fd_bd_sram__openram_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "QN_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "QN_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "QN_sky130_fd_bd_sram__openram_sense_amp".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "QN_sky130_fd_bd_sram__openram_write_driver".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "QN_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "QN_sky130_fd_sc_hd__a2111oi_1".
+Reading "QN_sky130_fd_sc_hd__o32a_2".
+Reading "QN_sky130_fd_sc_hd__nand4b_2".
+Reading "QN_sky130_fd_sc_hd__o21bai_4".
+Reading "QN_ycr_intf".
+Reading "QN_sky130_fd_sc_hd__nor4b_2".
+Reading "QN_peri_top".
+Reading "QN_sky130_fd_sc_hd__nor3b_2".
+Reading "QN_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "QN_sky130_fd_sc_hd__nor4b_4".
+Reading "QN_sky130_fd_sc_hd__or2b_4".
+Reading "QN_sky130_fd_sc_hd__o41a_2".
+Reading "QN_qspim_top".
+Reading "QN_sky130_fd_sc_hd__a41oi_4".
+Reading "QN_sky130_fd_sc_hd__o221a_4".
+Reading "QN_sky130_fd_sc_hd__a41o_2".
+Reading "QN_sky130_fd_sc_hd__a41o_4".
+Reading "QN_wb_interconnect".
+Reading "QN_bus_rep_east".
+Reading "QN_switchn".
+Reading "QN_resistor".
+Reading "QN_resistor_3xh".
+Reading "QN_switch2".
+Reading "QN_switch2n".
+Reading "QN_2bit_DAC".
+Reading "QN_resistor_h".
+Reading "QN_3bit_DAC".
+Reading "QN_4bit_DAC".
+Reading "QN_5bit_DAC".
+Reading "QN_6bit_DAC".
+Reading "QN_7bit_DAC".
+Reading "QN_8bit_DAC".
+Reading "QN_2x8bit_DAC".
+Reading "QN_4x8bit_DAC".
+Reading "QN_dac_top".
+Reading "QN_sky130_fd_sc_hd__einvn_8".
+Reading "QN_sky130_fd_sc_hd__clkinv_1".
+Reading "QN_sky130_fd_sc_hd__einvp_2".
+Reading "QN_sky130_fd_sc_hd__einvn_2".
+Reading "QN_sky130_fd_sc_hd__einvp_1".
+Reading "QN_dg_pll".
+Reading "QN_sky130_fd_sc_hd__dlclkp_2".
+Reading "QN_sky130_fd_sc_hd__dlclkp_1".
+Reading "QN_sky130_fd_sc_hd__o32ai_1".
+Reading "QN_sky130_fd_sc_hd__nor2b_1".
+Reading "QN_sky130_fd_sc_hd__a311oi_1".
+Reading "QN_wb_host".
+Reading "QN_sky130_fd_sc_hd__o41ai_1".
+Reading "QN_sky130_fd_sc_hd__a311oi_2".
+Reading "QN_sky130_fd_sc_hd__o311ai_4".
+Reading "QN_sky130_fd_sc_hd__or4bb_4".
+Reading "QN_sky130_fd_sc_hd__o41a_4".
+Reading "QN_uart_i2c_usb_spi_top".
+Reading "QN_sky130_fd_sc_hd__a21boi_4".
+Reading "QN_sky130_fd_sc_hd__dlxtn_2".
+Reading "QN_sky130_fd_sc_hd__dlxtn_1".
+Reading "QN_sky130_fd_sc_hd__nand4b_1".
+Reading "QN_pinmux_top".
+Reading "QN_bus_rep_south".
+Reading "QN_bus_rep_north".
+Reading "user_project_wrapper".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "constant_block".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "chip_io_gpio_connects".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "gpio_signal_buffering".
+Reading "caravel".
+   Generating output for cell caravel_000710d6
+Ended: 12/14/2022 12:41:29
diff --git a/tapeout/logs/fill_final.log b/tapeout/logs/fill_final.log
new file mode 100644
index 0000000..850e420
--- /dev/null
+++ b/tapeout/logs/fill_final.log
@@ -0,0 +1,114 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_final.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+Writing final GDS
+   Generating output for cell caravel_000710d6_fill_pattern_0_0
+Reading "caravel_000710d6_fill_pattern_0_0".
+   Generating output for cell caravel_000710d6_fill_pattern_1_0
+Reading "caravel_000710d6_fill_pattern_1_0".
+   Generating output for cell caravel_000710d6_fill_pattern_0_1
+Reading "caravel_000710d6_fill_pattern_0_1".
+   Generating output for cell caravel_000710d6_fill_pattern_1_1
+Reading "caravel_000710d6_fill_pattern_1_1".
+   Generating output for cell caravel_000710d6_fill_pattern_2_0
+Reading "caravel_000710d6_fill_pattern_2_0".
+   Generating output for cell caravel_000710d6_fill_pattern_2_1
+Reading "caravel_000710d6_fill_pattern_2_1".
+   Generating output for cell caravel_000710d6_fill_pattern_3_0
+Reading "caravel_000710d6_fill_pattern_3_0".
+   Generating output for cell caravel_000710d6_fill_pattern_3_1
+Reading "caravel_000710d6_fill_pattern_3_1".
+   Generating output for cell caravel_000710d6_fill_pattern_4_0
+Reading "caravel_000710d6_fill_pattern_4_0".
+   Generating output for cell caravel_000710d6_fill_pattern_4_1
+Reading "caravel_000710d6_fill_pattern_4_1".
+   Generating output for cell caravel_000710d6_fill_pattern_5_0
+Reading "caravel_000710d6_fill_pattern_5_0".
+   Generating output for cell caravel_000710d6_fill_pattern_5_1
+Reading "caravel_000710d6_fill_pattern_5_1".
+   Generating output for cell caravel_000710d6_fill_pattern_0_2
+Reading "caravel_000710d6_fill_pattern_0_2".
+   Generating output for cell caravel_000710d6_fill_pattern_1_2
+Reading "caravel_000710d6_fill_pattern_1_2".
+   Generating output for cell caravel_000710d6_fill_pattern_2_2
+Reading "caravel_000710d6_fill_pattern_2_2".
+   Generating output for cell caravel_000710d6_fill_pattern_3_2
+Reading "caravel_000710d6_fill_pattern_3_2".
+   Generating output for cell caravel_000710d6_fill_pattern_4_2
+Reading "caravel_000710d6_fill_pattern_4_2".
+   Generating output for cell caravel_000710d6_fill_pattern_5_2
+Reading "caravel_000710d6_fill_pattern_5_2".
+   Generating output for cell caravel_000710d6_fill_pattern_0_3
+Reading "caravel_000710d6_fill_pattern_0_3".
+   Generating output for cell caravel_000710d6_fill_pattern_1_3
+Reading "caravel_000710d6_fill_pattern_1_3".
+   Generating output for cell caravel_000710d6_fill_pattern_2_3
+Reading "caravel_000710d6_fill_pattern_2_3".
+   Generating output for cell caravel_000710d6_fill_pattern_3_3
+Reading "caravel_000710d6_fill_pattern_3_3".
+   Generating output for cell caravel_000710d6_fill_pattern_4_3
+Reading "caravel_000710d6_fill_pattern_4_3".
+   Generating output for cell caravel_000710d6_fill_pattern_5_3
+Reading "caravel_000710d6_fill_pattern_5_3".
+   Generating output for cell caravel_000710d6_fill_pattern_0_4
+Reading "caravel_000710d6_fill_pattern_0_4".
+   Generating output for cell caravel_000710d6_fill_pattern_1_4
+Reading "caravel_000710d6_fill_pattern_1_4".
+   Generating output for cell caravel_000710d6_fill_pattern_2_4
+Reading "caravel_000710d6_fill_pattern_2_4".
+   Generating output for cell caravel_000710d6_fill_pattern_3_4
+Reading "caravel_000710d6_fill_pattern_3_4".
+   Generating output for cell caravel_000710d6_fill_pattern_4_4
+Reading "caravel_000710d6_fill_pattern_4_4".
+   Generating output for cell caravel_000710d6_fill_pattern_5_4
+Reading "caravel_000710d6_fill_pattern_5_4".
+   Generating output for cell caravel_000710d6_fill_pattern_0_5
+Reading "caravel_000710d6_fill_pattern_0_5".
+   Generating output for cell caravel_000710d6_fill_pattern_1_5
+Reading "caravel_000710d6_fill_pattern_1_5".
+   Generating output for cell caravel_000710d6_fill_pattern_2_5
+Reading "caravel_000710d6_fill_pattern_2_5".
+   Generating output for cell caravel_000710d6_fill_pattern_3_5
+Reading "caravel_000710d6_fill_pattern_3_5".
+   Generating output for cell caravel_000710d6_fill_pattern_4_5
+Reading "caravel_000710d6_fill_pattern_4_5".
+   Generating output for cell caravel_000710d6_fill_pattern_5_5
+Reading "caravel_000710d6_fill_pattern_5_5".
+   Generating output for cell caravel_000710d6_fill_pattern_0_6
+Reading "caravel_000710d6_fill_pattern_0_6".
+   Generating output for cell caravel_000710d6_fill_pattern_1_6
+Reading "caravel_000710d6_fill_pattern_1_6".
+   Generating output for cell caravel_000710d6_fill_pattern_2_6
+Reading "caravel_000710d6_fill_pattern_2_6".
+   Generating output for cell caravel_000710d6_fill_pattern_3_6
+Reading "caravel_000710d6_fill_pattern_3_6".
+   Generating output for cell caravel_000710d6_fill_pattern_4_6
+Reading "caravel_000710d6_fill_pattern_4_6".
+   Generating output for cell caravel_000710d6_fill_pattern_5_6
+Reading "caravel_000710d6_fill_pattern_5_6".
+   Generating output for cell caravel_000710d6_fill_pattern_0_7
+Reading "caravel_000710d6_fill_pattern_0_7".
+   Generating output for cell caravel_000710d6_fill_pattern_1_7
+Reading "caravel_000710d6_fill_pattern_1_7".
+   Generating output for cell caravel_000710d6_fill_pattern_2_7
+Reading "caravel_000710d6_fill_pattern_2_7".
+   Generating output for cell caravel_000710d6_fill_pattern_3_7
+Reading "caravel_000710d6_fill_pattern_3_7".
+   Generating output for cell caravel_000710d6_fill_pattern_4_7
+Reading "caravel_000710d6_fill_pattern_4_7".
+   Generating output for cell caravel_000710d6_fill_pattern_5_7
+Reading "caravel_000710d6_fill_pattern_5_7".
+   Generating output for cell caravel_000710d6_fill_pattern
+Ended: 12/14/2022 12:40:05
diff --git a/tapeout/logs/fill_initial.log b/tapeout/logs/fill_initial.log
new file mode 100644
index 0000000..4221cde
--- /dev/null
+++ b/tapeout/logs/fill_initial.log
@@ -0,0 +1,1901 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill.tcl" from command line.
+Started: 12/14/2022 11:38:23
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: caravel
+Reading "caravel_logo".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "font_79".
+Reading "font_76".
+Reading "font_74".
+Reading "font_72".
+Reading "font_70".
+Reading "font_66".
+Reading "font_63".
+Reading "font_62".
+Reading "font_57".
+Reading "font_56".
+Reading "font_50".
+Reading "font_47".
+Reading "font_44".
+Reading "font_35".
+Reading "font_32".
+Reading "font_30".
+Reading "font_29".
+Reading "font_28".
+Reading "font_20".
+Reading "font_6F".
+Reading "font_6B".
+Reading "font_4F".
+Reading "font_4B".
+Reading "font_2D".
+Reading "copyright_block".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "alpha_7".
+Reading "alpha_1".
+Reading "alpha_D".
+Reading "alpha_6".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "gpio_defaults_block_1803".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "buff_flash_clkrst".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__macro_sparecell".
+Reading "sky130_fd_sc_hd__dfbbn_2".
+Reading "sky130_fd_sc_hd__or2_0".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__and2_0".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "housekeeping".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "digital_pll".
+Reading "user_id_programming".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "WG_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "WG_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "WG_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "WG_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "WG_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "WG_sky130_fd_sc_hvl__buf_8".
+Reading "WG_sky130_fd_sc_hvl__inv_8".
+Reading "WG_sky130_fd_sc_hvl__fill_4".
+Reading "WG_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "WG_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "WG_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+Reading "WJ_sky130_fd_sc_hd__decap_3".
+Reading "WJ_sky130_ef_sc_hd__decap_12".
+Reading "WJ_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "WJ_sky130_fd_sc_hd__fill_1".
+Reading "WJ_sky130_fd_sc_hd__decap_4".
+Reading "WJ_sky130_fd_sc_hd__decap_6".
+Reading "WJ_sky130_fd_sc_hd__fill_2".
+Reading "WJ_sky130_fd_sc_hd__decap_8".
+Reading "WJ_sky130_fd_sc_hd__diode_2".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_16".
+Reading "WJ_sky130_fd_sc_hd__o211a_1".
+Reading "WJ_sky130_fd_sc_hd__dfxtp_2".
+Reading "WJ_sky130_fd_sc_hd__o21a_1".
+Reading "WJ_sky130_fd_sc_hd__mux2_1".
+Reading "WJ_sky130_fd_sc_hd__or2_1".
+Reading "WJ_sky130_fd_sc_hd__dfxtp_1".
+Reading "WJ_sky130_fd_sc_hd__a22o_1".
+Reading "WJ_sky130_fd_sc_hd__a21o_2".
+Reading "WJ_sky130_fd_sc_hd__a21o_1".
+Reading "WJ_sky130_fd_sc_hd__a22o_4".
+Reading "WJ_sky130_fd_sc_hd__buf_8".
+Reading "WJ_sky130_fd_sc_hd__o21a_2".
+Reading "WJ_sky130_fd_sc_hd__mux2_2".
+Reading "WJ_sky130_fd_sc_hd__buf_4".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_8".
+Reading "WJ_sky130_fd_sc_hd__buf_6".
+Reading "WJ_sky130_fd_sc_hd__dfxtp_4".
+Reading "WJ_sky130_fd_sc_hd__buf_2".
+Reading "WJ_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "WJ_sky130_fd_sc_hd__o21ai_1".
+Reading "WJ_sky130_fd_sc_hd__mux4_1".
+Reading "WJ_sky130_fd_sc_hd__buf_12".
+Reading "WJ_sky130_fd_sc_hd__mux4_2".
+Reading "WJ_sky130_fd_sc_hd__inv_2".
+Reading "WJ_sky130_fd_sc_hd__and3_2".
+Reading "WJ_sky130_fd_sc_hd__nand2_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2o_1".
+Reading "WJ_sky130_fd_sc_hd__or3b_1".
+Reading "WJ_sky130_fd_sc_hd__o32a_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2o_2".
+Reading "WJ_sky130_fd_sc_hd__o311a_1".
+Reading "WJ_sky130_fd_sc_hd__o221a_1".
+Reading "WJ_sky130_fd_sc_hd__o31a_1".
+Reading "WJ_sky130_fd_sc_hd__o211a_2".
+Reading "WJ_sky130_fd_sc_hd__and3_1".
+Reading "WJ_sky130_fd_sc_hd__a211oi_1".
+Reading "WJ_sky130_fd_sc_hd__and4_4".
+Reading "WJ_sky130_fd_sc_hd__and4_1".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_4".
+Reading "WJ_sky130_fd_sc_hd__and3b_1".
+Reading "WJ_sky130_fd_sc_hd__a211o_4".
+Reading "WJ_sky130_fd_sc_hd__a211o_1".
+Reading "WJ_sky130_fd_sc_hd__o21ba_1".
+Reading "WJ_sky130_fd_sc_hd__a21oi_1".
+Reading "WJ_sky130_fd_sc_hd__nor2_1".
+Reading "WJ_sky130_fd_sc_hd__nand2_8".
+Reading "WJ_sky130_fd_sc_hd__a311o_1".
+Reading "WJ_sky130_fd_sc_hd__nor2_2".
+Reading "WJ_sky130_fd_sc_hd__a41o_1".
+Reading "WJ_sky130_fd_sc_hd__nor3_2".
+Reading "WJ_sky130_fd_sc_hd__or4bb_4".
+Reading "WJ_sky130_fd_sc_hd__nor3_1".
+Reading "WJ_sky130_fd_sc_hd__or4b_4".
+Reading "WJ_sky130_fd_sc_hd__or3b_4".
+Reading "WJ_sky130_fd_sc_hd__a31o_1".
+Reading "WJ_sky130_fd_sc_hd__a211o_2".
+Reading "WJ_sky130_fd_sc_hd__or2_2".
+Reading "WJ_sky130_fd_sc_hd__a31o_2".
+Reading "WJ_sky130_fd_sc_hd__a221o_1".
+Reading "WJ_sky130_fd_sc_hd__and4b_4".
+Reading "WJ_sky130_fd_sc_hd__and3_4".
+Reading "WJ_sky130_fd_sc_hd__mux2_8".
+Reading "WJ_sky130_fd_sc_hd__o21ai_2".
+Reading "WJ_sky130_fd_sc_hd__and4b_1".
+Reading "WJ_sky130_fd_sc_hd__or4b_1".
+Reading "WJ_sky130_fd_sc_hd__o211a_4".
+Reading "WJ_sky130_fd_sc_hd__a32o_1".
+Reading "WJ_sky130_fd_sc_hd__a21boi_1".
+Reading "WJ_sky130_fd_sc_hd__o41ai_4".
+Reading "WJ_sky130_fd_sc_hd__o31a_2".
+Reading "WJ_sky130_fd_sc_hd__nand2_4".
+Reading "WJ_sky130_fd_sc_hd__a31oi_4".
+Reading "WJ_sky130_fd_sc_hd__and4_2".
+Reading "WJ_sky130_fd_sc_hd__nand3_4".
+Reading "WJ_sky130_fd_sc_hd__and4b_2".
+Reading "WJ_sky130_fd_sc_hd__o41a_4".
+Reading "WJ_sky130_fd_sc_hd__and4bb_2".
+Reading "WJ_sky130_fd_sc_hd__clkinv_2".
+Reading "WJ_sky130_fd_sc_hd__and2b_2".
+Reading "WJ_sky130_fd_sc_hd__or4bb_1".
+Reading "WJ_sky130_fd_sc_hd__a21oi_2".
+Reading "WJ_sky130_fd_sc_hd__a221oi_1".
+Reading "WJ_sky130_fd_sc_hd__a31oi_1".
+Reading "WJ_sky130_fd_sc_hd__xor2_4".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_1".
+Reading "WJ_sky130_fd_sc_hd__nand3b_4".
+Reading "WJ_sky130_fd_sc_hd__nand2_2".
+Reading "WJ_sky130_fd_sc_hd__xnor2_1".
+Reading "WJ_sky130_fd_sc_hd__and2_1".
+Reading "WJ_sky130_fd_sc_hd__nor2_4".
+Reading "WJ_sky130_fd_sc_hd__nand4_4".
+Reading "WJ_sky130_fd_sc_hd__a32o_2".
+Reading "WJ_sky130_fd_sc_hd__nor4_1".
+Reading "WJ_sky130_fd_sc_hd__nand4_1".
+Reading "WJ_sky130_fd_sc_hd__xor2_1".
+Reading "WJ_sky130_fd_sc_hd__and4bb_4".
+Reading "WJ_sky130_fd_sc_hd__a41o_2".
+Reading "WJ_sky130_fd_sc_hd__o2bb2a_1".
+Reading "WJ_sky130_fd_sc_hd__xnor2_2".
+Reading "WJ_sky130_fd_sc_hd__xor2_2".
+Reading "WJ_sky130_fd_sc_hd__or2_4".
+Reading "WJ_sky130_fd_sc_hd__a2111oi_2".
+Reading "WJ_sky130_fd_sc_hd__nor4_4".
+Reading "WJ_sky130_fd_sc_hd__mux2_4".
+Reading "WJ_sky130_fd_sc_hd__and2b_1".
+Reading "WJ_sky130_fd_sc_hd__and2_2".
+Reading "WJ_sky130_fd_sc_hd__nor4b_1".
+Reading "WJ_sky130_fd_sc_hd__o2111ai_4".
+Reading "WJ_sky130_fd_sc_hd__nor4_2".
+Reading "WJ_sky130_fd_sc_hd__nand3b_2".
+Reading "WJ_sky130_fd_sc_hd__nand3_1".
+Reading "WJ_sky130_fd_sc_hd__nand2b_2".
+Reading "WJ_sky130_fd_sc_hd__o31ai_1".
+Reading "WJ_sky130_fd_sc_hd__o41a_1".
+Reading "WJ_sky130_fd_sc_hd__a21bo_1".
+Reading "WJ_sky130_fd_sc_hd__o41ai_1".
+Reading "WJ_sky130_fd_sc_hd__nand3b_1".
+Reading "WJ_sky130_fd_sc_hd__o2111a_1".
+Reading "WJ_sky130_fd_sc_hd__o21a_4".
+Reading "WJ_sky130_fd_sc_hd__o22a_1".
+Reading "WJ_sky130_fd_sc_hd__or3b_2".
+Reading "WJ_sky130_fd_sc_hd__nand2b_1".
+Reading "WJ_sky130_fd_sc_hd__nor4b_4".
+Reading "WJ_sky130_fd_sc_hd__o21bai_1".
+Reading "WJ_sky130_fd_sc_hd__nor3_4".
+Reading "WJ_sky130_fd_sc_hd__o41a_2".
+Reading "WJ_sky130_fd_sc_hd__or4b_2".
+Reading "WJ_sky130_fd_sc_hd__a221o_4".
+Reading "WJ_sky130_fd_sc_hd__a2111oi_1".
+Reading "WJ_sky130_fd_sc_hd__o31a_4".
+Reading "WJ_sky130_fd_sc_hd__nor2_8".
+Reading "WJ_sky130_fd_sc_hd__clkinv_4".
+Reading "WJ_sky130_fd_sc_hd__a221o_2".
+Reading "WJ_sky130_fd_sc_hd__o21ai_4".
+Reading "WJ_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "WJ_sky130_fd_sc_hd__clkbuf_2".
+Reading "WJ_sky130_fd_sc_hd__a31o_4".
+Reading "WJ_sky130_fd_sc_hd__ebufn_4".
+Reading "WJ_sky130_fd_sc_hd__dlxtp_1".
+Reading "WJ_sky130_fd_sc_hd__dlclkp_1".
+Reading "WJ_sky130_fd_sc_hd__conb_1".
+Reading "WJ_sky130_fd_sc_hd__inv_1".
+Reading "WJ_sky130_fd_sc_hd__nor4b_2".
+Reading "WJ_sky130_fd_sc_hd__and3b_2".
+Reading "WJ_sky130_fd_sc_hd__nor3b_2".
+Reading "WJ_RAM256".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+Reading "WJ_sky130_fd_sc_hd__a21o_4".
+Reading "WJ_sky130_fd_sc_hd__o2111a_4".
+Reading "WJ_sky130_fd_sc_hd__a22o_2".
+Reading "WJ_sky130_fd_sc_hd__o211ai_4".
+Reading "WJ_sky130_fd_sc_hd__o22ai_4".
+Reading "WJ_sky130_fd_sc_hd__a221oi_4".
+Reading "WJ_sky130_fd_sc_hd__and2b_4".
+Reading "WJ_sky130_fd_sc_hd__and3b_4".
+Reading "WJ_sky130_fd_sc_hd__and4bb_1".
+Reading "WJ_sky130_fd_sc_hd__a21oi_4".
+Reading "WJ_sky130_fd_sc_hd__o22ai_1".
+Reading "WJ_sky130_fd_sc_hd__inv_4".
+Reading "WJ_sky130_fd_sc_hd__a311o_2".
+Reading "WJ_sky130_fd_sc_hd__a2111o_1".
+Reading "WJ_sky130_fd_sc_hd__o311a_4".
+Reading "WJ_sky130_fd_sc_hd__o2111ai_1".
+Reading "WJ_sky130_fd_sc_hd__clkinv_8".
+Reading "WJ_sky130_fd_sc_hd__nand3_2".
+Reading "WJ_sky130_fd_sc_hd__a22oi_1".
+Reading "WJ_sky130_fd_sc_hd__nand4b_4".
+Reading "WJ_sky130_fd_sc_hd__o221ai_4".
+Reading "WJ_sky130_fd_sc_hd__nand4_2".
+Reading "WJ_sky130_fd_sc_hd__inv_6".
+Reading "WJ_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "WJ_sky130_fd_sc_hd__a311oi_4".
+Reading "WJ_sky130_fd_sc_hd__o32ai_4".
+Reading "WJ_sky130_fd_sc_hd__o211ai_1".
+Reading "WJ_sky130_fd_sc_hd__nand4b_1".
+Reading "WJ_sky130_fd_sc_hd__o211ai_2".
+Reading "WJ_sky130_fd_sc_hd__a22oi_4".
+Reading "WJ_sky130_fd_sc_hd__and2_4".
+Reading "WJ_sky130_fd_sc_hd__a211oi_4".
+Reading "WJ_sky130_fd_sc_hd__nor3b_4".
+Reading "WJ_sky130_fd_sc_hd__o22a_2".
+Reading "WJ_sky130_fd_sc_hd__a2111oi_4".
+Reading "WJ_sky130_fd_sc_hd__nand2b_4".
+Reading "WJ_sky130_fd_sc_hd__a2bb2o_4".
+Reading "WJ_sky130_fd_sc_hd__o2bb2a_2".
+Reading "WJ_sky130_fd_sc_hd__o2111ai_2".
+Reading "WJ_sky130_fd_sc_hd__a22oi_2".
+Reading "WJ_sky130_fd_sc_hd__nor3b_1".
+Reading "WJ_sky130_fd_sc_hd__o2bb2a_4".
+Reading "WJ_sky130_fd_sc_hd__o21bai_4".
+Reading "WJ_sky130_fd_sc_hd__o311ai_1".
+Reading "WJ_sky130_fd_sc_hd__a32oi_2".
+Reading "WJ_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "WJ_sky130_fd_sc_hd__o311ai_4".
+Reading "WJ_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "WJ_sky130_fd_sc_hd__o31ai_4".
+Reading "WJ_sky130_fd_sc_hd__o221a_2".
+Reading "WJ_sky130_fd_sc_hd__o2111a_2".
+Reading "WJ_sky130_fd_sc_hd__a31oi_2".
+Reading "WJ_sky130_fd_sc_hd__o311a_2".
+Reading "WJ_sky130_fd_sc_hd__o22a_4".
+Reading "WJ_sky130_fd_sc_hd__a32oi_4".
+Reading "WJ_sky130_fd_sc_hd__a211oi_2".
+Reading "WJ_sky130_fd_sc_hd__o31ai_2".
+Reading "WJ_sky130_fd_sc_hd__o221ai_1".
+Reading "WJ_sky130_fd_sc_hd__clkinv_16".
+Reading "WJ_sky130_fd_sc_hd__or4bb_2".
+Reading "WJ_sky130_fd_sc_hd__a221oi_2".
+Reading "WJ_sky130_fd_sc_hd__inv_8".
+Reading "WJ_sky130_fd_sc_hd__a311oi_2".
+Reading "WJ_sky130_fd_sc_hd__a311oi_1".
+Reading "WJ_sky130_fd_sc_hd__o311ai_2".
+Reading "WJ_sky130_fd_sc_hd__a32oi_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "WJ_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "WJ_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "WJ_sky130_fd_sc_hd__xnor2_4".
+Reading "WJ_sky130_fd_sc_hd__inv_12".
+Reading "WJ_sky130_fd_sc_hd__a2111o_4".
+Reading "WJ_sky130_fd_sc_hd__a32o_4".
+Reading "WJ_sky130_fd_sc_hd__o21ba_2".
+Reading "WJ_sky130_fd_sc_hd__a41oi_2".
+Reading "WJ_sky130_fd_sc_hd__o22ai_2".
+Reading "WJ_sky130_fd_sc_hd__o21bai_2".
+Reading "WJ_sky130_fd_sc_hd__a41oi_4".
+Reading "WJ_sky130_fd_sc_hd__a41o_4".
+Reading "WJ_sky130_fd_sc_hd__a311o_4".
+Reading "WJ_sky130_fd_sc_hd__o32ai_1".
+Reading "WJ_sky130_fd_sc_hd__a21boi_4".
+Reading "WJ_sky130_fd_sc_hd__o32ai_2".
+Reading "WJ_sky130_fd_sc_hd__a21bo_2".
+Reading "WJ_RAM128".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "mgmt_core_wrapper".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+    125000 uses
+    130000 uses
+    135000 uses
+    140000 uses
+    145000 uses
+    150000 uses
+    155000 uses
+    160000 uses
+    165000 uses
+    170000 uses
+    175000 uses
+    180000 uses
+    185000 uses
+    190000 uses
+    195000 uses
+    200000 uses
+    205000 uses
+    210000 uses
+    215000 uses
+    220000 uses
+Reading "gpio_defaults_block_0403".
+Reading "gpio_defaults_block_1800".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "mgmt_protect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "gpio_defaults_block_0801".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "QN_sky130_fd_sc_hd__nor4_1".
+Reading "QN_sky130_fd_sc_hd__a221oi_1".
+Reading "QN_sky130_fd_sc_hd__or4b_2".
+Reading "QN_sky130_fd_sc_hd__a2111o_2".
+Reading "QN_sky130_fd_sc_hd__a22oi_1".
+Reading "QN_sky130_fd_sc_hd__o2111ai_1".
+Reading "QN_sky130_fd_sc_hd__a211oi_1".
+Reading "QN_sky130_fd_sc_hd__o31ai_1".
+Reading "QN_sky130_fd_sc_hd__a22oi_2".
+Reading "QN_sky130_fd_sc_hd__o2111a_1".
+Reading "QN_sky130_fd_sc_hd__mux4_1".
+Reading "QN_sky130_fd_sc_hd__a21boi_1".
+Reading "QN_sky130_fd_sc_hd__dfxtp_1".
+Reading "QN_sky130_fd_sc_hd__a41o_1".
+Reading "QN_sky130_fd_sc_hd__and4b_2".
+Reading "QN_sky130_fd_sc_hd__o221a_2".
+Reading "QN_sky130_fd_sc_hd__dfrtp_4".
+Reading "QN_sky130_fd_sc_hd__mux2_2".
+Reading "QN_sky130_fd_sc_hd__or4_2".
+Reading "QN_sky130_fd_sc_hd__clkinv_2".
+Reading "QN_sky130_fd_sc_hd__nand3b_1".
+Reading "QN_sky130_fd_sc_hd__o31ai_2".
+Reading "QN_sky130_fd_sc_hd__a2bb2o_1".
+Reading "QN_sky130_fd_sc_hd__o21bai_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_8".
+Reading "QN_sky130_fd_sc_hd__o32ai_4".
+Reading "QN_sky130_fd_sc_hd__o221ai_1".
+Reading "QN_sky130_fd_sc_hd__o22ai_1".
+Reading "QN_sky130_fd_sc_hd__nand3_1".
+Reading "QN_sky130_fd_sc_hd__o2bb2a_1".
+Reading "QN_sky130_fd_sc_hd__nand4_1".
+Reading "QN_sky130_fd_sc_hd__dfstp_2".
+Reading "QN_sky130_fd_sc_hd__dfstp_1".
+Reading "QN_sky130_ef_sc_hd__decap_12".
+Reading "QN_sky130_fd_sc_hd__o221a_1".
+Reading "QN_sky130_fd_sc_hd__o211a_1".
+Reading "QN_sky130_fd_sc_hd__o31a_1".
+Reading "QN_sky130_fd_sc_hd__nand2_2".
+Reading "QN_sky130_fd_sc_hd__or4_1".
+Reading "QN_sky130_fd_sc_hd__or4b_1".
+Reading "QN_sky130_fd_sc_hd__o21ai_2".
+Reading "QN_sky130_fd_sc_hd__a211o_1".
+Reading "QN_sky130_fd_sc_hd__o211ai_1".
+Reading "QN_sky130_fd_sc_hd__and4_1".
+Reading "QN_sky130_fd_sc_hd__a211oi_2".
+Reading "QN_sky130_fd_sc_hd__and3b_2".
+Reading "QN_sky130_fd_sc_hd__or4bb_1".
+Reading "QN_sky130_fd_sc_hd__and3b_4".
+Reading "QN_sky130_fd_sc_hd__o21ba_1".
+Reading "QN_sky130_fd_sc_hd__dfrtp_2".
+Reading "QN_sky130_fd_sc_hd__and4b_1".
+Reading "QN_sky130_fd_sc_hd__a21oi_2".
+Reading "QN_sky130_fd_sc_hd__o22a_1".
+Reading "QN_sky130_fd_sc_hd__a311o_1".
+Reading "QN_sky130_fd_sc_hd__xnor2_2".
+Reading "QN_sky130_fd_sc_hd__nor3_1".
+Reading "QN_sky130_fd_sc_hd__a21oi_1".
+Reading "QN_sky130_fd_sc_hd__o311a_1".
+Reading "QN_sky130_fd_sc_hd__or3b_4".
+Reading "QN_sky130_fd_sc_hd__and2_1".
+Reading "QN_sky130_fd_sc_hd__nor3b_1".
+Reading "QN_sky130_fd_sc_hd__a21bo_1".
+Reading "QN_sky130_fd_sc_hd__o32a_1".
+Reading "QN_sky130_fd_sc_hd__xor2_1".
+Reading "QN_sky130_fd_sc_hd__nand4_4".
+Reading "QN_sky130_fd_sc_hd__a31o_1".
+Reading "QN_sky130_fd_sc_hd__nand2_1".
+Reading "QN_sky130_fd_sc_hd__xnor2_1".
+Reading "QN_sky130_fd_sc_hd__and2b_1".
+Reading "QN_sky130_fd_sc_hd__nor2_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_16".
+Reading "QN_sky130_fd_sc_hd__and3_1".
+Reading "QN_sky130_fd_sc_hd__o21ai_1".
+Reading "QN_sky130_fd_sc_hd__nand2b_1".
+Reading "QN_sky130_fd_sc_hd__a32o_1".
+Reading "QN_sky130_fd_sc_hd__and3b_1".
+Reading "QN_sky130_fd_sc_hd__buf_4".
+Reading "QN_sky130_fd_sc_hd__conb_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_4".
+Reading "QN_sky130_fd_sc_hd__a22o_1".
+Reading "QN_sky130_fd_sc_hd__or4b_4".
+Reading "QN_sky130_fd_sc_hd__and4bb_1".
+Reading "QN_sky130_fd_sc_hd__buf_6".
+Reading "QN_sky130_fd_sc_hd__or3b_1".
+Reading "QN_sky130_fd_sc_hd__a221o_1".
+Reading "QN_sky130_fd_sc_hd__a21o_1".
+Reading "QN_sky130_fd_sc_hd__inv_2".
+Reading "QN_sky130_fd_sc_hd__or2_1".
+Reading "QN_sky130_fd_sc_hd__o21a_1".
+Reading "QN_sky130_fd_sc_hd__or3_1".
+Reading "QN_sky130_fd_sc_hd__diode_2".
+Reading "QN_sky130_fd_sc_hd__clkbuf_1".
+Reading "QN_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "QN_sky130_fd_sc_hd__clkbuf_2".
+Reading "QN_sky130_fd_sc_hd__buf_2".
+Reading "QN_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "QN_sky130_fd_sc_hd__decap_8".
+Reading "QN_sky130_fd_sc_hd__dfrtp_1".
+Reading "QN_sky130_fd_sc_hd__decap_4".
+Reading "QN_sky130_fd_sc_hd__decap_6".
+Reading "QN_sky130_fd_sc_hd__fill_1".
+Reading "QN_sky130_fd_sc_hd__fill_2".
+Reading "QN_sky130_fd_sc_hd__decap_3".
+Reading "QN_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "QN_sky130_fd_sc_hd__mux2_1".
+Reading "QN_sky130_fd_sc_hd__buf_8".
+Reading "QN_sky130_fd_sc_hd__buf_12".
+Reading "QN_sky130_fd_sc_hd__o2bb2a_2".
+Reading "QN_sky130_fd_sc_hd__nand4_2".
+Reading "QN_sky130_fd_sc_hd__a221o_2".
+Reading "QN_sky130_fd_sc_hd__a31oi_2".
+Reading "QN_sky130_fd_sc_hd__or3b_2".
+Reading "QN_sky130_fd_sc_hd__or3_2".
+Reading "QN_sky130_fd_sc_hd__and2b_2".
+Reading "QN_sky130_fd_sc_hd__a31o_2".
+Reading "QN_sky130_fd_sc_hd__xor2_2".
+Reading "QN_sky130_fd_sc_hd__nor2_2".
+Reading "QN_sky130_fd_sc_hd__a22o_2".
+Reading "QN_sky130_fd_sc_hd__o21a_2".
+Reading "QN_sky130_fd_sc_hd__nand2b_2".
+Reading "QN_sky130_fd_sc_hd__o211a_2".
+Reading "QN_sky130_fd_sc_hd__a21o_2".
+Reading "QN_sky130_fd_sc_hd__o22a_2".
+Reading "QN_sky130_fd_sc_hd__nand3b_2".
+Reading "QN_sky130_fd_sc_hd__and4_2".
+Reading "QN_sky130_fd_sc_hd__a311o_2".
+Reading "QN_sky130_fd_sc_hd__a211o_2".
+Reading "QN_sky130_fd_sc_hd__nand3_2".
+Reading "QN_sky130_fd_sc_hd__and3_2".
+Reading "QN_sky130_fd_sc_hd__a32o_2".
+Reading "QN_sky130_fd_sc_hd__a21boi_2".
+Reading "QN_sky130_fd_sc_hd__and2_2".
+Reading "QN_sky130_fd_sc_hd__a2111oi_2".
+Reading "QN_sky130_fd_sc_hd__or2_2".
+Reading "QN_sky130_fd_sc_hd__and4_4".
+Reading "QN_sky130_fd_sc_hd__a2bb2o_2".
+Reading "QN_sky130_fd_sc_hd__and4bb_4".
+Reading "QN_sky130_fd_sc_hd__o31ai_4".
+Reading "QN_sky130_fd_sc_hd__o21ba_4".
+Reading "QN_sky130_fd_sc_hd__nand2_4".
+Reading "QN_sky130_fd_sc_hd__a31oi_1".
+Reading "QN_sky130_fd_sc_hd__o31a_2".
+Reading "QN_sky130_fd_sc_hd__a2111o_1".
+Reading "QN_sky130_fd_sc_hd__or3_4".
+Reading "QN_sky130_fd_sc_hd__o311a_4".
+Reading "QN_sky130_fd_sc_hd__nor2_8".
+Reading "QN_sky130_fd_sc_hd__and3_4".
+Reading "QN_sky130_fd_sc_hd__and2_4".
+Reading "QN_sky130_fd_sc_hd__a21bo_4".
+Reading "QN_sky130_fd_sc_hd__nor2_4".
+Reading "QN_sky130_fd_sc_hd__o22ai_4".
+Reading "QN_sky130_fd_sc_hd__a22oi_4".
+Reading "QN_sky130_fd_sc_hd__a21oi_4".
+Reading "QN_sky130_fd_sc_hd__a211oi_4".
+Reading "QN_sky130_fd_sc_hd__o21ai_4".
+Reading "QN_sky130_fd_sc_hd__or4_4".
+Reading "QN_sky130_fd_sc_hd__or2_4".
+Reading "QN_sky130_fd_sc_hd__nand2_8".
+Reading "QN_sky130_fd_sc_hd__xor2_4".
+Reading "QN_sky130_fd_sc_hd__dfxtp_2".
+Reading "QN_sky130_fd_sc_hd__a211o_4".
+Reading "QN_sky130_fd_sc_hd__a31o_4".
+Reading "QN_sky130_fd_sc_hd__a22o_4".
+Reading "QN_sky130_fd_sc_hd__o31a_4".
+Reading "QN_sky130_fd_sc_hd__xnor2_4".
+Reading "QN_sky130_fd_sc_hd__mux2_4".
+Reading "QN_sky130_fd_sc_hd__mux2_8".
+Reading "QN_sky130_fd_sc_hd__mux4_2".
+Reading "QN_sky130_fd_sc_hd__dfxtp_4".
+Reading "QN_sky130_fd_sc_hd__a221o_4".
+Reading "QN_sky130_fd_sc_hd__nand2b_4".
+Reading "QN_sky130_fd_sc_hd__clkinv_4".
+Reading "QN_sky130_fd_sc_hd__o221ai_4".
+Reading "QN_sky130_fd_sc_hd__nand3_4".
+Reading "QN_sky130_fd_sc_hd__o41a_1".
+Reading "QN_sky130_fd_sc_hd__nor3_2".
+Reading "QN_sky130_fd_sc_hd__nor4_4".
+Reading "QN_sky130_fd_sc_hd__a2111oi_4".
+Reading "QN_sky130_fd_sc_hd__a2111o_4".
+Reading "QN_sky130_fd_sc_hd__a31oi_4".
+Reading "QN_sky130_fd_sc_hd__o22ai_2".
+Reading "QN_sky130_fd_sc_hd__a32oi_4".
+Reading "QN_sky130_fd_sc_hd__a221oi_4".
+Reading "QN_sky130_fd_sc_hd__nor4b_1".
+Reading "QN_sky130_fd_sc_hd__nor3b_4".
+Reading "QN_sky130_fd_sc_hd__and4bb_2".
+Reading "QN_sky130_fd_sc_hd__a311o_4".
+Reading "QN_sky130_fd_sc_hd__o311ai_2".
+Reading "QN_sky130_fd_sc_hd__nor3_4".
+Reading "QN_sky130_fd_sc_hd__a311oi_4".
+Reading "QN_sky130_fd_sc_hd__o2111ai_2".
+Reading "QN_sky130_fd_sc_hd__o211ai_4".
+Reading "QN_sky130_fd_sc_hd__inv_4".
+Reading "QN_sky130_fd_sc_hd__o21bai_2".
+Reading "QN_sky130_fd_sc_hd__o22a_4".
+Reading "QN_sky130_fd_sc_hd__a2bb2o_4".
+Reading "QN_sky130_fd_sc_hd__o211a_4".
+Reading "QN_sky130_fd_sc_hd__o211ai_2".
+Reading "QN_sky130_fd_sc_hd__o21ba_2".
+Reading "QN_sky130_fd_sc_hd__o2111a_2".
+Reading "QN_sky130_fd_sc_hd__dfstp_4".
+Reading "QN_sky130_fd_sc_hd__o221ai_2".
+Reading "QN_sky130_fd_sc_hd__a21bo_2".
+Reading "QN_sky130_fd_sc_hd__o21a_4".
+Reading "QN_sky130_fd_sc_hd__and2b_4".
+Reading "QN_sky130_fd_sc_hd__nand3b_4".
+Reading "QN_sky130_fd_sc_hd__o32a_4".
+Reading "QN_sky130_fd_sc_hd__and4b_4".
+Reading "QN_ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "QN_sky130_fd_sc_hd__clkinv_8".
+Reading "QN_sky130_fd_sc_hd__or2b_1".
+Reading "QN_sky130_fd_sc_hd__o2111ai_4".
+Reading "QN_sky130_fd_sc_hd__or4bb_2".
+Reading "QN_sky130_fd_sc_hd__inv_6".
+Reading "QN_sky130_fd_sc_hd__a21o_4".
+Reading "QN_sky130_fd_sc_hd__o311a_2".
+Reading "QN_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "QN_sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "QN_sky130_fd_sc_hd__nor4_2".
+Reading "QN_sky130_fd_sc_hd__or2b_2".
+Reading "QN_sky130_fd_sc_hd__buf_1".
+Reading "QN_ycr4_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+Reading "QN_bus_rep_west".
+    5000 uses
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "QN_sky130_fd_bd_sram__openram_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "QN_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "QN_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "QN_sky130_fd_bd_sram__openram_sense_amp".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "QN_sky130_fd_bd_sram__openram_write_driver".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "QN_sky130_fd_bd_sram__openram_dp_cell".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "QN_sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "QN_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "QN_sky130_fd_sc_hd__a2111oi_1".
+Reading "QN_sky130_fd_sc_hd__o32a_2".
+Reading "QN_sky130_fd_sc_hd__nand4b_2".
+Reading "QN_sky130_fd_sc_hd__o21bai_4".
+Reading "QN_ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+Reading "QN_sky130_fd_sc_hd__nor4b_2".
+Reading "QN_peri_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+Reading "QN_sky130_fd_sc_hd__nor3b_2".
+Reading "QN_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "QN_sky130_fd_sc_hd__nor4b_4".
+Reading "QN_sky130_fd_sc_hd__or2b_4".
+Reading "QN_sky130_fd_sc_hd__o41a_2".
+Reading "QN_qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "QN_sky130_fd_sc_hd__a41oi_4".
+Reading "QN_sky130_fd_sc_hd__o221a_4".
+Reading "QN_sky130_fd_sc_hd__a41o_2".
+Reading "QN_sky130_fd_sc_hd__a41o_4".
+Reading "QN_wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "QN_bus_rep_east".
+    5000 uses
+Reading "QN_switchn".
+Reading "QN_resistor".
+Reading "QN_resistor_3xh".
+Reading "QN_switch2".
+Reading "QN_switch2n".
+Reading "QN_2bit_DAC".
+Reading "QN_resistor_h".
+Reading "QN_3bit_DAC".
+Reading "QN_4bit_DAC".
+Reading "QN_5bit_DAC".
+Reading "QN_6bit_DAC".
+Reading "QN_7bit_DAC".
+Reading "QN_8bit_DAC".
+Reading "QN_2x8bit_DAC".
+Reading "QN_4x8bit_DAC".
+Reading "QN_dac_top".
+Reading "QN_sky130_fd_sc_hd__einvn_8".
+Reading "QN_sky130_fd_sc_hd__clkinv_1".
+Reading "QN_sky130_fd_sc_hd__einvp_2".
+Reading "QN_sky130_fd_sc_hd__einvn_2".
+Reading "QN_sky130_fd_sc_hd__einvp_1".
+Reading "QN_dg_pll".
+Reading "QN_sky130_fd_sc_hd__dlclkp_2".
+Reading "QN_sky130_fd_sc_hd__dlclkp_1".
+Reading "QN_sky130_fd_sc_hd__o32ai_1".
+Reading "QN_sky130_fd_sc_hd__nor2b_1".
+Reading "QN_sky130_fd_sc_hd__a311oi_1".
+Reading "QN_wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "QN_sky130_fd_sc_hd__o41ai_1".
+Reading "QN_sky130_fd_sc_hd__a311oi_2".
+Reading "QN_sky130_fd_sc_hd__o311ai_4".
+Reading "QN_sky130_fd_sc_hd__or4bb_4".
+Reading "QN_sky130_fd_sc_hd__o41a_4".
+Reading "QN_uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "QN_sky130_fd_sc_hd__a21boi_4".
+Reading "QN_sky130_fd_sc_hd__dlxtn_2".
+Reading "QN_sky130_fd_sc_hd__dlxtn_1".
+Reading "QN_sky130_fd_sc_hd__nand4b_1".
+Reading "QN_pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "QN_bus_rep_south".
+    5000 uses
+Reading "QN_bus_rep_north".
+    5000 uses
+Reading "user_project_wrapper".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_io__res250_sub_small".
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717082342): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717082374): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717084966): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717084998): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717085030): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717085062): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717085094): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 717085190): NODE elements not supported: skipping.
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "constant_block".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "chip_io_gpio_connects".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "gpio_signal_buffering".
+Reading "caravel".
+Flattening layout of tile x=0 y=0. . . 
+Flattening layout of tile x=1 y=0. . . 
+Flattening layout of tile x=2 y=0. . . 
+Flattening layout of tile x=3 y=0. . . 
+Flattening layout of tile x=4 y=0. . . 
+Flattening layout of tile x=5 y=0. . . 
+Flattening layout of tile x=0 y=1. . . 
+Flattening layout of tile x=1 y=1. . . 
+Flattening layout of tile x=2 y=1. . . 
+Flattening layout of tile x=3 y=1. . . 
+Flattening layout of tile x=4 y=1. . . 
+Flattening layout of tile x=5 y=1. . . 
+Flattening layout of tile x=0 y=2. . . 
+Flattening layout of tile x=1 y=2. . . 
+Flattening layout of tile x=2 y=2. . . 
+Flattening layout of tile x=3 y=2. . . 
+Flattening layout of tile x=4 y=2. . . 
+Flattening layout of tile x=5 y=2. . . 
+Flattening layout of tile x=0 y=3. . . 
+Flattening layout of tile x=1 y=3. . . 
+Flattening layout of tile x=2 y=3. . . 
+Flattening layout of tile x=3 y=3. . . 
+Flattening layout of tile x=4 y=3. . . 
+Flattening layout of tile x=5 y=3. . . 
+Flattening layout of tile x=0 y=4. . . 
+Flattening layout of tile x=1 y=4. . . 
+Flattening layout of tile x=2 y=4. . . 
+Flattening layout of tile x=3 y=4. . . 
+Flattening layout of tile x=4 y=4. . . 
+Flattening layout of tile x=5 y=4. . . 
+Flattening layout of tile x=0 y=5. . . 
+Flattening layout of tile x=1 y=5. . . 
+Flattening layout of tile x=2 y=5. . . 
+Flattening layout of tile x=3 y=5. . . 
+Flattening layout of tile x=4 y=5. . . 
+Flattening layout of tile x=5 y=5. . . 
+Flattening layout of tile x=0 y=6. . . 
+Flattening layout of tile x=1 y=6. . . 
+Flattening layout of tile x=2 y=6. . . 
+Flattening layout of tile x=3 y=6. . . 
+Flattening layout of tile x=4 y=6. . . 
+Flattening layout of tile x=5 y=6. . . 
+Flattening layout of tile x=0 y=7. . . 
+Flattening layout of tile x=1 y=7. . . 
+Flattening layout of tile x=2 y=7. . . 
+Flattening layout of tile x=3 y=7. . . 
+Flattening layout of tile x=4 y=7. . . 
+Flattening layout of tile x=5 y=7. . . 
+Ended: 12/14/2022 12:03:14
diff --git a/tapeout/logs/fill_intermediate.log b/tapeout/logs/fill_intermediate.log
new file mode 100644
index 0000000..fa7442a
--- /dev/null
+++ b/tapeout/logs/fill_intermediate.log
@@ -0,0 +1,20073 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_3_2: 10000 rects
+caravel_000710d6_fill_pattern_2_3: 10000 rects
+caravel_000710d6_fill_pattern_0_5: 10000 rects
+caravel_000710d6_fill_pattern_2_7: 10000 rects
+caravel_000710d6_fill_pattern_5_0: 10000 rects
+caravel_000710d6_fill_pattern_2_3: 20000 rects
+caravel_000710d6_fill_pattern_4_5: 10000 rects
+caravel_000710d6_fill_pattern_4_1: 10000 rects
+caravel_000710d6_fill_pattern_3_2: 20000 rects
+caravel_000710d6_fill_pattern_0_7: 10000 rects
+caravel_000710d6_fill_pattern_0_1: 10000 rects
+caravel_000710d6_fill_pattern_0_5: 20000 rects
+caravel_000710d6_fill_pattern_1_0: 10000 rects
+caravel_000710d6_fill_pattern_5_0: 20000 rects
+caravel_000710d6_fill_pattern_5_4: 10000 rects
+caravel_000710d6_fill_pattern_2_7: 20000 rects
+caravel_000710d6_fill_pattern_4_5: 20000 rects
+caravel_000710d6_fill_pattern_2_3: 30000 rects
+caravel_000710d6_fill_pattern_3_6: 10000 rects
+caravel_000710d6_fill_pattern_1_4: 10000 rects
+caravel_000710d6_fill_pattern_4_1: 20000 rects
+caravel_000710d6_fill_pattern_3_2: 30000 rects
+caravel_000710d6_fill_pattern_0_7: 20000 rects
+caravel_000710d6_fill_pattern_3_4: 10000 rects
+caravel_000710d6_fill_pattern_4_3: 10000 rects
+caravel_000710d6_fill_pattern_0_1: 20000 rects
+caravel_000710d6_fill_pattern_0_5: 30000 rects
+caravel_000710d6_fill_pattern_1_0: 20000 rects
+caravel_000710d6_fill_pattern_5_0: 30000 rects
+caravel_000710d6_fill_pattern_5_4: 20000 rects
+caravel_000710d6_fill_pattern_4_5: 30000 rects
+caravel_000710d6_fill_pattern_2_7: 30000 rects
+caravel_000710d6_fill_pattern_3_6: 20000 rects
+caravel_000710d6_fill_pattern_2_3: 40000 rects
+caravel_000710d6_fill_pattern_1_4: 20000 rects
+caravel_000710d6_fill_pattern_3_2: 40000 rects
+caravel_000710d6_fill_pattern_3_4: 20000 rects
+caravel_000710d6_fill_pattern_0_7: 30000 rects
+caravel_000710d6_fill_pattern_4_3: 20000 rects
+caravel_000710d6_fill_pattern_4_1: 30000 rects
+caravel_000710d6_fill_pattern_0_1: 30000 rects
+caravel_000710d6_fill_pattern_0_5: 40000 rects
+caravel_000710d6_fill_pattern_1_0: 30000 rects
+caravel_000710d6_fill_pattern_5_0: 40000 rects
+caravel_000710d6_fill_pattern_5_4: 30000 rects
+caravel_000710d6_fill_pattern_4_5: 40000 rects
+caravel_000710d6_fill_pattern_2_7: 40000 rects
+caravel_000710d6_fill_pattern_3_6: 30000 rects
+caravel_000710d6_fill_pattern_3_2: 50000 rects
+caravel_000710d6_fill_pattern_2_3: 50000 rects
+caravel_000710d6_fill_pattern_1_4: 30000 rects
+caravel_000710d6_fill_pattern_0_7: 40000 rects
+caravel_000710d6_fill_pattern_3_4: 30000 rects
+caravel_000710d6_fill_pattern_4_3: 30000 rects
+caravel_000710d6_fill_pattern_0_1: 40000 rects
+caravel_000710d6_fill_pattern_4_1: 40000 rects
+caravel_000710d6_fill_pattern_0_5: 50000 rects
+caravel_000710d6_fill_pattern_1_0: 40000 rects
+caravel_000710d6_fill_pattern_5_4: 40000 rects
+caravel_000710d6_fill_pattern_4_5: 50000 rects
+caravel_000710d6_fill_pattern_3_6: 40000 rects
+caravel_000710d6_fill_pattern_3_2: 60000 rects
+caravel_000710d6_fill_pattern_0_7: 50000 rects
+caravel_000710d6_fill_pattern_5_0: 50000 rects
+caravel_000710d6_fill_pattern_3_4: 40000 rects
+caravel_000710d6_fill_pattern_2_7: 50000 rects
+caravel_000710d6_fill_pattern_4_3: 40000 rects
+caravel_000710d6_fill_pattern_1_4: 40000 rects
+caravel_000710d6_fill_pattern_0_1: 50000 rects
+caravel_000710d6_fill_pattern_2_3: 60000 rects
+caravel_000710d6_fill_pattern_0_5: 60000 rects
+caravel_000710d6_fill_pattern_4_1: 50000 rects
+caravel_000710d6_fill_pattern_2_5: 10000 rects
+caravel_000710d6_fill_pattern_1_0: 50000 rects
+caravel_000710d6_fill_pattern_5_4: 50000 rects
+caravel_000710d6_fill_pattern_4_5: 60000 rects
+caravel_000710d6_fill_pattern_0_7: 60000 rects
+caravel_000710d6_fill_pattern_3_2: 70000 rects
+caravel_000710d6_fill_pattern_3_6: 50000 rects
+caravel_000710d6_fill_pattern_3_4: 50000 rects
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_000710d6_fill_pattern_5_0
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+caravel_000710d6_fill_pattern_5_4: 1000000 rects
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+caravel_000710d6_fill_pattern_3_6: 1200000 rects
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+caravel_000710d6_fill_pattern_4_3: 1330000 rects
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+caravel_000710d6_fill_pattern_3_4: 1510000 rects
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+caravel_000710d6_fill_pattern_2_3: 1330000 rects
+caravel_000710d6_fill_pattern_4_5: 1450000 rects
+caravel_000710d6_fill_pattern_2_7: 990000 rects
+caravel_000710d6_fill_pattern_3_2: 1370000 rects
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+caravel_000710d6_fill_pattern_2_5: 1230000 rects
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+caravel_000710d6_fill_pattern_1_4: 1370000 rects
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+caravel_000710d6_fill_pattern_2_7: 1000000 rects
+caravel_000710d6_fill_pattern_3_6: 1210000 rects
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+caravel_000710d6_fill_pattern_3_2: 1390000 rects
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+caravel_000710d6_fill_pattern_0_5: 1480000 rects
+caravel_000710d6_fill_pattern_1_4: 1390000 rects
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+caravel_000710d6_fill_pattern_2_7: 1010000 rects
+caravel_000710d6_fill_pattern_2_5: 1260000 rects
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+caravel_000710d6_fill_pattern_4_5: 1480000 rects
+caravel_000710d6_fill_pattern_3_2: 1400000 rects
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+caravel_000710d6_fill_pattern_1_4: 1400000 rects
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+caravel_000710d6_fill_pattern_2_5: 1270000 rects
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+caravel_000710d6_fill_pattern_0_7: 970000 rects
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+caravel_000710d6_fill_pattern_1_4: 1410000 rects
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+caravel_000710d6_fill_pattern_0_5: 1500000 rects
+caravel_000710d6_fill_pattern_2_5: 1280000 rects
+caravel_000710d6_fill_pattern_4_3: 1400000 rects
+caravel_000710d6_fill_pattern_1_0: 1390000 rects
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+caravel_000710d6_fill_pattern_0_7: 980000 rects
+caravel_000710d6_fill_pattern_3_4: 1570000 rects
+caravel_000710d6_fill_pattern_2_3: 1390000 rects
+caravel_000710d6_fill_pattern_1_4: 1420000 rects
+caravel_000710d6_fill_pattern_4_5: 1500000 rects
+caravel_000710d6_fill_pattern_3_2: 1420000 rects
+caravel_000710d6_fill_pattern_4_1: 1320000 rects
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+caravel_000710d6_fill_pattern_2_7: 1030000 rects
+caravel_000710d6_fill_pattern_0_5: 1510000 rects
+caravel_000710d6_fill_pattern_0_7: 990000 rects
+caravel_000710d6_fill_pattern_4_3: 1410000 rects
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+caravel_000710d6_fill_pattern_1_4: 1430000 rects
+caravel_000710d6_fill_pattern_2_3: 1400000 rects
+caravel_000710d6_fill_pattern_2_7: 1040000 rects
+caravel_000710d6_fill_pattern_3_6: 1230000 rects
+caravel_000710d6_fill_pattern_2_5: 1300000 rects
+caravel_000710d6_fill_pattern_3_4: 1580000 rects
+caravel_000710d6_fill_pattern_3_2: 1430000 rects
+caravel_000710d6_fill_pattern_4_5: 1510000 rects
+caravel_000710d6_fill_pattern_0_7: 1000000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_0_5: 1520000 rects
+caravel_000710d6_fill_pattern_4_1: 1330000 rects
+caravel_000710d6_fill_pattern_1_0: 1400000 rects
+caravel_000710d6_fill_pattern_2_3: 1410000 rects
+caravel_000710d6_fill_pattern_2_7: 1050000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_5_4
+caravel_000710d6_fill_pattern_1_4: 1440000 rects
+caravel_000710d6_fill_pattern_4_3: 1420000 rects
+caravel_000710d6_fill_pattern_2_5: 1310000 rects
+caravel_000710d6_fill_pattern_0_1: 1380000 rects
+caravel_000710d6_fill_pattern_3_4: 1590000 rects
+caravel_000710d6_fill_pattern_3_2: 1440000 rects
+caravel_000710d6_fill_pattern_4_5: 1520000 rects
+caravel_000710d6_fill_pattern_2_7: 1060000 rects
+caravel_000710d6_fill_pattern_0_5: 1530000 rects
+caravel_000710d6_fill_pattern_2_3: 1420000 rects
+caravel_000710d6_fill_pattern_1_4: 1450000 rects
+caravel_000710d6_fill_pattern_2_5: 1320000 rects
+caravel_000710d6_fill_pattern_4_3: 1430000 rects
+caravel_000710d6_fill_pattern_4_1: 1340000 rects
+caravel_000710d6_fill_pattern_1_0: 1410000 rects
+caravel_000710d6_fill_pattern_0_1: 1390000 rects
+caravel_000710d6_fill_pattern_3_4: 1600000 rects
+caravel_000710d6_fill_pattern_2_7: 1070000 rects
+caravel_000710d6_fill_pattern_3_2: 1450000 rects
+caravel_000710d6_fill_pattern_3_6: 1240000 rects
+caravel_000710d6_fill_pattern_2_3: 1430000 rects
+caravel_000710d6_fill_pattern_1_4: 1460000 rects
+caravel_000710d6_fill_pattern_4_5: 1530000 rects
+caravel_000710d6_fill_pattern_0_5: 1540000 rects
+caravel_000710d6_fill_pattern_2_5: 1330000 rects
+caravel_000710d6_fill_pattern_4_3: 1440000 rects
+caravel_000710d6_fill_pattern_0_7: 1010000 rects
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+caravel_000710d6_fill_pattern_2_7: 1080000 rects
+caravel_000710d6_fill_pattern_1_0: 1420000 rects
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+caravel_000710d6_fill_pattern_3_2: 1460000 rects
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+caravel_000710d6_fill_pattern_0_5: 1550000 rects
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+caravel_000710d6_fill_pattern_2_7: 1090000 rects
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+caravel_000710d6_fill_pattern_2_3: 1450000 rects
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+caravel_000710d6_fill_pattern_3_4: 1620000 rects
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+caravel_000710d6_fill_pattern_4_5: 1550000 rects
+caravel_000710d6_fill_pattern_4_3: 1460000 rects
+caravel_000710d6_fill_pattern_1_0: 1440000 rects
+caravel_000710d6_fill_pattern_3_6: 1250000 rects
+caravel_000710d6_fill_pattern_2_3: 1460000 rects
+caravel_000710d6_fill_pattern_2_5: 1360000 rects
+caravel_000710d6_fill_pattern_1_4: 1490000 rects
+caravel_000710d6_fill_pattern_0_1: 1420000 rects
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+caravel_000710d6_fill_pattern_3_2: 1480000 rects
+caravel_000710d6_fill_pattern_3_4: 1630000 rects
+caravel_000710d6_fill_pattern_4_1: 1370000 rects
+caravel_000710d6_fill_pattern_0_5: 1570000 rects
+caravel_000710d6_fill_pattern_1_0: 1450000 rects
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+caravel_000710d6_fill_pattern_4_3: 1470000 rects
+caravel_000710d6_fill_pattern_2_3: 1470000 rects
+caravel_000710d6_fill_pattern_4_5: 1560000 rects
+caravel_000710d6_fill_pattern_1_4: 1500000 rects
+caravel_000710d6_fill_pattern_2_7: 1120000 rects
+caravel_000710d6_fill_pattern_3_2: 1490000 rects
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+caravel_000710d6_fill_pattern_3_4: 1640000 rects
+caravel_000710d6_fill_pattern_1_0: 1460000 rects
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+caravel_000710d6_fill_pattern_4_1: 1380000 rects
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+caravel_000710d6_fill_pattern_2_3: 1480000 rects
+caravel_000710d6_fill_pattern_1_4: 1510000 rects
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+caravel_000710d6_fill_pattern_4_5: 1570000 rects
+caravel_000710d6_fill_pattern_3_2: 1500000 rects
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+caravel_000710d6_fill_pattern_3_6: 1260000 rects
+caravel_000710d6_fill_pattern_2_5: 1390000 rects
+caravel_000710d6_fill_pattern_3_4: 1650000 rects
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+caravel_000710d6_fill_pattern_2_3: 1490000 rects
+caravel_000710d6_fill_pattern_1_4: 1520000 rects
+caravel_000710d6_fill_pattern_0_5: 1590000 rects
+caravel_000710d6_fill_pattern_4_3: 1490000 rects
+caravel_000710d6_fill_pattern_4_1: 1390000 rects
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+caravel_000710d6_fill_pattern_2_5: 1400000 rects
+caravel_000710d6_fill_pattern_0_1: 1450000 rects
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+caravel_000710d6_fill_pattern_0_5: 1600000 rects
+caravel_000710d6_fill_pattern_3_4: 1660000 rects
+caravel_000710d6_fill_pattern_1_0: 1480000 rects
+caravel_000710d6_fill_pattern_4_3: 1500000 rects
+caravel_000710d6_fill_pattern_3_2: 1520000 rects
+caravel_000710d6_fill_pattern_4_5: 1590000 rects
+caravel_000710d6_fill_pattern_2_5: 1410000 rects
+caravel_000710d6_fill_pattern_4_1: 1400000 rects
+caravel_000710d6_fill_pattern_1_4: 1540000 rects
+caravel_000710d6_fill_pattern_2_3: 1510000 rects
+caravel_000710d6_fill_pattern_2_7: 1140000 rects
+caravel_000710d6_fill_pattern_0_1: 1460000 rects
+caravel_000710d6_fill_pattern_0_5: 1610000 rects
+caravel_000710d6_fill_pattern_1_0: 1490000 rects
+caravel_000710d6_fill_pattern_3_4: 1670000 rects
+caravel_000710d6_fill_pattern_3_2: 1530000 rects
+caravel_000710d6_fill_pattern_4_3: 1510000 rects
+caravel_000710d6_fill_pattern_3_6: 1270000 rects
+caravel_000710d6_fill_pattern_2_5: 1420000 rects
+caravel_000710d6_fill_pattern_4_5: 1600000 rects
+caravel_000710d6_fill_pattern_1_4: 1550000 rects
+caravel_000710d6_fill_pattern_2_3: 1520000 rects
+caravel_000710d6_fill_pattern_4_1: 1410000 rects
+caravel_000710d6_fill_pattern_0_5: 1620000 rects
+caravel_000710d6_fill_pattern_0_1: 1470000 rects
+caravel_000710d6_fill_pattern_3_2: 1540000 rects
+caravel_000710d6_fill_pattern_2_5: 1430000 rects
+caravel_000710d6_fill_pattern_3_4: 1680000 rects
+caravel_000710d6_fill_pattern_4_3: 1520000 rects
+caravel_000710d6_fill_pattern_2_3: 1530000 rects
+caravel_000710d6_fill_pattern_1_0: 1500000 rects
+caravel_000710d6_fill_pattern_1_4: 1560000 rects
+caravel_000710d6_fill_pattern_4_5: 1610000 rects
+caravel_000710d6_fill_pattern_2_7: 1150000 rects
+caravel_000710d6_fill_pattern_2_5: 1440000 rects
+caravel_000710d6_fill_pattern_0_5: 1630000 rects
+caravel_000710d6_fill_pattern_3_2: 1550000 rects
+caravel_000710d6_fill_pattern_4_1: 1420000 rects
+caravel_000710d6_fill_pattern_0_1: 1480000 rects
+caravel_000710d6_fill_pattern_2_3: 1540000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_1_4: 1570000 rects
+caravel_000710d6_fill_pattern_1_0: 1510000 rects
+caravel_000710d6_fill_pattern_3_4: 1690000 rects
+caravel_000710d6_fill_pattern_4_3: 1530000 rects
+caravel_000710d6_fill_pattern_4_5: 1620000 rects
+caravel_000710d6_fill_pattern_2_5: 1450000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_0_7
+caravel_000710d6_fill_pattern_0_5: 1640000 rects
+caravel_000710d6_fill_pattern_3_6: 1280000 rects
+caravel_000710d6_fill_pattern_3_2: 1560000 rects
+caravel_000710d6_fill_pattern_2_3: 1550000 rects
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+caravel_000710d6_fill_pattern_0_1: 1490000 rects
+caravel_000710d6_fill_pattern_4_1: 1430000 rects
+caravel_000710d6_fill_pattern_3_4: 1700000 rects
+caravel_000710d6_fill_pattern_4_3: 1540000 rects
+caravel_000710d6_fill_pattern_2_5: 1460000 rects
+caravel_000710d6_fill_pattern_4_5: 1630000 rects
+caravel_000710d6_fill_pattern_3_2: 1570000 rects
+caravel_000710d6_fill_pattern_2_3: 1560000 rects
+caravel_000710d6_fill_pattern_0_5: 1650000 rects
+caravel_000710d6_fill_pattern_1_4: 1590000 rects
+caravel_000710d6_fill_pattern_1_0: 1520000 rects
+caravel_000710d6_fill_pattern_2_7: 1160000 rects
+caravel_000710d6_fill_pattern_0_1: 1500000 rects
+caravel_000710d6_fill_pattern_2_5: 1470000 rects
+caravel_000710d6_fill_pattern_4_3: 1550000 rects
+caravel_000710d6_fill_pattern_4_1: 1440000 rects
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+caravel_000710d6_fill_pattern_1_0: 1720000 rects
+caravel_000710d6_fill_pattern_4_5: 1830000 rects
+Ended: 12/14/2022 12:03:23
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+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_000710d6_fill_pattern_0_1: 1660000 rects
+caravel_000710d6_fill_pattern_1_0: 1740000 rects
+Processing system .magicrc file
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+caravel_000710d6_fill_pattern_3_6: 1380000 rects
+caravel_000710d6_fill_pattern_3_4: 1940000 rects
+caravel_000710d6_fill_pattern_3_2: 1790000 rects
+Sourcing design .magicrc for technology sky130A ...
+caravel_000710d6_fill_pattern_1_4: 1850000 rects
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_4_5: 1860000 rects
+caravel_000710d6_fill_pattern_0_5: 1910000 rects
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+caravel_000710d6_fill_pattern_2_7: 1340000 rects
+caravel_000710d6_fill_pattern_1_4: 1860000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_000710d6_fill_pattern_4_5: 1880000 rects
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+caravel_000710d6_fill_pattern_1_4: 1890000 rects
+caravel_000710d6_fill_pattern_2_3: 1840000 rects
+caravel_000710d6_fill_pattern_1_0: 1780000 rects
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+caravel_000710d6_fill_pattern_3_4: 2000000 rects
+caravel_000710d6_fill_pattern_0_5: 1940000 rects
+caravel_000710d6_fill_pattern_2_5: 1790000 rects
+caravel_000710d6_fill_pattern_1_0: 1790000 rects
+caravel_000710d6_fill_pattern_2_3: 1860000 rects
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+caravel_000710d6_fill_pattern_1_4: 1910000 rects
+caravel_000710d6_fill_pattern_4_5: 1930000 rects
+caravel_000710d6_fill_pattern_0_1: 1710000 rects
+caravel_000710d6_fill_pattern_3_4: 2010000 rects
+caravel_000710d6_fill_pattern_2_5: 1800000 rects
+caravel_000710d6_fill_pattern_2_3: 1870000 rects
+caravel_000710d6_fill_pattern_1_0: 1800000 rects
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+caravel_000710d6_fill_pattern_4_5: 1940000 rects
+caravel_000710d6_fill_pattern_1_4: 1920000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_3_4: 2020000 rects
+caravel_000710d6_fill_pattern_4_3: 1790000 rects
+caravel_000710d6_fill_pattern_0_1: 1720000 rects
+caravel_000710d6_fill_pattern_2_5: 1810000 rects
+caravel_000710d6_fill_pattern_2_3: 1880000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_000710d6_fill_pattern_3_2: 1860000 rects
+Loading sky130A Device Generator Menu ...
+caravel_000710d6_fill_pattern_4_1: 1620000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
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+   Generating output for cell caravel_000710d6_fill_pattern_2_7
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+caravel_000710d6_fill_pattern_3_6: 2170000 rects
+caravel_000710d6_fill_pattern_4_3: 2480000 rects
+Ended: 12/14/2022 12:03:31
+caravel_000710d6_fill_pattern_1_0: 3090000 rects
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+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_3: 3100000 rects
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+caravel_000710d6_fill_pattern_4_5: 2710000 rects
+caravel_000710d6_fill_pattern_1_6: 1940000 rects
+Processing system .magicrc file
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+caravel_000710d6_fill_pattern_0_1: 2570000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_3_4: 3050000 rects
+caravel_000710d6_fill_pattern_1_6: 1950000 rects
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+caravel_000710d6_fill_pattern_1_0: 3100000 rects
+caravel_000710d6_fill_pattern_4_1: 2290000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_000710d6_fill_pattern_1_6: 1960000 rects
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+caravel_000710d6_fill_pattern_3_6: 2240000 rects
+caravel_000710d6_fill_pattern_3_2: 2990000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_000710d6_fill_pattern_3_4: 3080000 rects
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
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+caravel_000710d6_fill_pattern_3_4: 4810000 rects
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+caravel_000710d6_fill_pattern_0_5: 4570000 rects
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+caravel_000710d6_fill_pattern_0_1: 4220000 rects
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+caravel_000710d6_fill_pattern_3_4: 4830000 rects
+caravel_000710d6_fill_pattern_1_0: 4200000 rects
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+caravel_000710d6_fill_pattern_3_4: 4840000 rects
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+caravel_000710d6_fill_pattern_0_5: 4590000 rects
+caravel_000710d6_fill_pattern_1_0: 4210000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_3_4: 4850000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_4_3
+caravel_000710d6_fill_pattern_0_1: 4250000 rects
+caravel_000710d6_fill_pattern_2_3: 3950000 rects
+caravel_000710d6_fill_pattern_3_2: 4120000 rects
+caravel_000710d6_fill_pattern_3_4: 4860000 rects
+caravel_000710d6_fill_pattern_1_4: 4260000 rects
+caravel_000710d6_fill_pattern_1_6: 3470000 rects
+caravel_000710d6_fill_pattern_2_5: 4260000 rects
+caravel_000710d6_fill_pattern_0_5: 4600000 rects
+caravel_000710d6_fill_pattern_1_0: 4220000 rects
+caravel_000710d6_fill_pattern_0_1: 4260000 rects
+caravel_000710d6_fill_pattern_3_4: 4870000 rects
+Ended: 12/14/2022 12:03:48
+caravel_000710d6_fill_pattern_4_5: 4450000 rects
+caravel_000710d6_fill_pattern_1_6: 3480000 rects
+caravel_000710d6_fill_pattern_0_1: 4270000 rects
+caravel_000710d6_fill_pattern_3_2: 4130000 rects
+caravel_000710d6_fill_pattern_3_4: 4880000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_5: 4270000 rects
+caravel_000710d6_fill_pattern_0_5: 4610000 rects
+caravel_000710d6_fill_pattern_2_3: 3960000 rects
+caravel_000710d6_fill_pattern_1_0: 4230000 rects
+caravel_000710d6_fill_pattern_0_1: 4280000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_1_4: 4270000 rects
+caravel_000710d6_fill_pattern_3_4: 4890000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_1_6: 3490000 rects
+caravel_000710d6_fill_pattern_0_5: 4620000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_000710d6_fill_pattern_3_4: 4900000 rects
+caravel_000710d6_fill_pattern_0_5: 4630000 rects
+caravel_000710d6_fill_pattern_2_5: 4280000 rects
+caravel_000710d6_fill_pattern_0_5: 4640000 rects
+caravel_000710d6_fill_pattern_4_5: 4460000 rects
+caravel_000710d6_fill_pattern_3_4: 4910000 rects
+caravel_000710d6_fill_pattern_1_0: 4240000 rects
+caravel_000710d6_fill_pattern_1_6: 3500000 rects
+caravel_000710d6_fill_pattern_0_5: 4650000 rects
+caravel_000710d6_fill_pattern_1_4: 4280000 rects
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+caravel_000710d6_fill_pattern_3_4: 4920000 rects
+caravel_000710d6_fill_pattern_3_2: 4150000 rects
+caravel_000710d6_fill_pattern_0_5: 4670000 rects
+caravel_000710d6_fill_pattern_2_5: 4290000 rects
+caravel_000710d6_fill_pattern_0_5: 4680000 rects
+caravel_000710d6_fill_pattern_1_6: 3510000 rects
+caravel_000710d6_fill_pattern_3_4: 4930000 rects
+caravel_000710d6_fill_pattern_0_5: 4690000 rects
+caravel_000710d6_fill_pattern_1_0: 4250000 rects
+caravel_000710d6_fill_pattern_0_5: 4700000 rects
+caravel_000710d6_fill_pattern_0_1: 4290000 rects
+caravel_000710d6_fill_pattern_1_4: 4290000 rects
+caravel_000710d6_fill_pattern_2_3: 3980000 rects
+caravel_000710d6_fill_pattern_3_4: 4940000 rects
+caravel_000710d6_fill_pattern_0_5: 4710000 rects
+caravel_000710d6_fill_pattern_4_5: 4470000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_0_5: 4720000 rects
+caravel_000710d6_fill_pattern_1_6: 3520000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_2_1: 20000 rects
+caravel_000710d6_fill_pattern_1_4: 4300000 rects
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+caravel_000710d6_fill_pattern_0_1: 4650000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_0_5
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+caravel_000710d6_fill_pattern_0_1: 4660000 rects
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+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_2_3: 4180000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_0_1
+caravel_000710d6_fill_pattern_2_1: 900000 rects
+caravel_000710d6_fill_pattern_1_0: 4520000 rects
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+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_1_6: 4240000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_4_5
+caravel_000710d6_fill_pattern_2_1: 1350000 rects
+caravel_000710d6_fill_pattern_1_4: 4610000 rects
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_3_4
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+   Generating output for cell caravel_000710d6_fill_pattern_1_6
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+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_2_5: 5280000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_3_2
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+caravel_000710d6_fill_pattern_2_3: 5160000 rects
+caravel_000710d6_fill_pattern_1_0: 6260000 rects
+Ended: 12/14/2022 12:04:08
+caravel_000710d6_fill_pattern_2_5: 5880000 rects
+caravel_000710d6_fill_pattern_2_3: 5170000 rects
+caravel_000710d6_fill_pattern_1_0: 6270000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_000710d6_fill_pattern_1_0: 6280000 rects
+caravel_000710d6_fill_pattern_2_1: 2830000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_1_4: 5370000 rects
+caravel_000710d6_fill_pattern_2_3: 5180000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_1_0: 6290000 rects
+caravel_000710d6_fill_pattern_2_5: 5900000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_000710d6_fill_pattern_2_5: 5910000 rects
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+caravel_000710d6_fill_pattern_1_0: 6370000 rects
+caravel_000710d6_fill_pattern_2_1: 2840000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
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+caravel_000710d6_fill_pattern_2_5: 5940000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_2_5: 7100000 rects
+caravel_000710d6_fill_pattern_2_5: 7110000 rects
+caravel_000710d6_fill_pattern_1_4: 6650000 rects
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+caravel_000710d6_fill_pattern_1_4: 6660000 rects
+caravel_000710d6_fill_pattern_2_3: 6400000 rects
+caravel_000710d6_fill_pattern_2_1: 3560000 rects
+caravel_000710d6_fill_pattern_1_4: 6670000 rects
+caravel_000710d6_fill_pattern_1_4: 6680000 rects
+caravel_000710d6_fill_pattern_2_1: 3570000 rects
+caravel_000710d6_fill_pattern_1_4: 6690000 rects
+caravel_000710d6_fill_pattern_2_3: 6410000 rects
+caravel_000710d6_fill_pattern_2_5: 7140000 rects
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+caravel_000710d6_fill_pattern_1_4: 6700000 rects
+caravel_000710d6_fill_pattern_2_1: 3580000 rects
+Ended: 12/14/2022 12:04:21
+caravel_000710d6_fill_pattern_1_4: 6710000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_2_1: 3590000 rects
+caravel_000710d6_fill_pattern_1_4: 6720000 rects
+caravel_000710d6_fill_pattern_2_3: 6420000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_3: 1950000 rects
+caravel_000710d6_fill_pattern_1_4: 6730000 rects
+caravel_000710d6_fill_pattern_2_1: 3600000 rects
+caravel_000710d6_fill_pattern_1_4: 6740000 rects
+caravel_000710d6_fill_pattern_2_3: 6430000 rects
+caravel_000710d6_fill_pattern_2_5: 7150000 rects
+caravel_000710d6_fill_pattern_1_4: 6750000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_2_1: 3610000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_0_3: 1960000 rects
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+caravel_000710d6_fill_pattern_3_0: 100000 rects
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+caravel_000710d6_fill_pattern_3_0: 150000 rects
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+caravel_000710d6_fill_pattern_3_0: 240000 rects
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+caravel_000710d6_fill_pattern_3_0: 260000 rects
+caravel_000710d6_fill_pattern_2_1: 3670000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_3_0: 270000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_2_5
+caravel_000710d6_fill_pattern_3_0: 280000 rects
+caravel_000710d6_fill_pattern_0_3: 2020000 rects
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+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_1_4: 7130000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_2_3
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_0_3
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+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_3_0
+Ended: 12/14/2022 12:05:38
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+Ended: 12/14/2022 12:06:08
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_1_2: 4010000 rects
+caravel_000710d6_fill_pattern_4_7: 530000 rects
+caravel_000710d6_fill_pattern_4_7: 540000 rects
+caravel_000710d6_fill_pattern_4_7: 550000 rects
+caravel_000710d6_fill_pattern_4_7: 560000 rects
+caravel_000710d6_fill_pattern_4_7: 570000 rects
+caravel_000710d6_fill_pattern_4_7: 580000 rects
+caravel_000710d6_fill_pattern_1_2: 4020000 rects
+caravel_000710d6_fill_pattern_4_7: 590000 rects
+caravel_000710d6_fill_pattern_4_7: 600000 rects
+caravel_000710d6_fill_pattern_4_7: 610000 rects
+caravel_000710d6_fill_pattern_1_2: 4030000 rects
+caravel_000710d6_fill_pattern_4_7: 620000 rects
+caravel_000710d6_fill_pattern_4_7: 630000 rects
+caravel_000710d6_fill_pattern_4_7: 640000 rects
+caravel_000710d6_fill_pattern_4_7: 650000 rects
+caravel_000710d6_fill_pattern_4_7: 660000 rects
+caravel_000710d6_fill_pattern_1_2: 4040000 rects
+caravel_000710d6_fill_pattern_4_7: 670000 rects
+caravel_000710d6_fill_pattern_4_7: 680000 rects
+caravel_000710d6_fill_pattern_4_7: 690000 rects
+caravel_000710d6_fill_pattern_1_2: 4050000 rects
+caravel_000710d6_fill_pattern_4_7: 700000 rects
+caravel_000710d6_fill_pattern_4_7: 710000 rects
+caravel_000710d6_fill_pattern_1_2: 4060000 rects
+caravel_000710d6_fill_pattern_4_7: 720000 rects
+caravel_000710d6_fill_pattern_4_7: 730000 rects
+caravel_000710d6_fill_pattern_1_2: 4070000 rects
+caravel_000710d6_fill_pattern_4_7: 740000 rects
+caravel_000710d6_fill_pattern_4_7: 750000 rects
+caravel_000710d6_fill_pattern_1_2: 4080000 rects
+caravel_000710d6_fill_pattern_4_7: 760000 rects
+caravel_000710d6_fill_pattern_4_7: 770000 rects
+caravel_000710d6_fill_pattern_1_2: 4090000 rects
+caravel_000710d6_fill_pattern_4_7: 780000 rects
+caravel_000710d6_fill_pattern_1_2: 4100000 rects
+caravel_000710d6_fill_pattern_1_2: 4110000 rects
+caravel_000710d6_fill_pattern_1_2: 4120000 rects
+caravel_000710d6_fill_pattern_1_2: 4130000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_1_2: 4140000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_4_7
+caravel_000710d6_fill_pattern_1_2: 4150000 rects
+caravel_000710d6_fill_pattern_1_2: 4160000 rects
+caravel_000710d6_fill_pattern_1_2: 4170000 rects
+caravel_000710d6_fill_pattern_1_2: 4180000 rects
+caravel_000710d6_fill_pattern_1_2: 4190000 rects
+caravel_000710d6_fill_pattern_1_2: 4200000 rects
+caravel_000710d6_fill_pattern_1_2: 4210000 rects
+caravel_000710d6_fill_pattern_1_2: 4220000 rects
+caravel_000710d6_fill_pattern_1_2: 4230000 rects
+caravel_000710d6_fill_pattern_1_2: 4240000 rects
+caravel_000710d6_fill_pattern_1_2: 4250000 rects
+caravel_000710d6_fill_pattern_1_2: 4260000 rects
+caravel_000710d6_fill_pattern_1_2: 4270000 rects
+caravel_000710d6_fill_pattern_1_2: 4280000 rects
+caravel_000710d6_fill_pattern_1_2: 4290000 rects
+caravel_000710d6_fill_pattern_1_2: 4300000 rects
+caravel_000710d6_fill_pattern_1_2: 4310000 rects
+caravel_000710d6_fill_pattern_1_2: 4320000 rects
+caravel_000710d6_fill_pattern_1_2: 4330000 rects
+caravel_000710d6_fill_pattern_1_2: 4340000 rects
+caravel_000710d6_fill_pattern_1_2: 4350000 rects
+caravel_000710d6_fill_pattern_1_2: 4360000 rects
+caravel_000710d6_fill_pattern_1_2: 4370000 rects
+caravel_000710d6_fill_pattern_1_2: 4380000 rects
+caravel_000710d6_fill_pattern_1_2: 4390000 rects
+caravel_000710d6_fill_pattern_1_2: 4400000 rects
+caravel_000710d6_fill_pattern_1_2: 4410000 rects
+caravel_000710d6_fill_pattern_1_2: 4420000 rects
+caravel_000710d6_fill_pattern_1_2: 4430000 rects
+caravel_000710d6_fill_pattern_1_2: 4440000 rects
+caravel_000710d6_fill_pattern_1_2: 4450000 rects
+caravel_000710d6_fill_pattern_1_2: 4460000 rects
+caravel_000710d6_fill_pattern_1_2: 4470000 rects
+Ended: 12/14/2022 12:06:14
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_1_2: 4480000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_1_2: 4490000 rects
+caravel_000710d6_fill_pattern_1_2: 4500000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_5_6: 10000 rects
+caravel_000710d6_fill_pattern_5_6: 20000 rects
+caravel_000710d6_fill_pattern_5_6: 30000 rects
+caravel_000710d6_fill_pattern_1_2: 4510000 rects
+caravel_000710d6_fill_pattern_5_6: 40000 rects
+caravel_000710d6_fill_pattern_5_6: 50000 rects
+caravel_000710d6_fill_pattern_5_6: 60000 rects
+caravel_000710d6_fill_pattern_5_6: 70000 rects
+caravel_000710d6_fill_pattern_5_6: 80000 rects
+caravel_000710d6_fill_pattern_1_2: 4520000 rects
+caravel_000710d6_fill_pattern_5_6: 90000 rects
+caravel_000710d6_fill_pattern_5_6: 100000 rects
+caravel_000710d6_fill_pattern_5_6: 110000 rects
+caravel_000710d6_fill_pattern_5_6: 120000 rects
+caravel_000710d6_fill_pattern_1_2: 4530000 rects
+caravel_000710d6_fill_pattern_5_6: 130000 rects
+caravel_000710d6_fill_pattern_5_6: 140000 rects
+caravel_000710d6_fill_pattern_5_6: 150000 rects
+caravel_000710d6_fill_pattern_5_6: 160000 rects
+caravel_000710d6_fill_pattern_5_6: 170000 rects
+caravel_000710d6_fill_pattern_1_2: 4540000 rects
+caravel_000710d6_fill_pattern_5_6: 180000 rects
+caravel_000710d6_fill_pattern_5_6: 190000 rects
+caravel_000710d6_fill_pattern_5_6: 200000 rects
+caravel_000710d6_fill_pattern_1_2: 4550000 rects
+caravel_000710d6_fill_pattern_5_6: 210000 rects
+caravel_000710d6_fill_pattern_5_6: 220000 rects
+caravel_000710d6_fill_pattern_5_6: 230000 rects
+caravel_000710d6_fill_pattern_1_2: 4560000 rects
+caravel_000710d6_fill_pattern_5_6: 240000 rects
+caravel_000710d6_fill_pattern_5_6: 250000 rects
+caravel_000710d6_fill_pattern_5_6: 260000 rects
+caravel_000710d6_fill_pattern_1_2: 4570000 rects
+caravel_000710d6_fill_pattern_5_6: 270000 rects
+caravel_000710d6_fill_pattern_5_6: 280000 rects
+caravel_000710d6_fill_pattern_5_6: 290000 rects
+caravel_000710d6_fill_pattern_1_2: 4580000 rects
+caravel_000710d6_fill_pattern_5_6: 300000 rects
+caravel_000710d6_fill_pattern_5_6: 310000 rects
+caravel_000710d6_fill_pattern_5_6: 320000 rects
+caravel_000710d6_fill_pattern_5_6: 330000 rects
+caravel_000710d6_fill_pattern_5_6: 340000 rects
+caravel_000710d6_fill_pattern_1_2: 4590000 rects
+caravel_000710d6_fill_pattern_5_6: 350000 rects
+caravel_000710d6_fill_pattern_5_6: 360000 rects
+caravel_000710d6_fill_pattern_5_6: 370000 rects
+caravel_000710d6_fill_pattern_5_6: 380000 rects
+caravel_000710d6_fill_pattern_5_6: 390000 rects
+caravel_000710d6_fill_pattern_5_6: 400000 rects
+caravel_000710d6_fill_pattern_1_2: 4600000 rects
+caravel_000710d6_fill_pattern_5_6: 410000 rects
+caravel_000710d6_fill_pattern_5_6: 420000 rects
+caravel_000710d6_fill_pattern_5_6: 430000 rects
+caravel_000710d6_fill_pattern_5_6: 440000 rects
+caravel_000710d6_fill_pattern_1_2: 4610000 rects
+caravel_000710d6_fill_pattern_5_6: 450000 rects
+caravel_000710d6_fill_pattern_5_6: 460000 rects
+caravel_000710d6_fill_pattern_5_6: 470000 rects
+caravel_000710d6_fill_pattern_5_6: 480000 rects
+caravel_000710d6_fill_pattern_5_6: 490000 rects
+caravel_000710d6_fill_pattern_5_6: 500000 rects
+caravel_000710d6_fill_pattern_5_6: 510000 rects
+caravel_000710d6_fill_pattern_1_2: 4620000 rects
+caravel_000710d6_fill_pattern_5_6: 520000 rects
+caravel_000710d6_fill_pattern_5_6: 530000 rects
+caravel_000710d6_fill_pattern_5_6: 540000 rects
+caravel_000710d6_fill_pattern_5_6: 550000 rects
+caravel_000710d6_fill_pattern_5_6: 560000 rects
+caravel_000710d6_fill_pattern_5_6: 570000 rects
+caravel_000710d6_fill_pattern_1_2: 4630000 rects
+caravel_000710d6_fill_pattern_5_6: 580000 rects
+caravel_000710d6_fill_pattern_5_6: 590000 rects
+caravel_000710d6_fill_pattern_5_6: 600000 rects
+caravel_000710d6_fill_pattern_5_6: 610000 rects
+caravel_000710d6_fill_pattern_5_6: 620000 rects
+caravel_000710d6_fill_pattern_5_6: 630000 rects
+caravel_000710d6_fill_pattern_1_2: 4640000 rects
+caravel_000710d6_fill_pattern_5_6: 640000 rects
+caravel_000710d6_fill_pattern_5_6: 650000 rects
+caravel_000710d6_fill_pattern_5_6: 660000 rects
+caravel_000710d6_fill_pattern_5_6: 670000 rects
+caravel_000710d6_fill_pattern_1_2: 4650000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_5_6
+caravel_000710d6_fill_pattern_1_2: 4660000 rects
+caravel_000710d6_fill_pattern_1_2: 4670000 rects
+caravel_000710d6_fill_pattern_1_2: 4680000 rects
+caravel_000710d6_fill_pattern_1_2: 4690000 rects
+caravel_000710d6_fill_pattern_1_2: 4700000 rects
+caravel_000710d6_fill_pattern_1_2: 4710000 rects
+caravel_000710d6_fill_pattern_1_2: 4720000 rects
+caravel_000710d6_fill_pattern_1_2: 4730000 rects
+caravel_000710d6_fill_pattern_1_2: 4740000 rects
+caravel_000710d6_fill_pattern_1_2: 4750000 rects
+caravel_000710d6_fill_pattern_1_2: 4760000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_1_2
+Ended: 12/14/2022 12:06:27
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_6: 10000 rects
+caravel_000710d6_fill_pattern_0_6: 20000 rects
+caravel_000710d6_fill_pattern_0_6: 30000 rects
+caravel_000710d6_fill_pattern_0_6: 40000 rects
+caravel_000710d6_fill_pattern_0_6: 50000 rects
+caravel_000710d6_fill_pattern_0_6: 60000 rects
+caravel_000710d6_fill_pattern_0_6: 70000 rects
+caravel_000710d6_fill_pattern_0_6: 80000 rects
+caravel_000710d6_fill_pattern_0_6: 90000 rects
+caravel_000710d6_fill_pattern_0_6: 100000 rects
+caravel_000710d6_fill_pattern_0_6: 110000 rects
+caravel_000710d6_fill_pattern_0_6: 120000 rects
+caravel_000710d6_fill_pattern_0_6: 130000 rects
+caravel_000710d6_fill_pattern_0_6: 140000 rects
+caravel_000710d6_fill_pattern_0_6: 150000 rects
+caravel_000710d6_fill_pattern_0_6: 160000 rects
+caravel_000710d6_fill_pattern_0_6: 170000 rects
+caravel_000710d6_fill_pattern_0_6: 180000 rects
+caravel_000710d6_fill_pattern_0_6: 190000 rects
+caravel_000710d6_fill_pattern_0_6: 200000 rects
+caravel_000710d6_fill_pattern_0_6: 210000 rects
+caravel_000710d6_fill_pattern_0_6: 220000 rects
+caravel_000710d6_fill_pattern_0_6: 230000 rects
+caravel_000710d6_fill_pattern_0_6: 240000 rects
+caravel_000710d6_fill_pattern_0_6: 250000 rects
+caravel_000710d6_fill_pattern_0_6: 260000 rects
+caravel_000710d6_fill_pattern_0_6: 270000 rects
+caravel_000710d6_fill_pattern_0_6: 280000 rects
+caravel_000710d6_fill_pattern_0_6: 290000 rects
+caravel_000710d6_fill_pattern_0_6: 300000 rects
+caravel_000710d6_fill_pattern_0_6: 310000 rects
+caravel_000710d6_fill_pattern_0_6: 320000 rects
+caravel_000710d6_fill_pattern_0_6: 330000 rects
+caravel_000710d6_fill_pattern_0_6: 340000 rects
+caravel_000710d6_fill_pattern_0_6: 350000 rects
+caravel_000710d6_fill_pattern_0_6: 360000 rects
+caravel_000710d6_fill_pattern_0_6: 370000 rects
+caravel_000710d6_fill_pattern_0_6: 380000 rects
+caravel_000710d6_fill_pattern_0_6: 390000 rects
+caravel_000710d6_fill_pattern_0_6: 400000 rects
+caravel_000710d6_fill_pattern_0_6: 410000 rects
+caravel_000710d6_fill_pattern_0_6: 420000 rects
+caravel_000710d6_fill_pattern_0_6: 430000 rects
+caravel_000710d6_fill_pattern_0_6: 440000 rects
+caravel_000710d6_fill_pattern_0_6: 450000 rects
+caravel_000710d6_fill_pattern_0_6: 460000 rects
+caravel_000710d6_fill_pattern_0_6: 470000 rects
+caravel_000710d6_fill_pattern_0_6: 480000 rects
+caravel_000710d6_fill_pattern_0_6: 490000 rects
+caravel_000710d6_fill_pattern_0_6: 500000 rects
+caravel_000710d6_fill_pattern_0_6: 510000 rects
+caravel_000710d6_fill_pattern_0_6: 520000 rects
+caravel_000710d6_fill_pattern_0_6: 530000 rects
+caravel_000710d6_fill_pattern_0_6: 540000 rects
+caravel_000710d6_fill_pattern_0_6: 550000 rects
+caravel_000710d6_fill_pattern_0_6: 560000 rects
+caravel_000710d6_fill_pattern_0_6: 570000 rects
+caravel_000710d6_fill_pattern_0_6: 580000 rects
+caravel_000710d6_fill_pattern_0_6: 590000 rects
+caravel_000710d6_fill_pattern_0_6: 600000 rects
+caravel_000710d6_fill_pattern_0_6: 610000 rects
+caravel_000710d6_fill_pattern_0_6: 620000 rects
+caravel_000710d6_fill_pattern_0_6: 630000 rects
+caravel_000710d6_fill_pattern_0_6: 640000 rects
+caravel_000710d6_fill_pattern_0_6: 650000 rects
+caravel_000710d6_fill_pattern_0_6: 660000 rects
+caravel_000710d6_fill_pattern_0_6: 670000 rects
+caravel_000710d6_fill_pattern_0_6: 680000 rects
+caravel_000710d6_fill_pattern_0_6: 690000 rects
+caravel_000710d6_fill_pattern_0_6: 700000 rects
+caravel_000710d6_fill_pattern_0_6: 710000 rects
+caravel_000710d6_fill_pattern_0_6: 720000 rects
+caravel_000710d6_fill_pattern_0_6: 730000 rects
+caravel_000710d6_fill_pattern_0_6: 740000 rects
+caravel_000710d6_fill_pattern_0_6: 750000 rects
+caravel_000710d6_fill_pattern_0_6: 760000 rects
+caravel_000710d6_fill_pattern_0_6: 770000 rects
+caravel_000710d6_fill_pattern_0_6: 780000 rects
+caravel_000710d6_fill_pattern_0_6: 790000 rects
+caravel_000710d6_fill_pattern_0_6: 800000 rects
+caravel_000710d6_fill_pattern_0_6: 810000 rects
+caravel_000710d6_fill_pattern_0_6: 820000 rects
+caravel_000710d6_fill_pattern_0_6: 830000 rects
+caravel_000710d6_fill_pattern_0_6: 840000 rects
+caravel_000710d6_fill_pattern_0_6: 850000 rects
+caravel_000710d6_fill_pattern_0_6: 860000 rects
+caravel_000710d6_fill_pattern_0_6: 870000 rects
+caravel_000710d6_fill_pattern_0_6: 880000 rects
+caravel_000710d6_fill_pattern_0_6: 890000 rects
+caravel_000710d6_fill_pattern_0_6: 900000 rects
+caravel_000710d6_fill_pattern_0_6: 910000 rects
+caravel_000710d6_fill_pattern_0_6: 920000 rects
+caravel_000710d6_fill_pattern_0_6: 930000 rects
+caravel_000710d6_fill_pattern_0_6: 940000 rects
+caravel_000710d6_fill_pattern_0_6: 950000 rects
+caravel_000710d6_fill_pattern_0_6: 960000 rects
+caravel_000710d6_fill_pattern_0_6: 970000 rects
+caravel_000710d6_fill_pattern_0_6: 980000 rects
+caravel_000710d6_fill_pattern_0_6: 990000 rects
+caravel_000710d6_fill_pattern_0_6: 1000000 rects
+caravel_000710d6_fill_pattern_0_6: 1010000 rects
+caravel_000710d6_fill_pattern_0_6: 1020000 rects
+caravel_000710d6_fill_pattern_0_6: 1030000 rects
+caravel_000710d6_fill_pattern_0_6: 1040000 rects
+caravel_000710d6_fill_pattern_0_6: 1050000 rects
+caravel_000710d6_fill_pattern_0_6: 1060000 rects
+caravel_000710d6_fill_pattern_0_6: 1070000 rects
+caravel_000710d6_fill_pattern_0_6: 1080000 rects
+caravel_000710d6_fill_pattern_0_6: 1090000 rects
+caravel_000710d6_fill_pattern_0_6: 1100000 rects
+caravel_000710d6_fill_pattern_0_6: 1110000 rects
+caravel_000710d6_fill_pattern_0_6: 1120000 rects
+caravel_000710d6_fill_pattern_0_6: 1130000 rects
+caravel_000710d6_fill_pattern_0_6: 1140000 rects
+caravel_000710d6_fill_pattern_0_6: 1150000 rects
+caravel_000710d6_fill_pattern_0_6: 1160000 rects
+caravel_000710d6_fill_pattern_0_6: 1170000 rects
+caravel_000710d6_fill_pattern_0_6: 1180000 rects
+caravel_000710d6_fill_pattern_0_6: 1190000 rects
+caravel_000710d6_fill_pattern_0_6: 1200000 rects
+caravel_000710d6_fill_pattern_0_6: 1210000 rects
+caravel_000710d6_fill_pattern_0_6: 1220000 rects
+caravel_000710d6_fill_pattern_0_6: 1230000 rects
+caravel_000710d6_fill_pattern_0_6: 1240000 rects
+caravel_000710d6_fill_pattern_0_6: 1250000 rects
+caravel_000710d6_fill_pattern_0_6: 1260000 rects
+caravel_000710d6_fill_pattern_0_6: 1270000 rects
+caravel_000710d6_fill_pattern_0_6: 1280000 rects
+caravel_000710d6_fill_pattern_0_6: 1290000 rects
+caravel_000710d6_fill_pattern_0_6: 1300000 rects
+caravel_000710d6_fill_pattern_0_6: 1310000 rects
+caravel_000710d6_fill_pattern_0_6: 1320000 rects
+Ended: 12/14/2022 12:06:33
+caravel_000710d6_fill_pattern_0_6: 1330000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_6: 1340000 rects
+caravel_000710d6_fill_pattern_0_6: 1350000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_6: 1360000 rects
+caravel_000710d6_fill_pattern_0_6: 1370000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_6: 1380000 rects
+caravel_000710d6_fill_pattern_0_6: 1390000 rects
+caravel_000710d6_fill_pattern_0_6: 1400000 rects
+caravel_000710d6_fill_pattern_0_6: 1410000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_6: 1420000 rects
+caravel_000710d6_fill_pattern_4_2: 10000 rects
+caravel_000710d6_fill_pattern_4_2: 20000 rects
+caravel_000710d6_fill_pattern_0_6: 1430000 rects
+caravel_000710d6_fill_pattern_4_2: 30000 rects
+caravel_000710d6_fill_pattern_4_2: 40000 rects
+caravel_000710d6_fill_pattern_4_2: 50000 rects
+caravel_000710d6_fill_pattern_0_6: 1440000 rects
+caravel_000710d6_fill_pattern_4_2: 60000 rects
+caravel_000710d6_fill_pattern_4_2: 70000 rects
+caravel_000710d6_fill_pattern_0_6: 1450000 rects
+caravel_000710d6_fill_pattern_4_2: 80000 rects
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+caravel_000710d6_fill_pattern_0_6: 1880000 rects
+Ended: 12/14/2022 12:06:38
+caravel_000710d6_fill_pattern_4_2: 1090000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_6: 1890000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_4_2: 1100000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_6: 1900000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_4_2: 1110000 rects
+caravel_000710d6_fill_pattern_0_6: 1910000 rects
+caravel_000710d6_fill_pattern_4_2: 1120000 rects
+caravel_000710d6_fill_pattern_0_6: 1920000 rects
+caravel_000710d6_fill_pattern_4_2: 1130000 rects
+caravel_000710d6_fill_pattern_0_6: 1930000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_4_2: 1140000 rects
+caravel_000710d6_fill_pattern_0_6: 1940000 rects
+caravel_000710d6_fill_pattern_2_4: 10000 rects
+caravel_000710d6_fill_pattern_2_4: 20000 rects
+caravel_000710d6_fill_pattern_4_2: 1150000 rects
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+caravel_000710d6_fill_pattern_2_4: 40000 rects
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+caravel_000710d6_fill_pattern_2_4: 100000 rects
+caravel_000710d6_fill_pattern_2_4: 110000 rects
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+caravel_000710d6_fill_pattern_2_4: 130000 rects
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+caravel_000710d6_fill_pattern_2_4: 240000 rects
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+caravel_000710d6_fill_pattern_2_4: 610000 rects
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+caravel_000710d6_fill_pattern_2_4: 620000 rects
+caravel_000710d6_fill_pattern_2_4: 630000 rects
+caravel_000710d6_fill_pattern_0_6: 2200000 rects
+caravel_000710d6_fill_pattern_4_2: 1400000 rects
+caravel_000710d6_fill_pattern_2_4: 640000 rects
+caravel_000710d6_fill_pattern_2_4: 650000 rects
+Ended: 12/14/2022 12:06:41
+caravel_000710d6_fill_pattern_4_2: 1410000 rects
+caravel_000710d6_fill_pattern_0_6: 2210000 rects
+caravel_000710d6_fill_pattern_2_4: 660000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_4: 670000 rects
+caravel_000710d6_fill_pattern_4_2: 1420000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_2_4: 680000 rects
+caravel_000710d6_fill_pattern_0_6: 2220000 rects
+caravel_000710d6_fill_pattern_2_4: 690000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_4_2: 1430000 rects
+caravel_000710d6_fill_pattern_2_4: 700000 rects
+caravel_000710d6_fill_pattern_0_6: 2230000 rects
+caravel_000710d6_fill_pattern_2_4: 710000 rects
+caravel_000710d6_fill_pattern_2_4: 720000 rects
+caravel_000710d6_fill_pattern_4_2: 1440000 rects
+caravel_000710d6_fill_pattern_2_4: 730000 rects
+caravel_000710d6_fill_pattern_0_6: 2240000 rects
+caravel_000710d6_fill_pattern_2_4: 740000 rects
+caravel_000710d6_fill_pattern_4_2: 1450000 rects
+caravel_000710d6_fill_pattern_2_4: 750000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_0_6: 2250000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_000710d6_fill_pattern_2_4: 760000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_4_2: 1460000 rects
+caravel_000710d6_fill_pattern_2_4: 770000 rects
+caravel_000710d6_fill_pattern_1_5: 10000 rects
+caravel_000710d6_fill_pattern_0_6: 2260000 rects
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+caravel_000710d6_fill_pattern_1_5: 20000 rects
+caravel_000710d6_fill_pattern_1_5: 30000 rects
+caravel_000710d6_fill_pattern_4_2: 1470000 rects
+caravel_000710d6_fill_pattern_2_4: 790000 rects
+caravel_000710d6_fill_pattern_1_5: 40000 rects
+caravel_000710d6_fill_pattern_0_6: 2270000 rects
+caravel_000710d6_fill_pattern_1_5: 50000 rects
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+caravel_000710d6_fill_pattern_1_5: 60000 rects
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+caravel_000710d6_fill_pattern_1_5: 70000 rects
+caravel_000710d6_fill_pattern_1_5: 80000 rects
+caravel_000710d6_fill_pattern_2_4: 820000 rects
+caravel_000710d6_fill_pattern_0_6: 2280000 rects
+caravel_000710d6_fill_pattern_1_5: 90000 rects
+caravel_000710d6_fill_pattern_2_4: 830000 rects
+caravel_000710d6_fill_pattern_1_5: 100000 rects
+caravel_000710d6_fill_pattern_4_2: 1490000 rects
+caravel_000710d6_fill_pattern_1_5: 110000 rects
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+caravel_000710d6_fill_pattern_1_5: 130000 rects
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+caravel_000710d6_fill_pattern_1_5: 150000 rects
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+caravel_000710d6_fill_pattern_2_4: 870000 rects
+caravel_000710d6_fill_pattern_1_5: 160000 rects
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+caravel_000710d6_fill_pattern_4_2: 1510000 rects
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+caravel_000710d6_fill_pattern_2_4: 3050000 rects
+caravel_000710d6_fill_pattern_1_5: 2680000 rects
+caravel_000710d6_fill_pattern_1_5: 2690000 rects
+caravel_000710d6_fill_pattern_2_4: 3060000 rects
+caravel_000710d6_fill_pattern_1_5: 2700000 rects
+caravel_000710d6_fill_pattern_0_6: 3650000 rects
+caravel_000710d6_fill_pattern_2_4: 3070000 rects
+caravel_000710d6_fill_pattern_1_5: 2710000 rects
+caravel_000710d6_fill_pattern_4_2: 2620000 rects
+caravel_000710d6_fill_pattern_2_4: 3080000 rects
+caravel_000710d6_fill_pattern_1_5: 2720000 rects
+caravel_000710d6_fill_pattern_1_5: 2730000 rects
+caravel_000710d6_fill_pattern_2_4: 3090000 rects
+caravel_000710d6_fill_pattern_1_5: 2740000 rects
+caravel_000710d6_fill_pattern_2_4: 3100000 rects
+caravel_000710d6_fill_pattern_1_5: 2750000 rects
+caravel_000710d6_fill_pattern_1_5: 2760000 rects
+caravel_000710d6_fill_pattern_2_4: 3110000 rects
+caravel_000710d6_fill_pattern_0_6: 3660000 rects
+caravel_000710d6_fill_pattern_1_5: 2770000 rects
+caravel_000710d6_fill_pattern_1_5: 2780000 rects
+caravel_000710d6_fill_pattern_2_4: 3120000 rects
+caravel_000710d6_fill_pattern_1_5: 2790000 rects
+caravel_000710d6_fill_pattern_2_4: 3130000 rects
+caravel_000710d6_fill_pattern_1_5: 2800000 rects
+caravel_000710d6_fill_pattern_0_6: 3670000 rects
+caravel_000710d6_fill_pattern_1_5: 2810000 rects
+caravel_000710d6_fill_pattern_2_4: 3140000 rects
+caravel_000710d6_fill_pattern_0_6: 3680000 rects
+caravel_000710d6_fill_pattern_1_5: 2820000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_0_6: 3690000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_4_2
+caravel_000710d6_fill_pattern_1_5: 2830000 rects
+caravel_000710d6_fill_pattern_2_4: 3150000 rects
+caravel_000710d6_fill_pattern_0_6: 3700000 rects
+caravel_000710d6_fill_pattern_1_5: 2840000 rects
+caravel_000710d6_fill_pattern_2_4: 3160000 rects
+caravel_000710d6_fill_pattern_1_5: 2850000 rects
+caravel_000710d6_fill_pattern_2_4: 3170000 rects
+caravel_000710d6_fill_pattern_1_5: 2860000 rects
+caravel_000710d6_fill_pattern_0_6: 3710000 rects
+caravel_000710d6_fill_pattern_2_4: 3180000 rects
+caravel_000710d6_fill_pattern_2_4: 3190000 rects
+caravel_000710d6_fill_pattern_1_5: 2870000 rects
+caravel_000710d6_fill_pattern_2_4: 3200000 rects
+caravel_000710d6_fill_pattern_2_4: 3210000 rects
+caravel_000710d6_fill_pattern_1_5: 2880000 rects
+caravel_000710d6_fill_pattern_2_4: 3220000 rects
+caravel_000710d6_fill_pattern_1_5: 2890000 rects
+caravel_000710d6_fill_pattern_2_4: 3230000 rects
+caravel_000710d6_fill_pattern_2_4: 3240000 rects
+Ended: 12/14/2022 12:06:54
+caravel_000710d6_fill_pattern_1_5: 2900000 rects
+caravel_000710d6_fill_pattern_2_4: 3250000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_2_4: 3260000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_0_6
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_1_5: 2910000 rects
+caravel_000710d6_fill_pattern_2_4: 3270000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_4: 3280000 rects
+caravel_000710d6_fill_pattern_1_5: 2920000 rects
+caravel_000710d6_fill_pattern_2_4: 3290000 rects
+caravel_000710d6_fill_pattern_2_4: 3300000 rects
+caravel_000710d6_fill_pattern_2_4: 3310000 rects
+caravel_000710d6_fill_pattern_1_5: 2930000 rects
+caravel_000710d6_fill_pattern_2_4: 3320000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_2_4: 3330000 rects
+caravel_000710d6_fill_pattern_1_5: 2940000 rects
+caravel_000710d6_fill_pattern_5_1: 10000 rects
+caravel_000710d6_fill_pattern_2_4: 3340000 rects
+caravel_000710d6_fill_pattern_5_1: 20000 rects
+caravel_000710d6_fill_pattern_5_1: 30000 rects
+caravel_000710d6_fill_pattern_2_4: 3350000 rects
+caravel_000710d6_fill_pattern_1_5: 2950000 rects
+caravel_000710d6_fill_pattern_5_1: 40000 rects
+caravel_000710d6_fill_pattern_5_1: 50000 rects
+caravel_000710d6_fill_pattern_2_4: 3360000 rects
+caravel_000710d6_fill_pattern_5_1: 60000 rects
+caravel_000710d6_fill_pattern_5_1: 70000 rects
+caravel_000710d6_fill_pattern_5_1: 80000 rects
+caravel_000710d6_fill_pattern_2_4: 3370000 rects
+caravel_000710d6_fill_pattern_1_5: 2960000 rects
+caravel_000710d6_fill_pattern_5_1: 90000 rects
+caravel_000710d6_fill_pattern_5_1: 100000 rects
+caravel_000710d6_fill_pattern_2_4: 3380000 rects
+caravel_000710d6_fill_pattern_5_1: 110000 rects
+caravel_000710d6_fill_pattern_5_1: 120000 rects
+caravel_000710d6_fill_pattern_2_4: 3390000 rects
+caravel_000710d6_fill_pattern_1_5: 2970000 rects
+caravel_000710d6_fill_pattern_5_1: 130000 rects
+caravel_000710d6_fill_pattern_2_4: 3400000 rects
+caravel_000710d6_fill_pattern_5_1: 140000 rects
+caravel_000710d6_fill_pattern_5_1: 150000 rects
+caravel_000710d6_fill_pattern_2_4: 3410000 rects
+caravel_000710d6_fill_pattern_1_5: 2980000 rects
+caravel_000710d6_fill_pattern_5_1: 160000 rects
+caravel_000710d6_fill_pattern_2_4: 3420000 rects
+caravel_000710d6_fill_pattern_5_1: 170000 rects
+caravel_000710d6_fill_pattern_5_1: 180000 rects
+caravel_000710d6_fill_pattern_2_4: 3430000 rects
+caravel_000710d6_fill_pattern_5_1: 190000 rects
+caravel_000710d6_fill_pattern_1_5: 2990000 rects
+caravel_000710d6_fill_pattern_2_4: 3440000 rects
+caravel_000710d6_fill_pattern_5_1: 200000 rects
+caravel_000710d6_fill_pattern_2_4: 3450000 rects
+caravel_000710d6_fill_pattern_5_1: 210000 rects
+caravel_000710d6_fill_pattern_1_5: 3000000 rects
+caravel_000710d6_fill_pattern_2_4: 3460000 rects
+caravel_000710d6_fill_pattern_5_1: 220000 rects
+caravel_000710d6_fill_pattern_5_1: 230000 rects
+caravel_000710d6_fill_pattern_2_4: 3470000 rects
+caravel_000710d6_fill_pattern_5_1: 240000 rects
+caravel_000710d6_fill_pattern_1_5: 3010000 rects
+caravel_000710d6_fill_pattern_2_4: 3480000 rects
+caravel_000710d6_fill_pattern_5_1: 250000 rects
+caravel_000710d6_fill_pattern_5_1: 260000 rects
+caravel_000710d6_fill_pattern_2_4: 3490000 rects
+caravel_000710d6_fill_pattern_5_1: 270000 rects
+caravel_000710d6_fill_pattern_1_5: 3020000 rects
+caravel_000710d6_fill_pattern_5_1: 280000 rects
+caravel_000710d6_fill_pattern_2_4: 3500000 rects
+caravel_000710d6_fill_pattern_2_4: 3510000 rects
+caravel_000710d6_fill_pattern_5_1: 290000 rects
+caravel_000710d6_fill_pattern_1_5: 3030000 rects
+caravel_000710d6_fill_pattern_2_4: 3520000 rects
+caravel_000710d6_fill_pattern_5_1: 300000 rects
+caravel_000710d6_fill_pattern_2_4: 3530000 rects
+caravel_000710d6_fill_pattern_1_5: 3040000 rects
+caravel_000710d6_fill_pattern_5_1: 310000 rects
+caravel_000710d6_fill_pattern_2_4: 3540000 rects
+caravel_000710d6_fill_pattern_2_4: 3550000 rects
+caravel_000710d6_fill_pattern_5_1: 320000 rects
+caravel_000710d6_fill_pattern_2_4: 3560000 rects
+caravel_000710d6_fill_pattern_1_5: 3050000 rects
+caravel_000710d6_fill_pattern_2_4: 3570000 rects
+caravel_000710d6_fill_pattern_5_1: 330000 rects
+caravel_000710d6_fill_pattern_2_4: 3580000 rects
+caravel_000710d6_fill_pattern_2_4: 3590000 rects
+caravel_000710d6_fill_pattern_5_1: 340000 rects
+caravel_000710d6_fill_pattern_1_5: 3060000 rects
+caravel_000710d6_fill_pattern_2_4: 3600000 rects
+caravel_000710d6_fill_pattern_2_4: 3610000 rects
+caravel_000710d6_fill_pattern_5_1: 350000 rects
+caravel_000710d6_fill_pattern_2_4: 3620000 rects
+Ended: 12/14/2022 12:06:56
+caravel_000710d6_fill_pattern_2_4: 3630000 rects
+caravel_000710d6_fill_pattern_1_5: 3070000 rects
+caravel_000710d6_fill_pattern_2_4: 3640000 rects
+caravel_000710d6_fill_pattern_5_1: 360000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_4: 3650000 rects
+caravel_000710d6_fill_pattern_2_4: 3660000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_5_1: 370000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_1_5: 3080000 rects
+caravel_000710d6_fill_pattern_2_4: 3670000 rects
+caravel_000710d6_fill_pattern_2_4: 3680000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_5_1: 380000 rects
+caravel_000710d6_fill_pattern_2_4: 3690000 rects
+caravel_000710d6_fill_pattern_2_4: 3700000 rects
+caravel_000710d6_fill_pattern_1_5: 3090000 rects
+caravel_000710d6_fill_pattern_5_1: 390000 rects
+caravel_000710d6_fill_pattern_2_4: 3710000 rects
+caravel_000710d6_fill_pattern_5_1: 400000 rects
+caravel_000710d6_fill_pattern_2_4: 3720000 rects
+caravel_000710d6_fill_pattern_1_5: 3100000 rects
+caravel_000710d6_fill_pattern_5_1: 410000 rects
+caravel_000710d6_fill_pattern_5_1: 420000 rects
+caravel_000710d6_fill_pattern_1_5: 3110000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_2_4: 3730000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_5_1: 430000 rects
+caravel_000710d6_fill_pattern_3_3: 10000 rects
+caravel_000710d6_fill_pattern_1_5: 3120000 rects
+caravel_000710d6_fill_pattern_3_3: 20000 rects
+caravel_000710d6_fill_pattern_3_3: 30000 rects
+caravel_000710d6_fill_pattern_5_1: 440000 rects
+caravel_000710d6_fill_pattern_2_4: 3740000 rects
+caravel_000710d6_fill_pattern_3_3: 40000 rects
+caravel_000710d6_fill_pattern_3_3: 50000 rects
+caravel_000710d6_fill_pattern_1_5: 3130000 rects
+caravel_000710d6_fill_pattern_5_1: 450000 rects
+caravel_000710d6_fill_pattern_3_3: 60000 rects
+caravel_000710d6_fill_pattern_3_3: 70000 rects
+caravel_000710d6_fill_pattern_3_3: 80000 rects
+caravel_000710d6_fill_pattern_5_1: 460000 rects
+caravel_000710d6_fill_pattern_1_5: 3140000 rects
+caravel_000710d6_fill_pattern_2_4: 3750000 rects
+caravel_000710d6_fill_pattern_3_3: 90000 rects
+caravel_000710d6_fill_pattern_3_3: 100000 rects
+caravel_000710d6_fill_pattern_5_1: 470000 rects
+caravel_000710d6_fill_pattern_3_3: 110000 rects
+caravel_000710d6_fill_pattern_3_3: 120000 rects
+caravel_000710d6_fill_pattern_1_5: 3150000 rects
+caravel_000710d6_fill_pattern_3_3: 130000 rects
+caravel_000710d6_fill_pattern_5_1: 480000 rects
+caravel_000710d6_fill_pattern_3_3: 140000 rects
+caravel_000710d6_fill_pattern_3_3: 150000 rects
+caravel_000710d6_fill_pattern_5_1: 490000 rects
+caravel_000710d6_fill_pattern_2_4: 3760000 rects
+caravel_000710d6_fill_pattern_3_3: 160000 rects
+caravel_000710d6_fill_pattern_1_5: 3160000 rects
+caravel_000710d6_fill_pattern_5_1: 500000 rects
+caravel_000710d6_fill_pattern_3_3: 170000 rects
+caravel_000710d6_fill_pattern_5_1: 510000 rects
+caravel_000710d6_fill_pattern_3_3: 180000 rects
+caravel_000710d6_fill_pattern_5_1: 520000 rects
+caravel_000710d6_fill_pattern_1_5: 3170000 rects
+caravel_000710d6_fill_pattern_3_3: 190000 rects
+caravel_000710d6_fill_pattern_5_1: 530000 rects
+caravel_000710d6_fill_pattern_2_4: 3770000 rects
+caravel_000710d6_fill_pattern_5_1: 540000 rects
+caravel_000710d6_fill_pattern_3_3: 200000 rects
+caravel_000710d6_fill_pattern_5_1: 550000 rects
+caravel_000710d6_fill_pattern_3_3: 210000 rects
+caravel_000710d6_fill_pattern_1_5: 3180000 rects
+caravel_000710d6_fill_pattern_5_1: 560000 rects
+caravel_000710d6_fill_pattern_3_3: 220000 rects
+caravel_000710d6_fill_pattern_3_3: 230000 rects
+caravel_000710d6_fill_pattern_5_1: 570000 rects
+caravel_000710d6_fill_pattern_2_4: 3780000 rects
+caravel_000710d6_fill_pattern_3_3: 240000 rects
+caravel_000710d6_fill_pattern_5_1: 580000 rects
+caravel_000710d6_fill_pattern_1_5: 3190000 rects
+caravel_000710d6_fill_pattern_3_3: 250000 rects
+caravel_000710d6_fill_pattern_5_1: 590000 rects
+caravel_000710d6_fill_pattern_3_3: 260000 rects
+caravel_000710d6_fill_pattern_5_1: 600000 rects
+caravel_000710d6_fill_pattern_3_3: 270000 rects
+caravel_000710d6_fill_pattern_3_3: 280000 rects
+caravel_000710d6_fill_pattern_1_5: 3200000 rects
+caravel_000710d6_fill_pattern_5_1: 610000 rects
+caravel_000710d6_fill_pattern_2_4: 3790000 rects
+caravel_000710d6_fill_pattern_3_3: 290000 rects
+caravel_000710d6_fill_pattern_3_3: 300000 rects
+caravel_000710d6_fill_pattern_5_1: 620000 rects
+caravel_000710d6_fill_pattern_3_3: 310000 rects
+caravel_000710d6_fill_pattern_1_5: 3210000 rects
+caravel_000710d6_fill_pattern_5_1: 630000 rects
+caravel_000710d6_fill_pattern_3_3: 320000 rects
+caravel_000710d6_fill_pattern_3_3: 330000 rects
+caravel_000710d6_fill_pattern_5_1: 640000 rects
+caravel_000710d6_fill_pattern_2_4: 3800000 rects
+caravel_000710d6_fill_pattern_3_3: 340000 rects
+caravel_000710d6_fill_pattern_3_3: 350000 rects
+caravel_000710d6_fill_pattern_5_1: 650000 rects
+caravel_000710d6_fill_pattern_1_5: 3220000 rects
+caravel_000710d6_fill_pattern_3_3: 360000 rects
+caravel_000710d6_fill_pattern_3_3: 370000 rects
+caravel_000710d6_fill_pattern_5_1: 660000 rects
+caravel_000710d6_fill_pattern_3_3: 380000 rects
+caravel_000710d6_fill_pattern_1_5: 3230000 rects
+caravel_000710d6_fill_pattern_3_3: 390000 rects
+caravel_000710d6_fill_pattern_5_1: 670000 rects
+caravel_000710d6_fill_pattern_2_4: 3810000 rects
+caravel_000710d6_fill_pattern_3_3: 400000 rects
+caravel_000710d6_fill_pattern_5_1: 680000 rects
+caravel_000710d6_fill_pattern_3_3: 410000 rects
+caravel_000710d6_fill_pattern_3_3: 420000 rects
+caravel_000710d6_fill_pattern_1_5: 3240000 rects
+caravel_000710d6_fill_pattern_5_1: 690000 rects
+caravel_000710d6_fill_pattern_3_3: 430000 rects
+caravel_000710d6_fill_pattern_3_3: 440000 rects
+caravel_000710d6_fill_pattern_2_4: 3820000 rects
+caravel_000710d6_fill_pattern_5_1: 700000 rects
+caravel_000710d6_fill_pattern_3_3: 450000 rects
+caravel_000710d6_fill_pattern_1_5: 3250000 rects
+caravel_000710d6_fill_pattern_3_3: 460000 rects
+caravel_000710d6_fill_pattern_5_1: 710000 rects
+caravel_000710d6_fill_pattern_3_3: 470000 rects
+caravel_000710d6_fill_pattern_5_1: 720000 rects
+caravel_000710d6_fill_pattern_3_3: 480000 rects
+caravel_000710d6_fill_pattern_5_1: 730000 rects
+caravel_000710d6_fill_pattern_3_3: 490000 rects
+caravel_000710d6_fill_pattern_2_4: 3830000 rects
+caravel_000710d6_fill_pattern_5_1: 740000 rects
+caravel_000710d6_fill_pattern_1_5: 3260000 rects
+caravel_000710d6_fill_pattern_3_3: 500000 rects
+caravel_000710d6_fill_pattern_5_1: 750000 rects
+caravel_000710d6_fill_pattern_3_3: 510000 rects
+caravel_000710d6_fill_pattern_5_1: 760000 rects
+caravel_000710d6_fill_pattern_3_3: 520000 rects
+caravel_000710d6_fill_pattern_1_5: 3270000 rects
+caravel_000710d6_fill_pattern_5_1: 770000 rects
+caravel_000710d6_fill_pattern_3_3: 530000 rects
+caravel_000710d6_fill_pattern_3_3: 540000 rects
+caravel_000710d6_fill_pattern_2_4: 3840000 rects
+caravel_000710d6_fill_pattern_5_1: 780000 rects
+caravel_000710d6_fill_pattern_3_3: 550000 rects
+caravel_000710d6_fill_pattern_3_3: 560000 rects
+caravel_000710d6_fill_pattern_1_5: 3280000 rects
+caravel_000710d6_fill_pattern_3_3: 570000 rects
+caravel_000710d6_fill_pattern_5_1: 790000 rects
+caravel_000710d6_fill_pattern_3_3: 580000 rects
+caravel_000710d6_fill_pattern_3_3: 590000 rects
+caravel_000710d6_fill_pattern_5_1: 800000 rects
+caravel_000710d6_fill_pattern_1_5: 3290000 rects
+caravel_000710d6_fill_pattern_3_3: 600000 rects
+caravel_000710d6_fill_pattern_2_4: 3850000 rects
+caravel_000710d6_fill_pattern_3_3: 610000 rects
+caravel_000710d6_fill_pattern_5_1: 810000 rects
+caravel_000710d6_fill_pattern_3_3: 620000 rects
+caravel_000710d6_fill_pattern_5_1: 820000 rects
+caravel_000710d6_fill_pattern_3_3: 630000 rects
+caravel_000710d6_fill_pattern_1_5: 3300000 rects
+caravel_000710d6_fill_pattern_5_1: 830000 rects
+caravel_000710d6_fill_pattern_3_3: 640000 rects
+caravel_000710d6_fill_pattern_5_1: 840000 rects
+caravel_000710d6_fill_pattern_3_3: 650000 rects
+caravel_000710d6_fill_pattern_5_1: 850000 rects
+caravel_000710d6_fill_pattern_2_4: 3860000 rects
+caravel_000710d6_fill_pattern_1_5: 3310000 rects
+caravel_000710d6_fill_pattern_3_3: 660000 rects
+caravel_000710d6_fill_pattern_5_1: 860000 rects
+caravel_000710d6_fill_pattern_3_3: 670000 rects
+caravel_000710d6_fill_pattern_3_3: 680000 rects
+caravel_000710d6_fill_pattern_5_1: 870000 rects
+caravel_000710d6_fill_pattern_3_3: 690000 rects
+caravel_000710d6_fill_pattern_1_5: 3320000 rects
+caravel_000710d6_fill_pattern_3_3: 700000 rects
+caravel_000710d6_fill_pattern_5_1: 880000 rects
+caravel_000710d6_fill_pattern_2_4: 3870000 rects
+caravel_000710d6_fill_pattern_3_3: 710000 rects
+caravel_000710d6_fill_pattern_3_3: 720000 rects
+caravel_000710d6_fill_pattern_5_1: 890000 rects
+caravel_000710d6_fill_pattern_3_3: 730000 rects
+caravel_000710d6_fill_pattern_1_5: 3330000 rects
+caravel_000710d6_fill_pattern_5_1: 900000 rects
+caravel_000710d6_fill_pattern_3_3: 740000 rects
+caravel_000710d6_fill_pattern_5_1: 910000 rects
+caravel_000710d6_fill_pattern_3_3: 750000 rects
+caravel_000710d6_fill_pattern_5_1: 920000 rects
+caravel_000710d6_fill_pattern_3_3: 760000 rects
+caravel_000710d6_fill_pattern_2_4: 3880000 rects
+caravel_000710d6_fill_pattern_1_5: 3340000 rects
+caravel_000710d6_fill_pattern_3_3: 770000 rects
+caravel_000710d6_fill_pattern_5_1: 930000 rects
+caravel_000710d6_fill_pattern_3_3: 780000 rects
+caravel_000710d6_fill_pattern_3_3: 790000 rects
+caravel_000710d6_fill_pattern_5_1: 940000 rects
+caravel_000710d6_fill_pattern_3_3: 800000 rects
+caravel_000710d6_fill_pattern_1_5: 3350000 rects
+caravel_000710d6_fill_pattern_5_1: 950000 rects
+caravel_000710d6_fill_pattern_3_3: 810000 rects
+caravel_000710d6_fill_pattern_5_1: 960000 rects
+caravel_000710d6_fill_pattern_2_4: 3890000 rects
+caravel_000710d6_fill_pattern_3_3: 820000 rects
+caravel_000710d6_fill_pattern_3_3: 830000 rects
+caravel_000710d6_fill_pattern_3_3: 840000 rects
+caravel_000710d6_fill_pattern_1_5: 3360000 rects
+caravel_000710d6_fill_pattern_3_3: 850000 rects
+caravel_000710d6_fill_pattern_3_3: 860000 rects
+caravel_000710d6_fill_pattern_3_3: 870000 rects
+caravel_000710d6_fill_pattern_2_4: 3900000 rects
+caravel_000710d6_fill_pattern_3_3: 880000 rects
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+caravel_000710d6_fill_pattern_3_3: 890000 rects
+caravel_000710d6_fill_pattern_3_3: 900000 rects
+caravel_000710d6_fill_pattern_3_3: 910000 rects
+caravel_000710d6_fill_pattern_3_3: 920000 rects
+caravel_000710d6_fill_pattern_1_5: 3380000 rects
+caravel_000710d6_fill_pattern_2_4: 3910000 rects
+caravel_000710d6_fill_pattern_3_3: 930000 rects
+caravel_000710d6_fill_pattern_3_3: 940000 rects
+caravel_000710d6_fill_pattern_3_3: 950000 rects
+caravel_000710d6_fill_pattern_1_5: 3390000 rects
+caravel_000710d6_fill_pattern_3_3: 960000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_5_1
+caravel_000710d6_fill_pattern_3_3: 970000 rects
+caravel_000710d6_fill_pattern_3_3: 980000 rects
+caravel_000710d6_fill_pattern_2_4: 3920000 rects
+caravel_000710d6_fill_pattern_3_3: 990000 rects
+caravel_000710d6_fill_pattern_1_5: 3400000 rects
+caravel_000710d6_fill_pattern_3_3: 1000000 rects
+caravel_000710d6_fill_pattern_3_3: 1010000 rects
+caravel_000710d6_fill_pattern_3_3: 1020000 rects
+caravel_000710d6_fill_pattern_3_3: 1030000 rects
+caravel_000710d6_fill_pattern_1_5: 3410000 rects
+caravel_000710d6_fill_pattern_3_3: 1040000 rects
+caravel_000710d6_fill_pattern_2_4: 3930000 rects
+caravel_000710d6_fill_pattern_3_3: 1050000 rects
+caravel_000710d6_fill_pattern_3_3: 1060000 rects
+caravel_000710d6_fill_pattern_1_5: 3420000 rects
+caravel_000710d6_fill_pattern_3_3: 1070000 rects
+caravel_000710d6_fill_pattern_3_3: 1080000 rects
+caravel_000710d6_fill_pattern_3_3: 1090000 rects
+caravel_000710d6_fill_pattern_2_4: 3940000 rects
+caravel_000710d6_fill_pattern_3_3: 1100000 rects
+caravel_000710d6_fill_pattern_1_5: 3430000 rects
+caravel_000710d6_fill_pattern_3_3: 1110000 rects
+caravel_000710d6_fill_pattern_3_3: 1120000 rects
+caravel_000710d6_fill_pattern_3_3: 1130000 rects
+caravel_000710d6_fill_pattern_3_3: 1140000 rects
+caravel_000710d6_fill_pattern_1_5: 3440000 rects
+caravel_000710d6_fill_pattern_3_3: 1150000 rects
+caravel_000710d6_fill_pattern_2_4: 3950000 rects
+caravel_000710d6_fill_pattern_3_3: 1160000 rects
+Ended: 12/14/2022 12:07:00
+caravel_000710d6_fill_pattern_3_3: 1170000 rects
+caravel_000710d6_fill_pattern_3_3: 1180000 rects
+caravel_000710d6_fill_pattern_1_5: 3450000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_3_3: 1190000 rects
+caravel_000710d6_fill_pattern_3_3: 1200000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_2_4: 3960000 rects
+caravel_000710d6_fill_pattern_3_3: 1210000 rects
+caravel_000710d6_fill_pattern_3_3: 1220000 rects
+caravel_000710d6_fill_pattern_1_5: 3460000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_3_3: 1230000 rects
+caravel_000710d6_fill_pattern_3_3: 1240000 rects
+caravel_000710d6_fill_pattern_3_3: 1250000 rects
+caravel_000710d6_fill_pattern_1_5: 3470000 rects
+caravel_000710d6_fill_pattern_3_3: 1260000 rects
+caravel_000710d6_fill_pattern_3_3: 1270000 rects
+caravel_000710d6_fill_pattern_2_4: 3970000 rects
+caravel_000710d6_fill_pattern_3_3: 1280000 rects
+caravel_000710d6_fill_pattern_3_3: 1290000 rects
+caravel_000710d6_fill_pattern_1_5: 3480000 rects
+caravel_000710d6_fill_pattern_3_3: 1300000 rects
+caravel_000710d6_fill_pattern_3_3: 1310000 rects
+caravel_000710d6_fill_pattern_3_3: 1320000 rects
+caravel_000710d6_fill_pattern_1_5: 3490000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_2_4: 3980000 rects
+caravel_000710d6_fill_pattern_3_3: 1330000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_3_3: 1340000 rects
+caravel_000710d6_fill_pattern_0_2: 10000 rects
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+caravel_000710d6_fill_pattern_0_2: 100000 rects
+caravel_000710d6_fill_pattern_3_3: 1420000 rects
+caravel_000710d6_fill_pattern_0_2: 110000 rects
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+caravel_000710d6_fill_pattern_0_2: 120000 rects
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+caravel_000710d6_fill_pattern_0_2: 130000 rects
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+caravel_000710d6_fill_pattern_0_2: 140000 rects
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+caravel_000710d6_fill_pattern_0_2: 150000 rects
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+caravel_000710d6_fill_pattern_0_2: 210000 rects
+caravel_000710d6_fill_pattern_3_3: 1500000 rects
+caravel_000710d6_fill_pattern_0_2: 220000 rects
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+caravel_000710d6_fill_pattern_0_2: 240000 rects
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+caravel_000710d6_fill_pattern_0_2: 250000 rects
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+caravel_000710d6_fill_pattern_1_5: 3570000 rects
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+caravel_000710d6_fill_pattern_3_3: 1540000 rects
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+caravel_000710d6_fill_pattern_0_2: 390000 rects
+caravel_000710d6_fill_pattern_0_2: 400000 rects
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+caravel_000710d6_fill_pattern_0_2: 440000 rects
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+caravel_000710d6_fill_pattern_0_2: 1450000 rects
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+caravel_000710d6_fill_pattern_0_2: 1690000 rects
+caravel_000710d6_fill_pattern_3_3: 2800000 rects
+caravel_000710d6_fill_pattern_0_2: 1700000 rects
+caravel_000710d6_fill_pattern_2_4: 4420000 rects
+caravel_000710d6_fill_pattern_1_5: 4190000 rects
+caravel_000710d6_fill_pattern_0_2: 1710000 rects
+caravel_000710d6_fill_pattern_0_2: 1720000 rects
+caravel_000710d6_fill_pattern_3_3: 2810000 rects
+caravel_000710d6_fill_pattern_0_2: 1730000 rects
+caravel_000710d6_fill_pattern_0_2: 1740000 rects
+caravel_000710d6_fill_pattern_1_5: 4200000 rects
+caravel_000710d6_fill_pattern_2_4: 4430000 rects
+caravel_000710d6_fill_pattern_3_3: 2820000 rects
+caravel_000710d6_fill_pattern_0_2: 1750000 rects
+caravel_000710d6_fill_pattern_0_2: 1760000 rects
+Ended: 12/14/2022 12:07:09
+caravel_000710d6_fill_pattern_0_2: 1770000 rects
+caravel_000710d6_fill_pattern_3_3: 2830000 rects
+caravel_000710d6_fill_pattern_0_2: 1780000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_2: 1790000 rects
+caravel_000710d6_fill_pattern_1_5: 4210000 rects
+caravel_000710d6_fill_pattern_2_4: 4440000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_0_2: 1800000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_3_3: 2840000 rects
+caravel_000710d6_fill_pattern_0_2: 1810000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_2: 1820000 rects
+caravel_000710d6_fill_pattern_0_2: 1830000 rects
+caravel_000710d6_fill_pattern_3_3: 2850000 rects
+caravel_000710d6_fill_pattern_1_5: 4220000 rects
+caravel_000710d6_fill_pattern_0_2: 1840000 rects
+caravel_000710d6_fill_pattern_2_4: 4450000 rects
+caravel_000710d6_fill_pattern_0_2: 1850000 rects
+caravel_000710d6_fill_pattern_0_2: 1860000 rects
+caravel_000710d6_fill_pattern_3_3: 2860000 rects
+caravel_000710d6_fill_pattern_0_2: 1870000 rects
+caravel_000710d6_fill_pattern_1_5: 4230000 rects
+caravel_000710d6_fill_pattern_0_2: 1880000 rects
+caravel_000710d6_fill_pattern_2_4: 4460000 rects
+caravel_000710d6_fill_pattern_0_2: 1890000 rects
+caravel_000710d6_fill_pattern_3_3: 2870000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_2: 1900000 rects
+caravel_000710d6_fill_pattern_0_2: 1910000 rects
+caravel_000710d6_fill_pattern_2_0: 10000 rects
+caravel_000710d6_fill_pattern_0_2: 1920000 rects
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+caravel_000710d6_fill_pattern_2_0: 20000 rects
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+caravel_000710d6_fill_pattern_2_4: 4470000 rects
+caravel_000710d6_fill_pattern_2_0: 30000 rects
+caravel_000710d6_fill_pattern_0_2: 1940000 rects
+caravel_000710d6_fill_pattern_2_0: 40000 rects
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+caravel_000710d6_fill_pattern_0_2: 1950000 rects
+caravel_000710d6_fill_pattern_2_0: 50000 rects
+caravel_000710d6_fill_pattern_2_0: 60000 rects
+caravel_000710d6_fill_pattern_0_2: 1960000 rects
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+caravel_000710d6_fill_pattern_2_0: 90000 rects
+caravel_000710d6_fill_pattern_0_2: 1990000 rects
+caravel_000710d6_fill_pattern_2_0: 100000 rects
+caravel_000710d6_fill_pattern_0_2: 2000000 rects
+caravel_000710d6_fill_pattern_2_0: 110000 rects
+caravel_000710d6_fill_pattern_1_5: 4260000 rects
+caravel_000710d6_fill_pattern_3_3: 2910000 rects
+caravel_000710d6_fill_pattern_2_0: 120000 rects
+caravel_000710d6_fill_pattern_0_2: 2010000 rects
+caravel_000710d6_fill_pattern_2_0: 130000 rects
+caravel_000710d6_fill_pattern_0_2: 2020000 rects
+caravel_000710d6_fill_pattern_2_4: 4490000 rects
+caravel_000710d6_fill_pattern_2_0: 140000 rects
+caravel_000710d6_fill_pattern_3_3: 2920000 rects
+caravel_000710d6_fill_pattern_0_2: 2030000 rects
+caravel_000710d6_fill_pattern_2_0: 150000 rects
+caravel_000710d6_fill_pattern_0_2: 2040000 rects
+caravel_000710d6_fill_pattern_2_0: 160000 rects
+caravel_000710d6_fill_pattern_0_2: 2050000 rects
+caravel_000710d6_fill_pattern_1_5: 4270000 rects
+Ended: 12/14/2022 12:07:10
+caravel_000710d6_fill_pattern_3_3: 2930000 rects
+caravel_000710d6_fill_pattern_2_0: 170000 rects
+caravel_000710d6_fill_pattern_0_2: 2060000 rects
+caravel_000710d6_fill_pattern_2_0: 180000 rects
+caravel_000710d6_fill_pattern_2_4: 4500000 rects
+caravel_000710d6_fill_pattern_3_3: 2940000 rects
+caravel_000710d6_fill_pattern_1_5: 4280000 rects
+caravel_000710d6_fill_pattern_2_0: 190000 rects
+caravel_000710d6_fill_pattern_0_2: 2070000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_2: 2080000 rects
+caravel_000710d6_fill_pattern_2_0: 200000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+caravel_000710d6_fill_pattern_2_0: 210000 rects
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_2: 2090000 rects
+caravel_000710d6_fill_pattern_3_3: 2950000 rects
+caravel_000710d6_fill_pattern_0_2: 2100000 rects
+caravel_000710d6_fill_pattern_2_0: 220000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_4: 4510000 rects
+caravel_000710d6_fill_pattern_1_5: 4290000 rects
+caravel_000710d6_fill_pattern_0_2: 2110000 rects
+caravel_000710d6_fill_pattern_2_0: 230000 rects
+caravel_000710d6_fill_pattern_3_3: 2960000 rects
+caravel_000710d6_fill_pattern_0_2: 2120000 rects
+caravel_000710d6_fill_pattern_2_0: 240000 rects
+caravel_000710d6_fill_pattern_0_2: 2130000 rects
+caravel_000710d6_fill_pattern_2_0: 250000 rects
+caravel_000710d6_fill_pattern_0_2: 2140000 rects
+caravel_000710d6_fill_pattern_2_0: 260000 rects
+caravel_000710d6_fill_pattern_3_3: 2970000 rects
+caravel_000710d6_fill_pattern_0_2: 2150000 rects
+caravel_000710d6_fill_pattern_2_4: 4520000 rects
+caravel_000710d6_fill_pattern_2_0: 270000 rects
+caravel_000710d6_fill_pattern_0_2: 2160000 rects
+caravel_000710d6_fill_pattern_1_5: 4300000 rects
+caravel_000710d6_fill_pattern_2_0: 280000 rects
+caravel_000710d6_fill_pattern_0_2: 2170000 rects
+caravel_000710d6_fill_pattern_3_3: 2980000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_2_0: 290000 rects
+caravel_000710d6_fill_pattern_0_2: 2180000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_2_0: 300000 rects
+caravel_000710d6_fill_pattern_0_2: 2190000 rects
+caravel_000710d6_fill_pattern_0_2: 2200000 rects
+caravel_000710d6_fill_pattern_2_4: 4530000 rects
+caravel_000710d6_fill_pattern_2_0: 310000 rects
+caravel_000710d6_fill_pattern_1_1: 10000 rects
+caravel_000710d6_fill_pattern_3_3: 2990000 rects
+caravel_000710d6_fill_pattern_1_5: 4310000 rects
+caravel_000710d6_fill_pattern_1_1: 20000 rects
+caravel_000710d6_fill_pattern_0_2: 2210000 rects
+caravel_000710d6_fill_pattern_2_0: 320000 rects
+caravel_000710d6_fill_pattern_1_1: 30000 rects
+caravel_000710d6_fill_pattern_0_2: 2220000 rects
+caravel_000710d6_fill_pattern_2_0: 330000 rects
+caravel_000710d6_fill_pattern_1_1: 40000 rects
+caravel_000710d6_fill_pattern_0_2: 2230000 rects
+caravel_000710d6_fill_pattern_3_3: 3000000 rects
+caravel_000710d6_fill_pattern_2_0: 340000 rects
+caravel_000710d6_fill_pattern_1_1: 50000 rects
+caravel_000710d6_fill_pattern_1_1: 60000 rects
+caravel_000710d6_fill_pattern_2_0: 350000 rects
+caravel_000710d6_fill_pattern_0_2: 2240000 rects
+caravel_000710d6_fill_pattern_2_4: 4540000 rects
+caravel_000710d6_fill_pattern_1_5: 4320000 rects
+caravel_000710d6_fill_pattern_1_1: 70000 rects
+caravel_000710d6_fill_pattern_2_0: 360000 rects
+caravel_000710d6_fill_pattern_0_2: 2250000 rects
+caravel_000710d6_fill_pattern_1_1: 80000 rects
+caravel_000710d6_fill_pattern_3_3: 3010000 rects
+caravel_000710d6_fill_pattern_2_0: 370000 rects
+caravel_000710d6_fill_pattern_1_1: 90000 rects
+caravel_000710d6_fill_pattern_0_2: 2260000 rects
+caravel_000710d6_fill_pattern_1_1: 100000 rects
+caravel_000710d6_fill_pattern_2_0: 380000 rects
+caravel_000710d6_fill_pattern_0_2: 2270000 rects
+caravel_000710d6_fill_pattern_1_1: 110000 rects
+caravel_000710d6_fill_pattern_2_0: 390000 rects
+caravel_000710d6_fill_pattern_3_3: 3020000 rects
+caravel_000710d6_fill_pattern_2_4: 4550000 rects
+caravel_000710d6_fill_pattern_2_0: 400000 rects
+caravel_000710d6_fill_pattern_1_1: 120000 rects
+caravel_000710d6_fill_pattern_0_2: 2280000 rects
+caravel_000710d6_fill_pattern_1_5: 4330000 rects
+caravel_000710d6_fill_pattern_1_1: 130000 rects
+caravel_000710d6_fill_pattern_2_0: 410000 rects
+caravel_000710d6_fill_pattern_0_2: 2290000 rects
+caravel_000710d6_fill_pattern_3_3: 3030000 rects
+caravel_000710d6_fill_pattern_1_1: 140000 rects
+caravel_000710d6_fill_pattern_2_0: 420000 rects
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+caravel_000710d6_fill_pattern_1_1: 950000 rects
+Ended: 12/14/2022 12:07:15
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+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_000710d6_fill_pattern_2_0: 1360000 rects
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+Processing system .magicrc file
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+caravel_000710d6_fill_pattern_2_0: 1370000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+caravel_000710d6_fill_pattern_1_1: 1000000 rects
+caravel_000710d6_fill_pattern_2_0: 1380000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_000710d6_fill_pattern_1_1: 1080000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
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+caravel_000710d6_fill_pattern_2_0: 1450000 rects
+caravel_000710d6_fill_pattern_1_5: 4560000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_1_5: 6200000 rects
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+caravel_000710d6_fill_pattern_2_0: 3140000 rects
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+caravel_000710d6_fill_pattern_3_3: 5450000 rects
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+caravel_000710d6_fill_pattern_2_0: 3160000 rects
+caravel_000710d6_fill_pattern_2_4: 5820000 rects
+Ended: 12/14/2022 12:07:34
+caravel_000710d6_fill_pattern_2_0: 3170000 rects
+caravel_000710d6_fill_pattern_2_4: 5830000 rects
+caravel_000710d6_fill_pattern_1_5: 6210000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_1_1: 3250000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_2_4: 5840000 rects
+caravel_000710d6_fill_pattern_2_0: 3180000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_000710d6_fill_pattern_2_4: 5850000 rects
+caravel_000710d6_fill_pattern_2_0: 3190000 rects
+caravel_000710d6_fill_pattern_1_1: 3270000 rects
+caravel_000710d6_fill_pattern_2_4: 5860000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_000710d6_fill_pattern_2_0: 3200000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_2_4: 6230000 rects
+caravel_000710d6_fill_pattern_1_1: 3520000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_5_5
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+caravel_000710d6_fill_pattern_2_4: 6600000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_2_0: 3620000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_1_5
+caravel_000710d6_fill_pattern_3_3: 5580000 rects
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+caravel_000710d6_fill_pattern_1_1: 4100000 rects
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+caravel_000710d6_fill_pattern_2_0: 4150000 rects
+caravel_000710d6_fill_pattern_2_4: 7230000 rects
+Ended: 12/14/2022 12:07:48
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_4: 7240000 rects
+caravel_000710d6_fill_pattern_2_0: 4160000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_1_1: 4120000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_4: 7250000 rects
+caravel_000710d6_fill_pattern_2_0: 4170000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_3_3
+caravel_000710d6_fill_pattern_1_1: 4130000 rects
+caravel_000710d6_fill_pattern_2_4: 7260000 rects
+caravel_000710d6_fill_pattern_2_0: 4180000 rects
+caravel_000710d6_fill_pattern_2_4: 7270000 rects
+caravel_000710d6_fill_pattern_2_0: 4190000 rects
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+caravel_000710d6_fill_pattern_2_4: 7280000 rects
+caravel_000710d6_fill_pattern_2_0: 4200000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_3_7: 20000 rects
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+caravel_000710d6_fill_pattern_2_4: 8230000 rects
+caravel_000710d6_fill_pattern_1_1: 5180000 rects
+caravel_000710d6_fill_pattern_2_4: 8240000 rects
+caravel_000710d6_fill_pattern_2_4: 8250000 rects
+caravel_000710d6_fill_pattern_2_4: 8260000 rects
+caravel_000710d6_fill_pattern_1_1: 5190000 rects
+caravel_000710d6_fill_pattern_2_0: 5620000 rects
+caravel_000710d6_fill_pattern_2_4: 8270000 rects
+caravel_000710d6_fill_pattern_2_4: 8280000 rects
+caravel_000710d6_fill_pattern_2_4: 8290000 rects
+caravel_000710d6_fill_pattern_2_4: 8300000 rects
+caravel_000710d6_fill_pattern_1_1: 5200000 rects
+caravel_000710d6_fill_pattern_2_4: 8310000 rects
+caravel_000710d6_fill_pattern_1_1: 5210000 rects
+caravel_000710d6_fill_pattern_2_0: 5630000 rects
+caravel_000710d6_fill_pattern_1_1: 5220000 rects
+caravel_000710d6_fill_pattern_1_1: 5230000 rects
+caravel_000710d6_fill_pattern_2_4: 8320000 rects
+caravel_000710d6_fill_pattern_2_0: 5640000 rects
+caravel_000710d6_fill_pattern_1_1: 5240000 rects
+caravel_000710d6_fill_pattern_1_1: 5250000 rects
+caravel_000710d6_fill_pattern_1_1: 5260000 rects
+caravel_000710d6_fill_pattern_2_0: 5650000 rects
+caravel_000710d6_fill_pattern_1_1: 5270000 rects
+caravel_000710d6_fill_pattern_1_1: 5280000 rects
+caravel_000710d6_fill_pattern_2_0: 5660000 rects
+caravel_000710d6_fill_pattern_1_1: 5290000 rects
+caravel_000710d6_fill_pattern_2_4: 8330000 rects
+caravel_000710d6_fill_pattern_1_1: 5300000 rects
+caravel_000710d6_fill_pattern_1_1: 5310000 rects
+caravel_000710d6_fill_pattern_2_0: 5670000 rects
+caravel_000710d6_fill_pattern_1_1: 5320000 rects
+caravel_000710d6_fill_pattern_1_1: 5330000 rects
+caravel_000710d6_fill_pattern_1_1: 5340000 rects
+caravel_000710d6_fill_pattern_2_0: 5680000 rects
+caravel_000710d6_fill_pattern_1_1: 5350000 rects
+caravel_000710d6_fill_pattern_1_1: 5360000 rects
+caravel_000710d6_fill_pattern_2_4: 8340000 rects
+caravel_000710d6_fill_pattern_2_0: 5690000 rects
+caravel_000710d6_fill_pattern_1_1: 5370000 rects
+caravel_000710d6_fill_pattern_1_1: 5380000 rects
+caravel_000710d6_fill_pattern_1_1: 5390000 rects
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+caravel_000710d6_fill_pattern_1_1: 5400000 rects
+caravel_000710d6_fill_pattern_1_1: 5410000 rects
+caravel_000710d6_fill_pattern_2_0: 5710000 rects
+caravel_000710d6_fill_pattern_1_1: 5420000 rects
+caravel_000710d6_fill_pattern_2_4: 8350000 rects
+caravel_000710d6_fill_pattern_1_1: 5430000 rects
+caravel_000710d6_fill_pattern_2_0: 5720000 rects
+caravel_000710d6_fill_pattern_1_1: 5440000 rects
+caravel_000710d6_fill_pattern_1_1: 5450000 rects
+caravel_000710d6_fill_pattern_1_1: 5460000 rects
+caravel_000710d6_fill_pattern_2_0: 5730000 rects
+caravel_000710d6_fill_pattern_1_1: 5470000 rects
+caravel_000710d6_fill_pattern_1_1: 5480000 rects
+caravel_000710d6_fill_pattern_2_0: 5740000 rects
+caravel_000710d6_fill_pattern_1_1: 5490000 rects
+caravel_000710d6_fill_pattern_1_1: 5500000 rects
+caravel_000710d6_fill_pattern_2_0: 5750000 rects
+caravel_000710d6_fill_pattern_1_1: 5510000 rects
+caravel_000710d6_fill_pattern_2_0: 5760000 rects
+caravel_000710d6_fill_pattern_1_1: 5520000 rects
+caravel_000710d6_fill_pattern_2_0: 5770000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_2_4
+caravel_000710d6_fill_pattern_1_1: 5530000 rects
+caravel_000710d6_fill_pattern_2_0: 5780000 rects
+caravel_000710d6_fill_pattern_1_1: 5540000 rects
+caravel_000710d6_fill_pattern_2_0: 5790000 rects
+caravel_000710d6_fill_pattern_1_1: 5550000 rects
+caravel_000710d6_fill_pattern_2_0: 5800000 rects
+caravel_000710d6_fill_pattern_2_0: 5810000 rects
+caravel_000710d6_fill_pattern_1_1: 5560000 rects
+caravel_000710d6_fill_pattern_1_1: 5570000 rects
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+caravel_000710d6_fill_pattern_2_0: 5830000 rects
+caravel_000710d6_fill_pattern_1_1: 5580000 rects
+caravel_000710d6_fill_pattern_2_0: 5840000 rects
+caravel_000710d6_fill_pattern_1_1: 5590000 rects
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+caravel_000710d6_fill_pattern_2_0: 5860000 rects
+caravel_000710d6_fill_pattern_2_0: 5870000 rects
+caravel_000710d6_fill_pattern_1_1: 5600000 rects
+caravel_000710d6_fill_pattern_2_0: 5880000 rects
+caravel_000710d6_fill_pattern_2_0: 5890000 rects
+caravel_000710d6_fill_pattern_2_0: 5900000 rects
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+caravel_000710d6_fill_pattern_1_1: 5710000 rects
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+caravel_000710d6_fill_pattern_2_0: 6110000 rects
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+caravel_000710d6_fill_pattern_2_0: 6150000 rects
+caravel_000710d6_fill_pattern_2_0: 6160000 rects
+caravel_000710d6_fill_pattern_2_0: 6170000 rects
+caravel_000710d6_fill_pattern_1_1: 5820000 rects
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+caravel_000710d6_fill_pattern_1_1: 5830000 rects
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+caravel_000710d6_fill_pattern_2_0: 6200000 rects
+caravel_000710d6_fill_pattern_1_1: 5840000 rects
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+caravel_000710d6_fill_pattern_2_0: 6220000 rects
+caravel_000710d6_fill_pattern_2_0: 6230000 rects
+caravel_000710d6_fill_pattern_1_1: 5850000 rects
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+caravel_000710d6_fill_pattern_2_0: 6250000 rects
+caravel_000710d6_fill_pattern_2_0: 6260000 rects
+caravel_000710d6_fill_pattern_2_0: 6270000 rects
+caravel_000710d6_fill_pattern_1_1: 5860000 rects
+caravel_000710d6_fill_pattern_2_0: 6280000 rects
+caravel_000710d6_fill_pattern_1_1: 5870000 rects
+caravel_000710d6_fill_pattern_1_1: 5880000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_2_0
+caravel_000710d6_fill_pattern_1_1: 5890000 rects
+caravel_000710d6_fill_pattern_1_1: 5900000 rects
+caravel_000710d6_fill_pattern_1_1: 5910000 rects
+caravel_000710d6_fill_pattern_1_1: 5920000 rects
+caravel_000710d6_fill_pattern_1_1: 5930000 rects
+caravel_000710d6_fill_pattern_1_1: 5940000 rects
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+caravel_000710d6_fill_pattern_1_1: 5980000 rects
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+caravel_000710d6_fill_pattern_1_1: 6030000 rects
+caravel_000710d6_fill_pattern_1_1: 6040000 rects
+caravel_000710d6_fill_pattern_1_1: 6050000 rects
+caravel_000710d6_fill_pattern_1_1: 6060000 rects
+caravel_000710d6_fill_pattern_1_1: 6070000 rects
+caravel_000710d6_fill_pattern_1_1: 6080000 rects
+caravel_000710d6_fill_pattern_1_1: 6090000 rects
+caravel_000710d6_fill_pattern_1_1: 6100000 rects
+caravel_000710d6_fill_pattern_1_1: 6110000 rects
+caravel_000710d6_fill_pattern_1_1: 6120000 rects
+caravel_000710d6_fill_pattern_1_1: 6130000 rects
+caravel_000710d6_fill_pattern_1_1: 6140000 rects
+caravel_000710d6_fill_pattern_1_1: 6150000 rects
+caravel_000710d6_fill_pattern_1_1: 6160000 rects
+caravel_000710d6_fill_pattern_1_1: 6170000 rects
+caravel_000710d6_fill_pattern_1_1: 6180000 rects
+caravel_000710d6_fill_pattern_1_1: 6190000 rects
+caravel_000710d6_fill_pattern_1_1: 6200000 rects
+caravel_000710d6_fill_pattern_1_1: 6210000 rects
+caravel_000710d6_fill_pattern_1_1: 6220000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_1_1
+Ended: 12/14/2022 12:08:34
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_0: 10000 rects
+caravel_000710d6_fill_pattern_0_0: 20000 rects
+caravel_000710d6_fill_pattern_0_0: 30000 rects
+caravel_000710d6_fill_pattern_0_0: 40000 rects
+caravel_000710d6_fill_pattern_0_0: 50000 rects
+caravel_000710d6_fill_pattern_0_0: 60000 rects
+caravel_000710d6_fill_pattern_0_0: 70000 rects
+caravel_000710d6_fill_pattern_0_0: 80000 rects
+caravel_000710d6_fill_pattern_0_0: 90000 rects
+caravel_000710d6_fill_pattern_0_0: 100000 rects
+caravel_000710d6_fill_pattern_0_0: 110000 rects
+caravel_000710d6_fill_pattern_0_0: 120000 rects
+caravel_000710d6_fill_pattern_0_0: 130000 rects
+caravel_000710d6_fill_pattern_0_0: 140000 rects
+caravel_000710d6_fill_pattern_0_0: 150000 rects
+caravel_000710d6_fill_pattern_0_0: 160000 rects
+caravel_000710d6_fill_pattern_0_0: 170000 rects
+caravel_000710d6_fill_pattern_0_0: 180000 rects
+caravel_000710d6_fill_pattern_0_0: 190000 rects
+caravel_000710d6_fill_pattern_0_0: 200000 rects
+caravel_000710d6_fill_pattern_0_0: 210000 rects
+caravel_000710d6_fill_pattern_0_0: 220000 rects
+caravel_000710d6_fill_pattern_0_0: 230000 rects
+caravel_000710d6_fill_pattern_0_0: 240000 rects
+caravel_000710d6_fill_pattern_0_0: 250000 rects
+caravel_000710d6_fill_pattern_0_0: 260000 rects
+caravel_000710d6_fill_pattern_0_0: 270000 rects
+caravel_000710d6_fill_pattern_0_0: 280000 rects
+caravel_000710d6_fill_pattern_0_0: 290000 rects
+caravel_000710d6_fill_pattern_0_0: 300000 rects
+caravel_000710d6_fill_pattern_0_0: 310000 rects
+caravel_000710d6_fill_pattern_0_0: 320000 rects
+caravel_000710d6_fill_pattern_0_0: 330000 rects
+caravel_000710d6_fill_pattern_0_0: 340000 rects
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+caravel_000710d6_fill_pattern_0_0: 520000 rects
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+caravel_000710d6_fill_pattern_0_0: 540000 rects
+caravel_000710d6_fill_pattern_0_0: 550000 rects
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+caravel_000710d6_fill_pattern_0_0: 570000 rects
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+caravel_000710d6_fill_pattern_0_0: 750000 rects
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+caravel_000710d6_fill_pattern_0_0: 780000 rects
+caravel_000710d6_fill_pattern_0_0: 790000 rects
+caravel_000710d6_fill_pattern_0_0: 800000 rects
+caravel_000710d6_fill_pattern_0_0: 810000 rects
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+caravel_000710d6_fill_pattern_0_0: 830000 rects
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+caravel_000710d6_fill_pattern_0_0: 850000 rects
+caravel_000710d6_fill_pattern_0_0: 860000 rects
+caravel_000710d6_fill_pattern_0_0: 870000 rects
+caravel_000710d6_fill_pattern_0_0: 880000 rects
+caravel_000710d6_fill_pattern_0_0: 890000 rects
+caravel_000710d6_fill_pattern_0_0: 900000 rects
+caravel_000710d6_fill_pattern_0_0: 910000 rects
+caravel_000710d6_fill_pattern_0_0: 920000 rects
+caravel_000710d6_fill_pattern_0_0: 930000 rects
+caravel_000710d6_fill_pattern_0_0: 940000 rects
+caravel_000710d6_fill_pattern_0_0: 950000 rects
+caravel_000710d6_fill_pattern_0_0: 960000 rects
+caravel_000710d6_fill_pattern_0_0: 970000 rects
+caravel_000710d6_fill_pattern_0_0: 980000 rects
+caravel_000710d6_fill_pattern_0_0: 990000 rects
+caravel_000710d6_fill_pattern_0_0: 1000000 rects
+caravel_000710d6_fill_pattern_0_0: 1010000 rects
+caravel_000710d6_fill_pattern_0_0: 1020000 rects
+caravel_000710d6_fill_pattern_0_0: 1030000 rects
+caravel_000710d6_fill_pattern_0_0: 1040000 rects
+caravel_000710d6_fill_pattern_0_0: 1050000 rects
+caravel_000710d6_fill_pattern_0_0: 1060000 rects
+caravel_000710d6_fill_pattern_0_0: 1070000 rects
+caravel_000710d6_fill_pattern_0_0: 1080000 rects
+Ended: 12/14/2022 12:08:39
+caravel_000710d6_fill_pattern_0_0: 1090000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_0: 1100000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_0_0: 1110000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_0: 1120000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_0: 1130000 rects
+caravel_000710d6_fill_pattern_0_0: 1140000 rects
+caravel_000710d6_fill_pattern_0_0: 1150000 rects
+caravel_000710d6_fill_pattern_0_0: 1160000 rects
+caravel_000710d6_fill_pattern_0_0: 1170000 rects
+caravel_000710d6_fill_pattern_0_0: 1180000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_0: 1190000 rects
+caravel_000710d6_fill_pattern_0_0: 1200000 rects
+caravel_000710d6_fill_pattern_4_4: 10000 rects
+caravel_000710d6_fill_pattern_4_4: 20000 rects
+caravel_000710d6_fill_pattern_0_0: 1210000 rects
+caravel_000710d6_fill_pattern_4_4: 30000 rects
+caravel_000710d6_fill_pattern_0_0: 1220000 rects
+caravel_000710d6_fill_pattern_4_4: 40000 rects
+caravel_000710d6_fill_pattern_4_4: 50000 rects
+caravel_000710d6_fill_pattern_0_0: 1230000 rects
+caravel_000710d6_fill_pattern_4_4: 60000 rects
+caravel_000710d6_fill_pattern_0_0: 1240000 rects
+caravel_000710d6_fill_pattern_4_4: 70000 rects
+caravel_000710d6_fill_pattern_4_4: 80000 rects
+caravel_000710d6_fill_pattern_0_0: 1250000 rects
+caravel_000710d6_fill_pattern_4_4: 90000 rects
+caravel_000710d6_fill_pattern_0_0: 1260000 rects
+caravel_000710d6_fill_pattern_4_4: 100000 rects
+caravel_000710d6_fill_pattern_4_4: 110000 rects
+caravel_000710d6_fill_pattern_0_0: 1270000 rects
+caravel_000710d6_fill_pattern_4_4: 120000 rects
+caravel_000710d6_fill_pattern_0_0: 1280000 rects
+caravel_000710d6_fill_pattern_4_4: 130000 rects
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+caravel_000710d6_fill_pattern_0_0: 2930000 rects
+caravel_000710d6_fill_pattern_4_4: 2630000 rects
+Ended: 12/14/2022 12:08:56
+caravel_000710d6_fill_pattern_0_0: 2940000 rects
+caravel_000710d6_fill_pattern_4_4: 2640000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_4_4: 2650000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_0: 2950000 rects
+caravel_000710d6_fill_pattern_4_4: 2660000 rects
+caravel_000710d6_fill_pattern_0_0: 2960000 rects
+caravel_000710d6_fill_pattern_4_4: 2670000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_000710d6_fill_pattern_2_6: 1590000 rects
+caravel_000710d6_fill_pattern_0_0: 3380000 rects
+Ended: 12/14/2022 12:09:03
+caravel_000710d6_fill_pattern_4_4: 3400000 rects
+caravel_000710d6_fill_pattern_2_6: 1600000 rects
+caravel_000710d6_fill_pattern_2_6: 1610000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_6: 1620000 rects
+caravel_000710d6_fill_pattern_4_4: 3410000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_0_0: 3390000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_2_6: 1630000 rects
+caravel_000710d6_fill_pattern_2_6: 1640000 rects
+caravel_000710d6_fill_pattern_4_4: 3420000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_6: 1650000 rects
+caravel_000710d6_fill_pattern_2_6: 1660000 rects
+caravel_000710d6_fill_pattern_0_0: 3400000 rects
+caravel_000710d6_fill_pattern_4_4: 3430000 rects
+caravel_000710d6_fill_pattern_2_6: 1670000 rects
+caravel_000710d6_fill_pattern_2_6: 1680000 rects
+caravel_000710d6_fill_pattern_4_4: 3440000 rects
+caravel_000710d6_fill_pattern_2_6: 1690000 rects
+caravel_000710d6_fill_pattern_0_0: 3410000 rects
+caravel_000710d6_fill_pattern_4_4: 3450000 rects
+caravel_000710d6_fill_pattern_2_6: 1700000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_4_4: 3460000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_000710d6_fill_pattern_2_6: 1710000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_0: 3420000 rects
+caravel_000710d6_fill_pattern_5_3: 10000 rects
+caravel_000710d6_fill_pattern_4_4: 3470000 rects
+caravel_000710d6_fill_pattern_2_6: 1720000 rects
+caravel_000710d6_fill_pattern_5_3: 20000 rects
+caravel_000710d6_fill_pattern_5_3: 30000 rects
+caravel_000710d6_fill_pattern_5_3: 40000 rects
+caravel_000710d6_fill_pattern_0_0: 3430000 rects
+caravel_000710d6_fill_pattern_4_4: 3480000 rects
+caravel_000710d6_fill_pattern_2_6: 1730000 rects
+caravel_000710d6_fill_pattern_5_3: 50000 rects
+caravel_000710d6_fill_pattern_5_3: 60000 rects
+caravel_000710d6_fill_pattern_2_6: 1740000 rects
+caravel_000710d6_fill_pattern_4_4: 3490000 rects
+caravel_000710d6_fill_pattern_5_3: 70000 rects
+caravel_000710d6_fill_pattern_0_0: 3440000 rects
+caravel_000710d6_fill_pattern_5_3: 80000 rects
+caravel_000710d6_fill_pattern_2_6: 1750000 rects
+caravel_000710d6_fill_pattern_4_4: 3500000 rects
+caravel_000710d6_fill_pattern_5_3: 90000 rects
+caravel_000710d6_fill_pattern_2_6: 1760000 rects
+caravel_000710d6_fill_pattern_5_3: 100000 rects
+caravel_000710d6_fill_pattern_0_0: 3450000 rects
+caravel_000710d6_fill_pattern_4_4: 3510000 rects
+caravel_000710d6_fill_pattern_2_6: 1770000 rects
+caravel_000710d6_fill_pattern_5_3: 110000 rects
+caravel_000710d6_fill_pattern_0_0: 3460000 rects
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+caravel_000710d6_fill_pattern_2_6: 1780000 rects
+caravel_000710d6_fill_pattern_5_3: 120000 rects
+caravel_000710d6_fill_pattern_0_0: 3470000 rects
+caravel_000710d6_fill_pattern_2_6: 1790000 rects
+caravel_000710d6_fill_pattern_5_3: 130000 rects
+caravel_000710d6_fill_pattern_4_4: 3530000 rects
+caravel_000710d6_fill_pattern_0_0: 3480000 rects
+caravel_000710d6_fill_pattern_5_3: 140000 rects
+caravel_000710d6_fill_pattern_2_6: 1800000 rects
+caravel_000710d6_fill_pattern_5_3: 150000 rects
+caravel_000710d6_fill_pattern_4_4: 3540000 rects
+caravel_000710d6_fill_pattern_2_6: 1810000 rects
+caravel_000710d6_fill_pattern_0_0: 3490000 rects
+caravel_000710d6_fill_pattern_5_3: 160000 rects
+caravel_000710d6_fill_pattern_5_3: 170000 rects
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+caravel_000710d6_fill_pattern_0_0: 3500000 rects
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+caravel_000710d6_fill_pattern_5_3: 190000 rects
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+caravel_000710d6_fill_pattern_2_6: 1850000 rects
+caravel_000710d6_fill_pattern_5_3: 200000 rects
+caravel_000710d6_fill_pattern_0_0: 3520000 rects
+caravel_000710d6_fill_pattern_5_3: 210000 rects
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+caravel_000710d6_fill_pattern_0_0: 3530000 rects
+caravel_000710d6_fill_pattern_2_6: 1870000 rects
+caravel_000710d6_fill_pattern_0_0: 3540000 rects
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+caravel_000710d6_fill_pattern_0_0: 3550000 rects
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+caravel_000710d6_fill_pattern_5_3: 230000 rects
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+caravel_000710d6_fill_pattern_0_0: 3570000 rects
+caravel_000710d6_fill_pattern_2_6: 1910000 rects
+caravel_000710d6_fill_pattern_0_0: 3580000 rects
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+caravel_000710d6_fill_pattern_0_0: 3600000 rects
+caravel_000710d6_fill_pattern_5_3: 250000 rects
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+caravel_000710d6_fill_pattern_0_0: 3640000 rects
+caravel_000710d6_fill_pattern_2_6: 1970000 rects
+caravel_000710d6_fill_pattern_4_4: 3560000 rects
+caravel_000710d6_fill_pattern_0_0: 3650000 rects
+caravel_000710d6_fill_pattern_5_3: 280000 rects
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+caravel_000710d6_fill_pattern_0_0: 3660000 rects
+caravel_000710d6_fill_pattern_2_6: 1990000 rects
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+caravel_000710d6_fill_pattern_0_0: 3680000 rects
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+caravel_000710d6_fill_pattern_0_0: 3710000 rects
+caravel_000710d6_fill_pattern_5_3: 350000 rects
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+caravel_000710d6_fill_pattern_5_3: 360000 rects
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+caravel_000710d6_fill_pattern_5_3: 370000 rects
+caravel_000710d6_fill_pattern_2_6: 2060000 rects
+caravel_000710d6_fill_pattern_0_0: 3730000 rects
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+caravel_000710d6_fill_pattern_4_4: 3570000 rects
+caravel_000710d6_fill_pattern_2_6: 2070000 rects
+caravel_000710d6_fill_pattern_0_0: 3740000 rects
+caravel_000710d6_fill_pattern_5_3: 390000 rects
+caravel_000710d6_fill_pattern_0_0: 3750000 rects
+caravel_000710d6_fill_pattern_2_6: 2080000 rects
+caravel_000710d6_fill_pattern_0_0: 3760000 rects
+caravel_000710d6_fill_pattern_5_3: 400000 rects
+caravel_000710d6_fill_pattern_2_6: 2090000 rects
+caravel_000710d6_fill_pattern_0_0: 3770000 rects
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+caravel_000710d6_fill_pattern_0_0: 3780000 rects
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+caravel_000710d6_fill_pattern_5_3: 440000 rects
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+caravel_000710d6_fill_pattern_0_0: 3800000 rects
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+caravel_000710d6_fill_pattern_0_0: 3860000 rects
+caravel_000710d6_fill_pattern_5_3: 520000 rects
+caravel_000710d6_fill_pattern_0_0: 3870000 rects
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+caravel_000710d6_fill_pattern_5_3: 560000 rects
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+caravel_000710d6_fill_pattern_0_0: 3910000 rects
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+caravel_000710d6_fill_pattern_2_6: 2220000 rects
+caravel_000710d6_fill_pattern_0_0: 3920000 rects
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+caravel_000710d6_fill_pattern_0_0: 3930000 rects
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+caravel_000710d6_fill_pattern_4_4: 3600000 rects
+caravel_000710d6_fill_pattern_5_3: 600000 rects
+caravel_000710d6_fill_pattern_2_6: 2250000 rects
+caravel_000710d6_fill_pattern_0_0: 3940000 rects
+caravel_000710d6_fill_pattern_5_3: 610000 rects
+caravel_000710d6_fill_pattern_2_6: 2260000 rects
+caravel_000710d6_fill_pattern_0_0: 3950000 rects
+caravel_000710d6_fill_pattern_5_3: 620000 rects
+caravel_000710d6_fill_pattern_2_6: 2270000 rects
+caravel_000710d6_fill_pattern_5_3: 630000 rects
+caravel_000710d6_fill_pattern_0_0: 3960000 rects
+caravel_000710d6_fill_pattern_2_6: 2280000 rects
+caravel_000710d6_fill_pattern_2_6: 2290000 rects
+caravel_000710d6_fill_pattern_2_6: 2300000 rects
+caravel_000710d6_fill_pattern_2_6: 2310000 rects
+caravel_000710d6_fill_pattern_2_6: 2320000 rects
+caravel_000710d6_fill_pattern_2_6: 2330000 rects
+caravel_000710d6_fill_pattern_2_6: 2340000 rects
+caravel_000710d6_fill_pattern_2_6: 2350000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_5_3
+caravel_000710d6_fill_pattern_2_6: 2360000 rects
+caravel_000710d6_fill_pattern_2_6: 2370000 rects
+caravel_000710d6_fill_pattern_2_6: 2380000 rects
+caravel_000710d6_fill_pattern_2_6: 2390000 rects
+caravel_000710d6_fill_pattern_2_6: 2400000 rects
+caravel_000710d6_fill_pattern_4_4: 3610000 rects
+caravel_000710d6_fill_pattern_2_6: 2410000 rects
+caravel_000710d6_fill_pattern_2_6: 2420000 rects
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+caravel_000710d6_fill_pattern_2_6: 2490000 rects
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+caravel_000710d6_fill_pattern_2_6: 2510000 rects
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+caravel_000710d6_fill_pattern_2_6: 2520000 rects
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+caravel_000710d6_fill_pattern_0_0: 3990000 rects
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+caravel_000710d6_fill_pattern_2_6: 2570000 rects
+caravel_000710d6_fill_pattern_0_0: 4010000 rects
+caravel_000710d6_fill_pattern_2_6: 2580000 rects
+caravel_000710d6_fill_pattern_4_4: 3720000 rects
+caravel_000710d6_fill_pattern_2_6: 2590000 rects
+caravel_000710d6_fill_pattern_0_0: 4020000 rects
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+caravel_000710d6_fill_pattern_2_6: 2610000 rects
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+caravel_000710d6_fill_pattern_4_4: 3770000 rects
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+caravel_000710d6_fill_pattern_0_0: 4050000 rects
+caravel_000710d6_fill_pattern_4_4: 3780000 rects
+caravel_000710d6_fill_pattern_4_4: 3790000 rects
+caravel_000710d6_fill_pattern_0_0: 4060000 rects
+caravel_000710d6_fill_pattern_4_4: 3800000 rects
+caravel_000710d6_fill_pattern_4_4: 3810000 rects
+caravel_000710d6_fill_pattern_2_6: 2630000 rects
+caravel_000710d6_fill_pattern_0_0: 4070000 rects
+caravel_000710d6_fill_pattern_4_4: 3820000 rects
+caravel_000710d6_fill_pattern_4_4: 3830000 rects
+caravel_000710d6_fill_pattern_4_4: 3840000 rects
+caravel_000710d6_fill_pattern_0_0: 4080000 rects
+caravel_000710d6_fill_pattern_4_4: 3850000 rects
+caravel_000710d6_fill_pattern_2_6: 2640000 rects
+caravel_000710d6_fill_pattern_4_4: 3860000 rects
+caravel_000710d6_fill_pattern_0_0: 4090000 rects
+caravel_000710d6_fill_pattern_4_4: 3870000 rects
+caravel_000710d6_fill_pattern_4_4: 3880000 rects
+caravel_000710d6_fill_pattern_0_0: 4100000 rects
+caravel_000710d6_fill_pattern_4_4: 3890000 rects
+caravel_000710d6_fill_pattern_4_4: 3900000 rects
+caravel_000710d6_fill_pattern_2_6: 2650000 rects
+caravel_000710d6_fill_pattern_0_0: 4110000 rects
+caravel_000710d6_fill_pattern_4_4: 3910000 rects
+caravel_000710d6_fill_pattern_0_0: 4120000 rects
+caravel_000710d6_fill_pattern_0_0: 4130000 rects
+Ended: 12/14/2022 12:09:09
+caravel_000710d6_fill_pattern_0_0: 4140000 rects
+caravel_000710d6_fill_pattern_2_6: 2660000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_4_4: 3920000 rects
+caravel_000710d6_fill_pattern_0_0: 4150000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_0: 4160000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_6: 2670000 rects
+caravel_000710d6_fill_pattern_4_4: 3930000 rects
+caravel_000710d6_fill_pattern_0_0: 4170000 rects
+caravel_000710d6_fill_pattern_0_0: 4180000 rects
+caravel_000710d6_fill_pattern_2_6: 2680000 rects
+caravel_000710d6_fill_pattern_0_0: 4190000 rects
+caravel_000710d6_fill_pattern_4_4: 3940000 rects
+caravel_000710d6_fill_pattern_0_0: 4200000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_2_6: 2690000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_0: 4210000 rects
+caravel_000710d6_fill_pattern_1_7: 10000 rects
+caravel_000710d6_fill_pattern_4_4: 3950000 rects
+caravel_000710d6_fill_pattern_1_7: 20000 rects
+caravel_000710d6_fill_pattern_0_0: 4220000 rects
+caravel_000710d6_fill_pattern_1_7: 30000 rects
+caravel_000710d6_fill_pattern_2_6: 2700000 rects
+caravel_000710d6_fill_pattern_1_7: 40000 rects
+caravel_000710d6_fill_pattern_0_0: 4230000 rects
+caravel_000710d6_fill_pattern_1_7: 50000 rects
+caravel_000710d6_fill_pattern_4_4: 3960000 rects
+caravel_000710d6_fill_pattern_1_7: 60000 rects
+caravel_000710d6_fill_pattern_0_0: 4240000 rects
+caravel_000710d6_fill_pattern_1_7: 70000 rects
+caravel_000710d6_fill_pattern_1_7: 80000 rects
+caravel_000710d6_fill_pattern_1_7: 90000 rects
+caravel_000710d6_fill_pattern_0_0: 4250000 rects
+caravel_000710d6_fill_pattern_1_7: 100000 rects
+caravel_000710d6_fill_pattern_4_4: 3970000 rects
+caravel_000710d6_fill_pattern_2_6: 2710000 rects
+caravel_000710d6_fill_pattern_1_7: 110000 rects
+caravel_000710d6_fill_pattern_0_0: 4260000 rects
+caravel_000710d6_fill_pattern_1_7: 120000 rects
+caravel_000710d6_fill_pattern_1_7: 130000 rects
+caravel_000710d6_fill_pattern_1_7: 140000 rects
+caravel_000710d6_fill_pattern_0_0: 4270000 rects
+caravel_000710d6_fill_pattern_4_4: 3980000 rects
+caravel_000710d6_fill_pattern_1_7: 150000 rects
+caravel_000710d6_fill_pattern_2_6: 2720000 rects
+caravel_000710d6_fill_pattern_1_7: 160000 rects
+caravel_000710d6_fill_pattern_0_0: 4280000 rects
+caravel_000710d6_fill_pattern_1_7: 170000 rects
+caravel_000710d6_fill_pattern_1_7: 180000 rects
+caravel_000710d6_fill_pattern_0_0: 4290000 rects
+caravel_000710d6_fill_pattern_4_4: 3990000 rects
+caravel_000710d6_fill_pattern_1_7: 190000 rects
+caravel_000710d6_fill_pattern_2_6: 2730000 rects
+caravel_000710d6_fill_pattern_1_7: 200000 rects
+caravel_000710d6_fill_pattern_0_0: 4300000 rects
+caravel_000710d6_fill_pattern_1_7: 210000 rects
+caravel_000710d6_fill_pattern_1_7: 220000 rects
+Ended: 12/14/2022 12:09:10
+caravel_000710d6_fill_pattern_0_0: 4310000 rects
+caravel_000710d6_fill_pattern_1_7: 230000 rects
+caravel_000710d6_fill_pattern_2_6: 2740000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_1_7: 240000 rects
+caravel_000710d6_fill_pattern_0_0: 4320000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_1_7: 250000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_0: 4330000 rects
+caravel_000710d6_fill_pattern_1_7: 260000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_6: 2750000 rects
+caravel_000710d6_fill_pattern_0_0: 4340000 rects
+caravel_000710d6_fill_pattern_1_7: 270000 rects
+caravel_000710d6_fill_pattern_1_7: 280000 rects
+caravel_000710d6_fill_pattern_0_0: 4350000 rects
+caravel_000710d6_fill_pattern_1_7: 290000 rects
+caravel_000710d6_fill_pattern_2_6: 2760000 rects
+caravel_000710d6_fill_pattern_1_7: 300000 rects
+caravel_000710d6_fill_pattern_0_0: 4360000 rects
+caravel_000710d6_fill_pattern_1_7: 310000 rects
+caravel_000710d6_fill_pattern_0_0: 4370000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_1_7: 320000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_2_6: 2770000 rects
+caravel_000710d6_fill_pattern_0_0: 4380000 rects
+caravel_000710d6_fill_pattern_1_7: 330000 rects
+caravel_000710d6_fill_pattern_3_5: 10000 rects
+caravel_000710d6_fill_pattern_3_5: 20000 rects
+caravel_000710d6_fill_pattern_1_7: 340000 rects
+caravel_000710d6_fill_pattern_0_0: 4390000 rects
+caravel_000710d6_fill_pattern_3_5: 30000 rects
+caravel_000710d6_fill_pattern_1_7: 350000 rects
+caravel_000710d6_fill_pattern_3_5: 40000 rects
+caravel_000710d6_fill_pattern_2_6: 2780000 rects
+caravel_000710d6_fill_pattern_0_0: 4400000 rects
+caravel_000710d6_fill_pattern_3_5: 50000 rects
+caravel_000710d6_fill_pattern_1_7: 360000 rects
+caravel_000710d6_fill_pattern_3_5: 60000 rects
+caravel_000710d6_fill_pattern_1_7: 370000 rects
+caravel_000710d6_fill_pattern_3_5: 70000 rects
+caravel_000710d6_fill_pattern_0_0: 4410000 rects
+caravel_000710d6_fill_pattern_3_5: 80000 rects
+caravel_000710d6_fill_pattern_1_7: 380000 rects
+caravel_000710d6_fill_pattern_3_5: 90000 rects
+caravel_000710d6_fill_pattern_2_6: 2790000 rects
+caravel_000710d6_fill_pattern_1_7: 390000 rects
+caravel_000710d6_fill_pattern_3_5: 100000 rects
+caravel_000710d6_fill_pattern_0_0: 4420000 rects
+caravel_000710d6_fill_pattern_3_5: 110000 rects
+caravel_000710d6_fill_pattern_1_7: 400000 rects
+caravel_000710d6_fill_pattern_4_4: 4000000 rects
+caravel_000710d6_fill_pattern_3_5: 120000 rects
+caravel_000710d6_fill_pattern_1_7: 410000 rects
+caravel_000710d6_fill_pattern_0_0: 4430000 rects
+caravel_000710d6_fill_pattern_3_5: 130000 rects
+caravel_000710d6_fill_pattern_3_5: 140000 rects
+caravel_000710d6_fill_pattern_1_7: 420000 rects
+caravel_000710d6_fill_pattern_4_4: 4010000 rects
+caravel_000710d6_fill_pattern_2_6: 2800000 rects
+caravel_000710d6_fill_pattern_3_5: 150000 rects
+caravel_000710d6_fill_pattern_0_0: 4440000 rects
+caravel_000710d6_fill_pattern_1_7: 430000 rects
+caravel_000710d6_fill_pattern_3_5: 160000 rects
+caravel_000710d6_fill_pattern_4_4: 4020000 rects
+caravel_000710d6_fill_pattern_3_5: 170000 rects
+caravel_000710d6_fill_pattern_3_5: 180000 rects
+caravel_000710d6_fill_pattern_1_7: 440000 rects
+caravel_000710d6_fill_pattern_0_0: 4450000 rects
+caravel_000710d6_fill_pattern_4_4: 4030000 rects
+caravel_000710d6_fill_pattern_3_5: 190000 rects
+caravel_000710d6_fill_pattern_2_6: 2810000 rects
+caravel_000710d6_fill_pattern_0_0: 4460000 rects
+caravel_000710d6_fill_pattern_3_5: 200000 rects
+caravel_000710d6_fill_pattern_4_4: 4040000 rects
+caravel_000710d6_fill_pattern_3_5: 210000 rects
+caravel_000710d6_fill_pattern_1_7: 450000 rects
+caravel_000710d6_fill_pattern_0_0: 4470000 rects
+caravel_000710d6_fill_pattern_4_4: 4050000 rects
+caravel_000710d6_fill_pattern_3_5: 220000 rects
+caravel_000710d6_fill_pattern_0_0: 4480000 rects
+caravel_000710d6_fill_pattern_3_5: 230000 rects
+caravel_000710d6_fill_pattern_4_4: 4060000 rects
+caravel_000710d6_fill_pattern_1_7: 460000 rects
+caravel_000710d6_fill_pattern_3_5: 240000 rects
+caravel_000710d6_fill_pattern_2_6: 2820000 rects
+caravel_000710d6_fill_pattern_4_4: 4070000 rects
+caravel_000710d6_fill_pattern_0_0: 4490000 rects
+caravel_000710d6_fill_pattern_4_4: 4080000 rects
+caravel_000710d6_fill_pattern_3_5: 250000 rects
+caravel_000710d6_fill_pattern_4_4: 4090000 rects
+caravel_000710d6_fill_pattern_3_5: 260000 rects
+caravel_000710d6_fill_pattern_1_7: 470000 rects
+caravel_000710d6_fill_pattern_0_0: 4500000 rects
+caravel_000710d6_fill_pattern_4_4: 4100000 rects
+caravel_000710d6_fill_pattern_3_5: 270000 rects
+caravel_000710d6_fill_pattern_4_4: 4110000 rects
+caravel_000710d6_fill_pattern_0_0: 4510000 rects
+caravel_000710d6_fill_pattern_3_5: 280000 rects
+caravel_000710d6_fill_pattern_2_6: 2830000 rects
+caravel_000710d6_fill_pattern_1_7: 480000 rects
+caravel_000710d6_fill_pattern_4_4: 4120000 rects
+caravel_000710d6_fill_pattern_3_5: 290000 rects
+caravel_000710d6_fill_pattern_0_0: 4520000 rects
+caravel_000710d6_fill_pattern_3_5: 300000 rects
+caravel_000710d6_fill_pattern_0_0: 4530000 rects
+caravel_000710d6_fill_pattern_1_7: 490000 rects
+caravel_000710d6_fill_pattern_3_5: 310000 rects
+caravel_000710d6_fill_pattern_4_4: 4130000 rects
+caravel_000710d6_fill_pattern_0_0: 4540000 rects
+caravel_000710d6_fill_pattern_3_5: 320000 rects
+caravel_000710d6_fill_pattern_0_0: 4550000 rects
+caravel_000710d6_fill_pattern_2_6: 2840000 rects
+caravel_000710d6_fill_pattern_3_5: 330000 rects
+caravel_000710d6_fill_pattern_1_7: 500000 rects
+caravel_000710d6_fill_pattern_0_0: 4560000 rects
+caravel_000710d6_fill_pattern_3_5: 340000 rects
+caravel_000710d6_fill_pattern_0_0: 4570000 rects
+caravel_000710d6_fill_pattern_3_5: 350000 rects
+caravel_000710d6_fill_pattern_0_0: 4580000 rects
+caravel_000710d6_fill_pattern_1_7: 510000 rects
+caravel_000710d6_fill_pattern_3_5: 360000 rects
+caravel_000710d6_fill_pattern_4_4: 4140000 rects
+caravel_000710d6_fill_pattern_0_0: 4590000 rects
+caravel_000710d6_fill_pattern_3_5: 370000 rects
+caravel_000710d6_fill_pattern_0_0: 4600000 rects
+caravel_000710d6_fill_pattern_1_7: 520000 rects
+caravel_000710d6_fill_pattern_4_4: 4150000 rects
+caravel_000710d6_fill_pattern_2_6: 2850000 rects
+caravel_000710d6_fill_pattern_3_5: 380000 rects
+caravel_000710d6_fill_pattern_0_0: 4610000 rects
+caravel_000710d6_fill_pattern_3_5: 390000 rects
+caravel_000710d6_fill_pattern_0_0: 4620000 rects
+caravel_000710d6_fill_pattern_3_5: 400000 rects
+caravel_000710d6_fill_pattern_0_0: 4630000 rects
+caravel_000710d6_fill_pattern_4_4: 4160000 rects
+caravel_000710d6_fill_pattern_1_7: 530000 rects
+caravel_000710d6_fill_pattern_3_5: 410000 rects
+caravel_000710d6_fill_pattern_0_0: 4640000 rects
+caravel_000710d6_fill_pattern_3_5: 420000 rects
+caravel_000710d6_fill_pattern_4_4: 4170000 rects
+caravel_000710d6_fill_pattern_0_0: 4650000 rects
+caravel_000710d6_fill_pattern_2_6: 2860000 rects
+caravel_000710d6_fill_pattern_1_7: 540000 rects
+caravel_000710d6_fill_pattern_4_4: 4180000 rects
+caravel_000710d6_fill_pattern_3_5: 430000 rects
+caravel_000710d6_fill_pattern_0_0: 4660000 rects
+caravel_000710d6_fill_pattern_4_4: 4190000 rects
+caravel_000710d6_fill_pattern_3_5: 440000 rects
+caravel_000710d6_fill_pattern_4_4: 4200000 rects
+caravel_000710d6_fill_pattern_0_0: 4670000 rects
+caravel_000710d6_fill_pattern_3_5: 450000 rects
+caravel_000710d6_fill_pattern_1_7: 550000 rects
+caravel_000710d6_fill_pattern_4_4: 4210000 rects
+caravel_000710d6_fill_pattern_0_0: 4680000 rects
+caravel_000710d6_fill_pattern_3_5: 460000 rects
+caravel_000710d6_fill_pattern_4_4: 4220000 rects
+caravel_000710d6_fill_pattern_3_5: 470000 rects
+caravel_000710d6_fill_pattern_2_6: 2870000 rects
+caravel_000710d6_fill_pattern_0_0: 4690000 rects
+caravel_000710d6_fill_pattern_1_7: 560000 rects
+caravel_000710d6_fill_pattern_3_5: 480000 rects
+caravel_000710d6_fill_pattern_0_0: 4700000 rects
+caravel_000710d6_fill_pattern_3_5: 490000 rects
+caravel_000710d6_fill_pattern_1_7: 570000 rects
+caravel_000710d6_fill_pattern_4_4: 4230000 rects
+caravel_000710d6_fill_pattern_3_5: 500000 rects
+caravel_000710d6_fill_pattern_0_0: 4710000 rects
+caravel_000710d6_fill_pattern_3_5: 510000 rects
+caravel_000710d6_fill_pattern_2_6: 2880000 rects
+caravel_000710d6_fill_pattern_3_5: 520000 rects
+caravel_000710d6_fill_pattern_1_7: 580000 rects
+caravel_000710d6_fill_pattern_3_5: 530000 rects
+caravel_000710d6_fill_pattern_0_0: 4720000 rects
+caravel_000710d6_fill_pattern_3_5: 540000 rects
+caravel_000710d6_fill_pattern_3_5: 550000 rects
+caravel_000710d6_fill_pattern_1_7: 590000 rects
+caravel_000710d6_fill_pattern_3_5: 560000 rects
+caravel_000710d6_fill_pattern_3_5: 570000 rects
+caravel_000710d6_fill_pattern_2_6: 2890000 rects
+caravel_000710d6_fill_pattern_3_5: 580000 rects
+caravel_000710d6_fill_pattern_4_4: 4240000 rects
+caravel_000710d6_fill_pattern_1_7: 600000 rects
+caravel_000710d6_fill_pattern_3_5: 590000 rects
+caravel_000710d6_fill_pattern_3_5: 600000 rects
+caravel_000710d6_fill_pattern_3_5: 610000 rects
+caravel_000710d6_fill_pattern_1_7: 610000 rects
+caravel_000710d6_fill_pattern_3_5: 620000 rects
+caravel_000710d6_fill_pattern_3_5: 630000 rects
+caravel_000710d6_fill_pattern_0_0: 4730000 rects
+caravel_000710d6_fill_pattern_2_6: 2900000 rects
+caravel_000710d6_fill_pattern_4_4: 4250000 rects
+caravel_000710d6_fill_pattern_3_5: 640000 rects
+caravel_000710d6_fill_pattern_1_7: 620000 rects
+caravel_000710d6_fill_pattern_3_5: 650000 rects
+caravel_000710d6_fill_pattern_4_4: 4260000 rects
+caravel_000710d6_fill_pattern_3_5: 660000 rects
+caravel_000710d6_fill_pattern_1_7: 630000 rects
+caravel_000710d6_fill_pattern_4_4: 4270000 rects
+caravel_000710d6_fill_pattern_3_5: 670000 rects
+caravel_000710d6_fill_pattern_4_4: 4280000 rects
+caravel_000710d6_fill_pattern_3_5: 680000 rects
+caravel_000710d6_fill_pattern_2_6: 2910000 rects
+caravel_000710d6_fill_pattern_1_7: 640000 rects
+caravel_000710d6_fill_pattern_0_0: 4740000 rects
+caravel_000710d6_fill_pattern_3_5: 690000 rects
+caravel_000710d6_fill_pattern_3_5: 700000 rects
+caravel_000710d6_fill_pattern_3_5: 710000 rects
+caravel_000710d6_fill_pattern_1_7: 650000 rects
+caravel_000710d6_fill_pattern_3_5: 720000 rects
+caravel_000710d6_fill_pattern_3_5: 730000 rects
+caravel_000710d6_fill_pattern_2_6: 2920000 rects
+caravel_000710d6_fill_pattern_1_7: 660000 rects
+caravel_000710d6_fill_pattern_0_0: 4750000 rects
+caravel_000710d6_fill_pattern_3_5: 740000 rects
+caravel_000710d6_fill_pattern_3_5: 750000 rects
+caravel_000710d6_fill_pattern_3_5: 760000 rects
+caravel_000710d6_fill_pattern_1_7: 670000 rects
+caravel_000710d6_fill_pattern_3_5: 770000 rects
+caravel_000710d6_fill_pattern_2_6: 2930000 rects
+caravel_000710d6_fill_pattern_4_4: 4290000 rects
+caravel_000710d6_fill_pattern_3_5: 780000 rects
+caravel_000710d6_fill_pattern_1_7: 680000 rects
+caravel_000710d6_fill_pattern_3_5: 790000 rects
+caravel_000710d6_fill_pattern_0_0: 4760000 rects
+caravel_000710d6_fill_pattern_3_5: 800000 rects
+caravel_000710d6_fill_pattern_3_5: 810000 rects
+caravel_000710d6_fill_pattern_1_7: 690000 rects
+caravel_000710d6_fill_pattern_2_6: 2940000 rects
+caravel_000710d6_fill_pattern_3_5: 820000 rects
+caravel_000710d6_fill_pattern_3_5: 830000 rects
+caravel_000710d6_fill_pattern_1_7: 700000 rects
+caravel_000710d6_fill_pattern_3_5: 840000 rects
+caravel_000710d6_fill_pattern_3_5: 850000 rects
+caravel_000710d6_fill_pattern_0_0: 4770000 rects
+caravel_000710d6_fill_pattern_3_5: 860000 rects
+caravel_000710d6_fill_pattern_1_7: 710000 rects
+caravel_000710d6_fill_pattern_3_5: 870000 rects
+caravel_000710d6_fill_pattern_1_7: 720000 rects
+caravel_000710d6_fill_pattern_2_6: 2950000 rects
+caravel_000710d6_fill_pattern_3_5: 880000 rects
+caravel_000710d6_fill_pattern_3_5: 890000 rects
+caravel_000710d6_fill_pattern_1_7: 730000 rects
+caravel_000710d6_fill_pattern_3_5: 900000 rects
+caravel_000710d6_fill_pattern_0_0: 4780000 rects
+caravel_000710d6_fill_pattern_1_7: 740000 rects
+caravel_000710d6_fill_pattern_3_5: 910000 rects
+caravel_000710d6_fill_pattern_3_5: 920000 rects
+caravel_000710d6_fill_pattern_1_7: 750000 rects
+caravel_000710d6_fill_pattern_2_6: 2960000 rects
+caravel_000710d6_fill_pattern_3_5: 930000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_4_4
+caravel_000710d6_fill_pattern_1_7: 760000 rects
+caravel_000710d6_fill_pattern_3_5: 940000 rects
+caravel_000710d6_fill_pattern_3_5: 950000 rects
+caravel_000710d6_fill_pattern_1_7: 770000 rects
+caravel_000710d6_fill_pattern_0_0: 4790000 rects
+caravel_000710d6_fill_pattern_3_5: 960000 rects
+caravel_000710d6_fill_pattern_1_7: 780000 rects
+caravel_000710d6_fill_pattern_3_5: 970000 rects
+caravel_000710d6_fill_pattern_2_6: 2970000 rects
+caravel_000710d6_fill_pattern_1_7: 790000 rects
+caravel_000710d6_fill_pattern_3_5: 980000 rects
+caravel_000710d6_fill_pattern_3_5: 990000 rects
+caravel_000710d6_fill_pattern_1_7: 800000 rects
+caravel_000710d6_fill_pattern_3_5: 1000000 rects
+caravel_000710d6_fill_pattern_0_0: 4800000 rects
+caravel_000710d6_fill_pattern_1_7: 810000 rects
+caravel_000710d6_fill_pattern_3_5: 1010000 rects
+caravel_000710d6_fill_pattern_1_7: 820000 rects
+caravel_000710d6_fill_pattern_2_6: 2980000 rects
+caravel_000710d6_fill_pattern_3_5: 1020000 rects
+caravel_000710d6_fill_pattern_1_7: 830000 rects
+caravel_000710d6_fill_pattern_3_5: 1030000 rects
+caravel_000710d6_fill_pattern_1_7: 840000 rects
+caravel_000710d6_fill_pattern_3_5: 1040000 rects
+caravel_000710d6_fill_pattern_0_0: 4810000 rects
+caravel_000710d6_fill_pattern_1_7: 850000 rects
+caravel_000710d6_fill_pattern_3_5: 1050000 rects
+caravel_000710d6_fill_pattern_2_6: 2990000 rects
+caravel_000710d6_fill_pattern_3_5: 1060000 rects
+caravel_000710d6_fill_pattern_1_7: 860000 rects
+caravel_000710d6_fill_pattern_3_5: 1070000 rects
+caravel_000710d6_fill_pattern_1_7: 870000 rects
+caravel_000710d6_fill_pattern_3_5: 1080000 rects
+caravel_000710d6_fill_pattern_0_0: 4820000 rects
+caravel_000710d6_fill_pattern_1_7: 880000 rects
+caravel_000710d6_fill_pattern_3_5: 1090000 rects
+caravel_000710d6_fill_pattern_2_6: 3000000 rects
+caravel_000710d6_fill_pattern_3_5: 1100000 rects
+caravel_000710d6_fill_pattern_1_7: 890000 rects
+caravel_000710d6_fill_pattern_3_5: 1110000 rects
+caravel_000710d6_fill_pattern_0_0: 4830000 rects
+caravel_000710d6_fill_pattern_3_5: 1120000 rects
+caravel_000710d6_fill_pattern_1_7: 900000 rects
+caravel_000710d6_fill_pattern_3_5: 1130000 rects
+caravel_000710d6_fill_pattern_0_0: 4840000 rects
+caravel_000710d6_fill_pattern_2_6: 3010000 rects
+caravel_000710d6_fill_pattern_3_5: 1140000 rects
+caravel_000710d6_fill_pattern_1_7: 910000 rects
+caravel_000710d6_fill_pattern_3_5: 1150000 rects
+caravel_000710d6_fill_pattern_0_0: 4850000 rects
+caravel_000710d6_fill_pattern_3_5: 1160000 rects
+Ended: 12/14/2022 12:09:14
+caravel_000710d6_fill_pattern_0_0: 4860000 rects
+caravel_000710d6_fill_pattern_1_7: 920000 rects
+caravel_000710d6_fill_pattern_3_5: 1170000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_6: 3020000 rects
+caravel_000710d6_fill_pattern_3_5: 1180000 rects
+caravel_000710d6_fill_pattern_0_0: 4870000 rects
+caravel_000710d6_fill_pattern_1_7: 930000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_0_0: 4880000 rects
+caravel_000710d6_fill_pattern_3_5: 1190000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_0: 4890000 rects
+caravel_000710d6_fill_pattern_1_7: 940000 rects
+caravel_000710d6_fill_pattern_3_5: 1200000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_0: 4900000 rects
+caravel_000710d6_fill_pattern_3_5: 1210000 rects
+caravel_000710d6_fill_pattern_2_6: 3030000 rects
+caravel_000710d6_fill_pattern_0_0: 4910000 rects
+caravel_000710d6_fill_pattern_1_7: 950000 rects
+caravel_000710d6_fill_pattern_3_5: 1220000 rects
+caravel_000710d6_fill_pattern_0_0: 4920000 rects
+caravel_000710d6_fill_pattern_0_0: 4930000 rects
+caravel_000710d6_fill_pattern_1_7: 960000 rects
+caravel_000710d6_fill_pattern_3_5: 1230000 rects
+caravel_000710d6_fill_pattern_0_0: 4940000 rects
+caravel_000710d6_fill_pattern_1_7: 970000 rects
+caravel_000710d6_fill_pattern_2_6: 3040000 rects
+caravel_000710d6_fill_pattern_3_5: 1240000 rects
+caravel_000710d6_fill_pattern_0_0: 4950000 rects
+caravel_000710d6_fill_pattern_1_7: 980000 rects
+caravel_000710d6_fill_pattern_3_5: 1250000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_1_7: 990000 rects
+caravel_000710d6_fill_pattern_0_0: 4960000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_3_5: 1260000 rects
+caravel_000710d6_fill_pattern_2_6: 3050000 rects
+caravel_000710d6_fill_pattern_1_7: 1000000 rects
+caravel_000710d6_fill_pattern_3_5: 1270000 rects
+caravel_000710d6_fill_pattern_4_0: 10000 rects
+caravel_000710d6_fill_pattern_3_5: 1280000 rects
+caravel_000710d6_fill_pattern_4_0: 20000 rects
+caravel_000710d6_fill_pattern_0_0: 4970000 rects
+caravel_000710d6_fill_pattern_1_7: 1010000 rects
+caravel_000710d6_fill_pattern_4_0: 30000 rects
+caravel_000710d6_fill_pattern_3_5: 1290000 rects
+caravel_000710d6_fill_pattern_4_0: 40000 rects
+caravel_000710d6_fill_pattern_1_7: 1020000 rects
+caravel_000710d6_fill_pattern_3_5: 1300000 rects
+caravel_000710d6_fill_pattern_4_0: 50000 rects
+caravel_000710d6_fill_pattern_2_6: 3060000 rects
+caravel_000710d6_fill_pattern_0_0: 4980000 rects
+caravel_000710d6_fill_pattern_4_0: 60000 rects
+caravel_000710d6_fill_pattern_3_5: 1310000 rects
+caravel_000710d6_fill_pattern_1_7: 1030000 rects
+caravel_000710d6_fill_pattern_4_0: 70000 rects
+caravel_000710d6_fill_pattern_3_5: 1320000 rects
+caravel_000710d6_fill_pattern_0_0: 4990000 rects
+caravel_000710d6_fill_pattern_4_0: 80000 rects
+caravel_000710d6_fill_pattern_1_7: 1040000 rects
+caravel_000710d6_fill_pattern_4_0: 90000 rects
+caravel_000710d6_fill_pattern_3_5: 1330000 rects
+caravel_000710d6_fill_pattern_0_0: 5000000 rects
+caravel_000710d6_fill_pattern_4_0: 100000 rects
+caravel_000710d6_fill_pattern_2_6: 3070000 rects
+caravel_000710d6_fill_pattern_1_7: 1050000 rects
+caravel_000710d6_fill_pattern_3_5: 1340000 rects
+caravel_000710d6_fill_pattern_0_0: 5010000 rects
+caravel_000710d6_fill_pattern_4_0: 110000 rects
+caravel_000710d6_fill_pattern_1_7: 1060000 rects
+caravel_000710d6_fill_pattern_0_0: 5020000 rects
+caravel_000710d6_fill_pattern_4_0: 120000 rects
+caravel_000710d6_fill_pattern_3_5: 1350000 rects
+caravel_000710d6_fill_pattern_1_7: 1070000 rects
+caravel_000710d6_fill_pattern_0_0: 5030000 rects
+caravel_000710d6_fill_pattern_4_0: 130000 rects
+caravel_000710d6_fill_pattern_1_7: 1080000 rects
+caravel_000710d6_fill_pattern_3_5: 1360000 rects
+caravel_000710d6_fill_pattern_0_0: 5040000 rects
+caravel_000710d6_fill_pattern_4_0: 140000 rects
+caravel_000710d6_fill_pattern_1_7: 1090000 rects
+caravel_000710d6_fill_pattern_2_6: 3080000 rects
+caravel_000710d6_fill_pattern_3_5: 1370000 rects
+caravel_000710d6_fill_pattern_4_0: 150000 rects
+caravel_000710d6_fill_pattern_1_7: 1100000 rects
+caravel_000710d6_fill_pattern_0_0: 5050000 rects
+caravel_000710d6_fill_pattern_3_5: 1380000 rects
+caravel_000710d6_fill_pattern_4_0: 160000 rects
+caravel_000710d6_fill_pattern_1_7: 1110000 rects
+caravel_000710d6_fill_pattern_4_0: 170000 rects
+caravel_000710d6_fill_pattern_1_7: 1120000 rects
+caravel_000710d6_fill_pattern_3_5: 1390000 rects
+caravel_000710d6_fill_pattern_4_0: 180000 rects
+caravel_000710d6_fill_pattern_1_7: 1130000 rects
+caravel_000710d6_fill_pattern_3_5: 1400000 rects
+caravel_000710d6_fill_pattern_2_6: 3090000 rects
+caravel_000710d6_fill_pattern_4_0: 190000 rects
+caravel_000710d6_fill_pattern_0_0: 5060000 rects
+caravel_000710d6_fill_pattern_3_5: 1410000 rects
+caravel_000710d6_fill_pattern_4_0: 200000 rects
+caravel_000710d6_fill_pattern_1_7: 1140000 rects
+caravel_000710d6_fill_pattern_4_0: 210000 rects
+caravel_000710d6_fill_pattern_3_5: 1420000 rects
+caravel_000710d6_fill_pattern_4_0: 220000 rects
+caravel_000710d6_fill_pattern_4_0: 230000 rects
+caravel_000710d6_fill_pattern_0_0: 5070000 rects
+caravel_000710d6_fill_pattern_2_6: 3100000 rects
+caravel_000710d6_fill_pattern_3_5: 1430000 rects
+caravel_000710d6_fill_pattern_4_0: 240000 rects
+caravel_000710d6_fill_pattern_1_7: 1150000 rects
+caravel_000710d6_fill_pattern_4_0: 250000 rects
+caravel_000710d6_fill_pattern_3_5: 1440000 rects
+caravel_000710d6_fill_pattern_4_0: 260000 rects
+caravel_000710d6_fill_pattern_1_7: 1160000 rects
+caravel_000710d6_fill_pattern_0_0: 5080000 rects
+caravel_000710d6_fill_pattern_3_5: 1450000 rects
+caravel_000710d6_fill_pattern_4_0: 270000 rects
+caravel_000710d6_fill_pattern_4_0: 280000 rects
+caravel_000710d6_fill_pattern_3_5: 1460000 rects
+caravel_000710d6_fill_pattern_2_6: 3110000 rects
+caravel_000710d6_fill_pattern_0_0: 5090000 rects
+caravel_000710d6_fill_pattern_4_0: 290000 rects
+caravel_000710d6_fill_pattern_3_5: 1470000 rects
+caravel_000710d6_fill_pattern_1_7: 1170000 rects
+caravel_000710d6_fill_pattern_0_0: 5100000 rects
+caravel_000710d6_fill_pattern_4_0: 300000 rects
+caravel_000710d6_fill_pattern_0_0: 5110000 rects
+caravel_000710d6_fill_pattern_4_0: 310000 rects
+caravel_000710d6_fill_pattern_3_5: 1480000 rects
+caravel_000710d6_fill_pattern_0_0: 5120000 rects
+caravel_000710d6_fill_pattern_4_0: 320000 rects
+caravel_000710d6_fill_pattern_1_7: 1180000 rects
+caravel_000710d6_fill_pattern_4_0: 330000 rects
+caravel_000710d6_fill_pattern_3_5: 1490000 rects
+caravel_000710d6_fill_pattern_2_6: 3120000 rects
+caravel_000710d6_fill_pattern_4_0: 340000 rects
+caravel_000710d6_fill_pattern_3_5: 1500000 rects
+caravel_000710d6_fill_pattern_1_7: 1190000 rects
+caravel_000710d6_fill_pattern_4_0: 350000 rects
+caravel_000710d6_fill_pattern_0_0: 5130000 rects
+caravel_000710d6_fill_pattern_4_0: 360000 rects
+caravel_000710d6_fill_pattern_3_5: 1510000 rects
+caravel_000710d6_fill_pattern_4_0: 370000 rects
+caravel_000710d6_fill_pattern_1_7: 1200000 rects
+caravel_000710d6_fill_pattern_3_5: 1520000 rects
+caravel_000710d6_fill_pattern_4_0: 380000 rects
+caravel_000710d6_fill_pattern_2_6: 3130000 rects
+caravel_000710d6_fill_pattern_4_0: 390000 rects
+caravel_000710d6_fill_pattern_3_5: 1530000 rects
+caravel_000710d6_fill_pattern_1_7: 1210000 rects
+caravel_000710d6_fill_pattern_4_0: 400000 rects
+caravel_000710d6_fill_pattern_3_5: 1540000 rects
+caravel_000710d6_fill_pattern_1_7: 1220000 rects
+caravel_000710d6_fill_pattern_4_0: 410000 rects
+caravel_000710d6_fill_pattern_0_0: 5140000 rects
+caravel_000710d6_fill_pattern_1_7: 1230000 rects
+caravel_000710d6_fill_pattern_3_5: 1550000 rects
+caravel_000710d6_fill_pattern_4_0: 420000 rects
+caravel_000710d6_fill_pattern_1_7: 1240000 rects
+caravel_000710d6_fill_pattern_4_0: 430000 rects
+caravel_000710d6_fill_pattern_3_5: 1560000 rects
+caravel_000710d6_fill_pattern_2_6: 3140000 rects
+caravel_000710d6_fill_pattern_1_7: 1250000 rects
+caravel_000710d6_fill_pattern_4_0: 440000 rects
+caravel_000710d6_fill_pattern_3_5: 1570000 rects
+caravel_000710d6_fill_pattern_4_0: 450000 rects
+caravel_000710d6_fill_pattern_4_0: 460000 rects
+caravel_000710d6_fill_pattern_3_5: 1580000 rects
+caravel_000710d6_fill_pattern_4_0: 470000 rects
+caravel_000710d6_fill_pattern_3_5: 1590000 rects
+caravel_000710d6_fill_pattern_1_7: 1260000 rects
+caravel_000710d6_fill_pattern_4_0: 480000 rects
+caravel_000710d6_fill_pattern_2_6: 3150000 rects
+caravel_000710d6_fill_pattern_4_0: 490000 rects
+caravel_000710d6_fill_pattern_3_5: 1600000 rects
+caravel_000710d6_fill_pattern_1_7: 1270000 rects
+caravel_000710d6_fill_pattern_4_0: 500000 rects
+caravel_000710d6_fill_pattern_4_0: 510000 rects
+caravel_000710d6_fill_pattern_3_5: 1610000 rects
+caravel_000710d6_fill_pattern_4_0: 520000 rects
+caravel_000710d6_fill_pattern_3_5: 1620000 rects
+caravel_000710d6_fill_pattern_4_0: 530000 rects
+caravel_000710d6_fill_pattern_1_7: 1280000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_4_0: 540000 rects
+caravel_000710d6_fill_pattern_2_6: 3160000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_0_0
+caravel_000710d6_fill_pattern_3_5: 1630000 rects
+caravel_000710d6_fill_pattern_4_0: 550000 rects
+caravel_000710d6_fill_pattern_3_5: 1640000 rects
+caravel_000710d6_fill_pattern_1_7: 1290000 rects
+caravel_000710d6_fill_pattern_4_0: 560000 rects
+caravel_000710d6_fill_pattern_4_0: 570000 rects
+caravel_000710d6_fill_pattern_3_5: 1650000 rects
+caravel_000710d6_fill_pattern_1_7: 1300000 rects
+caravel_000710d6_fill_pattern_2_6: 3170000 rects
+caravel_000710d6_fill_pattern_4_0: 580000 rects
+caravel_000710d6_fill_pattern_3_5: 1660000 rects
+caravel_000710d6_fill_pattern_4_0: 590000 rects
+caravel_000710d6_fill_pattern_1_7: 1310000 rects
+caravel_000710d6_fill_pattern_4_0: 600000 rects
+caravel_000710d6_fill_pattern_1_7: 1320000 rects
+caravel_000710d6_fill_pattern_4_0: 610000 rects
+caravel_000710d6_fill_pattern_3_5: 1670000 rects
+caravel_000710d6_fill_pattern_1_7: 1330000 rects
+caravel_000710d6_fill_pattern_4_0: 620000 rects
+caravel_000710d6_fill_pattern_3_5: 1680000 rects
+caravel_000710d6_fill_pattern_4_0: 630000 rects
+caravel_000710d6_fill_pattern_2_6: 3180000 rects
+caravel_000710d6_fill_pattern_1_7: 1340000 rects
+caravel_000710d6_fill_pattern_4_0: 640000 rects
+caravel_000710d6_fill_pattern_3_5: 1690000 rects
+caravel_000710d6_fill_pattern_4_0: 650000 rects
+caravel_000710d6_fill_pattern_3_5: 1700000 rects
+caravel_000710d6_fill_pattern_4_0: 660000 rects
+caravel_000710d6_fill_pattern_1_7: 1350000 rects
+caravel_000710d6_fill_pattern_3_5: 1710000 rects
+caravel_000710d6_fill_pattern_4_0: 670000 rects
+caravel_000710d6_fill_pattern_2_6: 3190000 rects
+caravel_000710d6_fill_pattern_3_5: 1720000 rects
+caravel_000710d6_fill_pattern_4_0: 680000 rects
+caravel_000710d6_fill_pattern_3_5: 1730000 rects
+caravel_000710d6_fill_pattern_4_0: 690000 rects
+caravel_000710d6_fill_pattern_1_7: 1360000 rects
+caravel_000710d6_fill_pattern_3_5: 1740000 rects
+caravel_000710d6_fill_pattern_4_0: 700000 rects
+caravel_000710d6_fill_pattern_1_7: 1370000 rects
+caravel_000710d6_fill_pattern_3_5: 1750000 rects
+caravel_000710d6_fill_pattern_4_0: 710000 rects
+caravel_000710d6_fill_pattern_2_6: 3200000 rects
+caravel_000710d6_fill_pattern_1_7: 1380000 rects
+caravel_000710d6_fill_pattern_1_7: 1390000 rects
+caravel_000710d6_fill_pattern_3_5: 1760000 rects
+caravel_000710d6_fill_pattern_4_0: 720000 rects
+caravel_000710d6_fill_pattern_3_5: 1770000 rects
+caravel_000710d6_fill_pattern_4_0: 730000 rects
+caravel_000710d6_fill_pattern_1_7: 1400000 rects
+caravel_000710d6_fill_pattern_3_5: 1780000 rects
+caravel_000710d6_fill_pattern_4_0: 740000 rects
+caravel_000710d6_fill_pattern_2_6: 3210000 rects
+caravel_000710d6_fill_pattern_3_5: 1790000 rects
+caravel_000710d6_fill_pattern_4_0: 750000 rects
+caravel_000710d6_fill_pattern_3_5: 1800000 rects
+caravel_000710d6_fill_pattern_4_0: 760000 rects
+caravel_000710d6_fill_pattern_3_5: 1810000 rects
+caravel_000710d6_fill_pattern_4_0: 770000 rects
+caravel_000710d6_fill_pattern_2_6: 3220000 rects
+caravel_000710d6_fill_pattern_3_5: 1820000 rects
+caravel_000710d6_fill_pattern_3_5: 1830000 rects
+caravel_000710d6_fill_pattern_4_0: 780000 rects
+caravel_000710d6_fill_pattern_3_5: 1840000 rects
+caravel_000710d6_fill_pattern_4_0: 790000 rects
+caravel_000710d6_fill_pattern_3_5: 1850000 rects
+caravel_000710d6_fill_pattern_2_6: 3230000 rects
+caravel_000710d6_fill_pattern_3_5: 1860000 rects
+caravel_000710d6_fill_pattern_4_0: 800000 rects
+caravel_000710d6_fill_pattern_3_5: 1870000 rects
+caravel_000710d6_fill_pattern_4_0: 810000 rects
+caravel_000710d6_fill_pattern_3_5: 1880000 rects
+caravel_000710d6_fill_pattern_4_0: 820000 rects
+caravel_000710d6_fill_pattern_3_5: 1890000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_000710d6_fill_pattern_2_6: 3240000 rects
+   Generating output for cell caravel_000710d6_fill_pattern_1_7
+caravel_000710d6_fill_pattern_4_0: 830000 rects
+caravel_000710d6_fill_pattern_3_5: 1900000 rects
+caravel_000710d6_fill_pattern_4_0: 840000 rects
+caravel_000710d6_fill_pattern_3_5: 1910000 rects
+caravel_000710d6_fill_pattern_4_0: 850000 rects
+caravel_000710d6_fill_pattern_3_5: 1920000 rects
+caravel_000710d6_fill_pattern_4_0: 860000 rects
+caravel_000710d6_fill_pattern_2_6: 3250000 rects
+caravel_000710d6_fill_pattern_3_5: 1930000 rects
+caravel_000710d6_fill_pattern_3_5: 1940000 rects
+caravel_000710d6_fill_pattern_4_0: 870000 rects
+caravel_000710d6_fill_pattern_3_5: 1950000 rects
+caravel_000710d6_fill_pattern_4_0: 880000 rects
+caravel_000710d6_fill_pattern_3_5: 1960000 rects
+caravel_000710d6_fill_pattern_2_6: 3260000 rects
+caravel_000710d6_fill_pattern_4_0: 890000 rects
+caravel_000710d6_fill_pattern_3_5: 1970000 rects
+caravel_000710d6_fill_pattern_4_0: 900000 rects
+caravel_000710d6_fill_pattern_4_0: 910000 rects
+caravel_000710d6_fill_pattern_3_5: 1980000 rects
+caravel_000710d6_fill_pattern_2_6: 3270000 rects
+caravel_000710d6_fill_pattern_4_0: 920000 rects
+caravel_000710d6_fill_pattern_4_0: 930000 rects
+caravel_000710d6_fill_pattern_3_5: 1990000 rects
+caravel_000710d6_fill_pattern_4_0: 940000 rects
+caravel_000710d6_fill_pattern_2_6: 3280000 rects
+caravel_000710d6_fill_pattern_3_5: 2000000 rects
+caravel_000710d6_fill_pattern_4_0: 950000 rects
+caravel_000710d6_fill_pattern_4_0: 960000 rects
+Ended: 12/14/2022 12:09:19
+caravel_000710d6_fill_pattern_3_5: 2010000 rects
+caravel_000710d6_fill_pattern_4_0: 970000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_2_6: 3290000 rects
+caravel_000710d6_fill_pattern_4_0: 980000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_3_5: 2020000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_4_0: 990000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_4_0: 1000000 rects
+caravel_000710d6_fill_pattern_4_0: 1010000 rects
+caravel_000710d6_fill_pattern_2_6: 3300000 rects
+caravel_000710d6_fill_pattern_3_5: 2030000 rects
+caravel_000710d6_fill_pattern_4_0: 1020000 rects
+caravel_000710d6_fill_pattern_4_0: 1030000 rects
+caravel_000710d6_fill_pattern_4_0: 1040000 rects
+caravel_000710d6_fill_pattern_3_5: 2040000 rects
+caravel_000710d6_fill_pattern_4_0: 1050000 rects
+caravel_000710d6_fill_pattern_2_6: 3310000 rects
+caravel_000710d6_fill_pattern_4_0: 1060000 rects
+caravel_000710d6_fill_pattern_4_0: 1070000 rects
+caravel_000710d6_fill_pattern_3_5: 2050000 rects
+caravel_000710d6_fill_pattern_4_0: 1080000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_2_6: 3320000 rects
+caravel_000710d6_fill_pattern_4_0: 1090000 rects
+caravel_000710d6_fill_pattern_3_5: 2060000 rects
+caravel_000710d6_fill_pattern_0_4: 10000 rects
+caravel_000710d6_fill_pattern_0_4: 20000 rects
+caravel_000710d6_fill_pattern_0_4: 30000 rects
+caravel_000710d6_fill_pattern_4_0: 1100000 rects
+caravel_000710d6_fill_pattern_0_4: 40000 rects
+caravel_000710d6_fill_pattern_2_6: 3330000 rects
+caravel_000710d6_fill_pattern_3_5: 2070000 rects
+caravel_000710d6_fill_pattern_0_4: 50000 rects
+caravel_000710d6_fill_pattern_0_4: 60000 rects
+caravel_000710d6_fill_pattern_0_4: 70000 rects
+caravel_000710d6_fill_pattern_4_0: 1110000 rects
+caravel_000710d6_fill_pattern_3_5: 2080000 rects
+caravel_000710d6_fill_pattern_0_4: 80000 rects
+caravel_000710d6_fill_pattern_0_4: 90000 rects
+caravel_000710d6_fill_pattern_2_6: 3340000 rects
+caravel_000710d6_fill_pattern_0_4: 100000 rects
+caravel_000710d6_fill_pattern_4_0: 1120000 rects
+caravel_000710d6_fill_pattern_0_4: 110000 rects
+caravel_000710d6_fill_pattern_3_5: 2090000 rects
+caravel_000710d6_fill_pattern_0_4: 120000 rects
+caravel_000710d6_fill_pattern_0_4: 130000 rects
+caravel_000710d6_fill_pattern_0_4: 140000 rects
+caravel_000710d6_fill_pattern_2_6: 3350000 rects
+caravel_000710d6_fill_pattern_3_5: 2100000 rects
+caravel_000710d6_fill_pattern_4_0: 1130000 rects
+caravel_000710d6_fill_pattern_0_4: 150000 rects
+caravel_000710d6_fill_pattern_0_4: 160000 rects
+caravel_000710d6_fill_pattern_0_4: 170000 rects
+caravel_000710d6_fill_pattern_3_5: 2110000 rects
+caravel_000710d6_fill_pattern_0_4: 180000 rects
+caravel_000710d6_fill_pattern_4_0: 1140000 rects
+caravel_000710d6_fill_pattern_2_6: 3360000 rects
+caravel_000710d6_fill_pattern_0_4: 190000 rects
+caravel_000710d6_fill_pattern_0_4: 200000 rects
+caravel_000710d6_fill_pattern_0_4: 210000 rects
+caravel_000710d6_fill_pattern_3_5: 2120000 rects
+caravel_000710d6_fill_pattern_0_4: 220000 rects
+caravel_000710d6_fill_pattern_4_0: 1150000 rects
+caravel_000710d6_fill_pattern_0_4: 230000 rects
+caravel_000710d6_fill_pattern_2_6: 3370000 rects
+caravel_000710d6_fill_pattern_0_4: 240000 rects
+caravel_000710d6_fill_pattern_3_5: 2130000 rects
+caravel_000710d6_fill_pattern_0_4: 250000 rects
+caravel_000710d6_fill_pattern_4_0: 1160000 rects
+caravel_000710d6_fill_pattern_0_4: 260000 rects
+caravel_000710d6_fill_pattern_0_4: 270000 rects
+caravel_000710d6_fill_pattern_3_5: 2140000 rects
+caravel_000710d6_fill_pattern_0_4: 280000 rects
+caravel_000710d6_fill_pattern_2_6: 3380000 rects
+caravel_000710d6_fill_pattern_0_4: 290000 rects
+caravel_000710d6_fill_pattern_4_0: 1170000 rects
+caravel_000710d6_fill_pattern_0_4: 300000 rects
+caravel_000710d6_fill_pattern_0_4: 310000 rects
+caravel_000710d6_fill_pattern_3_5: 2150000 rects
+caravel_000710d6_fill_pattern_0_4: 320000 rects
+caravel_000710d6_fill_pattern_4_0: 1180000 rects
+caravel_000710d6_fill_pattern_2_6: 3390000 rects
+caravel_000710d6_fill_pattern_0_4: 330000 rects
+caravel_000710d6_fill_pattern_0_4: 340000 rects
+caravel_000710d6_fill_pattern_3_5: 2160000 rects
+caravel_000710d6_fill_pattern_0_4: 350000 rects
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+caravel_000710d6_fill_pattern_0_4: 490000 rects
+caravel_000710d6_fill_pattern_0_4: 500000 rects
+caravel_000710d6_fill_pattern_4_0: 1230000 rects
+caravel_000710d6_fill_pattern_3_5: 2210000 rects
+Ended: 12/14/2022 12:09:21
+caravel_000710d6_fill_pattern_0_4: 510000 rects
+caravel_000710d6_fill_pattern_2_6: 3430000 rects
+caravel_000710d6_fill_pattern_0_4: 520000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_4: 530000 rects
+caravel_000710d6_fill_pattern_3_5: 2220000 rects
+caravel_000710d6_fill_pattern_4_0: 1240000 rects
+caravel_000710d6_fill_pattern_0_4: 540000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_4: 550000 rects
+caravel_000710d6_fill_pattern_0_4: 560000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_2_6: 3440000 rects
+caravel_000710d6_fill_pattern_3_5: 2230000 rects
+caravel_000710d6_fill_pattern_0_4: 570000 rects
+caravel_000710d6_fill_pattern_4_0: 1250000 rects
+caravel_000710d6_fill_pattern_0_4: 580000 rects
+caravel_000710d6_fill_pattern_0_4: 590000 rects
+caravel_000710d6_fill_pattern_0_4: 600000 rects
+caravel_000710d6_fill_pattern_3_5: 2240000 rects
+caravel_000710d6_fill_pattern_4_0: 1260000 rects
+caravel_000710d6_fill_pattern_0_4: 610000 rects
+caravel_000710d6_fill_pattern_2_6: 3450000 rects
+caravel_000710d6_fill_pattern_0_4: 620000 rects
+caravel_000710d6_fill_pattern_0_4: 630000 rects
+caravel_000710d6_fill_pattern_4_0: 1270000 rects
+caravel_000710d6_fill_pattern_3_5: 2250000 rects
+caravel_000710d6_fill_pattern_0_4: 640000 rects
+caravel_000710d6_fill_pattern_0_4: 650000 rects
+caravel_000710d6_fill_pattern_0_4: 660000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+caravel_000710d6_fill_pattern_2_6: 3460000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_000710d6_fill_pattern_0_4: 670000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_3_5: 2260000 rects
+caravel_000710d6_fill_pattern_4_0: 1280000 rects
+caravel_000710d6_fill_pattern_0_4: 680000 rects
+caravel_000710d6_fill_pattern_0_4: 690000 rects
+caravel_000710d6_fill_pattern_2_2: 10000 rects
+caravel_000710d6_fill_pattern_0_4: 700000 rects
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+caravel_000710d6_fill_pattern_2_2: 70000 rects
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+caravel_000710d6_fill_pattern_2_2: 100000 rects
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+caravel_000710d6_fill_pattern_4_0: 1540000 rects
+caravel_000710d6_fill_pattern_2_2: 650000 rects
+Ended: 12/14/2022 12:09:24
+caravel_000710d6_fill_pattern_0_4: 1470000 rects
+caravel_000710d6_fill_pattern_2_2: 660000 rects
+caravel_000710d6_fill_pattern_4_0: 1550000 rects
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+caravel_000710d6_fill_pattern_3_5: 2570000 rects
+caravel_000710d6_fill_pattern_2_2: 670000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_4: 1490000 rects
+caravel_000710d6_fill_pattern_2_6: 3670000 rects
+caravel_000710d6_fill_pattern_4_0: 1560000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_2_2: 680000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_4: 1500000 rects
+caravel_000710d6_fill_pattern_3_5: 2580000 rects
+caravel_000710d6_fill_pattern_2_2: 690000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_4: 1510000 rects
+caravel_000710d6_fill_pattern_4_0: 1570000 rects
+caravel_000710d6_fill_pattern_2_2: 700000 rects
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+caravel_000710d6_fill_pattern_4_0: 1600000 rects
+caravel_000710d6_fill_pattern_2_2: 750000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_0_4: 1580000 rects
+caravel_000710d6_fill_pattern_2_2: 760000 rects
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+caravel_000710d6_fill_pattern_1_3: 10000 rects
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+caravel_000710d6_fill_pattern_0_4: 4410000 rects
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+caravel_000710d6_fill_pattern_0_4: 4450000 rects
+caravel_000710d6_fill_pattern_2_6: 5940000 rects
+Ended: 12/14/2022 12:09:50
+caravel_000710d6_fill_pattern_0_4: 4460000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_0_4: 4470000 rects
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_0_4: 4480000 rects
+caravel_000710d6_fill_pattern_1_3: 4430000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_0_4: 4490000 rects
+caravel_000710d6_fill_pattern_0_4: 4500000 rects
+caravel_000710d6_fill_pattern_0_4: 4510000 rects
+caravel_000710d6_fill_pattern_0_4: 4520000 rects
+caravel_000710d6_fill_pattern_2_2: 4710000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_000710d6_fill_pattern_0_4: 4530000 rects
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_1_3: 4440000 rects
+caravel_000710d6_fill_pattern_0_4: 4540000 rects
+caravel_000710d6_fill_pattern_3_1: 10000 rects
+caravel_000710d6_fill_pattern_3_1: 20000 rects
+caravel_000710d6_fill_pattern_3_1: 30000 rects
+caravel_000710d6_fill_pattern_0_4: 4550000 rects
+caravel_000710d6_fill_pattern_3_1: 40000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_2_6
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+caravel_000710d6_fill_pattern_0_4: 4560000 rects
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+caravel_000710d6_fill_pattern_3_1: 100000 rects
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+caravel_000710d6_fill_pattern_2_2: 4880000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_0_4
+caravel_000710d6_fill_pattern_1_3: 4650000 rects
+caravel_000710d6_fill_pattern_3_1: 1690000 rects
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+caravel_000710d6_fill_pattern_3_1: 2270000 rects
+caravel_000710d6_fill_pattern_3_1: 2280000 rects
+Ended: 12/14/2022 12:10:02
+caravel_000710d6_fill_pattern_3_1: 2290000 rects
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_000710d6_fill_pattern_3_1: 2300000 rects
+Processing system .magicrc file
+caravel_000710d6_fill_pattern_3_1: 2310000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_000710d6_fill_pattern_1_3: 4790000 rects
+caravel_000710d6_fill_pattern_3_1: 2320000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_000710d6_fill_pattern_3_1: 2330000 rects
+caravel_000710d6_fill_pattern_3_1: 2340000 rects
+caravel_000710d6_fill_pattern_2_2: 4980000 rects
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+caravel_000710d6_fill_pattern_3_1: 2380000 rects
+caravel_000710d6_fill_pattern_3_1: 2390000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_000710d6_fill_pattern_3_1: 2400000 rects
+caravel_000710d6_fill_pattern_1_3: 4810000 rects
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+caravel_000710d6_fill_pattern_3_1: 2410000 rects
+caravel_000710d6_fill_pattern_1_3: 4820000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_5_7
+caravel_000710d6_fill_pattern_2_2: 5000000 rects
+caravel_000710d6_fill_pattern_3_1: 2420000 rects
+caravel_000710d6_fill_pattern_1_3: 4830000 rects
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+caravel_000710d6_fill_pattern_1_3: 4840000 rects
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+caravel_000710d6_fill_pattern_1_3: 4860000 rects
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+caravel_000710d6_fill_pattern_3_1: 2450000 rects
+caravel_000710d6_fill_pattern_1_3: 4880000 rects
+caravel_000710d6_fill_pattern_1_3: 4890000 rects
+caravel_000710d6_fill_pattern_2_2: 5020000 rects
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+caravel_000710d6_fill_pattern_1_3: 4900000 rects
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+caravel_000710d6_fill_pattern_1_3: 4980000 rects
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+caravel_000710d6_fill_pattern_3_1: 2500000 rects
+caravel_000710d6_fill_pattern_1_3: 5010000 rects
+Ended: 12/14/2022 12:10:04
+caravel_000710d6_fill_pattern_1_3: 5020000 rects
+caravel_000710d6_fill_pattern_1_3: 5030000 rects
+caravel_000710d6_fill_pattern_2_2: 5040000 rects
+caravel_000710d6_fill_pattern_1_3: 5040000 rects
+caravel_000710d6_fill_pattern_1_3: 5050000 rects
+caravel_000710d6_fill_pattern_3_1: 2510000 rects
+caravel_000710d6_fill_pattern_1_3: 5060000 rects
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+caravel_000710d6_fill_pattern_3_1: 4270000 rects
+caravel_000710d6_fill_pattern_3_1: 4280000 rects
+caravel_000710d6_fill_pattern_3_1: 4290000 rects
+caravel_000710d6_fill_pattern_3_1: 4300000 rects
+caravel_000710d6_fill_pattern_3_1: 4310000 rects
+caravel_000710d6_fill_pattern_3_1: 4320000 rects
+caravel_000710d6_fill_pattern_3_1: 4330000 rects
+caravel_000710d6_fill_pattern_3_1: 4340000 rects
+caravel_000710d6_fill_pattern_3_1: 4350000 rects
+caravel_000710d6_fill_pattern_3_1: 4360000 rects
+caravel_000710d6_fill_pattern_3_1: 4370000 rects
+caravel_000710d6_fill_pattern_3_1: 4380000 rects
+caravel_000710d6_fill_pattern_3_1: 4390000 rects
+caravel_000710d6_fill_pattern_3_1: 4400000 rects
+caravel_000710d6_fill_pattern_3_1: 4410000 rects
+caravel_000710d6_fill_pattern_3_1: 4420000 rects
+caravel_000710d6_fill_pattern_3_1: 4430000 rects
+caravel_000710d6_fill_pattern_3_1: 4440000 rects
+caravel_000710d6_fill_pattern_3_1: 4450000 rects
+caravel_000710d6_fill_pattern_3_1: 4460000 rects
+caravel_000710d6_fill_pattern_3_1: 4470000 rects
+caravel_000710d6_fill_pattern_3_1: 4480000 rects
+caravel_000710d6_fill_pattern_3_1: 4490000 rects
+caravel_000710d6_fill_pattern_3_1: 4500000 rects
+caravel_000710d6_fill_pattern_3_1: 4510000 rects
+caravel_000710d6_fill_pattern_3_1: 4520000 rects
+caravel_000710d6_fill_pattern_3_1: 4530000 rects
+caravel_000710d6_fill_pattern_3_1: 4540000 rects
+caravel_000710d6_fill_pattern_3_1: 4550000 rects
+caravel_000710d6_fill_pattern_3_1: 4560000 rects
+caravel_000710d6_fill_pattern_3_1: 4570000 rects
+caravel_000710d6_fill_pattern_3_1: 4580000 rects
+caravel_000710d6_fill_pattern_3_1: 4590000 rects
+caravel_000710d6_fill_pattern_3_1: 4600000 rects
+caravel_000710d6_fill_pattern_3_1: 4610000 rects
+caravel_000710d6_fill_pattern_3_1: 4620000 rects
+caravel_000710d6_fill_pattern_3_1: 4630000 rects
+caravel_000710d6_fill_pattern_3_1: 4640000 rects
+caravel_000710d6_fill_pattern_3_1: 4650000 rects
+caravel_000710d6_fill_pattern_3_1: 4660000 rects
+caravel_000710d6_fill_pattern_3_1: 4670000 rects
+caravel_000710d6_fill_pattern_3_1: 4680000 rects
+caravel_000710d6_fill_pattern_3_1: 4690000 rects
+caravel_000710d6_fill_pattern_3_1: 4700000 rects
+caravel_000710d6_fill_pattern_3_1: 4710000 rects
+caravel_000710d6_fill_pattern_3_1: 4720000 rects
+caravel_000710d6_fill_pattern_3_1: 4730000 rects
+caravel_000710d6_fill_pattern_3_1: 4740000 rects
+caravel_000710d6_fill_pattern_3_1: 4750000 rects
+caravel_000710d6_fill_pattern_3_1: 4760000 rects
+caravel_000710d6_fill_pattern_3_1: 4770000 rects
+caravel_000710d6_fill_pattern_3_1: 4780000 rects
+caravel_000710d6_fill_pattern_3_1: 4790000 rects
+caravel_000710d6_fill_pattern_3_1: 4800000 rects
+caravel_000710d6_fill_pattern_3_1: 4810000 rects
+caravel_000710d6_fill_pattern_3_1: 4820000 rects
+caravel_000710d6_fill_pattern_3_1: 4830000 rects
+caravel_000710d6_fill_pattern_3_1: 4840000 rects
+caravel_000710d6_fill_pattern_3_1: 4850000 rects
+caravel_000710d6_fill_pattern_3_1: 4860000 rects
+caravel_000710d6_fill_pattern_3_1: 4870000 rects
+caravel_000710d6_fill_pattern_3_1: 4880000 rects
+caravel_000710d6_fill_pattern_3_1: 4890000 rects
+caravel_000710d6_fill_pattern_3_1: 4900000 rects
+caravel_000710d6_fill_pattern_3_1: 4910000 rects
+caravel_000710d6_fill_pattern_3_1: 4920000 rects
+caravel_000710d6_fill_pattern_3_1: 4930000 rects
+caravel_000710d6_fill_pattern_3_1: 4940000 rects
+caravel_000710d6_fill_pattern_3_1: 4950000 rects
+caravel_000710d6_fill_pattern_3_1: 4960000 rects
+caravel_000710d6_fill_pattern_3_1: 4970000 rects
+caravel_000710d6_fill_pattern_3_1: 4980000 rects
+caravel_000710d6_fill_pattern_3_1: 4990000 rects
+caravel_000710d6_fill_pattern_3_1: 5000000 rects
+caravel_000710d6_fill_pattern_3_1: 5010000 rects
+caravel_000710d6_fill_pattern_3_1: 5020000 rects
+caravel_000710d6_fill_pattern_3_1: 5030000 rects
+caravel_000710d6_fill_pattern_3_1: 5040000 rects
+caravel_000710d6_fill_pattern_3_1: 5050000 rects
+caravel_000710d6_fill_pattern_3_1: 5060000 rects
+caravel_000710d6_fill_pattern_3_1: 5070000 rects
+caravel_000710d6_fill_pattern_3_1: 5080000 rects
+caravel_000710d6_fill_pattern_3_1: 5090000 rects
+caravel_000710d6_fill_pattern_3_1: 5100000 rects
+caravel_000710d6_fill_pattern_3_1: 5110000 rects
+caravel_000710d6_fill_pattern_3_1: 5120000 rects
+caravel_000710d6_fill_pattern_3_1: 5130000 rects
+caravel_000710d6_fill_pattern_3_1: 5140000 rects
+caravel_000710d6_fill_pattern_3_1: 5150000 rects
+caravel_000710d6_fill_pattern_3_1: 5160000 rects
+caravel_000710d6_fill_pattern_3_1: 5170000 rects
+caravel_000710d6_fill_pattern_3_1: 5180000 rects
+caravel_000710d6_fill_pattern_3_1: 5190000 rects
+caravel_000710d6_fill_pattern_3_1: 5200000 rects
+caravel_000710d6_fill_pattern_3_1: 5210000 rects
+caravel_000710d6_fill_pattern_3_1: 5220000 rects
+caravel_000710d6_fill_pattern_3_1: 5230000 rects
+caravel_000710d6_fill_pattern_3_1: 5240000 rects
+caravel_000710d6_fill_pattern_3_1: 5250000 rects
+caravel_000710d6_fill_pattern_3_1: 5260000 rects
+caravel_000710d6_fill_pattern_3_1: 5270000 rects
+caravel_000710d6_fill_pattern_3_1: 5280000 rects
+caravel_000710d6_fill_pattern_3_1: 5290000 rects
+caravel_000710d6_fill_pattern_3_1: 5300000 rects
+caravel_000710d6_fill_pattern_3_1: 5310000 rects
+caravel_000710d6_fill_pattern_3_1: 5320000 rects
+caravel_000710d6_fill_pattern_3_1: 5330000 rects
+caravel_000710d6_fill_pattern_3_1: 5340000 rects
+caravel_000710d6_fill_pattern_3_1: 5350000 rects
+caravel_000710d6_fill_pattern_3_1: 5360000 rects
+caravel_000710d6_fill_pattern_3_1: 5370000 rects
+caravel_000710d6_fill_pattern_3_1: 5380000 rects
+caravel_000710d6_fill_pattern_3_1: 5390000 rects
+caravel_000710d6_fill_pattern_3_1: 5400000 rects
+caravel_000710d6_fill_pattern_3_1: 5410000 rects
+caravel_000710d6_fill_pattern_3_1: 5420000 rects
+caravel_000710d6_fill_pattern_3_1: 5430000 rects
+caravel_000710d6_fill_pattern_3_1: 5440000 rects
+caravel_000710d6_fill_pattern_3_1: 5450000 rects
+caravel_000710d6_fill_pattern_3_1: 5460000 rects
+caravel_000710d6_fill_pattern_3_1: 5470000 rects
+caravel_000710d6_fill_pattern_3_1: 5480000 rects
+caravel_000710d6_fill_pattern_3_1: 5490000 rects
+caravel_000710d6_fill_pattern_3_1: 5500000 rects
+caravel_000710d6_fill_pattern_3_1: 5510000 rects
+caravel_000710d6_fill_pattern_3_1: 5520000 rects
+caravel_000710d6_fill_pattern_3_1: 5530000 rects
+caravel_000710d6_fill_pattern_3_1: 5540000 rects
+caravel_000710d6_fill_pattern_3_1: 5550000 rects
+caravel_000710d6_fill_pattern_3_1: 5560000 rects
+caravel_000710d6_fill_pattern_3_1: 5570000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_000710d6_fill_pattern_3_1
+Ended: 12/14/2022 12:11:16
+Ended: 12/14/2022 12:11:32
+Ended: 12/14/2022 12:11:36
+Ended: 12/14/2022 12:11:50
+Ended: 12/14/2022 12:11:56
+Ended: 12/14/2022 12:12:09
+Ended: 12/14/2022 12:12:11
+Ended: 12/14/2022 12:12:30
+Ended: 12/14/2022 12:12:37
+Ended: 12/14/2022 12:12:39
+Ended: 12/14/2022 12:12:58
+Ended: 12/14/2022 12:13:44
+Ended: 12/14/2022 12:14:23
+Ended: 12/14/2022 12:18:00
+Ended: 12/14/2022 12:20:13
diff --git a/tapeout/logs/gds.info b/tapeout/logs/gds.info
new file mode 100644
index 0000000..697fc15
--- /dev/null
+++ b/tapeout/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 1e5ace33ca8d8c89b41051dc1acf52d440b7aa0d
\ No newline at end of file
diff --git a/tapeout/logs/gen_gpio_defaults.log b/tapeout/logs/gen_gpio_defaults.log
new file mode 100644
index 0000000..d470522
--- /dev/null
+++ b/tapeout/logs/gen_gpio_defaults.log
@@ -0,0 +1,79 @@
+Step 1:  Create new cells for new GPIO default vectors.
+Creating new layout file /root/project/mag/gpio_defaults_block_1803.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v
+Layout file /root/project/mag/gpio_defaults_block_1803.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_0403.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v
+Creating new layout file /root/project/mag/gpio_defaults_block_0801.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0801.v
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_1800.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Step 2:  Modify top-level layouts to use the specified defaults.
+Done.
diff --git a/tapeout/logs/git.info b/tapeout/logs/git.info
new file mode 100644
index 0000000..398d038
--- /dev/null
+++ b/tapeout/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/dineshannayya/riscduino_qcore.git
+Branch: HEAD
+Commit: 7764ef40a007aa7e18c93005922bf01a9b39dba3
\ No newline at end of file
diff --git a/tapeout/logs/git_clone.log b/tapeout/logs/git_clone.log
new file mode 100644
index 0000000..7191ee3
--- /dev/null
+++ b/tapeout/logs/git_clone.log
@@ -0,0 +1,20 @@
+https://github.com/dineshannayya/riscduino_qcore.git
+Cloning into '/root/project'...
+Note: switching to '7764ef40a007aa7e18c93005922bf01a9b39dba3'.
+
+You are in 'detached HEAD' state. You can look around, make experimental
+changes and commit them, and you can discard any commits you make in this
+state without impacting any branches by switching back to a branch.
+
+If you want to create a new branch to retain commits you create, you may
+do so (now or later) by using -c with the switch command. Example:
+
+  git switch -c <new-branch-name>
+
+Or undo this operation with:
+
+  git switch -
+
+Turn off this advice by setting config variable advice.detachedHead to false
+
+HEAD is now at 7764ef4 bus repeater + peri_top + ws281x pad direction bug fix
diff --git a/tapeout/logs/klayout_beol.log b/tapeout/logs/klayout_beol.log
new file mode 100644
index 0000000..a02a56b
--- /dev/null
+++ b/tapeout/logs/klayout_beol.log
@@ -0,0 +1,1005 @@
+/opt/scripts/tech/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/scripts/tech/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/scripts/tech/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/scripts/tech/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/scripts/tech/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/scripts/tech/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/scripts/tech/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/scripts/tech/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/scripts/tech/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/scripts/tech/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 2579846 (flat)  4740 (hierarchical)
+    Elapsed: 0.480s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:125
+    Polygons (raw): 424241 (flat)  1037 (hierarchical)
+    Elapsed: 0.330s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:126
+    Polygons (raw): 1300406 (flat)  1472 (hierarchical)
+    Elapsed: 0.290s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:127
+    Polygons (raw): 856 (flat)  37 (hierarchical)
+    Elapsed: 0.020s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:128
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:129
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:130
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:131
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:132
+    Polygons (raw): 1177713 (flat)  708 (hierarchical)
+    Elapsed: 0.280s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:133
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:134
+    Polygons (raw): 54311 (flat)  575 (hierarchical)
+    Elapsed: 0.020s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:135
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:136
+    Polygons (raw): 5945 (flat)  38 (hierarchical)
+    Elapsed: 0.010s  Memory: 2632.00M
+"polygons" in: sky130A_mr.drc:137
+    Polygons (raw): 4094367 (flat)  11624 (hierarchical)
+    Elapsed: 0.330s  Memory: 2633.00M
+"polygons" in: sky130A_mr.drc:138
+    Polygons (raw): 33 (flat)  16 (hierarchical)
+    Elapsed: 0.020s  Memory: 2633.00M
+"polygons" in: sky130A_mr.drc:139
+    Polygons (raw): 1668082 (flat)  2018 (hierarchical)
+    Elapsed: 0.290s  Memory: 2633.00M
+"polygons" in: sky130A_mr.drc:140
+    Polygons (raw): 1535004 (flat)  1824 (hierarchical)
+    Elapsed: 0.300s  Memory: 2633.00M
+"polygons" in: sky130A_mr.drc:141
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+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/tapeout/4e5845c8-ff91-41de-9bb7-4309b0385c0a/outputs/klayout_beol_report.xml ..
+Total elapsed: 5167.880s  Memory: 10071.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/tapeout/logs/klayout_feol.log b/tapeout/logs/klayout_feol.log
new file mode 100644
index 0000000..0166e0e
--- /dev/null
+++ b/tapeout/logs/klayout_feol.log
@@ -0,0 +1,817 @@
+/opt/scripts/tech/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/scripts/tech/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/scripts/tech/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/scripts/tech/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/scripts/tech/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/scripts/tech/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/scripts/tech/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/scripts/tech/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/scripts/tech/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/scripts/tech/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
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+DRC section
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+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6739.00M
+"separation" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6739.00M
+"not_interacting" in: sky130A_mr.drc:388
+    Polygons (raw): 28599 (flat)  16940 (hierarchical)
+    Elapsed: 0.600s  Memory: 6739.00M
+"separation" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6739.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
+"not" in: sky130A_mr.drc:688
+    Polygons (raw): 54311 (flat)  575 (hierarchical)
+    Elapsed: 0.110s  Memory: 6739.00M
+"width" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.120s  Memory: 6739.00M
+"space" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.320s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6739.00M
+END: 75/20 (hvi)
+START: 125/20 (hvntm)
+"not" in: sky130A_mr.drc:695
+    Polygons (raw): 33 (flat)  16 (hierarchical)
+    Elapsed: 0.050s  Memory: 6739.00M
+"width" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.370s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6739.00M
+"space" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 6739.00M
+"output" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6739.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/tapeout/4e5845c8-ff91-41de-9bb7-4309b0385c0a/outputs/klayout_feol_report.xml ..
+Total elapsed: 2318.050s  Memory: 6723.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/tapeout/logs/klayout_fom_density.log b/tapeout/logs/klayout_fom_density.log
new file mode 100644
index 0000000..493147c
--- /dev/null
+++ b/tapeout/logs/klayout_fom_density.log
@@ -0,0 +1,58 @@
+fom_density.drc:: sourcing design file=/mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/tapeout/4e5845c8-ff91-41de-9bb7-4309b0385c0a/outputs/caravel_000710d6.oas topcell=caravel_000710d6 ...
+done.
+flattening chip boundary...
+done.
+step size = 70.0
+llx=5.964999999999999 lly=5.999999999999999 urx=3594.0349999999994 ury=5193.999999999999
+x_cnt = 51
+y_cnt = 74
+dbu = 0.0009999999999999998
+bbox_area = 18614907.159999993
+calculating subtile areas (= 3774)...
+tiles per step = 10
+calculating window step densities (= 2730)...
+{{ CHECK }} 0/2730
+{{ CHECK }} 65/2730
+{{ CHECK }} 130/2730
+{{ CHECK }} 195/2730
+{{ CHECK }} 260/2730
+{{ CHECK }} 325/2730
+{{ CHECK }} 390/2730
+{{ CHECK }} 455/2730
+{{ CHECK }} 520/2730
+{{ CHECK }} 585/2730
+{{ CHECK }} 650/2730
+{{ CHECK }} 715/2730
+{{ CHECK }} 780/2730
+{{ CHECK }} 845/2730
+{{ CHECK }} 910/2730
+{{ CHECK }} 975/2730
+{{ CHECK }} 1040/2730
+{{ CHECK }} 1105/2730
+{{ CHECK }} 1170/2730
+{{ CHECK }} 1235/2730
+{{ CHECK }} 1300/2730
+{{ CHECK }} 1365/2730
+{{ CHECK }} 1430/2730
+{{ CHECK }} 1495/2730
+{{ CHECK }} 1560/2730
+{{ CHECK }} 1625/2730
+{{ CHECK }} 1690/2730
+{{ CHECK }} 1755/2730
+{{ CHECK }} 1820/2730
+{{ CHECK }} 1885/2730
+{{ CHECK }} 1950/2730
+{{ CHECK }} 2015/2730
+{{ CHECK }} 2080/2730
+{{ CHECK }} 2145/2730
+{{ CHECK }} 2210/2730
+{{ CHECK }} 2275/2730
+{{ CHECK }} 2340/2730
+{{ CHECK }} 2405/2730
+{{ CHECK }} 2470/2730
+{{ CHECK }} 2535/2730
+{{ CHECK }} 2600/2730
+{{ CHECK }} 2665/2730
+minimum fom density  = 0.3556
+maximum fom density  = 0.4988
+finish received: success = true
diff --git a/tapeout/logs/klayout_gds2oas.log b/tapeout/logs/klayout_gds2oas.log
new file mode 100644
index 0000000..42dcd5f
--- /dev/null
+++ b/tapeout/logs/klayout_gds2oas.log
@@ -0,0 +1 @@
+[INFO] Changing from /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/tapeout/4e5845c8-ff91-41de-9bb7-4309b0385c0a/outputs/caravel_000710d6.gds to /mnt/uffs/user/u5295_dinesha/design/riscduino-qcore_q2_3/jobs/tapeout/4e5845c8-ff91-41de-9bb7-4309b0385c0a/outputs/caravel_000710d6.oas
diff --git a/tapeout/logs/klayout_met_density.log b/tapeout/logs/klayout_met_density.log
new file mode 100644
index 0000000..3777718
--- /dev/null
+++ b/tapeout/logs/klayout_met_density.log
@@ -0,0 +1,6 @@
+li1_ca_density is 0.4604546745804218
+m1_ca_density is 0.5562916782143921
+m2_ca_density is 0.5965317630382055
+m3_ca_density is 0.5544283406112225
+m4_ca_density is 0.47952470873175324
+m5_ca_density is 0.511630876809218
diff --git a/tapeout/logs/klayout_missing_cells.log b/tapeout/logs/klayout_missing_cells.log
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tapeout/logs/klayout_missing_cells.log
diff --git a/tapeout/logs/klayout_zero_area.log b/tapeout/logs/klayout_zero_area.log
new file mode 100644
index 0000000..5305848
--- /dev/null
+++ b/tapeout/logs/klayout_zero_area.log
@@ -0,0 +1,4 @@
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	 3584284 kB
+VmHWM:	 2993996 kB
diff --git a/tapeout/logs/missing_cells.info b/tapeout/logs/missing_cells.info
new file mode 100644
index 0000000..bc59c12
--- /dev/null
+++ b/tapeout/logs/missing_cells.info
@@ -0,0 +1 @@
+False
diff --git a/tapeout/logs/oasis.info b/tapeout/logs/oasis.info
new file mode 100644
index 0000000..97126dd
--- /dev/null
+++ b/tapeout/logs/oasis.info
@@ -0,0 +1 @@
+caravel_000710d6.oas: fba433da964414574d0a3d6ee6e7b8bd6eb2bb69
\ No newline at end of file
diff --git a/tapeout/logs/pdks.info b/tapeout/logs/pdks.info
new file mode 100644
index 0000000..a007d09
--- /dev/null
+++ b/tapeout/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+sky130A PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/tapeout/logs/rram.info b/tapeout/logs/rram.info
new file mode 100644
index 0000000..bc59c12
--- /dev/null
+++ b/tapeout/logs/rram.info
@@ -0,0 +1 @@
+False
diff --git a/tapeout/logs/set_user_id.log b/tapeout/logs/set_user_id.log
new file mode 100644
index 0000000..cae5b87
--- /dev/null
+++ b/tapeout/logs/set_user_id.log
@@ -0,0 +1,10 @@
+Project Chip ID is: 463062
+Setting Project Chip ID to: 000710d6
+Step 1: Modify Layout of the user_id_programming subcell
+Done!
+Step 2: Add user project ID parameter to source verilog.
+Done!
+Step 3: Add user project ID parameter to gate-level verilog.
+Done!
+Step 4: Add user project ID text to top level layout.
+Done!
diff --git a/tapeout/logs/ship_truck.log b/tapeout/logs/ship_truck.log
new file mode 100644
index 0000000..d3fa680
--- /dev/null
+++ b/tapeout/logs/ship_truck.log
@@ -0,0 +1,2227 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/mag2gds.tcl" from command line.
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+Scaled magic input cell user_id_textblock geometry by factor of 2
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+Processing timestamp mismatches: simple_por.
+Scaled magic input cell caravel_motto geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 24
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_49 geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_68 geometry by factor of 24
+Scaled magic input cell font_54 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_69 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_56 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_35 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_4F geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+Scaled magic input cell alpha_0 geometry by factor of 2
+Scaled magic input cell alpha_7 geometry by factor of 72
+Scaled magic input cell alpha_1 geometry by factor of 72
+Scaled magic input cell alpha_D geometry by factor of 72
+Scaled magic input cell alpha_6 geometry by factor of 72
+caravel_clocking: 10000 rects
+caravel_clocking: 20000 rects
+caravel_clocking: 30000 rects
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+housekeeping: 360000 rects
+housekeeping: 370000 rects
+housekeeping: 380000 rects
+housekeeping: 390000 rects
+housekeeping: 400000 rects
+housekeeping: 410000 rects
+housekeeping: 420000 rects
+housekeeping: 430000 rects
+housekeeping: 440000 rects
+housekeeping: 450000 rects
+housekeeping: 460000 rects
+housekeeping: 470000 rects
+housekeeping: 480000 rects
+housekeeping: 490000 rects
+housekeeping: 500000 rects
+housekeeping: 510000 rects
+housekeeping: 520000 rects
+digital_pll: 10000 rects
+digital_pll: 20000 rects
+mgmt_protect: 10000 rects
+mgmt_protect: 20000 rects
+mgmt_protect: 30000 rects
+mgmt_protect: 40000 rects
+mgmt_protect: 50000 rects
+mgmt_protect: 60000 rects
+mgmt_protect: 70000 rects
+mgmt_protect: 80000 rects
+mgmt_protect: 90000 rects
+mgmt_protect: 100000 rects
+mgmt_protect: 110000 rects
+mgmt_protect: 120000 rects
+mgmt_protect: 130000 rects
+mgmt_protect: 140000 rects
+mgmt_protect: 150000 rects
+mgmt_protect: 160000 rects
+mgmt_protect: 170000 rects
+mgmt_protect: 180000 rects
+mgmt_protect: 190000 rects
+mgmt_protect: 200000 rects
+mgmt_protect: 210000 rects
+mgmt_protect: 220000 rects
+mgmt_protect: 230000 rects
+mgmt_protect: 240000 rects
+mgmt_protect: 250000 rects
+mgmt_protect: 260000 rects
+mgmt_protect: 270000 rects
+mgmt_protect: 280000 rects
+mgmt_protect: 290000 rects
+mgmt_protect: 300000 rects
+mgmt_protect: 310000 rects
+mgmt_protect: 320000 rects
+mgmt_protect: 330000 rects
+mgmt_protect: 340000 rects
+mgmt_protect: 350000 rects
+mgmt_protect: 360000 rects
+mgmt_protect: 370000 rects
+mgmt_protect: 380000 rects
+mgmt_protect: 390000 rects
+mgmt_protect: 400000 rects
+sky130_fd_io__corner_bus_overlay: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 20000 rects
+sky130_fd_io__top_ground_hvc_wpad: 30000 rects
+sky130_fd_io__top_ground_hvc_wpad: 40000 rects
+sky130_fd_io__top_ground_hvc_wpad: 50000 rects
+sky130_fd_io__top_ground_hvc_wpad: 60000 rects
+sky130_fd_io__top_ground_hvc_wpad: 70000 rects
+sky130_fd_io__top_ground_hvc_wpad: 80000 rects
+sky130_fd_io__top_ground_hvc_wpad: 90000 rects
+sky130_fd_io__top_ground_hvc_wpad: 100000 rects
+sky130_fd_io__top_ground_hvc_wpad: 110000 rects
+sky130_fd_io__top_ground_hvc_wpad: 120000 rects
+sky130_fd_io__top_ground_hvc_wpad: 130000 rects
+sky130_fd_io__top_ground_hvc_wpad: 140000 rects
+sky130_fd_io__top_ground_hvc_wpad: 150000 rects
+sky130_fd_io__top_ground_hvc_wpad: 160000 rects
+sky130_fd_io__top_ground_hvc_wpad: 170000 rects
+sky130_fd_io__top_ground_hvc_wpad: 180000 rects
+sky130_fd_io__top_ground_hvc_wpad: 190000 rects
+sky130_fd_io__top_ground_hvc_wpad: 200000 rects
+sky130_fd_io__top_ground_hvc_wpad: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180851 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808336 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808666 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808678 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808679 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180839 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808671 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808672 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808663 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808660 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808675 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808676 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808662 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808661 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__genrivetdlring__example_559591418082 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__gendlring__example_559591418081 geometry by factor of 2
+sky130_fd_io__top_xres4v2: 10000 rects
+sky130_fd_io__top_xres4v2: 20000 rects
+sky130_fd_io__top_xres4v2: 30000 rects
+sky130_fd_io__top_xres4v2: 40000 rects
+sky130_fd_io__top_xres4v2: 50000 rects
+sky130_fd_io__top_xres4v2: 60000 rects
+sky130_fd_io__top_xres4v2: 70000 rects
+sky130_fd_io__top_xres4v2: 80000 rects
+sky130_fd_io__top_xres4v2: 90000 rects
+sky130_fd_io__top_xres4v2: 100000 rects
+sky130_fd_io__top_xres4v2: 110000 rects
+sky130_fd_io__top_xres4v2: 120000 rects
+sky130_fd_io__top_xres4v2: 130000 rects
+sky130_fd_io__top_xres4v2: 140000 rects
+sky130_fd_io__top_xres4v2: 150000 rects
+sky130_fd_io__top_xres4v2: 160000 rects
+sky130_fd_io__top_xres4v2: 170000 rects
+sky130_fd_io__top_xres4v2: 180000 rects
+sky130_fd_io__top_xres4v2: 190000 rects
+sky130_fd_io__top_xres4v2: 200000 rects
+sky130_fd_io__top_xres4v2: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808719 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808765 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808717 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808243 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180890 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808264 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180858 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180833 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_55959141808288 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180859 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808289 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808274 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808728 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808727 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808726 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808725 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808724 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808554 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808553 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808552 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808551 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808402 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808350 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808261 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808260 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808259 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808400 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808372 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808326 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808290 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808128 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808127 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180897 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180819 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808147 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808157 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808156 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808155 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808154 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808153 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808152 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808151 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808150 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808149 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808148 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808158 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808137 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808370 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808316 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808385 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418088 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808612 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180848 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180849 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m2m3__example_55959141808714 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2s_cdns_55959141808652 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2o_cdns_55959141808653 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808659 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__pfet_01v8__example_55959141808657 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808202 geometry by factor of 2
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 10000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 20000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 30000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808273 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808740 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808739 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808738 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808737 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808736 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808735 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808734 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808733 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808732 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808731 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808730 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808752 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808751 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808750 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808749 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808748 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808747 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808746 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808745 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808744 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808743 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808742 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808741 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808324 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808270 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808187 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808338 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808337 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808700 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808559 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808729 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_p_em1c_cdns_55959141808753 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180860 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180857 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 50000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808649 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808646 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808378 geometry by factor of 2
+sky130_fd_io__xres4v2_in_buf: 10000 rects
+sky130_fd_io__xres4v2_in_buf: 20000 rects
+sky130_fd_io__xres4v2_in_buf: 30000 rects
+sky130_fd_io__xres4v2_in_buf: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808782 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808449 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808452 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808233 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180827 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180835 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808242 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180829 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808237 geometry by factor of 2
+sky130_fd_io__top_gpiov2: 10000 rects
+sky130_fd_io__top_gpiov2: 20000 rects
+sky130_fd_io__top_gpiov2: 30000 rects
+sky130_fd_io__top_gpiov2: 40000 rects
+sky130_fd_io__top_gpiov2: 50000 rects
+sky130_fd_io__top_gpiov2: 60000 rects
+sky130_fd_io__top_gpiov2: 70000 rects
+sky130_fd_io__top_gpiov2: 80000 rects
+sky130_fd_io__top_gpiov2: 90000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808418 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808190 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808191 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808517 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808518 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180815 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180816 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180884 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808106 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808504 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180875 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2s_cdns_55959141808438 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2o_cdns_55959141808439 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180882 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180881 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180880 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180879 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180823 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808510 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808394 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808298 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808440 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180878 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808434 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808102 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808115 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808100 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808140 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808280 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808425 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808306 geometry by factor of 2
+sky130_fd_io__gpiov2_amux: 10000 rects
+sky130_fd_io__gpiov2_amux: 20000 rects
+sky130_fd_io__gpiov2_amux: 30000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808178 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808488 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808122 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808123 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808476 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180868 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180869 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808581 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808278 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808462 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808200 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180894 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd__example_55959141808258 geometry by factor of 2
+sky130_fd_io__amux_switch_1v2b: 10000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808563 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808251 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd2__example_55959141808561 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808267 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808266 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808633 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808322 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808321 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808320 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808294 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808325 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808323 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808291 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__pfet_01v8__example_55959141808640 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808194 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808328 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808327 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808272 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808271 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808143 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808275 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808276 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808297 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808296 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808295 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808293 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808292 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808300 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808299 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__nfet_01v8__example_55959141808308 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_55959141808301 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808302 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180854 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808368 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808625 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808373 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808374 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808398 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808397 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808396 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808395 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808401 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808399 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808269 geometry by factor of 2
+sky130_fd_io__gpio_odrvr_subv2: 10000 rects
+sky130_fd_io__gpio_odrvr_subv2: 20000 rects
+sky130_fd_io__gpio_odrvr_subv2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418080 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180832 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180852 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418082 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418085 geometry by factor of 2
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 10000 rects
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 20000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808655 geometry by factor of 2
+sky130_fd_io__top_ground_lvc_wpad: 10000 rects
+sky130_fd_io__top_ground_lvc_wpad: 20000 rects
+sky130_fd_io__top_ground_lvc_wpad: 30000 rects
+sky130_fd_io__top_ground_lvc_wpad: 40000 rects
+sky130_fd_io__top_ground_lvc_wpad: 50000 rects
+sky130_fd_io__top_ground_lvc_wpad: 60000 rects
+sky130_fd_io__top_ground_lvc_wpad: 70000 rects
+sky130_fd_io__top_ground_lvc_wpad: 80000 rects
+sky130_fd_io__top_ground_lvc_wpad: 90000 rects
+sky130_fd_io__top_ground_lvc_wpad: 100000 rects
+sky130_fd_io__top_ground_lvc_wpad: 110000 rects
+sky130_fd_io__top_ground_lvc_wpad: 120000 rects
+sky130_fd_io__top_ground_lvc_wpad: 130000 rects
+sky130_fd_io__top_ground_lvc_wpad: 140000 rects
+sky130_fd_io__top_ground_lvc_wpad: 150000 rects
+sky130_fd_io__top_ground_lvc_wpad: 160000 rects
+sky130_fd_io__top_ground_lvc_wpad: 170000 rects
+sky130_fd_io__top_ground_lvc_wpad: 180000 rects
+sky130_fd_io__top_ground_lvc_wpad: 190000 rects
+sky130_fd_io__top_ground_lvc_wpad: 200000 rects
+sky130_fd_io__top_ground_lvc_wpad: 210000 rects
+sky130_fd_io__top_ground_lvc_wpad: 220000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808684 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808686 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808685 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__gnd2gnd_tap geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808683 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808702 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808682 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808694 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808681 geometry by factor of 2
+sky130_fd_io__overlay_vssio_hvc: 10000 rects
+sky130_fd_io__hvc_clampv2: 10000 rects
+sky130_fd_io__hvc_clampv2: 20000 rects
+sky130_fd_io__hvc_clampv2: 30000 rects
+sky130_fd_io__hvc_clampv2: 40000 rects
+sky130_fd_io__hvc_clampv2: 50000 rects
+sky130_fd_io__hvc_clampv2: 60000 rects
+sky130_fd_io__hvc_clampv2: 70000 rects
+sky130_fd_io__hvc_clampv2: 80000 rects
+sky130_fd_io__hvc_clampv2: 90000 rects
+sky130_fd_io__hvc_clampv2: 100000 rects
+sky130_fd_io__hvc_clampv2: 110000 rects
+sky130_fd_io__hvc_clampv2: 120000 rects
+sky130_fd_io__hvc_clampv2: 130000 rects
+sky130_fd_io__hvc_clampv2: 140000 rects
+sky130_fd_io__hvc_clampv2: 150000 rects
+sky130_fd_io__hvc_clampv2: 160000 rects
+sky130_fd_io__hvc_clampv2: 170000 rects
+sky130_fd_io__hvc_clampv2: 180000 rects
+sky130_fd_io__hvc_clampv2: 190000 rects
+sky130_fd_io__hvc_clampv2: 200000 rects
+sky130_fd_io__hvc_clampv2: 210000 rects
+sky130_fd_io__hvc_clampv2: 220000 rects
+sky130_fd_io__hvc_clampv2: 230000 rects
+sky130_fd_io__hvc_clampv2: 240000 rects
+sky130_fd_io__hvc_clampv2: 250000 rects
+sky130_fd_io__hvc_clampv2: 260000 rects
+sky130_fd_io__hvc_clampv2: 270000 rects
+sky130_fd_io__hvc_clampv2: 280000 rects
+sky130_fd_io__top_power_lvc_wpad: 10000 rects
+sky130_fd_io__top_power_lvc_wpad: 20000 rects
+sky130_fd_io__top_power_lvc_wpad: 30000 rects
+sky130_fd_io__top_power_lvc_wpad: 40000 rects
+sky130_fd_io__top_power_lvc_wpad: 50000 rects
+sky130_fd_io__top_power_lvc_wpad: 60000 rects
+sky130_fd_io__top_power_lvc_wpad: 70000 rects
+sky130_fd_io__top_power_lvc_wpad: 80000 rects
+sky130_fd_io__top_power_lvc_wpad: 90000 rects
+sky130_fd_io__top_power_lvc_wpad: 100000 rects
+sky130_fd_io__top_power_lvc_wpad: 110000 rects
+sky130_fd_io__top_power_lvc_wpad: 120000 rects
+sky130_fd_io__top_power_lvc_wpad: 130000 rects
+sky130_fd_io__top_power_lvc_wpad: 140000 rects
+sky130_fd_io__top_power_lvc_wpad: 150000 rects
+sky130_fd_io__top_power_lvc_wpad: 160000 rects
+sky130_fd_io__top_power_lvc_wpad: 170000 rects
+sky130_fd_io__top_power_lvc_wpad: 180000 rects
+sky130_fd_io__top_power_lvc_wpad: 190000 rects
+sky130_fd_io__top_power_lvc_wpad: 200000 rects
+sky130_fd_io__top_power_lvc_wpad: 210000 rects
+sky130_fd_io__top_power_lvc_wpad: 220000 rects
+sky130_fd_io__top_power_lvc_wpad: 230000 rects
+sky130_fd_io__overlay_vddio_hvc: 10000 rects
+Processing timestamp mismatches: sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__buf_8, sky130_ef_sc_hd__decap_12, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_sc_hd__fill_8, sky130_fd_sc_hd__fill_4, constant_block, sky130_fd_sc_hd__buf_16, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__fill_2, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__corner_pad, sky130_ef_io__com_bus_slice_20um, gpio_control_power_routing, gpio_control_power_routing_right, gpio_control_power_routing_top, gpio_defaults_block_0801, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__inv_12, mprj2_logic_high, mprj_logic_high, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hvl__conb_1, mgmt_protect_hv, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hd__bufbuf_8, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__and3b_4, sky130_fd_sc_hd__and3b_2, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__and2b_4, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, gpio_defaults_block_1800, gpio_defaults_block_0403, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__o21ba_2, sky130_fd_sc_hd__nand4b_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__xor2_2, sky130_fd_sc_hd__a21boi_2, sky130_fd_sc_hd__nand3b_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__clkinv_1, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__nand3_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__nand2b_2, sky130_fd_sc_hd__a211o_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__and2b_2, sky130_fd_sc_hd__xnor2_2, sky130_fd_sc_hd__and4b_2, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__a21o_4, sky130_fd_sc_hd__a21oi_4, sky130_fd_sc_hd__a221o_4, sky130_fd_sc_hd__a221oi_1, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o31a_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__xor2_1, sky130_fd_sc_hd__o21a_4, sky130_fd_sc_hd__nand3b_4, sky130_fd_sc_hd__and4b_4, sky130_fd_sc_hd__a31oi_4, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__a2111oi_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__o41a_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nand4b_1, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__a21boi_1, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__nand2b_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_4, sky130_fd_sc_hd__a2111o_4, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__and4bb_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__dlygate4sd3_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o31ai_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__nand2b_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__mux2_4, gpio_defaults_block_1803, sky130_fd_sc_hd__and2_0, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or2_0, sky130_fd_sc_hd__dfbbn_2, sky130_fd_sc_hd__macro_sparecell, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__a41oi_1, sky130_fd_sc_hd__o2bb2ai_1, sky130_fd_sc_hd__o31ai_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, alpha_6, alpha_D, alpha_1, alpha_7, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__decap_8.
+   Generating output for cell caravel_logo
+   Generating output for cell font_22
+   Generating output for cell font_73
+   Generating output for cell font_43
+   Generating output for cell font_49
+   Generating output for cell font_65
+   Generating output for cell font_68
+   Generating output for cell font_54
+   Generating output for cell font_67
+   Generating output for cell font_6E
+   Generating output for cell font_69
+   Generating output for cell font_6C
+   Generating output for cell font_61
+   Generating output for cell font_53
+   Generating output for cell caravel_motto
+   Generating output for cell font_79
+   Generating output for cell font_76
+   Generating output for cell font_74
+   Generating output for cell font_72
+   Generating output for cell font_70
+   Generating output for cell font_66
+   Generating output for cell font_63
+   Generating output for cell font_62
+   Generating output for cell font_57
+   Generating output for cell font_56
+   Generating output for cell font_50
+   Generating output for cell font_47
+   Generating output for cell font_44
+   Generating output for cell font_35
+   Generating output for cell font_32
+   Generating output for cell font_30
+   Generating output for cell font_29
+   Generating output for cell font_28
+   Generating output for cell font_20
+   Generating output for cell font_6F
+   Generating output for cell font_6B
+   Generating output for cell font_4F
+   Generating output for cell font_4B
+   Generating output for cell font_2D
+   Generating output for cell copyright_block
+   Generating output for cell open_source
+   Generating output for cell sky130_fd_sc_hvl__decap_8
+   Generating output for cell sky130_fd_sc_hvl__decap_4
+   Generating output for cell sky130_fd_sc_hvl__diode_2
+   Generating output for cell sky130_fd_sc_hvl__fill_1
+   Generating output for cell sky130_fd_sc_hvl__fill_2
+   Generating output for cell sky130_fd_sc_hvl__lsbufhv2lv_1
+   Generating output for cell xres_buf
+   Generating output for cell alpha_7
+   Generating output for cell alpha_1
+   Generating output for cell alpha_D
+   Generating output for cell alpha_6
+   Generating output for cell alpha_0
+   Generating output for cell user_id_textblock
+   Generating output for cell sky130_fd_sc_hd__decap_6
+   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__decap_4
+   Generating output for cell sky130_fd_sc_hd__decap_3
+   Generating output for cell sky130_fd_sc_hd__fill_2
+   Generating output for cell sky130_fd_sc_hd__fill_1
+   Generating output for cell sky130_fd_sc_hd__conb_1
+   Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
+   Generating output for cell gpio_defaults_block_1803
+   Generating output for cell sky130_fd_sc_hd__o21bai_1
+   Generating output for cell sky130_fd_sc_hd__nand3b_1
+   Generating output for cell sky130_fd_sc_hd__nand4bb_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_2
+   Generating output for cell sky130_fd_sc_hd__o31ai_2
+   Generating output for cell sky130_fd_sc_hd__o2bb2ai_1
+   Generating output for cell sky130_fd_sc_hd__a41oi_1
+   Generating output for cell sky130_fd_sc_hd__o211ai_4
+   Generating output for cell sky130_fd_sc_hd__nor3b_2
+   Generating output for cell sky130_fd_sc_hd__xnor2_1
+   Generating output for cell sky130_fd_sc_hd__o2111ai_1
+   Generating output for cell sky130_fd_sc_hd__nand3_1
+   Generating output for cell sky130_fd_sc_hd__a31o_1
+   Generating output for cell sky130_fd_sc_hd__o21a_1
+   Generating output for cell sky130_fd_sc_hd__nand2b_1
+   Generating output for cell sky130_fd_sc_hd__o22a_1
+   Generating output for cell sky130_fd_sc_hd__o21ai_1
+   Generating output for cell sky130_fd_sc_hd__a2bb2o_1
+   Generating output for cell sky130_fd_sc_hd__nor2_1
+   Generating output for cell sky130_fd_sc_hd__a21oi_1
+   Generating output for cell sky130_fd_sc_hd__nor3_2
+   Generating output for cell sky130_fd_sc_hd__nor3_1
+   Generating output for cell sky130_fd_sc_hd__nor4_1
+   Generating output for cell sky130_fd_sc_hd__o31ai_1
+   Generating output for cell sky130_fd_sc_hd__a21o_1
+   Generating output for cell sky130_fd_sc_hd__o31a_1
+   Generating output for cell sky130_fd_sc_hd__mux2_1
+   Generating output for cell sky130_fd_sc_hd__dfxtp_1
+   Generating output for cell sky130_fd_sc_hd__dfstp_1
+   Generating output for cell sky130_fd_sc_hd__dfrtp_4
+   Generating output for cell sky130_fd_sc_hd__dfrtn_1
+   Generating output for cell sky130_fd_sc_hd__dfstp_2
+   Generating output for cell sky130_fd_sc_hd__dfrtp_1
+   Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
+   Generating output for cell sky130_fd_sc_hd__buf_12
+   Generating output for cell sky130_fd_sc_hd__o21a_2
+   Generating output for cell sky130_fd_sc_hd__nand2b_2
+   Generating output for cell sky130_fd_sc_hd__o21ai_2
+   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__dfrtp_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_16
+   Generating output for cell sky130_fd_sc_hd__clkbuf_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_1
+   Generating output for cell sky130_fd_sc_hd__nor2_2
+   Generating output for cell sky130_fd_sc_hd__diode_2
+   Generating output for cell sky130_fd_sc_hd__inv_4
+   Generating output for cell sky130_fd_sc_hd__clkinv_4
+   Generating output for cell sky130_fd_sc_hd__inv_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_2
+   Generating output for cell sky130_fd_sc_hd__and2_1
+   Generating output for cell sky130_fd_sc_hd__clkbuf_4
+   Generating output for cell sky130_fd_sc_hd__nand2_1
+   Generating output for cell sky130_fd_sc_hd__buf_4
+   Generating output for cell sky130_fd_sc_hd__decap_8
+   Generating output for cell sky130_ef_sc_hd__decap_12
+   Generating output for cell caravel_clocking
+   Generating output for cell sky130_fd_sc_hd__clkbuf_8
+   Generating output for cell buff_flash_clkrst
+   Generating output for cell sky130_fd_sc_hd__nand2_2
+   Generating output for cell sky130_fd_sc_hd__macro_sparecell
+   Generating output for cell sky130_fd_sc_hd__dfbbn_2
+   Generating output for cell sky130_fd_sc_hd__or2_0
+   Generating output for cell sky130_fd_sc_hd__o21ai_4
+   Generating output for cell sky130_fd_sc_hd__and2_0
+   Generating output for cell sky130_fd_sc_hd__mux2_4
+   Generating output for cell sky130_fd_sc_hd__dlygate4sd3_1
+   Generating output for cell sky130_fd_sc_hd__and2b_2
+   Generating output for cell sky130_fd_sc_hd__and3b_2
+   Generating output for cell sky130_fd_sc_hd__and2_2
+   Generating output for cell sky130_fd_sc_hd__buf_16
+   Generating output for cell gpio_logic_high
+   Generating output for cell gpio_control_block
+   Generating output for cell sky130_fd_sc_hd__dfstp_4
+   Generating output for cell sky130_fd_sc_hd__a32o_1
+   Generating output for cell sky130_fd_sc_hd__a22o_1
+   Generating output for cell sky130_fd_sc_hd__a221o_1
+   Generating output for cell sky130_fd_sc_hd__a211o_4
+   Generating output for cell sky130_fd_sc_hd__a21bo_1
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_1
+   Generating output for cell sky130_fd_sc_hd__a221o_2
+   Generating output for cell sky130_fd_sc_hd__a211o_1
+   Generating output for cell sky130_fd_sc_hd__o21ba_1
+   Generating output for cell sky130_fd_sc_hd__and4b_1
+   Generating output for cell sky130_fd_sc_hd__and4bb_1
+   Generating output for cell sky130_fd_sc_hd__and4bb_2
+   Generating output for cell sky130_fd_sc_hd__and3_4
+   Generating output for cell sky130_fd_sc_hd__nand3_4
+   Generating output for cell sky130_fd_sc_hd__a311o_1
+   Generating output for cell sky130_fd_sc_hd__nor2_4
+   Generating output for cell sky130_fd_sc_hd__nor2_8
+   Generating output for cell sky130_fd_sc_hd__o221a_1
+   Generating output for cell sky130_fd_sc_hd__a2111o_1
+   Generating output for cell sky130_fd_sc_hd__nor4_2
+   Generating output for cell sky130_fd_sc_hd__a2111o_4
+   Generating output for cell sky130_fd_sc_hd__nor4_4
+   Generating output for cell sky130_fd_sc_hd__a2111o_2
+   Generating output for cell sky130_fd_sc_hd__nand2b_4
+   Generating output for cell sky130_fd_sc_hd__and3_1
+   Generating output for cell sky130_fd_sc_hd__o32a_1
+   Generating output for cell sky130_fd_sc_hd__a21boi_1
+   Generating output for cell sky130_fd_sc_hd__nand4_1
+   Generating output for cell sky130_fd_sc_hd__o311a_1
+   Generating output for cell sky130_fd_sc_hd__o211a_1
+   Generating output for cell sky130_fd_sc_hd__o2111a_1
+   Generating output for cell sky130_fd_sc_hd__nand4b_1
+   Generating output for cell sky130_fd_sc_hd__a31oi_1
+   Generating output for cell sky130_fd_sc_hd__and4_1
+   Generating output for cell sky130_fd_sc_hd__a41o_1
+   Generating output for cell sky130_fd_sc_hd__and2b_1
+   Generating output for cell sky130_fd_sc_hd__a311oi_2
+   Generating output for cell sky130_fd_sc_hd__o41a_1
+   Generating output for cell sky130_fd_sc_hd__nor3b_1
+   Generating output for cell sky130_fd_sc_hd__a2111oi_1
+   Generating output for cell sky130_fd_sc_hd__nand4b_4
+   Generating output for cell sky130_fd_sc_hd__a31oi_4
+   Generating output for cell sky130_fd_sc_hd__and4b_4
+   Generating output for cell sky130_fd_sc_hd__nand3b_4
+   Generating output for cell sky130_fd_sc_hd__o21a_4
+   Generating output for cell sky130_fd_sc_hd__xor2_1
+   Generating output for cell sky130_fd_sc_hd__nor3_4
+   Generating output for cell sky130_fd_sc_hd__o221a_4
+   Generating output for cell sky130_fd_sc_hd__mux2_8
+   Generating output for cell sky130_fd_sc_hd__o31a_4
+   Generating output for cell sky130_fd_sc_hd__and4_2
+   Generating output for cell sky130_fd_sc_hd__a221oi_1
+   Generating output for cell sky130_fd_sc_hd__a221o_4
+   Generating output for cell sky130_fd_sc_hd__a21oi_4
+   Generating output for cell sky130_fd_sc_hd__a21o_4
+   Generating output for cell sky130_fd_sc_hd__inv_6
+   Generating output for cell sky130_fd_sc_hd__a31o_2
+   Generating output for cell sky130_fd_sc_hd__nand4_2
+   Generating output for cell sky130_fd_sc_hd__and4b_2
+   Generating output for cell sky130_fd_sc_hd__xnor2_2
+   Generating output for cell sky130_fd_sc_hd__a21oi_2
+   Generating output for cell sky130_fd_sc_hd__a211o_2
+   Generating output for cell sky130_fd_sc_hd__and3_2
+   Generating output for cell sky130_fd_sc_hd__o211a_2
+   Generating output for cell sky130_fd_sc_hd__o31a_2
+   Generating output for cell sky130_fd_sc_hd__nand3_2
+   Generating output for cell sky130_fd_sc_hd__a21o_2
+   Generating output for cell sky130_fd_sc_hd__a22o_2
+   Generating output for cell sky130_fd_sc_hd__mux2_2
+   Generating output for cell sky130_fd_sc_hd__and2b_4
+   Generating output for cell sky130_fd_sc_hd__and3b_1
+   Generating output for cell sky130_fd_sc_hd__and3b_4
+   Generating output for cell sky130_fd_sc_hd__and2_4
+   Generating output for cell sky130_fd_sc_hd__nand2_4
+   Generating output for cell sky130_fd_sc_hd__nand2_8
+   Generating output for cell sky130_fd_sc_hd__buf_6
+   Generating output for cell sky130_fd_sc_hd__buf_8
+   Generating output for cell housekeeping
+   Generating output for cell sky130_fd_sc_hd__einvp_1
+   Generating output for cell sky130_fd_sc_hd__clkinv_1
+   Generating output for cell sky130_fd_sc_hd__einvn_4
+   Generating output for cell sky130_fd_sc_hd__einvn_8
+   Generating output for cell sky130_fd_sc_hd__einvp_2
+   Generating output for cell sky130_fd_sc_hd__or2_2
+   Generating output for cell sky130_fd_sc_hd__a32o_2
+   Generating output for cell sky130_fd_sc_hd__o2111a_2
+   Generating output for cell sky130_fd_sc_hd__o22a_2
+   Generating output for cell sky130_fd_sc_hd__o221a_2
+   Generating output for cell sky130_fd_sc_hd__nand3b_2
+   Generating output for cell sky130_fd_sc_hd__a21boi_2
+   Generating output for cell sky130_fd_sc_hd__xor2_2
+   Generating output for cell sky130_fd_sc_hd__o2bb2a_2
+   Generating output for cell sky130_fd_sc_hd__nand4b_2
+   Generating output for cell sky130_fd_sc_hd__o21ba_2
+   Generating output for cell sky130_fd_sc_hd__o32a_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_8
+   Generating output for cell digital_pll
+   Generating output for cell user_id_programming
+   Generating output for cell simple_por
+Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "sky130_fd_sc_hvl__schmittbuf_1".
+Reading "sky130_fd_sc_hvl__buf_8".
+Reading "sky130_fd_sc_hvl__inv_8".
+Reading "sky130_fd_sc_hvl__fill_4".
+Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+   Generating output for cell mgmt_core_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__dlxtp_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "RAM256".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__a32oi_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a41oi_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o32ai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "RAM128".
+Reading "mgmt_core_wrapper".
+   Generating output for cell gpio_defaults_block_0403
+   Generating output for cell gpio_defaults_block_1800
+   Generating output for cell sky130_fd_sc_hd__inv_8
+   Generating output for cell sky130_fd_sc_hd__dfbbp_1
+   Generating output for cell spare_logic_block
+   Generating output for cell sky130_fd_sc_hd__bufbuf_8
+   Generating output for cell sky130_fd_sc_hvl__conb_1
+   Generating output for cell mgmt_protect_hv
+   Generating output for cell mprj_logic_high
+   Generating output for cell mprj2_logic_high
+   Generating output for cell sky130_fd_sc_hd__inv_12
+   Generating output for cell mgmt_protect
+   Generating output for cell gpio_defaults_block_0801
+   Generating output for cell gpio_control_power_routing_top
+   Generating output for cell gpio_control_power_routing_right
+   Generating output for cell gpio_control_power_routing
+   Generating output for cell caravel_power_routing
+   Generating output for cell user_project_wrapper
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "ycr_core_top".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "ycr4_iconnect".
+Reading "bus_rep_west".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "ycr_intf".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "peri_top".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "qspim_top".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+Reading "bus_rep_east".
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__dlclkp_2".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "wb_host".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "uart_i2c_usb_spi_top".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "pinmux_top".
+Reading "bus_rep_south".
+Reading "bus_rep_north".
+Reading "user_project_wrapper".
+   Generating output for cell sky130_ef_io__com_bus_slice_20um
+   Generating output for cell sky130_fd_io__corner_bus_overlay
+   Generating output for cell sky130_ef_io__corner_pad
+   Generating output for cell sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
+   Generating output for cell sky130_ef_io__com_bus_slice_1um
+   Generating output for cell sky130_ef_io__com_bus_slice_5um
+   Generating output for cell sky130_ef_io__com_bus_slice_10um
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180851
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808664
+   Generating output for cell sky130_fd_io__sio_clamp_pcap_4x5
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808680
+   Generating output for cell sky130_fd_io__esd_rcclamp_nfetcap
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808336
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808666
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808665
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808678
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808679
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808677
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180839
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808667
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808671
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808672
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808673
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808663
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808660
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808670
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808668
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808675
+   Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808676
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808674
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808662
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808661
+   Generating output for cell sky130_fd_pr__via_l1m1__example_559591418084
+   Generating output for cell sky130_fd_pr__genrivetdlring__example_559591418082
+   Generating output for cell sky130_fd_pr__gendlring__example_559591418081
+   Generating output for cell sky130_fd_pr__padplhp__example_559591418080
+   Generating output for cell sky130_fd_io__pad_esd
+   Generating output for cell sky130_fd_io__com_bus_slice
+   Generating output for cell sky130_fd_io__com_bus_hookup
+   Generating output for cell sky130_fd_io__com_busses_esd
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808669
+   Generating output for cell sky130_fd_io__top_ground_hvc_wpad
+   Generating output for cell sky130_fd_io__overlay_vssa_hvc
+   Generating output for cell sky130_ef_io__hvc_vdda_overlay
+   Generating output for cell sky130_ef_io__vssa_hvc_clamped_pad
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808719
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808767
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808765
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808764
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808720
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808718
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808717
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808716
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808243
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808723
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808722
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180890
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808721
+   Generating output for cell sky130_fd_io__xres_inv_hysv2
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180838
+   Generating output for cell sky130_fd_io__tk_tie_r_out_esd
+   Generating output for cell sky130_fd_io__res250_sub_small
+   Generating output for cell sky130_fd_io__res250only_small
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808264
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180858
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180833
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180864
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808715
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180863
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180862
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808288
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180859
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808289
+   Generating output for cell sky130_fd_io__com_res_weak_v2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808274
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808728
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808727
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808726
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808725
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808724
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808554
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808553
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808552
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808551
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808402
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808350
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808261
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808260
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808259
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808400
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808372
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808326
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808290
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808128
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808127
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180897
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180819
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808555
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808147
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808157
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808156
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808155
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808154
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808153
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808152
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808151
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808150
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808149
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808148
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808158
+   Generating output for cell sky130_fd_io__signal_5_sym_hv_local_5term
+   Generating output for cell sky130_fd_io__gpio_buf_localesdv2
+   Generating output for cell sky130_fd_pr__via_pol1__example_559591418083
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808137
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418086
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808371
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808370
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808369
+   Generating output for cell sky130_fd_io__hvsbt_inv_x1
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808316
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808421
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808385
+   Generating output for cell sky130_fd_pr__dfl1sd__example_559591418088
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808422
+   Generating output for cell sky130_fd_io__hvsbt_inv_x2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808612
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808616
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808615
+   Generating output for cell sky130_fd_io__hvsbt_inv_x4
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180848
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180849
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808766
+   Generating output for cell sky130_fd_pr__via_m2m3__example_55959141808714
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418081
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808652
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808653
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180812
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180811
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418086
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418084
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808659
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808658
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808657
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808202
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strong_axres4v2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808273
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808740
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808739
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808738
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808737
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808736
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808735
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808734
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808733
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808732
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808731
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808730
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808752
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808751
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808750
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808749
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808748
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808747
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808746
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808745
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808744
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808743
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808742
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808741
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808324
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808270
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808187
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808755
+   Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808754
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808338
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808337
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808763
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808700
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808559
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808762
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808729
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
+   Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
+   Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
+   Generating output for cell sky130_fd_io__xres_p_em1c_cdns_55959141808753
+   Generating output for cell sky130_fd_io__xres2v2_rcfilter_lpfv2
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180860
+   Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180861
+   Generating output for cell sky130_fd_io__com_res_weak_bentbigres
+   Generating output for cell sky130_fd_io__com_res_weak
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180857
+   Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808649
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808651
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808650
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808648
+   Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808646
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808647
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808645
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808378
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_xres4v2
+   Generating output for cell sky130_fd_io__top_gpio_pad
+   Generating output for cell sky130_fd_io__com_busses
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808768
+   Generating output for cell sky130_fd_pr__res_bent_nd__example_55959141808769
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808787
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808786
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808782
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808785
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808449
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808784
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808452
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808783
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808781
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808780
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808779
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808233
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180827
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808778
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180835
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808777
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808776
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808775
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808242
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808774
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180829
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808773
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808237
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808772
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808771
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808770
+   Generating output for cell sky130_fd_io__tap_1
+   Generating output for cell sky130_fd_io__inv_1
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_559591418085
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418089
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418087
+   Generating output for cell sky130_fd_io__hvsbt_nand2
+   Generating output for cell sky130_fd_io__xres4v2_in_buf
+   Generating output for cell sky130_fd_io__top_xres4v2
+   Generating output for cell sky130_fd_sc_hd__fill_4
+   Generating output for cell sky130_fd_sc_hd__fill_8
+   Generating output for cell constant_block
+   Generating output for cell sky130_fd_io__res75only_small
+   Generating output for cell sky130_fd_io__com_bus_slice_m4
+   Generating output for cell sky130_fd_io__overlay_gpiov2_m4
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808420
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808419
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808418
+   Generating output for cell sky130_fd_io__hvsbt_nor
+   Generating output for cell sky130_fd_io__hvsbt_nand2v2
+   Generating output for cell sky130_fd_io__gpiov2_ictl_logic
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808190
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808611
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180811
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808549
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808548
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808191
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808189
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808517
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808518
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808610
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808609
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180815
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180816
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808608
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808604
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808533
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808529
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180884
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808230
+   Generating output for cell sky130_fd_io__gpiov2_in_buf
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808537
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808106
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808481
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808607
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808504
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808600
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808550
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808528
+   Generating output for cell sky130_fd_io__gpiov2_ipath_hvls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808595
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180825
+   Generating output for cell sky130_fd_io__gpiov2_inbuf_lvinv_x1
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180812
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808599
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808598
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808597
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808596
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808547
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808546
+   Generating output for cell sky130_fd_io__gpiov2_ipath_lvls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808606
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180875
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808605
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808540
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808603
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808602
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808601
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808535
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808527
+   Generating output for cell sky130_fd_io__gpiov2_vcchib_in_buf
+   Generating output for cell sky130_fd_io__gpiov2_ibuf_se
+   Generating output for cell sky130_fd_io__gpiov2_buf_localesd
+   Generating output for cell sky130_fd_io__gpiov2_ipath
+   Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808438
+   Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808439
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180882
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180881
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180880
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180879
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808430
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180823
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180822
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180813
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808624
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808510
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808623
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808622
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808621
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808620
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808619
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808618
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808116
+   Generating output for cell sky130_fd_io__com_ctl_lsv2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808394
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808298
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808440
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180878
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808434
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808435
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808433
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808432
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808102
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808431
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808115
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808429
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808428
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808100
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808140
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808427
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808426
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808280
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808425
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808424
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808423
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808306
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808383
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808382
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808380
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808379
+   Generating output for cell sky130_fd_io__com_ctl_ls_v2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808617
+   Generating output for cell sky130_fd_io__com_ctl_ls_en_1_v2
+   Generating output for cell sky130_fd_io__com_ctl_ls_1v2
+   Generating output for cell sky130_fd_io__gpiov2_ctl_lsbank
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808614
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808613
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8v2
+   Generating output for cell sky130_fd_io__hvsbt_inv_x8
+   Generating output for cell sky130_fd_io__com_ctl_ls
+   Generating output for cell sky130_fd_io__com_ctl_hldv2
+   Generating output for cell sky130_fd_io__gpiov2_ctl
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808178
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808591
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808594
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808593
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808488
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808592
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808586
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808122
+   Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808123
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808477
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808476
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808475
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808589
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808570
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808569
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808588
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808587
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808590
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808460
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808468
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808467
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808466
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808465
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808464
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808463
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_ls
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_inv_1
+   Generating output for cell sky130_fd_io__gpiov2_amux_ls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808573
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808572
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808579
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808578
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808577
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808576
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808566
+   Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180868
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180869
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808565
+   Generating output for cell sky130_fd_io__gpiov2_amx_pucsd_inv
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808441
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808571
+   Generating output for cell sky130_fd_io__gpiov2_amx_inv4
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808567
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808568
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv2
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808581
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808580
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808278
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808462
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808583
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808582
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808498
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808497
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808496
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr_ls
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808574
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808575
+   Generating output for cell sky130_fd_io__amx_inv1
+   Generating output for cell sky130_fd_io__gpiov2_amux_drvr
+   Generating output for cell sky130_fd_io__xor2_1
+   Generating output for cell sky130_fd_io__nor2_1
+   Generating output for cell sky130_fd_io__nand2_1
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808200
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808457
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808451
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808450
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180894
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808584
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808455
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808447
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808445
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808248
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand5
+   Generating output for cell sky130_fd_pr__dfm1sd__example_55959141808258
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808585
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808446
+   Generating output for cell sky130_fd_io__gpiov2_amux_nand4
+   Generating output for cell sky130_fd_io__gpiov2_amux_decoder
+   Generating output for cell sky130_fd_io__gpiov2_amux_ctl_logic
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808563
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808564
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808562
+   Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808251
+   Generating output for cell sky130_fd_pr__dfm1sd2__example_55959141808561
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808560
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808558
+   Generating output for cell sky130_fd_io__amux_switch_1v2b
+   Generating output for cell sky130_fd_io__gpiov2_amux
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808416
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808417
+   Generating output for cell sky130_fd_io__hvsbt_xorv2
+   Generating output for cell sky130_fd_io__hvsbt_xor
+   Generating output for cell sky130_fd_io__com_ctl_ls_octl
+   Generating output for cell sky130_fd_io__gpiov2_octl
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808267
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808266
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808642
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808184
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808141
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808643
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808183
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808139
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808636
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808635
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808634
+   Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808633
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808632
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808630
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808638
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808637
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr3
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808629
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808628
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808627
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808626
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808354
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808631
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180888
+   Generating output for cell sky130_fd_io__gpiov2_octl_mux
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808322
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808321
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808320
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808294
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808325
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808323
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808291
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808641
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808640
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808639
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808348
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808347
+   Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808194
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808346
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808345
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808344
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808343
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808334
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808333
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808332
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808331
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808330
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808329
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808304
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808134
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808328
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808327
+   Generating output for cell sky130_fd_io__com_pdpredrvr_pbiasv2
+   Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808272
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808271
+   Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808143
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808142
+   Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808101
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808144
+   Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_5595914180899
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808275
+   Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808276
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808286
+   Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808285
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808284
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808283
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808644
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808287
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808282
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808281
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a
+   Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808297
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808296
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808295
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808293
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808292
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808300
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808299
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808319
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808318
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808317
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808315
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808314
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808313
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808312
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808311
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808310
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808309
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808308
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808307
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808305
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808303
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808301
+   Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808302
+   Generating output for cell sky130_fd_io__feascom_pupredrvr_nbiasv2
+   Generating output for cell sky130_fd_io__gpio_pupredrvr_strongv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808361
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808360
+   Generating output for cell sky130_fd_io__feas_com_pupredrvr_weak
+   Generating output for cell sky130_fd_pr__via_pol1__example_5595914180854
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808363
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808362
+   Generating output for cell sky130_fd_io__com_pupredrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808366
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808365
+   Generating output for cell sky130_fd_io__com_pdpredrvr_weakv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808364
+   Generating output for cell sky130_fd_io__com_pdpredrvr_strong_slowv2
+   Generating output for cell sky130_fd_io__gpiov2_obpredrvr
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808368
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808625
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808373
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808374
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808393
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808392
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808391
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808390
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808389
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808388
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808387
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808386
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808384
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808381
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808377
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808376
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808375
+   Generating output for cell sky130_fd_io__gpio_dat_lsv2
+   Generating output for cell sky130_fd_io__gpio_dat_ls_1v2
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808398
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808397
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808396
+   Generating output for cell sky130_fd_pr__via_pol1__example_55959141808395
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808401
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808399
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808269
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808410
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808409
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808408
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808407
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808406
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808405
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808404
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808403
+   Generating output for cell sky130_fd_io__com_cclat
+   Generating output for cell sky130_fd_io__com_opath_datoev2
+   Generating output for cell sky130_fd_io__gpiov2_octl_dat
+   Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418080
+   Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180832
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180856
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180855
+   Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180853
+   Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180852
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418083
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418082
+   Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpiov2_pddrvr_strong
+   Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418085
+   Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270v2
+   Generating output for cell sky130_fd_io__gpio_pudrvr_strongv2
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180850
+   Generating output for cell sky130_fd_io__gpio_pddrvr_weakv2
+   Generating output for cell sky130_fd_io__gpio_pddrvr_strong_slowv2
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808656
+   Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808655
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808654
+   Generating output for cell sky130_fd_io__com_pudrvr_weakv2
+   Generating output for cell sky130_fd_io__com_pudrvr_strong_slowv2
+   Generating output for cell sky130_fd_io__gpio_odrvr_subv2
+   Generating output for cell sky130_fd_io__gpio_odrvrv2
+   Generating output for cell sky130_fd_io__gpio_opathv2
+   Generating output for cell sky130_fd_io__top_gpiov2
+   Generating output for cell sky130_fd_io__overlay_gpiov2
+   Generating output for cell sky130_ef_io__gpiov2_pad
+   Generating output for cell sky130_ef_io__gpiov2_pad_wrapped
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808691
+   Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808687
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808684
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808686
+   Generating output for cell sky130_fd_pr__tpl1__example_55959141808685
+   Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808683
+   Generating output for cell sky130_fd_io__gnd2gnd_strap
+   Generating output for cell sky130_fd_io__gnd2gnd_tap
+   Generating output for cell sky130_fd_io__gnd2gnd_diff
+   Generating output for cell sky130_fd_io__gnd2gnd_sub_dnwl
+   Generating output for cell sky130_fd_io__gnd2gnd_120x2_lv_isosub
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808690
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808702
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808705
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808682
+   Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808694
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808693
+   Generating output for cell sky130_fd_pr__dfl1__example_55959141808681
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808688
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808699
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808698
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808697
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808696
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808695
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808704
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808703
+   Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808701
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808689
+   Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808692
+   Generating output for cell sky130_fd_io__top_ground_lvc_wpad
+   Generating output for cell sky130_fd_io__overlay_vssd_lvc
+   Generating output for cell sky130_ef_io__lvc_vccdx_overlay
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped_pad
+   Generating output for cell sky130_fd_io__overlay_vssio_hvc
+   Generating output for cell sky130_ef_io__hvc_vssio_overlay
+   Generating output for cell sky130_ef_io__vssio_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__hvc_clampv2
+   Generating output for cell sky130_fd_io__top_power_hvc_wpadv2
+   Generating output for cell sky130_fd_io__overlay_vdda_hvc
+   Generating output for cell sky130_ef_io__vdda_hvc_clamped_pad
+   Generating output for cell sky130_fd_io__top_power_lvc_wpad
+   Generating output for cell sky130_fd_io__overlay_vccd_lvc
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped_pad
+   Generating output for cell sky130_ef_io__disconnect_vdda_slice_5um
+   Generating output for cell sky130_fd_io__overlay_vddio_hvc
+   Generating output for cell sky130_ef_io__hvc_vddio_overlay
+   Generating output for cell sky130_ef_io__vddio_hvc_clamped_pad
+   Generating output for cell chip_io_gpio_connects
+   Generating output for cell sky130_ef_io__lvc_vccdy_overlay
+   Generating output for cell sky130_ef_io__vssd_lvc_clamped3_pad
+   Generating output for cell sky130_ef_io__vccd_lvc_clamped3_pad
+   Generating output for cell chip_io
+   Generating output for cell gpio_signal_buffering
+   Generating output for cell caravel
diff --git a/tapeout/logs/tools.info b/tapeout/logs/tools.info
new file mode 100644
index 0000000..98b8cee
--- /dev/null
+++ b/tapeout/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.28
+Magic: 8.3.348
\ No newline at end of file
diff --git a/tapeout/logs/uncompress.log b/tapeout/logs/uncompress.log
new file mode 100644
index 0000000..cf8015b
--- /dev/null
+++ b/tapeout/logs/uncompress.log
@@ -0,0 +1,5 @@
+make: Nothing to be done for `check-env'.
+gds/user_project_wrapper.gds.gz -> gds/user_project_wrapper.gds
+lef/user_project_wrapper.lef.gz -> lef/user_project_wrapper.lef
+verilog/gl/user_project_wrapper.v.gz -> verilog/gl/user_project_wrapper.v
+All files are uncompressed!
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.00.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.00.split
new file mode 100644
index 0000000..022960a
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.00.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.01.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.01.split
new file mode 100644
index 0000000..0d0f1c8
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.01.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.02.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.02.split
new file mode 100644
index 0000000..cd17fe3
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.02.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.03.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.03.split
new file mode 100644
index 0000000..14625fd
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.03.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.04.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.04.split
new file mode 100644
index 0000000..6e7ffbe
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.04.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.05.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.05.split
new file mode 100644
index 0000000..bad855d
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.05.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_000710d6.gds.gz.06.split b/tapeout/outputs/gds/caravel_000710d6.gds.gz.06.split
new file mode 100644
index 0000000..44672f9
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_000710d6.gds.gz.06.split
Binary files differ
diff --git a/tapeout/outputs/klayout_beol_report.xml b/tapeout/outputs/klayout_beol_report.xml
new file mode 100644
index 0000000..7372035
--- /dev/null
+++ b/tapeout/outputs/klayout_beol_report.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/sky130A_mr.drc'</generator>
+ <top-cell>caravel_000710d6</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_000710d6</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_beol_report.xml.summary b/tapeout/outputs/klayout_beol_report.xml.summary
new file mode 100644
index 0000000..79b5c11
--- /dev/null
+++ b/tapeout/outputs/klayout_beol_report.xml.summary
@@ -0,0 +1,72 @@
+       0 791_m1.4 : min. m1 enclosure of mcon : 0.03um
+       0 ct.1: non-ring mcon should be rectangular
+       0 ct.1_a : minimum width of mcon : 0.17um
+       0 ct.1_b : maximum length of mcon : 0.17um
+       0 ct.2 : min. mcon spacing : 0.19um
+       0 ct.4 : mcon should covered by li
+       0 li.1 : min. li width : 0.17um
+       0 li.3 : min. li spacing : 0.17um
+       0 li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um
+       0 li.6 : min. li area : 0.0561um²
+       0 m1.1 : min. m1 width : 0.14um
+       0 m1.2 : min. m1 spacing : 0.14um
+       0 m1.3ab : min. 3um.m1 spacing m1 : 0.28um
+       0 m1.4 : mcon periphery must be enclosed by m1
+       0 m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um
+       0 m1.4a_a : mcon periph must be enclosed by met1 for specific cells
+       0 m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um
+       0 m1.6 : min. m1 area : 0.083um²
+       0 m1.7 : min. m1 with holes area : 0.14um²
+       0 m2.1 : min. m2 width : 0.14um
+       0 m2.2 : min. m2 spacing : 0.14um
+       0 m2.3ab : min. 3um.m2 spacing m2 : 0.28um
+       0 m2.4 : min. m2 enclosure of via : 0.055um
+       0 m2.4_a : via in periphery must be enclosed by met2
+       0 m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um
+       0 m2.6 : min. m2 area : 0.0676um²
+       0 m2.7 : min. m2 holes area : 0.14um²
+       0 m3.1 : min. m3 width : 0.3um
+       0 m3.2 : min. m3 spacing : 0.3um
+       0 m3.3cd : min. 3um.m3 spacing m3 : 0.4um
+       0 m3.4 : min. m3 enclosure of via2 : 0.065um
+       0 m3.4_a : via2 must be enclosed by met3
+       0 m4.1 : min. m4 width : 0.3um
+       0 m4.2 : min. m4 spacing : 0.3um
+       0 m4.3 : min. m4 enclosure of via3 : 0.065um
+       0 m4.3_a : via3 must be enclosed by met4
+       0 m4.4a : min. m4 area : 0.240um²
+       0 m4.5ab : min. 3um.m4 spacing m4 : 0.4um
+       0 m5.1 : min. m5 width : 1.6um
+       0 m5.2 : min. m5 spacing : 1.6um
+       0 m5.3 : min. m5 enclosure of via4 : 0.31um
+       0 m5.3_a : via must be enclosed by m5
+       0 m5.4 : min. m5 area : 4.0um²
+       0 pad.2 : min. pad spacing : 1.27um
+       0 via2.1a : via2 outside of moduleCut should be rectangular
+       0 via2.1a_a : min. width of via2 outside of moduleCut : 0.2um
+       0 via2.1a_b : maximum length of via2 : 0.2um
+       0 via2.2 : min. via2 spacing : 0.2um
+       0 via2.4 : min. m2 enclosure of via2 : 0.04um
+       0 via2.4_a : via must be enclosed by met2
+       0 via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um
+       0 via3.1 : via3 outside of moduleCut should be rectangular
+       0 via3.1_a : min. width of via3 outside of moduleCut : 0.2um
+       0 via3.1_b : maximum length of via3 : 0.2um
+       0 via3.2 : min. via3 spacing : 0.2um
+       0 via3.4 : min. m3 enclosure of via3 : 0.06um
+       0 via3.4_a : non-ring via3 must be enclosed by met3
+       0 via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um
+       0 via4.1 : via4 outside of moduleCut should be rectangular
+       0 via4.1_a : min. width of via4 outside of moduleCut : 0.8um
+       0 via4.1_b : maximum length of via4 : 0.8um
+       0 via4.2 : min. via4 spacing : 0.8um
+       0 via4.4 : min. m4 enclosure of via4 : 0.19um
+       0 via4.4_a : m4 must enclose all via4
+       0 via.1a : via outside of moduleCut should be rectangular
+       0 via.1a_a : min. width of via outside of moduleCut : 0.15um
+       0 via.1a_b : maximum length of via : 0.15um
+       0 via.2 : min. via spacing : 0.17um
+       0 via.4a : min. m1 enclosure of 0.15um via : 0.055um
+       0 via.4a_a : 0.15um via must be enclosed by met1
+       0 via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um
+       0 total error(s) among 71 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_feol_report.xml b/tapeout/outputs/klayout_feol_report.xml
new file mode 100644
index 0000000..8b31da2
--- /dev/null
+++ b/tapeout/outputs/klayout_feol_report.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/sky130A_mr.drc'</generator>
+ <top-cell>caravel_000710d6</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_000710d6</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_feol_report.xml.summary b/tapeout/outputs/klayout_feol_report.xml.summary
new file mode 100644
index 0000000..2a7a007
--- /dev/null
+++ b/tapeout/outputs/klayout_feol_report.xml.summary
@@ -0,0 +1,60 @@
+       0 cap2m.1 : min. cap2m width : 1.0um
+       0 cap2m.2a : min. cap2m spacing : 0.84um
+       0 cap2m.2b : min. cap2m spacing : 1.2um
+       0 cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um
+       0 cap2m.3 : min. m4 enclosure of cap2m : 0.14um
+       0 cap2m.3_a : min. m4 enclosure of cap2m : 0.14um
+       0 cap2m.4 : min. cap2m enclosure of via4 : 0.14um
+       0 cap2m.5 : min. cap2m spacing to via4 : 0.14um
+       0 cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um
+       0 capm.1 : min. capm width : 1.0um
+       0 capm.2a : min. capm spacing : 0.84um
+       0 capm.2b : min. capm spacing : 1.2um
+       0 capm.2b_a : min. spacing of m3_bot_plate : 1.2um
+       0 capm.3 : min. capm and m3 enclosure of m3 : 0.14um
+       0 capm.3_a : min. m3 enclosure of capm : 0.14um
+       0 capm.4 : min. capm enclosure of via3 : 0.14um
+       0 capm.5 : min. capm spacing to via3 : 0.14um
+       0 capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um
+       0 difftap.1 : min. diff width across areaid:ce : 0.15um
+       0 difftap.1_a : min. diff width in periphery : 0.15um
+       0 difftap.1_b : min. tap width across areaid:ce : 0.15um
+       0 difftap.1_c : min. tap width in periphery : 0.15um
+       0 difftap.3 : min. difftap spacing : 0.27um
+       0 dnwell.2 : min. dnwell width : 3.0um
+       0 hvi.1 : min. hvi width : 0.6um
+       0 hvi.2a : min. hvi spacing : 0.7um
+       0 hvntm.1 : min. hvntm width : 0.7um
+       0 hvntm.2 : min. hvntm spacing : 0.7um
+       0 hvtp.1 : min. hvtp width : 0.38um
+       0 hvtp.2 : min. hvtp spacing : 0.38um
+       0 hvtr.1 : min. hvtr width : 0.38um
+       0 hvtr.2 : min. hvtr spacing : 0.38um
+       0 hvtr.2_a : hvtr must not overlap hvtp
+       0 licon.1 : licon should be rectangle
+       0 licon.1_a/b : minimum/maximum width of licon : 0.17um
+       0 licon.13 : min. difftap licon spacing to npc : 0.09um
+       0 licon.13_a : licon of diffTap in periphery must not overlap npc
+       0 licon.17 : Licons may not overlap both poly and (diff or tap)
+       0 lvtn.1a : min. lvtn width : 0.38um
+       0 lvtn.2 : min. lvtn spacing : 0.38um
+       0 ncm.1 : min. ncm width : 0.38um
+       0 ncm.2a : min. ncm spacing : 0.38um
+       0 npc.1 : min. npc width : 0.27um
+       0 npc.2 : min. npc spacing, should be manually merged if less than : 0.27um
+       0 nsd.1 : min. nsdm width : 0.38um
+       0 nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um
+       0 nwell.1 : min. nwell width : 0.84um
+       0 nwell.2a : min. nwell spacing (merged if less) : 1.27um
+       0 nwell.6 : min enclosure of nwellHole by dnwell : 1.03um
+       0 poly.1a : min. poly width : 0.15um
+       0 poly.2 : min. poly spacing : 0.21um
+       0 psd.1 : min. psdm width : 0.38um
+       0 psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um
+       0 rpm.1a : min. rpm width : 1.27um
+       0 rpm.2 : min. rpm spacing : 0.84um
+       0 tunm.1 : min. tunm width : 0.41um
+       0 tunm.2 : min. tunm spacing : 0.5um
+       0 urpm.1a : min. rpm width : 1.27um
+       0 urpm.2 : min. rpm spacing : 0.84um
+       0 total error(s) among 59 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_fom_density_report.xml b/tapeout/outputs/klayout_fom_density_report.xml
new file mode 100644
index 0000000..4f0bda6
--- /dev/null
+++ b/tapeout/outputs/klayout_fom_density_report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/fom_density.drc'</generator>
+ <top-cell>caravel_000710d6</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_000710d6</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_fom_density_report.xml.summary b/tapeout/outputs/klayout_fom_density_report.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/tapeout/outputs/klayout_fom_density_report.xml.summary
@@ -0,0 +1 @@
+       0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_met_density_report.xml b/tapeout/outputs/klayout_met_density_report.xml
new file mode 100644
index 0000000..6c0e551
--- /dev/null
+++ b/tapeout/outputs/klayout_met_density_report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/met_density.lydrc'</generator>
+ <top-cell>caravel_000710d6</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>caravel_000710d6</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_met_density_report.xml.summary b/tapeout/outputs/klayout_met_density_report.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/tapeout/outputs/klayout_met_density_report.xml.summary
@@ -0,0 +1 @@
+       0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/mag/caravel.mag b/tapeout/outputs/mag/caravel.mag
new file mode 100644
index 0000000..4afe9bc
--- /dev/null
+++ b/tapeout/outputs/mag/caravel.mag
@@ -0,0 +1,83878 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1667299471
+<< checkpaint >>
+rect -1260 -1260 718860 1038860
+<< metal1 >>
+rect 366174 1027828 366180 1027880
+rect 366232 1027868 366238 1027880
+rect 366542 1027868 366548 1027880
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+<< metal5 >>
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+rect 6811 111610 18976 123778
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+rect 650466 93382 650508 93618
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+rect 6167 70054 19620 80934
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+rect 362138 41702 403120 41938
+rect 361860 41660 403120 41702
+rect 402800 41300 403120 41660
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+rect 403444 41300 403764 41660
+rect 365356 41258 402476 41300
+rect 365356 41022 365398 41258
+rect 365634 41022 402198 41258
+rect 402434 41022 402476 41258
+rect 365356 40980 402476 41022
+rect 402800 40980 403764 41300
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+rect 422120 41938 423820 41980
+rect 422120 41702 422162 41938
+rect 422398 41702 423820 41938
+rect 422120 41660 423820 41702
+rect 424972 41938 441668 41980
+rect 424972 41702 425014 41938
+rect 425250 41702 441390 41938
+rect 441626 41702 441668 41938
+rect 424972 41660 441668 41702
+rect 442084 41660 450684 41980
+rect 412460 41300 412780 41660
+rect 411724 40980 412780 41300
+rect 421476 41300 421796 41660
+rect 423500 41300 423820 41660
+rect 442084 41300 442404 41660
+rect 421476 40980 422440 41300
+rect 423500 40980 442404 41300
+rect 450364 41300 450684 41660
+rect 451100 41938 463932 41980
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+rect 463890 41702 463932 41938
+rect 451100 41660 463932 41702
+rect 451100 41300 451420 41660
+rect 450364 40980 451420 41300
+rect 422120 40620 422440 40980
+rect 422120 40578 425292 40620
+rect 422120 40342 425014 40578
+rect 425250 40342 425292 40578
+rect 422120 40300 425292 40342
+rect 80222 6811 92390 18976
+rect 136713 7143 144150 18309
+rect 187640 6598 200160 19088
+rect 243266 6167 254146 19620
+rect 296240 6598 308760 19088
+rect 351040 6598 363560 19088
+rect 405840 6598 418360 19088
+rect 460640 6598 473160 19088
+rect 515440 6598 527960 19088
+rect 570422 6811 582590 18976
+rect 624222 6811 636390 18976
+use caravel_logo  caravel_logo
+timestamp 1638586901
+transform 1 0 269370 0 1 5100
+box -2520 0 15000 15560
+use caravel_motto  caravel_motto
+timestamp 1637698310
+transform 1 0 -54372 0 1 -4446
+box 373080 14838 395618 19242
+use caravel_power_routing  caravel_power_routing
+timestamp 1666994345
+transform 1 0 0 0 1 0
+box 6022 30806 711814 1031696
+use caravel_clocking  clock_ctrl
+timestamp 1666097791
+transform 1 0 626764 0 1 55284
+box 136 496 20000 20000
+use copyright_block  copyright_block
+timestamp 1665519328
+transform 1 0 149582 0 1 16298
+box -262 -10348 35048 2764
+use buff_flash_clkrst  flash_clkrst_buffers
+timestamp 1665682149
+transform 1 0 458400 0 1 47600
+box 330 0 7699 5000
+use gpio_control_block  gpio_control_bidir_1\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 121000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_1\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 166200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[0\]
+timestamp 1666126335
+transform 1 0 7631 0 1 289000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[1\]
+timestamp 1666126335
+transform 1 0 7631 0 1 245800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_bidir_2\[2\]
+timestamp 1666126335
+transform 1 0 7631 0 1 202600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 523800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 568800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[2\]
+timestamp 1666126335
+transform -1 0 710203 0 1 614000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[3\]
+timestamp 1666126335
+transform -1 0 710203 0 1 659000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[4\]
+timestamp 1666126335
+transform -1 0 710203 0 1 704200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[5\]
+timestamp 1666126335
+transform -1 0 710203 0 1 749200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[6\]
+timestamp 1666126335
+transform -1 0 710203 0 1 927600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[7\]
+timestamp 1666126335
+transform 0 1 549200 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[8\]
+timestamp 1666126335
+transform 0 1 497800 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[9\]
+timestamp 1666126335
+transform 0 1 420800 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1\[10\]
+timestamp 1666126335
+transform 0 1 353400 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 211200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 256400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[2\]
+timestamp 1666126335
+transform -1 0 710203 0 1 301400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[3\]
+timestamp 1666126335
+transform -1 0 710203 0 1 346400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[4\]
+timestamp 1666126335
+transform -1 0 710203 0 1 391600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_1a\[5\]
+timestamp 1666126335
+transform -1 0 710203 0 1 479800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[0\]
+timestamp 1666126335
+transform 0 1 303000 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[1\]
+timestamp 1666126335
+transform 0 1 251400 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[2\]
+timestamp 1666126335
+transform 0 1 200000 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[3\]
+timestamp 1666126335
+transform 0 1 148600 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[4\]
+timestamp 1666126335
+transform 0 1 97200 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[5\]
+timestamp 1666126335
+transform 1 0 7631 0 1 931200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[6\]
+timestamp 1666126335
+transform 1 0 7631 0 1 805400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[7\]
+timestamp 1666126335
+transform 1 0 7631 0 1 762200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[8\]
+timestamp 1666126335
+transform 1 0 7631 0 1 719000
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[9\]
+timestamp 1666126335
+transform 1 0 7631 0 1 675800
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[10\]
+timestamp 1666126335
+transform 1 0 7631 0 1 632600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[11\]
+timestamp 1666126335
+transform 1 0 7631 0 1 589400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[12\]
+timestamp 1666126335
+transform 1 0 7631 0 1 546200
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[13\]
+timestamp 1666126335
+transform 1 0 7631 0 1 418600
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[14\]
+timestamp 1666126335
+transform 1 0 7631 0 1 375400
+box 872 416 34000 13000
+use gpio_control_block  gpio_control_in_2\[15\]
+timestamp 1666126335
+transform 1 0 7631 0 1 332200
+box 872 416 34000 13000
+use gpio_defaults_block_1803 gpio_defaults_block_0 ~/caravel_top_level/mag
+timestamp 1666360185
+transform -1 0 709467 0 1 134000
+box -38 0 6018 2224
+use gpio_defaults_block_1803 gpio_defaults_block_1
+timestamp 1666360185
+transform -1 0 709467 0 1 179200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_2
+timestamp 1666360185
+transform -1 0 709467 0 1 224200
+box -38 0 6018 2224
+use gpio_defaults_block_0801 gpio_defaults_block_3
+timestamp 1666360185
+transform -1 0 709467 0 1 269400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_4
+timestamp 1666360185
+transform -1 0 709467 0 1 314400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_5
+timestamp 1666360185
+transform -1 0 709467 0 1 359400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_6
+timestamp 1666360185
+transform -1 0 709467 0 1 404600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_7
+timestamp 1666360185
+transform -1 0 709467 0 1 492800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_8
+timestamp 1666360185
+transform -1 0 709467 0 1 536800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_9
+timestamp 1666360185
+transform -1 0 709467 0 1 581800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_10
+timestamp 1666360185
+transform -1 0 709467 0 1 627000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_11
+timestamp 1666360185
+transform -1 0 709467 0 1 672000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_12
+timestamp 1666360185
+transform -1 0 709467 0 1 717200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_13
+timestamp 1666360185
+transform -1 0 709467 0 1 762200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_14
+timestamp 1666360185
+transform -1 0 709467 0 1 940600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_15
+timestamp 1666360185
+transform 0 1 562194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_16
+timestamp 1666360185
+transform 0 1 510794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_17
+timestamp 1666360185
+transform 0 1 433794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_18
+timestamp 1666360185
+transform 0 1 366394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_19
+timestamp 1666360185
+transform 0 1 315994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_20
+timestamp 1666360185
+transform 0 1 264394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_21
+timestamp 1666360185
+transform 0 1 212994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_22
+timestamp 1666360185
+transform 0 1 161594 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_23
+timestamp 1666360185
+transform 0 1 110194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_24
+timestamp 1666360185
+transform 1 0 8367 0 1 944200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_25
+timestamp 1666360185
+transform 1 0 8367 0 1 818400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_26
+timestamp 1666360185
+transform 1 0 8367 0 1 775200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_27
+timestamp 1666360185
+transform 1 0 8367 0 1 732000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_28
+timestamp 1666360185
+transform 1 0 8367 0 1 688800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_29
+timestamp 1666360185
+transform 1 0 8367 0 1 645600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_30
+timestamp 1666360185
+transform 1 0 8367 0 1 602400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_31
+timestamp 1666360185
+transform 1 0 8367 0 1 559200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_32
+timestamp 1666360185
+transform 1 0 8367 0 1 431600
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_33
+timestamp 1666360185
+transform 1 0 8367 0 1 388400
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_34
+timestamp 1666360185
+transform 1 0 8367 0 1 345200
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_35
+timestamp 1666360185
+transform 1 0 8367 0 1 302000
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_36
+timestamp 1666360185
+transform 1 0 8367 0 1 258800
+box -38 0 6018 2224
+use gpio_defaults_block_1800 gpio_defaults_block_37
+timestamp 1666360185
+transform 1 0 8367 0 1 215600
+box -38 0 6018 2224
+use housekeeping  housekeeping
+timestamp 1666084955
+transform 1 0 592434 0 1 100002
+box 0 0 74046 110190
+use mgmt_protect  mgmt_buffers
+timestamp 1666987233
+transform 1 0 128180 0 1 232036
+box 1066 -400 424400 32400
+use user_project_wrapper  mprj
+timestamp 1637147503
+transform 1 0 65308 0 1 278718
+box -8726 -7654 592650 711590
+use open_source  open_source
+timestamp 1666123577
+transform 1 0 206098 0 1 2054
+box 752 5164 29030 16242
+use chip_io  padframe
+timestamp 1666101711
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use digital_pll  pll
+timestamp 1666101174
+transform 1 0 628146 0 1 80944
+box 0 0 20000 15000
+use simple_por  por
+timestamp 1650914729
+transform 1 0 650146 0 -1 55282
+box -52 -62 11344 8684
+use xres_buf  rstb_level
+timestamp 1649268499
+transform -1 0 145710 0 -1 50488
+box 374 -400 3540 3800
+use gpio_signal_buffering  sigbuf
+timestamp 1666028385
+transform 1 0 0 0 1 0
+box 39992 41960 677583 997915
+use mgmt_core_wrapper  soc
+timestamp 1668034664
+transform 1 0 52034 0 1 53002
+box -156 0 524096 164000
+use spare_logic_block  spare_logic\[0\]
+timestamp 1638030917
+transform 1 0 88632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic\[1\]
+timestamp 1638030917
+transform 1 0 108632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block  spare_logic\[2\]
+timestamp 1638030917
+transform 1 0 640874 0 1 220592
+box 0 0 9000 9000
+use spare_logic_block  spare_logic\[3\]
+timestamp 1638030917
+transform 1 0 578632 0 1 232528
+box 0 0 9000 9000
+use user_id_textblock  user_id_textblock
+timestamp 1608324878
+transform 1 0 96272 0 1 6890
+box -656 1508 33720 10344
+use user_id_programming  user_id_value
+timestamp 1650371074
+transform 1 0 656624 0 1 88126
+box 0 0 7109 7077
+<< labels >>
+flabel metal5 s 187640 6598 200160 19088 0 FreeSans 16000 0 0 0 clock
+port 1 nsew signal input
+flabel metal5 s 351040 6598 363560 19088 0 FreeSans 16000 0 0 0 flash_clk
+port 2 nsew signal output
+flabel metal5 s 296240 6598 308760 19088 0 FreeSans 16000 0 0 0 flash_csb
+port 3 nsew signal output
+flabel metal5 s 405840 6598 418360 19088 0 FreeSans 16000 0 0 0 flash_io0
+port 4 nsew signal output
+flabel metal5 s 460640 6598 473160 19088 0 FreeSans 16000 0 0 0 flash_io1
+port 5 nsew signal output
+flabel metal5 s 515440 6598 527960 19088 0 FreeSans 16000 0 0 0 gpio
+port 6 nsew signal bidirectional
+flabel metal5 s 698512 101240 711002 113760 0 FreeSans 16000 0 0 0 mprj_io[0]
+port 7 nsew signal bidirectional
+flabel metal5 s 698512 684440 711002 696960 0 FreeSans 16000 0 0 0 mprj_io[10]
+port 8 nsew signal bidirectional
+flabel metal5 s 698512 729440 711002 741960 0 FreeSans 16000 0 0 0 mprj_io[11]
+port 9 nsew signal bidirectional
+flabel metal5 s 698512 774440 711002 786960 0 FreeSans 16000 0 0 0 mprj_io[12]
+port 10 nsew signal bidirectional
+flabel metal5 s 698512 863640 711002 876160 0 FreeSans 16000 0 0 0 mprj_io[13]
+port 11 nsew signal bidirectional
+flabel metal5 s 698512 952840 711002 965360 0 FreeSans 16000 0 0 0 mprj_io[14]
+port 12 nsew signal bidirectional
+flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 16000 0 0 0 mprj_io[15]
+port 13 nsew signal bidirectional
+flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 16000 0 0 0 mprj_io[16]
+port 14 nsew signal bidirectional
+flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 16000 0 0 0 mprj_io[17]
+port 15 nsew signal bidirectional
+flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 16000 0 0 0 mprj_io[18]
+port 16 nsew signal bidirectional
+flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 16000 0 0 0 mprj_io[19]
+port 17 nsew signal bidirectional
+flabel metal5 s 698512 146440 711002 158960 0 FreeSans 16000 0 0 0 mprj_io[1]
+port 18 nsew signal bidirectional
+flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 16000 0 0 0 mprj_io[20]
+port 19 nsew signal bidirectional
+flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 16000 0 0 0 mprj_io[21]
+port 20 nsew signal bidirectional
+flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 16000 0 0 0 mprj_io[22]
+port 21 nsew signal bidirectional
+flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 16000 0 0 0 mprj_io[23]
+port 22 nsew signal bidirectional
+flabel metal5 s 6598 956440 19088 968960 0 FreeSans 16000 0 0 0 mprj_io[24]
+port 23 nsew signal bidirectional
+flabel metal5 s 6598 786640 19088 799160 0 FreeSans 16000 0 0 0 mprj_io[25]
+port 24 nsew signal bidirectional
+flabel metal5 s 6598 743440 19088 755960 0 FreeSans 16000 0 0 0 mprj_io[26]
+port 25 nsew signal bidirectional
+flabel metal5 s 6598 700240 19088 712760 0 FreeSans 16000 0 0 0 mprj_io[27]
+port 26 nsew signal bidirectional
+flabel metal5 s 6598 657040 19088 669560 0 FreeSans 16000 0 0 0 mprj_io[28]
+port 27 nsew signal bidirectional
+flabel metal5 s 6598 613840 19088 626360 0 FreeSans 16000 0 0 0 mprj_io[29]
+port 28 nsew signal bidirectional
+flabel metal5 s 698512 191440 711002 203960 0 FreeSans 16000 0 0 0 mprj_io[2]
+port 29 nsew signal bidirectional
+flabel metal5 s 6598 570640 19088 583160 0 FreeSans 16000 0 0 0 mprj_io[30]
+port 30 nsew signal bidirectional
+flabel metal5 s 6598 527440 19088 539960 0 FreeSans 16000 0 0 0 mprj_io[31]
+port 31 nsew signal bidirectional
+flabel metal5 s 6598 399840 19088 412360 0 FreeSans 16000 0 0 0 mprj_io[32]
+port 32 nsew signal bidirectional
+flabel metal5 s 6598 356640 19088 369160 0 FreeSans 16000 0 0 0 mprj_io[33]
+port 33 nsew signal bidirectional
+flabel metal5 s 6598 313440 19088 325960 0 FreeSans 16000 0 0 0 mprj_io[34]
+port 34 nsew signal bidirectional
+flabel metal5 s 6598 270240 19088 282760 0 FreeSans 16000 0 0 0 mprj_io[35]
+port 35 nsew signal bidirectional
+flabel metal5 s 6598 227040 19088 239560 0 FreeSans 16000 0 0 0 mprj_io[36]
+port 36 nsew signal bidirectional
+flabel metal5 s 6598 183840 19088 196360 0 FreeSans 16000 0 0 0 mprj_io[37]
+port 37 nsew signal bidirectional
+flabel metal5 s 698512 236640 711002 249160 0 FreeSans 16000 0 0 0 mprj_io[3]
+port 38 nsew signal bidirectional
+flabel metal5 s 698512 281640 711002 294160 0 FreeSans 16000 0 0 0 mprj_io[4]
+port 39 nsew signal bidirectional
+flabel metal5 s 698512 326640 711002 339160 0 FreeSans 16000 0 0 0 mprj_io[5]
+port 40 nsew signal bidirectional
+flabel metal5 s 698512 371840 711002 384360 0 FreeSans 16000 0 0 0 mprj_io[6]
+port 41 nsew signal bidirectional
+flabel metal5 s 698512 549040 711002 561560 0 FreeSans 16000 0 0 0 mprj_io[7]
+port 42 nsew signal bidirectional
+flabel metal5 s 698512 594240 711002 606760 0 FreeSans 16000 0 0 0 mprj_io[8]
+port 43 nsew signal bidirectional
+flabel metal5 s 698512 639240 711002 651760 0 FreeSans 16000 0 0 0 mprj_io[9]
+port 44 nsew signal bidirectional
+flabel metal5 s 136713 7143 144150 18309 0 FreeSans 16000 0 0 0 resetb
+port 45 nsew signal input
+flabel metal5 s 6167 70054 19620 80934 0 FreeSans 16000 0 0 0 vccd
+port 46 nsew power input
+flabel metal5 s 697980 909666 711433 920546 0 FreeSans 16000 0 0 0 vccd1
+port 47 nsew power input
+flabel metal5 s 6167 914054 19620 924934 0 FreeSans 16000 0 0 0 vccd2
+port 48 nsew power input
+flabel metal5 s 624222 6811 636390 18976 0 FreeSans 16000 0 0 0 vdda
+port 49 nsew power input
+flabel metal5 s 698624 819822 710789 831990 0 FreeSans 16000 0 0 0 vdda1
+port 50 nsew power input
+flabel metal5 s 698624 505222 710789 517390 0 FreeSans 16000 0 0 0 vdda1_2
+port 51 nsew power input
+flabel metal5 s 6811 484410 18976 496578 0 FreeSans 16000 0 0 0 vdda2
+port 52 nsew power input
+flabel metal5 s 6811 111610 18976 123778 0 FreeSans 16000 0 0 0 vddio
+port 53 nsew power input
+flabel metal5 s 6811 871210 18976 883378 0 FreeSans 16000 0 0 0 vddio_2
+port 54 nsew power input
+flabel metal5 s 80222 6811 92390 18976 0 FreeSans 16000 0 0 0 vssa
+port 55 nsew ground input
+flabel metal5 s 577010 1018624 589178 1030789 0 FreeSans 16000 0 0 0 vssa1
+port 56 nsew ground input
+flabel metal5 s 698624 417022 710789 429190 0 FreeSans 16000 0 0 0 vssa1_2
+port 57 nsew ground input
+flabel metal5 s 6811 829010 18976 841178 0 FreeSans 16000 0 0 0 vssa2
+port 58 nsew ground input
+flabel metal5 s 243266 6167 254146 19620 0 FreeSans 16000 0 0 0 vssd
+port 59 nsew ground input
+flabel metal5 s 697980 461866 711433 472746 0 FreeSans 16000 0 0 0 vssd1
+port 60 nsew ground input
+flabel metal5 s 6167 442854 19620 453734 0 FreeSans 16000 0 0 0 vssd2
+port 61 nsew ground input
+flabel metal5 s 570422 6811 582590 18976 0 FreeSans 16000 0 0 0 vssio
+port 62 nsew ground input
+flabel metal5 s 334810 1018624 346978 1030789 0 FreeSans 16000 0 0 0 vssio_2
+port 63 nsew ground input
+<< properties >>
+string FIXED_BBOX 0 0 717600 1037600
+string LEFclass BLOCK
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_0403.mag b/tapeout/outputs/mag/gpio_defaults_block_0403.mag
new file mode 100644
index 0000000..e15b2ba
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_0403.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4721 833 4755 867
+rect 1225 765 1259 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4813 765 4847 799
+rect 5411 765 5445 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
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+rect 3122 2150 4278 2202
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+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
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+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
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+rect 0 1040 5980 1062
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+rect 2038 796 2044 808
+rect 1038 768 1409 796
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+rect 658 688 664 740
+rect 716 728 722 740
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+rect 4161 768 4344 796
+rect 4200 756 4264 768
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+rect 4396 756 4402 808
+rect 4798 796 4804 808
+rect 4759 768 4804 796
+rect 4798 756 4804 768
+rect 4856 796 4862 808
+rect 4936 796 5000 808
+rect 5258 796 5264 808
+rect 4856 768 5000 796
+rect 5219 768 5264 796
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+rect 5316 756 5322 768
+rect 5396 756 5460 768
+rect 1636 728 1722 756
+rect 1636 716 1642 728
+rect 716 688 722 700
+rect 0 570 5980 592
+rect 0 518 778 570
+rect 830 518 842 570
+rect 894 518 906 570
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+rect 0 496 5980 518
+<< via1 >>
+rect 78 2150 130 2202
+rect 142 2150 194 2202
+rect 206 2150 258 2202
+rect 270 2150 322 2202
+rect 1478 2150 1530 2202
+rect 1542 2150 1594 2202
+rect 1606 2150 1658 2202
+rect 1670 2150 1722 2202
+rect 2878 2150 2930 2202
+rect 2942 2150 2994 2202
+rect 3006 2150 3058 2202
+rect 3070 2150 3122 2202
+rect 4278 2150 4330 2202
+rect 4342 2150 4394 2202
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+rect 4470 2150 4522 2202
+rect 778 1606 830 1658
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+rect 2178 1606 2230 1658
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+rect 2306 1606 2358 1658
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+rect 3578 1606 3630 1658
+rect 3642 1606 3694 1658
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+rect 78 1062 130 1114
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+rect 206 1062 258 1114
+rect 270 1062 322 1114
+rect 1478 1062 1530 1114
+rect 1542 1062 1594 1114
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+rect 2942 1062 2994 1114
+rect 3006 1062 3058 1114
+rect 3070 1062 3122 1114
+rect 4278 1062 4330 1114
+rect 4342 1062 4394 1114
+rect 4406 1062 4458 1114
+rect 4470 1062 4522 1114
+rect 204 824 256 876
+rect 1262 864 1314 916
+rect 5724 824 5776 876
+rect 664 688 716 740
+rect 1584 716 1636 768
+rect 2044 756 2096 808
+rect 2504 756 2556 808
+rect 2964 756 3016 808
+rect 3424 756 3476 808
+rect 3884 756 3936 808
+rect 4344 756 4396 808
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+rect 5264 756 5316 808
+rect 778 518 830 570
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+rect 4978 518 5030 570
+rect 5042 518 5094 570
+rect 5106 518 5158 570
+rect 5170 518 5222 570
+<< metal2 >>
+rect 78 2204 322 2224
+rect 78 2202 92 2204
+rect 148 2202 172 2204
+rect 228 2202 252 2204
+rect 308 2202 322 2204
+rect 78 2148 92 2150
+rect 148 2148 172 2150
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+rect 308 2148 322 2150
+rect 78 2128 322 2148
+rect 1478 2204 1722 2224
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+rect 1628 2202 1652 2204
+rect 1708 2202 1722 2204
+rect 1478 2148 1492 2150
+rect 1548 2148 1572 2150
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+rect 1708 2148 1722 2150
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+rect 2878 2204 3122 2224
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+rect 2948 2202 2972 2204
+rect 3028 2202 3052 2204
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+rect 2878 2148 2892 2150
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+rect 3028 2148 3052 2150
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+rect 4278 2204 4522 2224
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+rect 4348 2202 4372 2204
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+rect 3578 572 3822 592
+rect 3578 570 3592 572
+rect 3648 570 3672 572
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+rect 3808 570 3822 572
+rect 3578 516 3592 518
+rect 3648 516 3672 518
+rect 3728 516 3752 518
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+<< via4 >>
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+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_0801.mag b/tapeout/outputs/mag/gpio_defaults_block_0801.mag
new file mode 100644
index 0000000..a5d837d
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_0801.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4721 833 4755 867
+rect 1363 765 1397 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
+rect 1594 2150 1606 2202
+rect 1658 2150 1670 2202
+rect 1722 2150 2878 2202
+rect 2930 2150 2942 2202
+rect 2994 2150 3006 2202
+rect 3058 2150 3070 2202
+rect 3122 2150 4278 2202
+rect 4330 2150 4342 2202
+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
+rect 830 1606 842 1658
+rect 894 1606 906 1658
+rect 958 1606 970 1658
+rect 1022 1606 2178 1658
+rect 2230 1606 2242 1658
+rect 2294 1606 2306 1658
+rect 2358 1606 2370 1658
+rect 2422 1606 3578 1658
+rect 3630 1606 3642 1658
+rect 3694 1606 3706 1658
+rect 3758 1606 3770 1658
+rect 3822 1606 4978 1658
+rect 5030 1606 5042 1658
+rect 5094 1606 5106 1658
+rect 5158 1606 5170 1658
+rect 5222 1606 5980 1658
+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
+rect 0 1062 78 1114
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+rect 4522 1062 5980 1114
+rect 0 1040 5980 1062
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+rect 1256 864 1262 916
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+rect 2038 796 2044 808
+rect 1038 768 1409 796
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+rect 2035 768 2044 796
+rect 658 688 664 740
+rect 716 728 722 740
+rect 1038 728 1066 768
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+rect 1351 759 1409 768
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+rect 2096 768 2240 796
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+rect 2096 756 2102 768
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+rect 2556 756 2562 808
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+rect 3267 768 3424 796
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+rect 3878 796 3884 808
+rect 3701 768 3884 796
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+rect 3878 756 3884 768
+rect 3936 756 3942 808
+rect 4200 796 4264 808
+rect 4338 796 4344 808
+rect 4161 768 4344 796
+rect 4200 756 4264 768
+rect 4338 756 4344 768
+rect 4396 756 4402 808
+rect 4798 796 4804 808
+rect 4759 768 4804 796
+rect 4798 756 4804 768
+rect 4856 796 4862 808
+rect 4936 796 5000 808
+rect 5258 796 5264 808
+rect 4856 768 5000 796
+rect 5219 768 5264 796
+rect 4856 756 4862 768
+rect 4936 756 5000 768
+rect 5258 756 5264 768
+rect 5316 796 5322 808
+rect 5396 796 5460 808
+rect 5316 768 5460 796
+rect 5316 756 5322 768
+rect 5396 756 5460 768
+rect 1636 728 1722 756
+rect 1636 716 1642 728
+rect 716 688 722 700
+rect 0 570 5980 592
+rect 0 518 778 570
+rect 830 518 842 570
+rect 894 518 906 570
+rect 958 518 970 570
+rect 1022 518 2178 570
+rect 2230 518 2242 570
+rect 2294 518 2306 570
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+rect 2422 518 3578 570
+rect 3630 518 3642 570
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+rect 3758 518 3770 570
+rect 3822 518 4978 570
+rect 5030 518 5042 570
+rect 5094 518 5106 570
+rect 5158 518 5170 570
+rect 5222 518 5980 570
+rect 0 496 5980 518
+<< via1 >>
+rect 78 2150 130 2202
+rect 142 2150 194 2202
+rect 206 2150 258 2202
+rect 270 2150 322 2202
+rect 1478 2150 1530 2202
+rect 1542 2150 1594 2202
+rect 1606 2150 1658 2202
+rect 1670 2150 1722 2202
+rect 2878 2150 2930 2202
+rect 2942 2150 2994 2202
+rect 3006 2150 3058 2202
+rect 3070 2150 3122 2202
+rect 4278 2150 4330 2202
+rect 4342 2150 4394 2202
+rect 4406 2150 4458 2202
+rect 4470 2150 4522 2202
+rect 778 1606 830 1658
+rect 842 1606 894 1658
+rect 906 1606 958 1658
+rect 970 1606 1022 1658
+rect 2178 1606 2230 1658
+rect 2242 1606 2294 1658
+rect 2306 1606 2358 1658
+rect 2370 1606 2422 1658
+rect 3578 1606 3630 1658
+rect 3642 1606 3694 1658
+rect 3706 1606 3758 1658
+rect 3770 1606 3822 1658
+rect 4978 1606 5030 1658
+rect 5042 1606 5094 1658
+rect 5106 1606 5158 1658
+rect 5170 1606 5222 1658
+rect 78 1062 130 1114
+rect 142 1062 194 1114
+rect 206 1062 258 1114
+rect 270 1062 322 1114
+rect 1478 1062 1530 1114
+rect 1542 1062 1594 1114
+rect 1606 1062 1658 1114
+rect 1670 1062 1722 1114
+rect 2878 1062 2930 1114
+rect 2942 1062 2994 1114
+rect 3006 1062 3058 1114
+rect 3070 1062 3122 1114
+rect 4278 1062 4330 1114
+rect 4342 1062 4394 1114
+rect 4406 1062 4458 1114
+rect 4470 1062 4522 1114
+rect 204 824 256 876
+rect 1262 864 1314 916
+rect 5724 824 5776 876
+rect 664 688 716 740
+rect 1584 716 1636 768
+rect 2044 756 2096 808
+rect 2504 756 2556 808
+rect 2964 756 3016 808
+rect 3424 756 3476 808
+rect 3884 756 3936 808
+rect 4344 756 4396 808
+rect 4804 756 4856 808
+rect 5264 756 5316 808
+rect 778 518 830 570
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+rect 3770 518 3822 570
+rect 4978 518 5030 570
+rect 5042 518 5094 570
+rect 5106 518 5158 570
+rect 5170 518 5222 570
+<< metal2 >>
+rect 78 2204 322 2224
+rect 78 2202 92 2204
+rect 148 2202 172 2204
+rect 228 2202 252 2204
+rect 308 2202 322 2204
+rect 78 2148 92 2150
+rect 148 2148 172 2150
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+rect 78 2128 322 2148
+rect 1478 2204 1722 2224
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+rect 1548 2202 1572 2204
+rect 1628 2202 1652 2204
+rect 1708 2202 1722 2204
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+rect 1548 2148 1572 2150
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+rect 1708 2148 1722 2150
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+rect 2878 2204 3122 2224
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+rect 3028 2202 3052 2204
+rect 3108 2202 3122 2204
+rect 2878 2148 2892 2150
+rect 2948 2148 2972 2150
+rect 3028 2148 3052 2150
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+rect 4278 2204 4522 2224
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+rect 4348 2202 4372 2204
+rect 4428 2202 4452 2204
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+rect 4278 2148 4292 2150
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+rect 4278 2128 4522 2148
+rect 778 1660 1022 1680
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+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_1800.mag b/tapeout/outputs/mag/gpio_defaults_block_1800.mag
new file mode 100644
index 0000000..442025f
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_1800.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 1087 833 1121 867
+rect 1639 833 1673 867
+rect 4583 833 4617 867
+rect 1363 765 1397 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
+rect 1594 2150 1606 2202
+rect 1658 2150 1670 2202
+rect 1722 2150 2878 2202
+rect 2930 2150 2942 2202
+rect 2994 2150 3006 2202
+rect 3058 2150 3070 2202
+rect 3122 2150 4278 2202
+rect 4330 2150 4342 2202
+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
+rect 830 1606 842 1658
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+rect 958 1606 970 1658
+rect 1022 1606 2178 1658
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+rect 0 1584 5980 1606
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+rect 1038 768 1409 796
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+rect 658 688 664 740
+rect 716 728 722 740
+rect 1038 728 1066 768
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+rect 3878 756 3884 768
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+rect 4200 796 4264 808
+rect 4338 796 4344 808
+rect 4161 768 4344 796
+rect 4200 756 4264 768
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+rect 4396 756 4402 808
+rect 4798 796 4804 808
+rect 4759 768 4804 796
+rect 4798 756 4804 768
+rect 4856 796 4862 808
+rect 4936 796 5000 808
+rect 5258 796 5264 808
+rect 4856 768 5000 796
+rect 5219 768 5264 796
+rect 4856 756 4862 768
+rect 4936 756 5000 768
+rect 5258 756 5264 768
+rect 5316 796 5322 808
+rect 5396 796 5460 808
+rect 5316 768 5460 796
+rect 5316 756 5322 768
+rect 5396 756 5460 768
+rect 1636 728 1722 756
+rect 1636 716 1642 728
+rect 716 688 722 700
+rect 0 570 5980 592
+rect 0 518 778 570
+rect 830 518 842 570
+rect 894 518 906 570
+rect 958 518 970 570
+rect 1022 518 2178 570
+rect 2230 518 2242 570
+rect 2294 518 2306 570
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+rect 3822 518 4978 570
+rect 5030 518 5042 570
+rect 5094 518 5106 570
+rect 5158 518 5170 570
+rect 5222 518 5980 570
+rect 0 496 5980 518
+<< via1 >>
+rect 78 2150 130 2202
+rect 142 2150 194 2202
+rect 206 2150 258 2202
+rect 270 2150 322 2202
+rect 1478 2150 1530 2202
+rect 1542 2150 1594 2202
+rect 1606 2150 1658 2202
+rect 1670 2150 1722 2202
+rect 2878 2150 2930 2202
+rect 2942 2150 2994 2202
+rect 3006 2150 3058 2202
+rect 3070 2150 3122 2202
+rect 4278 2150 4330 2202
+rect 4342 2150 4394 2202
+rect 4406 2150 4458 2202
+rect 4470 2150 4522 2202
+rect 778 1606 830 1658
+rect 842 1606 894 1658
+rect 906 1606 958 1658
+rect 970 1606 1022 1658
+rect 2178 1606 2230 1658
+rect 2242 1606 2294 1658
+rect 2306 1606 2358 1658
+rect 2370 1606 2422 1658
+rect 3578 1606 3630 1658
+rect 3642 1606 3694 1658
+rect 3706 1606 3758 1658
+rect 3770 1606 3822 1658
+rect 4978 1606 5030 1658
+rect 5042 1606 5094 1658
+rect 5106 1606 5158 1658
+rect 5170 1606 5222 1658
+rect 78 1062 130 1114
+rect 142 1062 194 1114
+rect 206 1062 258 1114
+rect 270 1062 322 1114
+rect 1478 1062 1530 1114
+rect 1542 1062 1594 1114
+rect 1606 1062 1658 1114
+rect 1670 1062 1722 1114
+rect 2878 1062 2930 1114
+rect 2942 1062 2994 1114
+rect 3006 1062 3058 1114
+rect 3070 1062 3122 1114
+rect 4278 1062 4330 1114
+rect 4342 1062 4394 1114
+rect 4406 1062 4458 1114
+rect 4470 1062 4522 1114
+rect 204 824 256 876
+rect 1262 864 1314 916
+rect 5724 824 5776 876
+rect 664 688 716 740
+rect 1584 716 1636 768
+rect 2044 756 2096 808
+rect 2504 756 2556 808
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+rect 4288 1060 4292 1116
+rect 4292 1060 4348 1116
+rect 4348 1060 4352 1116
+rect 4288 1056 4352 1060
+rect 4368 1116 4432 1120
+rect 4368 1060 4372 1116
+rect 4372 1060 4428 1116
+rect 4428 1060 4432 1116
+rect 4368 1056 4432 1060
+rect 4448 1116 4512 1120
+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_1803.mag b/tapeout/outputs/mag/gpio_defaults_block_1803.mag
new file mode 100644
index 0000000..39a381a
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_1803.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4583 833 4617 867
+rect 1225 765 1259 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
+rect 1594 2150 1606 2202
+rect 1658 2150 1670 2202
+rect 1722 2150 2878 2202
+rect 2930 2150 2942 2202
+rect 2994 2150 3006 2202
+rect 3058 2150 3070 2202
+rect 3122 2150 4278 2202
+rect 4330 2150 4342 2202
+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
+rect 830 1606 842 1658
+rect 894 1606 906 1658
+rect 958 1606 970 1658
+rect 1022 1606 2178 1658
+rect 2230 1606 2242 1658
+rect 2294 1606 2306 1658
+rect 2358 1606 2370 1658
+rect 2422 1606 3578 1658
+rect 3630 1606 3642 1658
+rect 3694 1606 3706 1658
+rect 3758 1606 3770 1658
+rect 3822 1606 4978 1658
+rect 5030 1606 5042 1658
+rect 5094 1606 5106 1658
+rect 5158 1606 5170 1658
+rect 5222 1606 5980 1658
+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
+rect 0 1062 78 1114
+rect 130 1062 142 1114
+rect 194 1062 206 1114
+rect 258 1062 270 1114
+rect 322 1062 1478 1114
+rect 1530 1062 1542 1114
+rect 1594 1062 1606 1114
+rect 1658 1062 1670 1114
+rect 1722 1062 2878 1114
+rect 2930 1062 2942 1114
+rect 2994 1062 3006 1114
+rect 3058 1062 3070 1114
+rect 3122 1062 4278 1114
+rect 4330 1062 4342 1114
+rect 4394 1062 4406 1114
+rect 4458 1062 4470 1114
+rect 4522 1062 5980 1114
+rect 0 1040 5980 1062
+rect 198 824 204 876
+rect 256 864 262 876
+rect 937 864 995 873
+rect 1075 864 1133 873
+rect 1256 864 1262 916
+rect 1314 904 1320 916
+rect 1314 876 1450 904
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+rect 1422 864 1450 876
+rect 1489 864 1547 873
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+rect 256 824 262 836
+rect 937 827 995 836
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+rect 1627 827 1685 836
+rect 4571 864 4629 873
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+rect 5718 824 5724 836
+rect 5776 824 5782 876
+rect 1213 796 1271 805
+rect 1351 796 1409 805
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+rect 2038 796 2044 808
+rect 1038 768 1409 796
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+rect 658 688 664 740
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+rect 1038 728 1066 768
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+rect 4856 796 4862 808
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+rect 5219 768 5264 796
+rect 4856 756 4862 768
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+rect 3052 1060 3108 1116
+rect 3108 1060 3112 1116
+rect 3048 1056 3112 1060
+rect 4288 1116 4352 1120
+rect 4288 1060 4292 1116
+rect 4292 1060 4348 1116
+rect 4348 1060 4352 1116
+rect 4288 1056 4352 1060
+rect 4368 1116 4432 1120
+rect 4368 1060 4372 1116
+rect 4372 1060 4428 1116
+rect 4428 1060 4432 1116
+rect 4368 1056 4432 1060
+rect 4448 1116 4512 1120
+rect 4448 1060 4452 1116
+rect 4452 1060 4508 1116
+rect 4508 1060 4512 1116
+rect 4448 1056 4512 1060
+rect 788 572 852 576
+rect 788 516 792 572
+rect 792 516 848 572
+rect 848 516 852 572
+rect 788 512 852 516
+rect 868 572 932 576
+rect 868 516 872 572
+rect 872 516 928 572
+rect 928 516 932 572
+rect 868 512 932 516
+rect 948 572 1012 576
+rect 948 516 952 572
+rect 952 516 1008 572
+rect 1008 516 1012 572
+rect 948 512 1012 516
+rect 2188 572 2252 576
+rect 2188 516 2192 572
+rect 2192 516 2248 572
+rect 2248 516 2252 572
+rect 2188 512 2252 516
+rect 2268 572 2332 576
+rect 2268 516 2272 572
+rect 2272 516 2328 572
+rect 2328 516 2332 572
+rect 2268 512 2332 516
+rect 2348 572 2412 576
+rect 2348 516 2352 572
+rect 2352 516 2408 572
+rect 2408 516 2412 572
+rect 2348 512 2412 516
+rect 3588 572 3652 576
+rect 3588 516 3592 572
+rect 3592 516 3648 572
+rect 3648 516 3652 572
+rect 3588 512 3652 516
+rect 3668 572 3732 576
+rect 3668 516 3672 572
+rect 3672 516 3728 572
+rect 3728 516 3732 572
+rect 3668 512 3732 516
+rect 3748 572 3812 576
+rect 3748 516 3752 572
+rect 3752 516 3808 572
+rect 3808 516 3812 572
+rect 3748 512 3812 516
+rect 4988 572 5052 576
+rect 4988 516 4992 572
+rect 4992 516 5048 572
+rect 5048 516 5052 572
+rect 4988 512 5052 516
+rect 5068 572 5132 576
+rect 5068 516 5072 572
+rect 5072 516 5128 572
+rect 5128 516 5132 572
+rect 5068 512 5132 516
+rect 5148 572 5212 576
+rect 5148 516 5152 572
+rect 5152 516 5208 572
+rect 5208 516 5212 572
+rect 5148 512 5212 516
+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
+rect 152 2144 168 2208
+rect 232 2144 248 2208
+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
+rect 152 1056 168 1120
+rect 232 1056 248 1120
+rect 312 1056 340 1120
+rect 60 1014 340 1056
+rect 60 778 82 1014
+rect 318 778 340 1014
+rect 60 496 340 778
+rect 760 1714 1040 2224
+rect 760 1478 782 1714
+rect 1018 1478 1040 1714
+rect 760 576 1040 1478
+rect 760 512 788 576
+rect 852 512 868 576
+rect 932 512 948 576
+rect 1012 512 1040 576
+rect 760 496 1040 512
+rect 1460 2208 1740 2224
+rect 1460 2144 1488 2208
+rect 1552 2144 1568 2208
+rect 1632 2144 1648 2208
+rect 1712 2144 1740 2208
+rect 1460 1120 1740 2144
+rect 1460 1056 1488 1120
+rect 1552 1056 1568 1120
+rect 1632 1056 1648 1120
+rect 1712 1056 1740 1120
+rect 1460 1014 1740 1056
+rect 1460 778 1482 1014
+rect 1718 778 1740 1014
+rect 1460 496 1740 778
+rect 2160 1714 2440 2224
+rect 2160 1478 2182 1714
+rect 2418 1478 2440 1714
+rect 2160 576 2440 1478
+rect 2160 512 2188 576
+rect 2252 512 2268 576
+rect 2332 512 2348 576
+rect 2412 512 2440 576
+rect 2160 496 2440 512
+rect 2860 2208 3140 2224
+rect 2860 2144 2888 2208
+rect 2952 2144 2968 2208
+rect 3032 2144 3048 2208
+rect 3112 2144 3140 2208
+rect 2860 1120 3140 2144
+rect 2860 1056 2888 1120
+rect 2952 1056 2968 1120
+rect 3032 1056 3048 1120
+rect 3112 1056 3140 1120
+rect 2860 1014 3140 1056
+rect 2860 778 2882 1014
+rect 3118 778 3140 1014
+rect 2860 496 3140 778
+rect 3560 1714 3840 2224
+rect 3560 1478 3582 1714
+rect 3818 1478 3840 1714
+rect 3560 576 3840 1478
+rect 3560 512 3588 576
+rect 3652 512 3668 576
+rect 3732 512 3748 576
+rect 3812 512 3840 576
+rect 3560 496 3840 512
+rect 4260 2208 4540 2224
+rect 4260 2144 4288 2208
+rect 4352 2144 4368 2208
+rect 4432 2144 4448 2208
+rect 4512 2144 4540 2208
+rect 4260 1120 4540 2144
+rect 4260 1056 4288 1120
+rect 4352 1056 4368 1120
+rect 4432 1056 4448 1120
+rect 4512 1056 4540 1120
+rect 4260 1014 4540 1056
+rect 4260 778 4282 1014
+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1  FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_prog_zero.mag b/tapeout/outputs/mag/user_id_prog_zero.mag
new file mode 100644
index 0000000..6ad139c
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_prog_zero.mag
@@ -0,0 +1,3074 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1650371074
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1961 3553 1995 3587
+rect 2697 3553 2731 3587
+rect 3157 3553 3191 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< locali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1961 3553 1995 3587
+rect 2697 3553 2731 3587
+rect 3157 3553 3191 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< metal1 >>
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+rect 3390 2148 3394 2204
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+rect 3390 2144 3454 2148
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+rect 3530 2148 3534 2204
+rect 3470 2144 3534 2148
+rect 3550 2204 3614 2208
+rect 3550 2148 3554 2204
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+rect 3610 2148 3614 2204
+rect 3550 2144 3614 2148
+rect 3630 2204 3694 2208
+rect 3630 2148 3634 2204
+rect 3634 2148 3690 2204
+rect 3690 2148 3694 2204
+rect 3630 2144 3694 2148
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+rect 5095 2144 5159 2148
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+rect 5235 2148 5239 2204
+rect 5175 2144 5239 2148
+rect 5255 2204 5319 2208
+rect 5255 2148 5259 2204
+rect 5259 2148 5315 2204
+rect 5315 2148 5319 2204
+rect 5255 2144 5319 2148
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+rect 2637 1604 2641 1660
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+rect 2657 1660 2721 1664
+rect 2657 1604 2661 1660
+rect 2661 1604 2717 1660
+rect 2717 1604 2721 1660
+rect 2657 1600 2721 1604
+rect 2737 1660 2801 1664
+rect 2737 1604 2741 1660
+rect 2741 1604 2797 1660
+rect 2797 1604 2801 1660
+rect 2737 1600 2801 1604
+rect 2817 1660 2881 1664
+rect 2817 1604 2821 1660
+rect 2821 1604 2877 1660
+rect 2877 1604 2881 1660
+rect 2817 1600 2881 1604
+rect 4202 1660 4266 1664
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+rect 4206 1604 4262 1660
+rect 4262 1604 4266 1660
+rect 4202 1600 4266 1604
+rect 4282 1660 4346 1664
+rect 4282 1604 4286 1660
+rect 4286 1604 4342 1660
+rect 4342 1604 4346 1660
+rect 4282 1600 4346 1604
+rect 4362 1660 4426 1664
+rect 4362 1604 4366 1660
+rect 4366 1604 4422 1660
+rect 4422 1604 4426 1660
+rect 4362 1600 4426 1604
+rect 4442 1660 4506 1664
+rect 4442 1604 4446 1660
+rect 4446 1604 4502 1660
+rect 4502 1604 4506 1660
+rect 4442 1600 4506 1604
+rect 1764 1116 1828 1120
+rect 1764 1060 1768 1116
+rect 1768 1060 1824 1116
+rect 1824 1060 1828 1116
+rect 1764 1056 1828 1060
+rect 1844 1116 1908 1120
+rect 1844 1060 1848 1116
+rect 1848 1060 1904 1116
+rect 1904 1060 1908 1116
+rect 1844 1056 1908 1060
+rect 1924 1116 1988 1120
+rect 1924 1060 1928 1116
+rect 1928 1060 1984 1116
+rect 1984 1060 1988 1116
+rect 1924 1056 1988 1060
+rect 2004 1116 2068 1120
+rect 2004 1060 2008 1116
+rect 2008 1060 2064 1116
+rect 2064 1060 2068 1116
+rect 2004 1056 2068 1060
+rect 3390 1116 3454 1120
+rect 3390 1060 3394 1116
+rect 3394 1060 3450 1116
+rect 3450 1060 3454 1116
+rect 3390 1056 3454 1060
+rect 3470 1116 3534 1120
+rect 3470 1060 3474 1116
+rect 3474 1060 3530 1116
+rect 3530 1060 3534 1116
+rect 3470 1056 3534 1060
+rect 3550 1116 3614 1120
+rect 3550 1060 3554 1116
+rect 3554 1060 3610 1116
+rect 3610 1060 3614 1116
+rect 3550 1056 3614 1060
+rect 3630 1116 3694 1120
+rect 3630 1060 3634 1116
+rect 3634 1060 3690 1116
+rect 3690 1060 3694 1116
+rect 3630 1056 3694 1060
+rect 5015 1116 5079 1120
+rect 5015 1060 5019 1116
+rect 5019 1060 5075 1116
+rect 5075 1060 5079 1116
+rect 5015 1056 5079 1060
+rect 5095 1116 5159 1120
+rect 5095 1060 5099 1116
+rect 5099 1060 5155 1116
+rect 5155 1060 5159 1116
+rect 5095 1056 5159 1060
+rect 5175 1116 5239 1120
+rect 5175 1060 5179 1116
+rect 5179 1060 5235 1116
+rect 5235 1060 5239 1116
+rect 5175 1056 5239 1060
+rect 5255 1116 5319 1120
+rect 5255 1060 5259 1116
+rect 5259 1060 5315 1116
+rect 5315 1060 5319 1116
+rect 5255 1056 5319 1060
+<< metal4 >>
+rect 1756 5472 2076 6032
+rect 1756 5408 1764 5472
+rect 1828 5408 1844 5472
+rect 1908 5408 1924 5472
+rect 1988 5408 2004 5472
+rect 2068 5408 2076 5472
+rect 1756 5238 2076 5408
+rect 1756 5002 1798 5238
+rect 2034 5002 2076 5238
+rect 1756 4384 2076 5002
+rect 1756 4320 1764 4384
+rect 1828 4320 1844 4384
+rect 1908 4320 1924 4384
+rect 1988 4320 2004 4384
+rect 2068 4320 2076 4384
+rect 1756 3606 2076 4320
+rect 1756 3370 1798 3606
+rect 2034 3370 2076 3606
+rect 1756 3296 2076 3370
+rect 1756 3232 1764 3296
+rect 1828 3232 1844 3296
+rect 1908 3232 1924 3296
+rect 1988 3232 2004 3296
+rect 2068 3232 2076 3296
+rect 1756 2208 2076 3232
+rect 1756 2144 1764 2208
+rect 1828 2144 1844 2208
+rect 1908 2144 1924 2208
+rect 1988 2144 2004 2208
+rect 2068 2144 2076 2208
+rect 1756 1974 2076 2144
+rect 1756 1738 1798 1974
+rect 2034 1738 2076 1974
+rect 1756 1120 2076 1738
+rect 1756 1056 1764 1120
+rect 1828 1056 1844 1120
+rect 1908 1056 1924 1120
+rect 1988 1056 2004 1120
+rect 2068 1056 2076 1120
+rect 1756 1040 2076 1056
+rect 2569 6016 2889 6032
+rect 2569 5952 2577 6016
+rect 2641 5952 2657 6016
+rect 2721 5952 2737 6016
+rect 2801 5952 2817 6016
+rect 2881 5952 2889 6016
+rect 2569 4928 2889 5952
+rect 2569 4864 2577 4928
+rect 2641 4864 2657 4928
+rect 2721 4864 2737 4928
+rect 2801 4864 2817 4928
+rect 2881 4864 2889 4928
+rect 2569 4422 2889 4864
+rect 2569 4186 2611 4422
+rect 2847 4186 2889 4422
+rect 2569 3840 2889 4186
+rect 2569 3776 2577 3840
+rect 2641 3776 2657 3840
+rect 2721 3776 2737 3840
+rect 2801 3776 2817 3840
+rect 2881 3776 2889 3840
+rect 2569 2790 2889 3776
+rect 2569 2752 2611 2790
+rect 2847 2752 2889 2790
+rect 2569 2688 2577 2752
+rect 2881 2688 2889 2752
+rect 2569 2554 2611 2688
+rect 2847 2554 2889 2688
+rect 2569 1664 2889 2554
+rect 2569 1600 2577 1664
+rect 2641 1600 2657 1664
+rect 2721 1600 2737 1664
+rect 2801 1600 2817 1664
+rect 2881 1600 2889 1664
+rect 2569 1040 2889 1600
+rect 3382 5472 3702 6032
+rect 3382 5408 3390 5472
+rect 3454 5408 3470 5472
+rect 3534 5408 3550 5472
+rect 3614 5408 3630 5472
+rect 3694 5408 3702 5472
+rect 3382 5238 3702 5408
+rect 3382 5002 3424 5238
+rect 3660 5002 3702 5238
+rect 3382 4384 3702 5002
+rect 3382 4320 3390 4384
+rect 3454 4320 3470 4384
+rect 3534 4320 3550 4384
+rect 3614 4320 3630 4384
+rect 3694 4320 3702 4384
+rect 3382 3606 3702 4320
+rect 3382 3370 3424 3606
+rect 3660 3370 3702 3606
+rect 3382 3296 3702 3370
+rect 3382 3232 3390 3296
+rect 3454 3232 3470 3296
+rect 3534 3232 3550 3296
+rect 3614 3232 3630 3296
+rect 3694 3232 3702 3296
+rect 3382 2208 3702 3232
+rect 3382 2144 3390 2208
+rect 3454 2144 3470 2208
+rect 3534 2144 3550 2208
+rect 3614 2144 3630 2208
+rect 3694 2144 3702 2208
+rect 3382 1974 3702 2144
+rect 3382 1738 3424 1974
+rect 3660 1738 3702 1974
+rect 3382 1120 3702 1738
+rect 3382 1056 3390 1120
+rect 3454 1056 3470 1120
+rect 3534 1056 3550 1120
+rect 3614 1056 3630 1120
+rect 3694 1056 3702 1120
+rect 3382 1040 3702 1056
+rect 4194 6016 4514 6032
+rect 4194 5952 4202 6016
+rect 4266 5952 4282 6016
+rect 4346 5952 4362 6016
+rect 4426 5952 4442 6016
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+rect 4194 4928 4514 5952
+rect 4194 4864 4202 4928
+rect 4266 4864 4282 4928
+rect 4346 4864 4362 4928
+rect 4426 4864 4442 4928
+rect 4506 4864 4514 4928
+rect 4194 4422 4514 4864
+rect 4194 4186 4236 4422
+rect 4472 4186 4514 4422
+rect 4194 3840 4514 4186
+rect 4194 3776 4202 3840
+rect 4266 3776 4282 3840
+rect 4346 3776 4362 3840
+rect 4426 3776 4442 3840
+rect 4506 3776 4514 3840
+rect 4194 2790 4514 3776
+rect 4194 2752 4236 2790
+rect 4472 2752 4514 2790
+rect 4194 2688 4202 2752
+rect 4506 2688 4514 2752
+rect 4194 2554 4236 2688
+rect 4472 2554 4514 2688
+rect 4194 1664 4514 2554
+rect 4194 1600 4202 1664
+rect 4266 1600 4282 1664
+rect 4346 1600 4362 1664
+rect 4426 1600 4442 1664
+rect 4506 1600 4514 1664
+rect 4194 1040 4514 1600
+rect 5007 5472 5327 6032
+rect 5007 5408 5015 5472
+rect 5079 5408 5095 5472
+rect 5159 5408 5175 5472
+rect 5239 5408 5255 5472
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+rect 5007 5238 5327 5408
+rect 5007 5002 5049 5238
+rect 5285 5002 5327 5238
+rect 5007 4384 5327 5002
+rect 5007 4320 5015 4384
+rect 5079 4320 5095 4384
+rect 5159 4320 5175 4384
+rect 5239 4320 5255 4384
+rect 5319 4320 5327 4384
+rect 5007 3606 5327 4320
+rect 5007 3370 5049 3606
+rect 5285 3370 5327 3606
+rect 5007 3296 5327 3370
+rect 5007 3232 5015 3296
+rect 5079 3232 5095 3296
+rect 5159 3232 5175 3296
+rect 5239 3232 5255 3296
+rect 5319 3232 5327 3296
+rect 5007 2208 5327 3232
+rect 5007 2144 5015 2208
+rect 5079 2144 5095 2208
+rect 5159 2144 5175 2208
+rect 5239 2144 5255 2208
+rect 5319 2144 5327 2208
+rect 5007 1974 5327 2144
+rect 5007 1738 5049 1974
+rect 5285 1738 5327 1974
+rect 5007 1120 5327 1738
+rect 5007 1056 5015 1120
+rect 5079 1056 5095 1120
+rect 5159 1056 5175 1120
+rect 5239 1056 5255 1120
+rect 5319 1056 5327 1120
+rect 5007 1040 5327 1056
+<< via4 >>
+rect 1798 5002 2034 5238
+rect 1798 3370 2034 3606
+rect 1798 1738 2034 1974
+rect 2611 4186 2847 4422
+rect 2611 2752 2847 2790
+rect 2611 2688 2641 2752
+rect 2641 2688 2657 2752
+rect 2657 2688 2721 2752
+rect 2721 2688 2737 2752
+rect 2737 2688 2801 2752
+rect 2801 2688 2817 2752
+rect 2817 2688 2847 2752
+rect 2611 2554 2847 2688
+rect 3424 5002 3660 5238
+rect 3424 3370 3660 3606
+rect 3424 1738 3660 1974
+rect 4236 4186 4472 4422
+rect 4236 2752 4472 2790
+rect 4236 2688 4266 2752
+rect 4266 2688 4282 2752
+rect 4282 2688 4346 2752
+rect 4346 2688 4362 2752
+rect 4362 2688 4426 2752
+rect 4426 2688 4442 2752
+rect 4442 2688 4472 2752
+rect 4236 2554 4472 2688
+rect 5049 5002 5285 5238
+rect 5049 3370 5285 3606
+rect 5049 1738 5285 1974
+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
+rect 1104 4422 5980 4464
+rect 1104 4186 2611 4422
+rect 2847 4186 4236 4422
+rect 4472 4186 5980 4422
+rect 1104 4144 5980 4186
+rect 1104 3606 5980 3648
+rect 1104 3370 1798 3606
+rect 2034 3370 3424 3606
+rect 3660 3370 5049 3606
+rect 5285 3370 5980 3606
+rect 1104 3328 5980 3370
+rect 1104 2790 5980 2832
+rect 1104 2554 2611 2790
+rect 2847 2554 4236 2790
+rect 4472 2554 5980 2790
+rect 1104 2512 5980 2554
+rect 1104 1974 5980 2016
+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_15 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_21
+timestamp 1648946573
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_29 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_39
+timestamp 1648946573
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_1_6
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_12
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_3_42
+timestamp 1648946573
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_2  FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_5_23
+timestamp 1648946573
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_12
+timestamp 1648946573
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4  FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_40
+timestamp 1648946573
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[1\]
+timestamp 1648946573
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[2\]
+timestamp 1648946573
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[3\]
+timestamp 1648946573
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[4\]
+timestamp 1648946573
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[5\]
+timestamp 1648946573
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[6\]
+timestamp 1648946573
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[7\]
+timestamp 1648946573
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[8\]
+timestamp 1648946573
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[9\]
+timestamp 1648946573
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[10\]
+timestamp 1648946573
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[11\]
+timestamp 1648946573
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[12\]
+timestamp 1648946573
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[13\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[14\]
+timestamp 1648946573
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[15\]
+timestamp 1648946573
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[16\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[17\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[18\]
+timestamp 1648946573
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[19\]
+timestamp 1648946573
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[20\]
+timestamp 1648946573
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[21\]
+timestamp 1648946573
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[22\]
+timestamp 1648946573
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[23\]
+timestamp 1648946573
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[24\]
+timestamp 1648946573
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[25\]
+timestamp 1648946573
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[26\]
+timestamp 1648946573
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[27\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[28\]
+timestamp 1648946573
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[29\]
+timestamp 1648946573
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[30\]
+timestamp 1648946573
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[31\]
+timestamp 1648946573
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_programming.mag b/tapeout/outputs/mag/user_id_programming.mag
new file mode 100644
index 0000000..acbbddb
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_programming.mag
@@ -0,0 +1,3074 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1650371074
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 1961 4641 1995 4675
+rect 3065 4641 3099 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5365 4029 5399 4063
+rect 1685 3553 1719 3587
+rect 1777 3553 1811 3587
+rect 2513 3553 2547 3587
+rect 2973 3553 3007 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4629 2397 4663 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1501 1377 1535 1411
+rect 2973 1377 3007 1411
+rect 4445 1377 4479 1411
+<< locali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 1961 4641 1995 4675
+rect 3065 4641 3099 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5365 4029 5399 4063
+rect 1685 3553 1719 3587
+rect 1777 3553 1811 3587
+rect 2513 3553 2547 3587
+rect 2973 3553 3007 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4629 2397 4663 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1501 1377 1535 1411
+rect 2973 1377 3007 1411
+rect 4445 1377 4479 1411
+<< metal1 >>
+rect 1104 6010 5980 6032
+rect 1104 5958 2607 6010
+rect 2659 5958 2671 6010
+rect 2723 5958 2735 6010
+rect 2787 5958 2799 6010
+rect 2851 5958 4232 6010
+rect 4284 5958 4296 6010
+rect 4348 5958 4360 6010
+rect 4412 5958 4424 6010
+rect 4476 5958 5980 6010
+rect 1104 5936 5980 5958
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+rect 5097 5414 5109 5466
+rect 5161 5414 5173 5466
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+rect 5289 5414 5980 5466
+rect 1104 5392 5980 5414
+rect 4062 5108 4068 5160
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+rect 4157 5148 4215 5157
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+rect 4120 5108 4126 5120
+rect 4157 5111 4215 5120
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+rect 4614 5108 4620 5160
+rect 4672 5148 4678 5160
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+rect 5261 5148 5319 5157
+rect 4672 5120 5319 5148
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+rect 1104 4922 5980 4944
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+rect 4346 3776 4362 3840
+rect 4426 3776 4442 3840
+rect 4506 3776 4514 3840
+rect 4194 2790 4514 3776
+rect 4194 2752 4236 2790
+rect 4472 2752 4514 2790
+rect 4194 2688 4202 2752
+rect 4506 2688 4514 2752
+rect 4194 2554 4236 2688
+rect 4472 2554 4514 2688
+rect 4194 1664 4514 2554
+rect 4194 1600 4202 1664
+rect 4266 1600 4282 1664
+rect 4346 1600 4362 1664
+rect 4426 1600 4442 1664
+rect 4506 1600 4514 1664
+rect 4194 1040 4514 1600
+rect 5007 5472 5327 6032
+rect 5007 5408 5015 5472
+rect 5079 5408 5095 5472
+rect 5159 5408 5175 5472
+rect 5239 5408 5255 5472
+rect 5319 5408 5327 5472
+rect 5007 5238 5327 5408
+rect 5007 5002 5049 5238
+rect 5285 5002 5327 5238
+rect 5007 4384 5327 5002
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+rect 5007 3606 5327 4320
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+rect 5285 3370 5327 3606
+rect 5007 3296 5327 3370
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+rect 5079 3232 5095 3296
+rect 5159 3232 5175 3296
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+rect 5007 2208 5327 3232
+rect 5007 2144 5015 2208
+rect 5079 2144 5095 2208
+rect 5159 2144 5175 2208
+rect 5239 2144 5255 2208
+rect 5319 2144 5327 2208
+rect 5007 1974 5327 2144
+rect 5007 1738 5049 1974
+rect 5285 1738 5327 1974
+rect 5007 1120 5327 1738
+rect 5007 1056 5015 1120
+rect 5079 1056 5095 1120
+rect 5159 1056 5175 1120
+rect 5239 1056 5255 1120
+rect 5319 1056 5327 1120
+rect 5007 1040 5327 1056
+<< via4 >>
+rect 1798 5002 2034 5238
+rect 1798 3370 2034 3606
+rect 1798 1738 2034 1974
+rect 2611 4186 2847 4422
+rect 2611 2752 2847 2790
+rect 2611 2688 2641 2752
+rect 2641 2688 2657 2752
+rect 2657 2688 2721 2752
+rect 2721 2688 2737 2752
+rect 2737 2688 2801 2752
+rect 2801 2688 2817 2752
+rect 2817 2688 2847 2752
+rect 2611 2554 2847 2688
+rect 3424 5002 3660 5238
+rect 3424 3370 3660 3606
+rect 3424 1738 3660 1974
+rect 4236 4186 4472 4422
+rect 4236 2752 4472 2790
+rect 4236 2688 4266 2752
+rect 4266 2688 4282 2752
+rect 4282 2688 4346 2752
+rect 4346 2688 4362 2752
+rect 4362 2688 4426 2752
+rect 4426 2688 4442 2752
+rect 4442 2688 4472 2752
+rect 4236 2554 4472 2688
+rect 5049 5002 5285 5238
+rect 5049 3370 5285 3606
+rect 5049 1738 5285 1974
+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
+rect 1104 4422 5980 4464
+rect 1104 4186 2611 4422
+rect 2847 4186 4236 4422
+rect 4472 4186 5980 4422
+rect 1104 4144 5980 4186
+rect 1104 3606 5980 3648
+rect 1104 3370 1798 3606
+rect 2034 3370 3424 3606
+rect 3660 3370 5049 3606
+rect 5285 3370 5980 3606
+rect 1104 3328 5980 3370
+rect 1104 2790 5980 2832
+rect 1104 2554 2611 2790
+rect 2847 2554 4236 2790
+rect 4472 2554 5980 2790
+rect 1104 2512 5980 2554
+rect 1104 1974 5980 2016
+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1  FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_15 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_21
+timestamp 1648946573
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_0_29 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_8  FILLER_0_39
+timestamp 1648946573
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  FILLER_1_6
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_12
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1  FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__fill_2  FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_3_42
+timestamp 1648946573
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2  FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4  FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_2  FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8  FILLER_5_23
+timestamp 1648946573
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3  FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6  FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6  FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_12
+timestamp 1648946573
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3  FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4  FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1  FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8  FILLER_6_40
+timestamp 1648946573
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2  FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6  FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1  FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4  FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4  FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12  FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6  FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3  PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3  PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1  PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[1\]
+timestamp 1648946573
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[2\]
+timestamp 1648946573
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[3\]
+timestamp 1648946573
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[4\]
+timestamp 1648946573
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[5\]
+timestamp 1648946573
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[6\]
+timestamp 1648946573
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[7\]
+timestamp 1648946573
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[8\]
+timestamp 1648946573
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[9\]
+timestamp 1648946573
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[10\]
+timestamp 1648946573
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[11\]
+timestamp 1648946573
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[12\]
+timestamp 1648946573
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[13\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[14\]
+timestamp 1648946573
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[15\]
+timestamp 1648946573
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[16\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[17\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[18\]
+timestamp 1648946573
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[19\]
+timestamp 1648946573
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[20\]
+timestamp 1648946573
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[21\]
+timestamp 1648946573
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[22\]
+timestamp 1648946573
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[23\]
+timestamp 1648946573
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[24\]
+timestamp 1648946573
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[25\]
+timestamp 1648946573
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[26\]
+timestamp 1648946573
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[27\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[28\]
+timestamp 1648946573
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[29\]
+timestamp 1648946573
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[30\]
+timestamp 1648946573
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1  mask_rev_value\[31\]
+timestamp 1648946573
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_textblock.mag b/tapeout/outputs/mag/user_id_textblock.mag
new file mode 100644
index 0000000..ef714c1
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_6  alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+use alpha_D  alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_2 hexdigits
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_1  alphaX_3 hexdigits
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_7  alphaX_4 hexdigits
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_5
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_6
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0  alphaX_7
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/tapeout/outputs/oas/caravel_000710d6.oas b/tapeout/outputs/oas/caravel_000710d6.oas
new file mode 100644
index 0000000..f52cbda
--- /dev/null
+++ b/tapeout/outputs/oas/caravel_000710d6.oas
Binary files differ
diff --git a/tapeout/outputs/sky130A.magicrc b/tapeout/outputs/sky130A.magicrc
new file mode 100644
index 0000000..5d93e4e
--- /dev/null
+++ b/tapeout/outputs/sky130A.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+    scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDK_ROOT
+# "file nativename" guards against a local PDK_ROOT with "~" in the name
+if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} {
+    set PDK_ROOT /usr/local/pdk/volare/sky130/build/0059588eebfc704681dc2368bd1d33d96281d10f
+}
+
+# loading technology
+tech load $PDK_ROOT/sky130A/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDK_ROOT/sky130A/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDK_ROOT/sky130A/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}]} {
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_pr
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_io
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_osu_sc
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_pr/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_io/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_osu_sc/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/tapeout/outputs/verilog/gl/caravel.v b/tapeout/outputs/verilog/gl/caravel.v
new file mode 100644
index 0000000..4b63be3
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/caravel.v
@@ -0,0 +1,5435 @@
+/* Generated by Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) */
+
+module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+  wire caravel_clk;
+  wire caravel_clk2;
+  wire caravel_clk_buf;
+  wire caravel_rstn;
+  wire caravel_rstn_buf;
+  wire clk_passthru;
+  input clock;
+  wire clock_core;
+  wire clock_core_buf;
+  wire debug_in;
+  wire debug_mode;
+  wire debug_oeb;
+  wire debug_out;
+  wire ext_clk_sel;
+  wire ext_reset;
+  output flash_clk;
+  wire flash_clk_core;
+  wire flash_clk_frame;
+  wire flash_clk_frame_buf;
+  wire flash_clk_ieb;
+  wire flash_clk_ieb_buf;
+  wire flash_clk_oeb;
+  wire flash_clk_oeb_buf;
+  wire flash_clk_oeb_core;
+  output flash_csb;
+  wire flash_csb_core;
+  wire flash_csb_frame;
+  wire flash_csb_frame_buf;
+  wire flash_csb_ieb;
+  wire flash_csb_ieb_buf;
+  wire flash_csb_oeb;
+  wire flash_csb_oeb_buf;
+  wire flash_csb_oeb_core;
+  output flash_io0;
+  wire flash_io0_di;
+  wire flash_io0_di_buf;
+  wire flash_io0_di_core;
+  wire flash_io0_do;
+  wire flash_io0_do_buf;
+  wire flash_io0_do_core;
+  wire flash_io0_ieb;
+  wire flash_io0_ieb_buf;
+  wire flash_io0_ieb_core;
+  wire flash_io0_oeb;
+  wire flash_io0_oeb_buf;
+  wire flash_io0_oeb_core;
+  output flash_io1;
+  wire flash_io1_di;
+  wire flash_io1_di_buf;
+  wire flash_io1_di_core;
+  wire flash_io1_do;
+  wire flash_io1_do_buf;
+  wire flash_io1_do_core;
+  wire flash_io1_ieb;
+  wire flash_io1_ieb_buf;
+  wire flash_io1_ieb_core;
+  wire flash_io1_oeb;
+  wire flash_io1_oeb_buf;
+  wire flash_io1_oeb_core;
+  wire flash_io2_di_core;
+  wire flash_io2_do_core;
+  wire flash_io2_ieb_core;
+  wire flash_io2_oeb_core;
+  wire flash_io3_di_core;
+  wire flash_io3_do_core;
+  wire flash_io3_ieb_core;
+  wire flash_io3_oeb_core;
+  inout gpio;
+  wire \gpio_clock_1[0] ;
+  wire \gpio_clock_1[10] ;
+  wire \gpio_clock_1[11] ;
+  wire \gpio_clock_1[12] ;
+  wire \gpio_clock_1[13] ;
+  wire \gpio_clock_1[14] ;
+  wire \gpio_clock_1[15] ;
+  wire \gpio_clock_1[16] ;
+  wire \gpio_clock_1[17] ;
+  wire \gpio_clock_1[18] ;
+  wire \gpio_clock_1[1] ;
+  wire \gpio_clock_1[2] ;
+  wire \gpio_clock_1[3] ;
+  wire \gpio_clock_1[4] ;
+  wire \gpio_clock_1[5] ;
+  wire \gpio_clock_1[6] ;
+  wire \gpio_clock_1[7] ;
+  wire \gpio_clock_1[8] ;
+  wire \gpio_clock_1[9] ;
+  wire \gpio_clock_1_shifted[0] ;
+  wire \gpio_clock_1_shifted[10] ;
+  wire \gpio_clock_1_shifted[11] ;
+  wire \gpio_clock_1_shifted[12] ;
+  wire \gpio_clock_1_shifted[13] ;
+  wire \gpio_clock_1_shifted[14] ;
+  wire \gpio_clock_1_shifted[15] ;
+  wire \gpio_clock_1_shifted[16] ;
+  wire \gpio_clock_1_shifted[17] ;
+  wire \gpio_clock_1_shifted[18] ;
+  wire \gpio_clock_1_shifted[1] ;
+  wire \gpio_clock_1_shifted[2] ;
+  wire \gpio_clock_1_shifted[3] ;
+  wire \gpio_clock_1_shifted[4] ;
+  wire \gpio_clock_1_shifted[5] ;
+  wire \gpio_clock_1_shifted[6] ;
+  wire \gpio_clock_1_shifted[7] ;
+  wire \gpio_clock_1_shifted[8] ;
+  wire \gpio_clock_1_shifted[9] ;
+  wire \gpio_clock_2[0] ;
+  wire \gpio_clock_2[10] ;
+  wire \gpio_clock_2[11] ;
+  wire \gpio_clock_2[12] ;
+  wire \gpio_clock_2[13] ;
+  wire \gpio_clock_2[14] ;
+  wire \gpio_clock_2[15] ;
+  wire \gpio_clock_2[16] ;
+  wire \gpio_clock_2[17] ;
+  wire \gpio_clock_2[18] ;
+  wire \gpio_clock_2[1] ;
+  wire \gpio_clock_2[2] ;
+  wire \gpio_clock_2[3] ;
+  wire \gpio_clock_2[4] ;
+  wire \gpio_clock_2[5] ;
+  wire \gpio_clock_2[6] ;
+  wire \gpio_clock_2[7] ;
+  wire \gpio_clock_2[8] ;
+  wire \gpio_clock_2[9] ;
+  wire \gpio_clock_2_shifted[0] ;
+  wire \gpio_clock_2_shifted[10] ;
+  wire \gpio_clock_2_shifted[11] ;
+  wire \gpio_clock_2_shifted[12] ;
+  wire \gpio_clock_2_shifted[13] ;
+  wire \gpio_clock_2_shifted[14] ;
+  wire \gpio_clock_2_shifted[15] ;
+  wire \gpio_clock_2_shifted[16] ;
+  wire \gpio_clock_2_shifted[17] ;
+  wire \gpio_clock_2_shifted[18] ;
+  wire \gpio_clock_2_shifted[1] ;
+  wire \gpio_clock_2_shifted[2] ;
+  wire \gpio_clock_2_shifted[3] ;
+  wire \gpio_clock_2_shifted[4] ;
+  wire \gpio_clock_2_shifted[5] ;
+  wire \gpio_clock_2_shifted[6] ;
+  wire \gpio_clock_2_shifted[7] ;
+  wire \gpio_clock_2_shifted[8] ;
+  wire \gpio_clock_2_shifted[9] ;
+  wire \gpio_defaults[0] ;
+  wire \gpio_defaults[100] ;
+  wire \gpio_defaults[101] ;
+  wire \gpio_defaults[102] ;
+  wire \gpio_defaults[103] ;
+  wire \gpio_defaults[104] ;
+  wire \gpio_defaults[105] ;
+  wire \gpio_defaults[106] ;
+  wire \gpio_defaults[107] ;
+  wire \gpio_defaults[108] ;
+  wire \gpio_defaults[109] ;
+  wire \gpio_defaults[10] ;
+  wire \gpio_defaults[110] ;
+  wire \gpio_defaults[111] ;
+  wire \gpio_defaults[112] ;
+  wire \gpio_defaults[113] ;
+  wire \gpio_defaults[114] ;
+  wire \gpio_defaults[115] ;
+  wire \gpio_defaults[116] ;
+  wire \gpio_defaults[117] ;
+  wire \gpio_defaults[118] ;
+  wire \gpio_defaults[119] ;
+  wire \gpio_defaults[11] ;
+  wire \gpio_defaults[120] ;
+  wire \gpio_defaults[121] ;
+  wire \gpio_defaults[122] ;
+  wire \gpio_defaults[123] ;
+  wire \gpio_defaults[124] ;
+  wire \gpio_defaults[125] ;
+  wire \gpio_defaults[126] ;
+  wire \gpio_defaults[127] ;
+  wire \gpio_defaults[128] ;
+  wire \gpio_defaults[129] ;
+  wire \gpio_defaults[12] ;
+  wire \gpio_defaults[130] ;
+  wire \gpio_defaults[131] ;
+  wire \gpio_defaults[132] ;
+  wire \gpio_defaults[133] ;
+  wire \gpio_defaults[134] ;
+  wire \gpio_defaults[135] ;
+  wire \gpio_defaults[136] ;
+  wire \gpio_defaults[137] ;
+  wire \gpio_defaults[138] ;
+  wire \gpio_defaults[139] ;
+  wire \gpio_defaults[13] ;
+  wire \gpio_defaults[140] ;
+  wire \gpio_defaults[141] ;
+  wire \gpio_defaults[142] ;
+  wire \gpio_defaults[143] ;
+  wire \gpio_defaults[144] ;
+  wire \gpio_defaults[145] ;
+  wire \gpio_defaults[146] ;
+  wire \gpio_defaults[147] ;
+  wire \gpio_defaults[148] ;
+  wire \gpio_defaults[149] ;
+  wire \gpio_defaults[14] ;
+  wire \gpio_defaults[150] ;
+  wire \gpio_defaults[151] ;
+  wire \gpio_defaults[152] ;
+  wire \gpio_defaults[153] ;
+  wire \gpio_defaults[154] ;
+  wire \gpio_defaults[155] ;
+  wire \gpio_defaults[156] ;
+  wire \gpio_defaults[157] ;
+  wire \gpio_defaults[158] ;
+  wire \gpio_defaults[159] ;
+  wire \gpio_defaults[15] ;
+  wire \gpio_defaults[160] ;
+  wire \gpio_defaults[161] ;
+  wire \gpio_defaults[162] ;
+  wire \gpio_defaults[163] ;
+  wire \gpio_defaults[164] ;
+  wire \gpio_defaults[165] ;
+  wire \gpio_defaults[166] ;
+  wire \gpio_defaults[167] ;
+  wire \gpio_defaults[168] ;
+  wire \gpio_defaults[169] ;
+  wire \gpio_defaults[16] ;
+  wire \gpio_defaults[170] ;
+  wire \gpio_defaults[171] ;
+  wire \gpio_defaults[172] ;
+  wire \gpio_defaults[173] ;
+  wire \gpio_defaults[174] ;
+  wire \gpio_defaults[175] ;
+  wire \gpio_defaults[176] ;
+  wire \gpio_defaults[177] ;
+  wire \gpio_defaults[178] ;
+  wire \gpio_defaults[179] ;
+  wire \gpio_defaults[17] ;
+  wire \gpio_defaults[180] ;
+  wire \gpio_defaults[181] ;
+  wire \gpio_defaults[182] ;
+  wire \gpio_defaults[183] ;
+  wire \gpio_defaults[184] ;
+  wire \gpio_defaults[185] ;
+  wire \gpio_defaults[186] ;
+  wire \gpio_defaults[187] ;
+  wire \gpio_defaults[188] ;
+  wire \gpio_defaults[189] ;
+  wire \gpio_defaults[18] ;
+  wire \gpio_defaults[190] ;
+  wire \gpio_defaults[191] ;
+  wire \gpio_defaults[192] ;
+  wire \gpio_defaults[193] ;
+  wire \gpio_defaults[194] ;
+  wire \gpio_defaults[195] ;
+  wire \gpio_defaults[196] ;
+  wire \gpio_defaults[197] ;
+  wire \gpio_defaults[198] ;
+  wire \gpio_defaults[199] ;
+  wire \gpio_defaults[19] ;
+  wire \gpio_defaults[1] ;
+  wire \gpio_defaults[200] ;
+  wire \gpio_defaults[201] ;
+  wire \gpio_defaults[202] ;
+  wire \gpio_defaults[203] ;
+  wire \gpio_defaults[204] ;
+  wire \gpio_defaults[205] ;
+  wire \gpio_defaults[206] ;
+  wire \gpio_defaults[207] ;
+  wire \gpio_defaults[208] ;
+  wire \gpio_defaults[209] ;
+  wire \gpio_defaults[20] ;
+  wire \gpio_defaults[210] ;
+  wire \gpio_defaults[211] ;
+  wire \gpio_defaults[212] ;
+  wire \gpio_defaults[213] ;
+  wire \gpio_defaults[214] ;
+  wire \gpio_defaults[215] ;
+  wire \gpio_defaults[216] ;
+  wire \gpio_defaults[217] ;
+  wire \gpio_defaults[218] ;
+  wire \gpio_defaults[219] ;
+  wire \gpio_defaults[21] ;
+  wire \gpio_defaults[220] ;
+  wire \gpio_defaults[221] ;
+  wire \gpio_defaults[222] ;
+  wire \gpio_defaults[223] ;
+  wire \gpio_defaults[224] ;
+  wire \gpio_defaults[225] ;
+  wire \gpio_defaults[226] ;
+  wire \gpio_defaults[227] ;
+  wire \gpio_defaults[228] ;
+  wire \gpio_defaults[229] ;
+  wire \gpio_defaults[22] ;
+  wire \gpio_defaults[230] ;
+  wire \gpio_defaults[231] ;
+  wire \gpio_defaults[232] ;
+  wire \gpio_defaults[233] ;
+  wire \gpio_defaults[234] ;
+  wire \gpio_defaults[235] ;
+  wire \gpio_defaults[236] ;
+  wire \gpio_defaults[237] ;
+  wire \gpio_defaults[238] ;
+  wire \gpio_defaults[239] ;
+  wire \gpio_defaults[23] ;
+  wire \gpio_defaults[240] ;
+  wire \gpio_defaults[241] ;
+  wire \gpio_defaults[242] ;
+  wire \gpio_defaults[243] ;
+  wire \gpio_defaults[244] ;
+  wire \gpio_defaults[245] ;
+  wire \gpio_defaults[246] ;
+  wire \gpio_defaults[247] ;
+  wire \gpio_defaults[248] ;
+  wire \gpio_defaults[249] ;
+  wire \gpio_defaults[24] ;
+  wire \gpio_defaults[250] ;
+  wire \gpio_defaults[251] ;
+  wire \gpio_defaults[252] ;
+  wire \gpio_defaults[253] ;
+  wire \gpio_defaults[254] ;
+  wire \gpio_defaults[255] ;
+  wire \gpio_defaults[256] ;
+  wire \gpio_defaults[257] ;
+  wire \gpio_defaults[258] ;
+  wire \gpio_defaults[259] ;
+  wire \gpio_defaults[25] ;
+  wire \gpio_defaults[260] ;
+  wire \gpio_defaults[261] ;
+  wire \gpio_defaults[262] ;
+  wire \gpio_defaults[263] ;
+  wire \gpio_defaults[264] ;
+  wire \gpio_defaults[265] ;
+  wire \gpio_defaults[266] ;
+  wire \gpio_defaults[267] ;
+  wire \gpio_defaults[268] ;
+  wire \gpio_defaults[269] ;
+  wire \gpio_defaults[26] ;
+  wire \gpio_defaults[270] ;
+  wire \gpio_defaults[271] ;
+  wire \gpio_defaults[272] ;
+  wire \gpio_defaults[273] ;
+  wire \gpio_defaults[274] ;
+  wire \gpio_defaults[275] ;
+  wire \gpio_defaults[276] ;
+  wire \gpio_defaults[277] ;
+  wire \gpio_defaults[278] ;
+  wire \gpio_defaults[279] ;
+  wire \gpio_defaults[27] ;
+  wire \gpio_defaults[280] ;
+  wire \gpio_defaults[281] ;
+  wire \gpio_defaults[282] ;
+  wire \gpio_defaults[283] ;
+  wire \gpio_defaults[284] ;
+  wire \gpio_defaults[285] ;
+  wire \gpio_defaults[286] ;
+  wire \gpio_defaults[287] ;
+  wire \gpio_defaults[288] ;
+  wire \gpio_defaults[289] ;
+  wire \gpio_defaults[28] ;
+  wire \gpio_defaults[290] ;
+  wire \gpio_defaults[291] ;
+  wire \gpio_defaults[292] ;
+  wire \gpio_defaults[293] ;
+  wire \gpio_defaults[294] ;
+  wire \gpio_defaults[295] ;
+  wire \gpio_defaults[296] ;
+  wire \gpio_defaults[297] ;
+  wire \gpio_defaults[298] ;
+  wire \gpio_defaults[299] ;
+  wire \gpio_defaults[29] ;
+  wire \gpio_defaults[2] ;
+  wire \gpio_defaults[300] ;
+  wire \gpio_defaults[301] ;
+  wire \gpio_defaults[302] ;
+  wire \gpio_defaults[303] ;
+  wire \gpio_defaults[304] ;
+  wire \gpio_defaults[305] ;
+  wire \gpio_defaults[306] ;
+  wire \gpio_defaults[307] ;
+  wire \gpio_defaults[308] ;
+  wire \gpio_defaults[309] ;
+  wire \gpio_defaults[30] ;
+  wire \gpio_defaults[310] ;
+  wire \gpio_defaults[311] ;
+  wire \gpio_defaults[312] ;
+  wire \gpio_defaults[313] ;
+  wire \gpio_defaults[314] ;
+  wire \gpio_defaults[315] ;
+  wire \gpio_defaults[316] ;
+  wire \gpio_defaults[317] ;
+  wire \gpio_defaults[318] ;
+  wire \gpio_defaults[319] ;
+  wire \gpio_defaults[31] ;
+  wire \gpio_defaults[320] ;
+  wire \gpio_defaults[321] ;
+  wire \gpio_defaults[322] ;
+  wire \gpio_defaults[323] ;
+  wire \gpio_defaults[324] ;
+  wire \gpio_defaults[325] ;
+  wire \gpio_defaults[326] ;
+  wire \gpio_defaults[327] ;
+  wire \gpio_defaults[328] ;
+  wire \gpio_defaults[329] ;
+  wire \gpio_defaults[32] ;
+  wire \gpio_defaults[330] ;
+  wire \gpio_defaults[331] ;
+  wire \gpio_defaults[332] ;
+  wire \gpio_defaults[333] ;
+  wire \gpio_defaults[334] ;
+  wire \gpio_defaults[335] ;
+  wire \gpio_defaults[336] ;
+  wire \gpio_defaults[337] ;
+  wire \gpio_defaults[338] ;
+  wire \gpio_defaults[339] ;
+  wire \gpio_defaults[33] ;
+  wire \gpio_defaults[340] ;
+  wire \gpio_defaults[341] ;
+  wire \gpio_defaults[342] ;
+  wire \gpio_defaults[343] ;
+  wire \gpio_defaults[344] ;
+  wire \gpio_defaults[345] ;
+  wire \gpio_defaults[346] ;
+  wire \gpio_defaults[347] ;
+  wire \gpio_defaults[348] ;
+  wire \gpio_defaults[349] ;
+  wire \gpio_defaults[34] ;
+  wire \gpio_defaults[350] ;
+  wire \gpio_defaults[351] ;
+  wire \gpio_defaults[352] ;
+  wire \gpio_defaults[353] ;
+  wire \gpio_defaults[354] ;
+  wire \gpio_defaults[355] ;
+  wire \gpio_defaults[356] ;
+  wire \gpio_defaults[357] ;
+  wire \gpio_defaults[358] ;
+  wire \gpio_defaults[359] ;
+  wire \gpio_defaults[35] ;
+  wire \gpio_defaults[360] ;
+  wire \gpio_defaults[361] ;
+  wire \gpio_defaults[362] ;
+  wire \gpio_defaults[363] ;
+  wire \gpio_defaults[364] ;
+  wire \gpio_defaults[365] ;
+  wire \gpio_defaults[366] ;
+  wire \gpio_defaults[367] ;
+  wire \gpio_defaults[368] ;
+  wire \gpio_defaults[369] ;
+  wire \gpio_defaults[36] ;
+  wire \gpio_defaults[370] ;
+  wire \gpio_defaults[371] ;
+  wire \gpio_defaults[372] ;
+  wire \gpio_defaults[373] ;
+  wire \gpio_defaults[374] ;
+  wire \gpio_defaults[375] ;
+  wire \gpio_defaults[376] ;
+  wire \gpio_defaults[377] ;
+  wire \gpio_defaults[378] ;
+  wire \gpio_defaults[379] ;
+  wire \gpio_defaults[37] ;
+  wire \gpio_defaults[380] ;
+  wire \gpio_defaults[381] ;
+  wire \gpio_defaults[382] ;
+  wire \gpio_defaults[383] ;
+  wire \gpio_defaults[384] ;
+  wire \gpio_defaults[385] ;
+  wire \gpio_defaults[386] ;
+  wire \gpio_defaults[387] ;
+  wire \gpio_defaults[388] ;
+  wire \gpio_defaults[389] ;
+  wire \gpio_defaults[38] ;
+  wire \gpio_defaults[390] ;
+  wire \gpio_defaults[391] ;
+  wire \gpio_defaults[392] ;
+  wire \gpio_defaults[393] ;
+  wire \gpio_defaults[394] ;
+  wire \gpio_defaults[395] ;
+  wire \gpio_defaults[396] ;
+  wire \gpio_defaults[397] ;
+  wire \gpio_defaults[398] ;
+  wire \gpio_defaults[399] ;
+  wire \gpio_defaults[39] ;
+  wire \gpio_defaults[3] ;
+  wire \gpio_defaults[400] ;
+  wire \gpio_defaults[401] ;
+  wire \gpio_defaults[402] ;
+  wire \gpio_defaults[403] ;
+  wire \gpio_defaults[404] ;
+  wire \gpio_defaults[405] ;
+  wire \gpio_defaults[406] ;
+  wire \gpio_defaults[407] ;
+  wire \gpio_defaults[408] ;
+  wire \gpio_defaults[409] ;
+  wire \gpio_defaults[40] ;
+  wire \gpio_defaults[410] ;
+  wire \gpio_defaults[411] ;
+  wire \gpio_defaults[412] ;
+  wire \gpio_defaults[413] ;
+  wire \gpio_defaults[414] ;
+  wire \gpio_defaults[415] ;
+  wire \gpio_defaults[416] ;
+  wire \gpio_defaults[417] ;
+  wire \gpio_defaults[418] ;
+  wire \gpio_defaults[419] ;
+  wire \gpio_defaults[41] ;
+  wire \gpio_defaults[420] ;
+  wire \gpio_defaults[421] ;
+  wire \gpio_defaults[422] ;
+  wire \gpio_defaults[423] ;
+  wire \gpio_defaults[424] ;
+  wire \gpio_defaults[425] ;
+  wire \gpio_defaults[426] ;
+  wire \gpio_defaults[427] ;
+  wire \gpio_defaults[428] ;
+  wire \gpio_defaults[429] ;
+  wire \gpio_defaults[42] ;
+  wire \gpio_defaults[430] ;
+  wire \gpio_defaults[431] ;
+  wire \gpio_defaults[432] ;
+  wire \gpio_defaults[433] ;
+  wire \gpio_defaults[434] ;
+  wire \gpio_defaults[435] ;
+  wire \gpio_defaults[436] ;
+  wire \gpio_defaults[437] ;
+  wire \gpio_defaults[438] ;
+  wire \gpio_defaults[439] ;
+  wire \gpio_defaults[43] ;
+  wire \gpio_defaults[440] ;
+  wire \gpio_defaults[441] ;
+  wire \gpio_defaults[442] ;
+  wire \gpio_defaults[443] ;
+  wire \gpio_defaults[444] ;
+  wire \gpio_defaults[445] ;
+  wire \gpio_defaults[446] ;
+  wire \gpio_defaults[447] ;
+  wire \gpio_defaults[448] ;
+  wire \gpio_defaults[449] ;
+  wire \gpio_defaults[44] ;
+  wire \gpio_defaults[450] ;
+  wire \gpio_defaults[451] ;
+  wire \gpio_defaults[452] ;
+  wire \gpio_defaults[453] ;
+  wire \gpio_defaults[454] ;
+  wire \gpio_defaults[455] ;
+  wire \gpio_defaults[456] ;
+  wire \gpio_defaults[457] ;
+  wire \gpio_defaults[458] ;
+  wire \gpio_defaults[459] ;
+  wire \gpio_defaults[45] ;
+  wire \gpio_defaults[460] ;
+  wire \gpio_defaults[461] ;
+  wire \gpio_defaults[462] ;
+  wire \gpio_defaults[463] ;
+  wire \gpio_defaults[464] ;
+  wire \gpio_defaults[465] ;
+  wire \gpio_defaults[466] ;
+  wire \gpio_defaults[467] ;
+  wire \gpio_defaults[468] ;
+  wire \gpio_defaults[469] ;
+  wire \gpio_defaults[46] ;
+  wire \gpio_defaults[470] ;
+  wire \gpio_defaults[471] ;
+  wire \gpio_defaults[472] ;
+  wire \gpio_defaults[473] ;
+  wire \gpio_defaults[474] ;
+  wire \gpio_defaults[475] ;
+  wire \gpio_defaults[476] ;
+  wire \gpio_defaults[477] ;
+  wire \gpio_defaults[478] ;
+  wire \gpio_defaults[479] ;
+  wire \gpio_defaults[47] ;
+  wire \gpio_defaults[480] ;
+  wire \gpio_defaults[481] ;
+  wire \gpio_defaults[482] ;
+  wire \gpio_defaults[483] ;
+  wire \gpio_defaults[484] ;
+  wire \gpio_defaults[485] ;
+  wire \gpio_defaults[486] ;
+  wire \gpio_defaults[487] ;
+  wire \gpio_defaults[488] ;
+  wire \gpio_defaults[489] ;
+  wire \gpio_defaults[48] ;
+  wire \gpio_defaults[490] ;
+  wire \gpio_defaults[491] ;
+  wire \gpio_defaults[492] ;
+  wire \gpio_defaults[493] ;
+  wire \gpio_defaults[49] ;
+  wire \gpio_defaults[4] ;
+  wire \gpio_defaults[50] ;
+  wire \gpio_defaults[51] ;
+  wire \gpio_defaults[52] ;
+  wire \gpio_defaults[53] ;
+  wire \gpio_defaults[54] ;
+  wire \gpio_defaults[55] ;
+  wire \gpio_defaults[56] ;
+  wire \gpio_defaults[57] ;
+  wire \gpio_defaults[58] ;
+  wire \gpio_defaults[59] ;
+  wire \gpio_defaults[5] ;
+  wire \gpio_defaults[60] ;
+  wire \gpio_defaults[61] ;
+  wire \gpio_defaults[62] ;
+  wire \gpio_defaults[63] ;
+  wire \gpio_defaults[64] ;
+  wire \gpio_defaults[65] ;
+  wire \gpio_defaults[66] ;
+  wire \gpio_defaults[67] ;
+  wire \gpio_defaults[68] ;
+  wire \gpio_defaults[69] ;
+  wire \gpio_defaults[6] ;
+  wire \gpio_defaults[70] ;
+  wire \gpio_defaults[71] ;
+  wire \gpio_defaults[72] ;
+  wire \gpio_defaults[73] ;
+  wire \gpio_defaults[74] ;
+  wire \gpio_defaults[75] ;
+  wire \gpio_defaults[76] ;
+  wire \gpio_defaults[77] ;
+  wire \gpio_defaults[78] ;
+  wire \gpio_defaults[79] ;
+  wire \gpio_defaults[7] ;
+  wire \gpio_defaults[80] ;
+  wire \gpio_defaults[81] ;
+  wire \gpio_defaults[82] ;
+  wire \gpio_defaults[83] ;
+  wire \gpio_defaults[84] ;
+  wire \gpio_defaults[85] ;
+  wire \gpio_defaults[86] ;
+  wire \gpio_defaults[87] ;
+  wire \gpio_defaults[88] ;
+  wire \gpio_defaults[89] ;
+  wire \gpio_defaults[8] ;
+  wire \gpio_defaults[90] ;
+  wire \gpio_defaults[91] ;
+  wire \gpio_defaults[92] ;
+  wire \gpio_defaults[93] ;
+  wire \gpio_defaults[94] ;
+  wire \gpio_defaults[95] ;
+  wire \gpio_defaults[96] ;
+  wire \gpio_defaults[97] ;
+  wire \gpio_defaults[98] ;
+  wire \gpio_defaults[99] ;
+  wire \gpio_defaults[9] ;
+  wire gpio_in_core;
+  wire gpio_inenb_core;
+  wire \gpio_load_1[0] ;
+  wire \gpio_load_1[10] ;
+  wire \gpio_load_1[11] ;
+  wire \gpio_load_1[12] ;
+  wire \gpio_load_1[13] ;
+  wire \gpio_load_1[14] ;
+  wire \gpio_load_1[15] ;
+  wire \gpio_load_1[16] ;
+  wire \gpio_load_1[17] ;
+  wire \gpio_load_1[18] ;
+  wire \gpio_load_1[1] ;
+  wire \gpio_load_1[2] ;
+  wire \gpio_load_1[3] ;
+  wire \gpio_load_1[4] ;
+  wire \gpio_load_1[5] ;
+  wire \gpio_load_1[6] ;
+  wire \gpio_load_1[7] ;
+  wire \gpio_load_1[8] ;
+  wire \gpio_load_1[9] ;
+  wire \gpio_load_1_shifted[0] ;
+  wire \gpio_load_1_shifted[10] ;
+  wire \gpio_load_1_shifted[11] ;
+  wire \gpio_load_1_shifted[12] ;
+  wire \gpio_load_1_shifted[13] ;
+  wire \gpio_load_1_shifted[14] ;
+  wire \gpio_load_1_shifted[15] ;
+  wire \gpio_load_1_shifted[16] ;
+  wire \gpio_load_1_shifted[17] ;
+  wire \gpio_load_1_shifted[18] ;
+  wire \gpio_load_1_shifted[1] ;
+  wire \gpio_load_1_shifted[2] ;
+  wire \gpio_load_1_shifted[3] ;
+  wire \gpio_load_1_shifted[4] ;
+  wire \gpio_load_1_shifted[5] ;
+  wire \gpio_load_1_shifted[6] ;
+  wire \gpio_load_1_shifted[7] ;
+  wire \gpio_load_1_shifted[8] ;
+  wire \gpio_load_1_shifted[9] ;
+  wire \gpio_load_2[0] ;
+  wire \gpio_load_2[10] ;
+  wire \gpio_load_2[11] ;
+  wire \gpio_load_2[12] ;
+  wire \gpio_load_2[13] ;
+  wire \gpio_load_2[14] ;
+  wire \gpio_load_2[15] ;
+  wire \gpio_load_2[16] ;
+  wire \gpio_load_2[17] ;
+  wire \gpio_load_2[18] ;
+  wire \gpio_load_2[1] ;
+  wire \gpio_load_2[2] ;
+  wire \gpio_load_2[3] ;
+  wire \gpio_load_2[4] ;
+  wire \gpio_load_2[5] ;
+  wire \gpio_load_2[6] ;
+  wire \gpio_load_2[7] ;
+  wire \gpio_load_2[8] ;
+  wire \gpio_load_2[9] ;
+  wire \gpio_load_2_shifted[0] ;
+  wire \gpio_load_2_shifted[10] ;
+  wire \gpio_load_2_shifted[11] ;
+  wire \gpio_load_2_shifted[12] ;
+  wire \gpio_load_2_shifted[13] ;
+  wire \gpio_load_2_shifted[14] ;
+  wire \gpio_load_2_shifted[15] ;
+  wire \gpio_load_2_shifted[16] ;
+  wire \gpio_load_2_shifted[17] ;
+  wire \gpio_load_2_shifted[18] ;
+  wire \gpio_load_2_shifted[1] ;
+  wire \gpio_load_2_shifted[2] ;
+  wire \gpio_load_2_shifted[3] ;
+  wire \gpio_load_2_shifted[4] ;
+  wire \gpio_load_2_shifted[5] ;
+  wire \gpio_load_2_shifted[6] ;
+  wire \gpio_load_2_shifted[7] ;
+  wire \gpio_load_2_shifted[8] ;
+  wire \gpio_load_2_shifted[9] ;
+  wire gpio_mode0_core;
+  wire gpio_mode1_core;
+  wire gpio_out_core;
+  wire gpio_outenb_core;
+  wire \gpio_resetn_1[0] ;
+  wire \gpio_resetn_1[10] ;
+  wire \gpio_resetn_1[11] ;
+  wire \gpio_resetn_1[12] ;
+  wire \gpio_resetn_1[13] ;
+  wire \gpio_resetn_1[14] ;
+  wire \gpio_resetn_1[15] ;
+  wire \gpio_resetn_1[16] ;
+  wire \gpio_resetn_1[17] ;
+  wire \gpio_resetn_1[18] ;
+  wire \gpio_resetn_1[1] ;
+  wire \gpio_resetn_1[2] ;
+  wire \gpio_resetn_1[3] ;
+  wire \gpio_resetn_1[4] ;
+  wire \gpio_resetn_1[5] ;
+  wire \gpio_resetn_1[6] ;
+  wire \gpio_resetn_1[7] ;
+  wire \gpio_resetn_1[8] ;
+  wire \gpio_resetn_1[9] ;
+  wire \gpio_resetn_1_shifted[0] ;
+  wire \gpio_resetn_1_shifted[10] ;
+  wire \gpio_resetn_1_shifted[11] ;
+  wire \gpio_resetn_1_shifted[12] ;
+  wire \gpio_resetn_1_shifted[13] ;
+  wire \gpio_resetn_1_shifted[14] ;
+  wire \gpio_resetn_1_shifted[15] ;
+  wire \gpio_resetn_1_shifted[16] ;
+  wire \gpio_resetn_1_shifted[17] ;
+  wire \gpio_resetn_1_shifted[18] ;
+  wire \gpio_resetn_1_shifted[1] ;
+  wire \gpio_resetn_1_shifted[2] ;
+  wire \gpio_resetn_1_shifted[3] ;
+  wire \gpio_resetn_1_shifted[4] ;
+  wire \gpio_resetn_1_shifted[5] ;
+  wire \gpio_resetn_1_shifted[6] ;
+  wire \gpio_resetn_1_shifted[7] ;
+  wire \gpio_resetn_1_shifted[8] ;
+  wire \gpio_resetn_1_shifted[9] ;
+  wire \gpio_resetn_2[0] ;
+  wire \gpio_resetn_2[10] ;
+  wire \gpio_resetn_2[11] ;
+  wire \gpio_resetn_2[12] ;
+  wire \gpio_resetn_2[13] ;
+  wire \gpio_resetn_2[14] ;
+  wire \gpio_resetn_2[15] ;
+  wire \gpio_resetn_2[16] ;
+  wire \gpio_resetn_2[17] ;
+  wire \gpio_resetn_2[18] ;
+  wire \gpio_resetn_2[1] ;
+  wire \gpio_resetn_2[2] ;
+  wire \gpio_resetn_2[3] ;
+  wire \gpio_resetn_2[4] ;
+  wire \gpio_resetn_2[5] ;
+  wire \gpio_resetn_2[6] ;
+  wire \gpio_resetn_2[7] ;
+  wire \gpio_resetn_2[8] ;
+  wire \gpio_resetn_2[9] ;
+  wire \gpio_resetn_2_shifted[0] ;
+  wire \gpio_resetn_2_shifted[10] ;
+  wire \gpio_resetn_2_shifted[11] ;
+  wire \gpio_resetn_2_shifted[12] ;
+  wire \gpio_resetn_2_shifted[13] ;
+  wire \gpio_resetn_2_shifted[14] ;
+  wire \gpio_resetn_2_shifted[15] ;
+  wire \gpio_resetn_2_shifted[16] ;
+  wire \gpio_resetn_2_shifted[17] ;
+  wire \gpio_resetn_2_shifted[18] ;
+  wire \gpio_resetn_2_shifted[1] ;
+  wire \gpio_resetn_2_shifted[2] ;
+  wire \gpio_resetn_2_shifted[3] ;
+  wire \gpio_resetn_2_shifted[4] ;
+  wire \gpio_resetn_2_shifted[5] ;
+  wire \gpio_resetn_2_shifted[6] ;
+  wire \gpio_resetn_2_shifted[7] ;
+  wire \gpio_resetn_2_shifted[8] ;
+  wire \gpio_resetn_2_shifted[9] ;
+  wire \gpio_serial_link_1[0] ;
+  wire \gpio_serial_link_1[10] ;
+  wire \gpio_serial_link_1[11] ;
+  wire \gpio_serial_link_1[12] ;
+  wire \gpio_serial_link_1[13] ;
+  wire \gpio_serial_link_1[14] ;
+  wire \gpio_serial_link_1[15] ;
+  wire \gpio_serial_link_1[16] ;
+  wire \gpio_serial_link_1[17] ;
+  wire \gpio_serial_link_1[18] ;
+  wire \gpio_serial_link_1[1] ;
+  wire \gpio_serial_link_1[2] ;
+  wire \gpio_serial_link_1[3] ;
+  wire \gpio_serial_link_1[4] ;
+  wire \gpio_serial_link_1[5] ;
+  wire \gpio_serial_link_1[6] ;
+  wire \gpio_serial_link_1[7] ;
+  wire \gpio_serial_link_1[8] ;
+  wire \gpio_serial_link_1[9] ;
+  wire \gpio_serial_link_1_shifted[0] ;
+  wire \gpio_serial_link_1_shifted[10] ;
+  wire \gpio_serial_link_1_shifted[11] ;
+  wire \gpio_serial_link_1_shifted[12] ;
+  wire \gpio_serial_link_1_shifted[13] ;
+  wire \gpio_serial_link_1_shifted[14] ;
+  wire \gpio_serial_link_1_shifted[15] ;
+  wire \gpio_serial_link_1_shifted[16] ;
+  wire \gpio_serial_link_1_shifted[17] ;
+  wire \gpio_serial_link_1_shifted[18] ;
+  wire \gpio_serial_link_1_shifted[1] ;
+  wire \gpio_serial_link_1_shifted[2] ;
+  wire \gpio_serial_link_1_shifted[3] ;
+  wire \gpio_serial_link_1_shifted[4] ;
+  wire \gpio_serial_link_1_shifted[5] ;
+  wire \gpio_serial_link_1_shifted[6] ;
+  wire \gpio_serial_link_1_shifted[7] ;
+  wire \gpio_serial_link_1_shifted[8] ;
+  wire \gpio_serial_link_1_shifted[9] ;
+  wire \gpio_serial_link_2[0] ;
+  wire \gpio_serial_link_2[10] ;
+  wire \gpio_serial_link_2[11] ;
+  wire \gpio_serial_link_2[12] ;
+  wire \gpio_serial_link_2[13] ;
+  wire \gpio_serial_link_2[14] ;
+  wire \gpio_serial_link_2[15] ;
+  wire \gpio_serial_link_2[16] ;
+  wire \gpio_serial_link_2[17] ;
+  wire \gpio_serial_link_2[18] ;
+  wire \gpio_serial_link_2[1] ;
+  wire \gpio_serial_link_2[2] ;
+  wire \gpio_serial_link_2[3] ;
+  wire \gpio_serial_link_2[4] ;
+  wire \gpio_serial_link_2[5] ;
+  wire \gpio_serial_link_2[6] ;
+  wire \gpio_serial_link_2[7] ;
+  wire \gpio_serial_link_2[8] ;
+  wire \gpio_serial_link_2[9] ;
+  wire \gpio_serial_link_2_shifted[0] ;
+  wire \gpio_serial_link_2_shifted[10] ;
+  wire \gpio_serial_link_2_shifted[11] ;
+  wire \gpio_serial_link_2_shifted[12] ;
+  wire \gpio_serial_link_2_shifted[13] ;
+  wire \gpio_serial_link_2_shifted[14] ;
+  wire \gpio_serial_link_2_shifted[15] ;
+  wire \gpio_serial_link_2_shifted[16] ;
+  wire \gpio_serial_link_2_shifted[17] ;
+  wire \gpio_serial_link_2_shifted[18] ;
+  wire \gpio_serial_link_2_shifted[1] ;
+  wire \gpio_serial_link_2_shifted[2] ;
+  wire \gpio_serial_link_2_shifted[3] ;
+  wire \gpio_serial_link_2_shifted[4] ;
+  wire \gpio_serial_link_2_shifted[5] ;
+  wire \gpio_serial_link_2_shifted[6] ;
+  wire \gpio_serial_link_2_shifted[7] ;
+  wire \gpio_serial_link_2_shifted[8] ;
+  wire \gpio_serial_link_2_shifted[9] ;
+  wire hk_ack_i;
+  wire hk_cyc_o;
+  wire \hk_dat_i[0] ;
+  wire \hk_dat_i[10] ;
+  wire \hk_dat_i[11] ;
+  wire \hk_dat_i[12] ;
+  wire \hk_dat_i[13] ;
+  wire \hk_dat_i[14] ;
+  wire \hk_dat_i[15] ;
+  wire \hk_dat_i[16] ;
+  wire \hk_dat_i[17] ;
+  wire \hk_dat_i[18] ;
+  wire \hk_dat_i[19] ;
+  wire \hk_dat_i[1] ;
+  wire \hk_dat_i[20] ;
+  wire \hk_dat_i[21] ;
+  wire \hk_dat_i[22] ;
+  wire \hk_dat_i[23] ;
+  wire \hk_dat_i[24] ;
+  wire \hk_dat_i[25] ;
+  wire \hk_dat_i[26] ;
+  wire \hk_dat_i[27] ;
+  wire \hk_dat_i[28] ;
+  wire \hk_dat_i[29] ;
+  wire \hk_dat_i[2] ;
+  wire \hk_dat_i[30] ;
+  wire \hk_dat_i[31] ;
+  wire \hk_dat_i[3] ;
+  wire \hk_dat_i[4] ;
+  wire \hk_dat_i[5] ;
+  wire \hk_dat_i[6] ;
+  wire \hk_dat_i[7] ;
+  wire \hk_dat_i[8] ;
+  wire \hk_dat_i[9] ;
+  wire hk_stb_o;
+  wire \irq_spi[0] ;
+  wire \irq_spi[1] ;
+  wire \irq_spi[2] ;
+  wire \la_data_in_mprj[0] ;
+  wire \la_data_in_mprj[100] ;
+  wire \la_data_in_mprj[101] ;
+  wire \la_data_in_mprj[102] ;
+  wire \la_data_in_mprj[103] ;
+  wire \la_data_in_mprj[104] ;
+  wire \la_data_in_mprj[105] ;
+  wire \la_data_in_mprj[106] ;
+  wire \la_data_in_mprj[107] ;
+  wire \la_data_in_mprj[108] ;
+  wire \la_data_in_mprj[109] ;
+  wire \la_data_in_mprj[10] ;
+  wire \la_data_in_mprj[110] ;
+  wire \la_data_in_mprj[111] ;
+  wire \la_data_in_mprj[112] ;
+  wire \la_data_in_mprj[113] ;
+  wire \la_data_in_mprj[114] ;
+  wire \la_data_in_mprj[115] ;
+  wire \la_data_in_mprj[116] ;
+  wire \la_data_in_mprj[117] ;
+  wire \la_data_in_mprj[118] ;
+  wire \la_data_in_mprj[119] ;
+  wire \la_data_in_mprj[11] ;
+  wire \la_data_in_mprj[120] ;
+  wire \la_data_in_mprj[121] ;
+  wire \la_data_in_mprj[122] ;
+  wire \la_data_in_mprj[123] ;
+  wire \la_data_in_mprj[124] ;
+  wire \la_data_in_mprj[125] ;
+  wire \la_data_in_mprj[126] ;
+  wire \la_data_in_mprj[127] ;
+  wire \la_data_in_mprj[12] ;
+  wire \la_data_in_mprj[13] ;
+  wire \la_data_in_mprj[14] ;
+  wire \la_data_in_mprj[15] ;
+  wire \la_data_in_mprj[16] ;
+  wire \la_data_in_mprj[17] ;
+  wire \la_data_in_mprj[18] ;
+  wire \la_data_in_mprj[19] ;
+  wire \la_data_in_mprj[1] ;
+  wire \la_data_in_mprj[20] ;
+  wire \la_data_in_mprj[21] ;
+  wire \la_data_in_mprj[22] ;
+  wire \la_data_in_mprj[23] ;
+  wire \la_data_in_mprj[24] ;
+  wire \la_data_in_mprj[25] ;
+  wire \la_data_in_mprj[26] ;
+  wire \la_data_in_mprj[27] ;
+  wire \la_data_in_mprj[28] ;
+  wire \la_data_in_mprj[29] ;
+  wire \la_data_in_mprj[2] ;
+  wire \la_data_in_mprj[30] ;
+  wire \la_data_in_mprj[31] ;
+  wire \la_data_in_mprj[32] ;
+  wire \la_data_in_mprj[33] ;
+  wire \la_data_in_mprj[34] ;
+  wire \la_data_in_mprj[35] ;
+  wire \la_data_in_mprj[36] ;
+  wire \la_data_in_mprj[37] ;
+  wire \la_data_in_mprj[38] ;
+  wire \la_data_in_mprj[39] ;
+  wire \la_data_in_mprj[3] ;
+  wire \la_data_in_mprj[40] ;
+  wire \la_data_in_mprj[41] ;
+  wire \la_data_in_mprj[42] ;
+  wire \la_data_in_mprj[43] ;
+  wire \la_data_in_mprj[44] ;
+  wire \la_data_in_mprj[45] ;
+  wire \la_data_in_mprj[46] ;
+  wire \la_data_in_mprj[47] ;
+  wire \la_data_in_mprj[48] ;
+  wire \la_data_in_mprj[49] ;
+  wire \la_data_in_mprj[4] ;
+  wire \la_data_in_mprj[50] ;
+  wire \la_data_in_mprj[51] ;
+  wire \la_data_in_mprj[52] ;
+  wire \la_data_in_mprj[53] ;
+  wire \la_data_in_mprj[54] ;
+  wire \la_data_in_mprj[55] ;
+  wire \la_data_in_mprj[56] ;
+  wire \la_data_in_mprj[57] ;
+  wire \la_data_in_mprj[58] ;
+  wire \la_data_in_mprj[59] ;
+  wire \la_data_in_mprj[5] ;
+  wire \la_data_in_mprj[60] ;
+  wire \la_data_in_mprj[61] ;
+  wire \la_data_in_mprj[62] ;
+  wire \la_data_in_mprj[63] ;
+  wire \la_data_in_mprj[64] ;
+  wire \la_data_in_mprj[65] ;
+  wire \la_data_in_mprj[66] ;
+  wire \la_data_in_mprj[67] ;
+  wire \la_data_in_mprj[68] ;
+  wire \la_data_in_mprj[69] ;
+  wire \la_data_in_mprj[6] ;
+  wire \la_data_in_mprj[70] ;
+  wire \la_data_in_mprj[71] ;
+  wire \la_data_in_mprj[72] ;
+  wire \la_data_in_mprj[73] ;
+  wire \la_data_in_mprj[74] ;
+  wire \la_data_in_mprj[75] ;
+  wire \la_data_in_mprj[76] ;
+  wire \la_data_in_mprj[77] ;
+  wire \la_data_in_mprj[78] ;
+  wire \la_data_in_mprj[79] ;
+  wire \la_data_in_mprj[7] ;
+  wire \la_data_in_mprj[80] ;
+  wire \la_data_in_mprj[81] ;
+  wire \la_data_in_mprj[82] ;
+  wire \la_data_in_mprj[83] ;
+  wire \la_data_in_mprj[84] ;
+  wire \la_data_in_mprj[85] ;
+  wire \la_data_in_mprj[86] ;
+  wire \la_data_in_mprj[87] ;
+  wire \la_data_in_mprj[88] ;
+  wire \la_data_in_mprj[89] ;
+  wire \la_data_in_mprj[8] ;
+  wire \la_data_in_mprj[90] ;
+  wire \la_data_in_mprj[91] ;
+  wire \la_data_in_mprj[92] ;
+  wire \la_data_in_mprj[93] ;
+  wire \la_data_in_mprj[94] ;
+  wire \la_data_in_mprj[95] ;
+  wire \la_data_in_mprj[96] ;
+  wire \la_data_in_mprj[97] ;
+  wire \la_data_in_mprj[98] ;
+  wire \la_data_in_mprj[99] ;
+  wire \la_data_in_mprj[9] ;
+  wire \la_data_in_user[0] ;
+  wire \la_data_in_user[100] ;
+  wire \la_data_in_user[101] ;
+  wire \la_data_in_user[102] ;
+  wire \la_data_in_user[103] ;
+  wire \la_data_in_user[104] ;
+  wire \la_data_in_user[105] ;
+  wire \la_data_in_user[106] ;
+  wire \la_data_in_user[107] ;
+  wire \la_data_in_user[108] ;
+  wire \la_data_in_user[109] ;
+  wire \la_data_in_user[10] ;
+  wire \la_data_in_user[110] ;
+  wire \la_data_in_user[111] ;
+  wire \la_data_in_user[112] ;
+  wire \la_data_in_user[113] ;
+  wire \la_data_in_user[114] ;
+  wire \la_data_in_user[115] ;
+  wire \la_data_in_user[116] ;
+  wire \la_data_in_user[117] ;
+  wire \la_data_in_user[118] ;
+  wire \la_data_in_user[119] ;
+  wire \la_data_in_user[11] ;
+  wire \la_data_in_user[120] ;
+  wire \la_data_in_user[121] ;
+  wire \la_data_in_user[122] ;
+  wire \la_data_in_user[123] ;
+  wire \la_data_in_user[124] ;
+  wire \la_data_in_user[125] ;
+  wire \la_data_in_user[126] ;
+  wire \la_data_in_user[127] ;
+  wire \la_data_in_user[12] ;
+  wire \la_data_in_user[13] ;
+  wire \la_data_in_user[14] ;
+  wire \la_data_in_user[15] ;
+  wire \la_data_in_user[16] ;
+  wire \la_data_in_user[17] ;
+  wire \la_data_in_user[18] ;
+  wire \la_data_in_user[19] ;
+  wire \la_data_in_user[1] ;
+  wire \la_data_in_user[20] ;
+  wire \la_data_in_user[21] ;
+  wire \la_data_in_user[22] ;
+  wire \la_data_in_user[23] ;
+  wire \la_data_in_user[24] ;
+  wire \la_data_in_user[25] ;
+  wire \la_data_in_user[26] ;
+  wire \la_data_in_user[27] ;
+  wire \la_data_in_user[28] ;
+  wire \la_data_in_user[29] ;
+  wire \la_data_in_user[2] ;
+  wire \la_data_in_user[30] ;
+  wire \la_data_in_user[31] ;
+  wire \la_data_in_user[32] ;
+  wire \la_data_in_user[33] ;
+  wire \la_data_in_user[34] ;
+  wire \la_data_in_user[35] ;
+  wire \la_data_in_user[36] ;
+  wire \la_data_in_user[37] ;
+  wire \la_data_in_user[38] ;
+  wire \la_data_in_user[39] ;
+  wire \la_data_in_user[3] ;
+  wire \la_data_in_user[40] ;
+  wire \la_data_in_user[41] ;
+  wire \la_data_in_user[42] ;
+  wire \la_data_in_user[43] ;
+  wire \la_data_in_user[44] ;
+  wire \la_data_in_user[45] ;
+  wire \la_data_in_user[46] ;
+  wire \la_data_in_user[47] ;
+  wire \la_data_in_user[48] ;
+  wire \la_data_in_user[49] ;
+  wire \la_data_in_user[4] ;
+  wire \la_data_in_user[50] ;
+  wire \la_data_in_user[51] ;
+  wire \la_data_in_user[52] ;
+  wire \la_data_in_user[53] ;
+  wire \la_data_in_user[54] ;
+  wire \la_data_in_user[55] ;
+  wire \la_data_in_user[56] ;
+  wire \la_data_in_user[57] ;
+  wire \la_data_in_user[58] ;
+  wire \la_data_in_user[59] ;
+  wire \la_data_in_user[5] ;
+  wire \la_data_in_user[60] ;
+  wire \la_data_in_user[61] ;
+  wire \la_data_in_user[62] ;
+  wire \la_data_in_user[63] ;
+  wire \la_data_in_user[64] ;
+  wire \la_data_in_user[65] ;
+  wire \la_data_in_user[66] ;
+  wire \la_data_in_user[67] ;
+  wire \la_data_in_user[68] ;
+  wire \la_data_in_user[69] ;
+  wire \la_data_in_user[6] ;
+  wire \la_data_in_user[70] ;
+  wire \la_data_in_user[71] ;
+  wire \la_data_in_user[72] ;
+  wire \la_data_in_user[73] ;
+  wire \la_data_in_user[74] ;
+  wire \la_data_in_user[75] ;
+  wire \la_data_in_user[76] ;
+  wire \la_data_in_user[77] ;
+  wire \la_data_in_user[78] ;
+  wire \la_data_in_user[79] ;
+  wire \la_data_in_user[7] ;
+  wire \la_data_in_user[80] ;
+  wire \la_data_in_user[81] ;
+  wire \la_data_in_user[82] ;
+  wire \la_data_in_user[83] ;
+  wire \la_data_in_user[84] ;
+  wire \la_data_in_user[85] ;
+  wire \la_data_in_user[86] ;
+  wire \la_data_in_user[87] ;
+  wire \la_data_in_user[88] ;
+  wire \la_data_in_user[89] ;
+  wire \la_data_in_user[8] ;
+  wire \la_data_in_user[90] ;
+  wire \la_data_in_user[91] ;
+  wire \la_data_in_user[92] ;
+  wire \la_data_in_user[93] ;
+  wire \la_data_in_user[94] ;
+  wire \la_data_in_user[95] ;
+  wire \la_data_in_user[96] ;
+  wire \la_data_in_user[97] ;
+  wire \la_data_in_user[98] ;
+  wire \la_data_in_user[99] ;
+  wire \la_data_in_user[9] ;
+  wire \la_data_out_mprj[0] ;
+  wire \la_data_out_mprj[100] ;
+  wire \la_data_out_mprj[101] ;
+  wire \la_data_out_mprj[102] ;
+  wire \la_data_out_mprj[103] ;
+  wire \la_data_out_mprj[104] ;
+  wire \la_data_out_mprj[105] ;
+  wire \la_data_out_mprj[106] ;
+  wire \la_data_out_mprj[107] ;
+  wire \la_data_out_mprj[108] ;
+  wire \la_data_out_mprj[109] ;
+  wire \la_data_out_mprj[10] ;
+  wire \la_data_out_mprj[110] ;
+  wire \la_data_out_mprj[111] ;
+  wire \la_data_out_mprj[112] ;
+  wire \la_data_out_mprj[113] ;
+  wire \la_data_out_mprj[114] ;
+  wire \la_data_out_mprj[115] ;
+  wire \la_data_out_mprj[116] ;
+  wire \la_data_out_mprj[117] ;
+  wire \la_data_out_mprj[118] ;
+  wire \la_data_out_mprj[119] ;
+  wire \la_data_out_mprj[11] ;
+  wire \la_data_out_mprj[120] ;
+  wire \la_data_out_mprj[121] ;
+  wire \la_data_out_mprj[122] ;
+  wire \la_data_out_mprj[123] ;
+  wire \la_data_out_mprj[124] ;
+  wire \la_data_out_mprj[125] ;
+  wire \la_data_out_mprj[126] ;
+  wire \la_data_out_mprj[127] ;
+  wire \la_data_out_mprj[12] ;
+  wire \la_data_out_mprj[13] ;
+  wire \la_data_out_mprj[14] ;
+  wire \la_data_out_mprj[15] ;
+  wire \la_data_out_mprj[16] ;
+  wire \la_data_out_mprj[17] ;
+  wire \la_data_out_mprj[18] ;
+  wire \la_data_out_mprj[19] ;
+  wire \la_data_out_mprj[1] ;
+  wire \la_data_out_mprj[20] ;
+  wire \la_data_out_mprj[21] ;
+  wire \la_data_out_mprj[22] ;
+  wire \la_data_out_mprj[23] ;
+  wire \la_data_out_mprj[24] ;
+  wire \la_data_out_mprj[25] ;
+  wire \la_data_out_mprj[26] ;
+  wire \la_data_out_mprj[27] ;
+  wire \la_data_out_mprj[28] ;
+  wire \la_data_out_mprj[29] ;
+  wire \la_data_out_mprj[2] ;
+  wire \la_data_out_mprj[30] ;
+  wire \la_data_out_mprj[31] ;
+  wire \la_data_out_mprj[32] ;
+  wire \la_data_out_mprj[33] ;
+  wire \la_data_out_mprj[34] ;
+  wire \la_data_out_mprj[35] ;
+  wire \la_data_out_mprj[36] ;
+  wire \la_data_out_mprj[37] ;
+  wire \la_data_out_mprj[38] ;
+  wire \la_data_out_mprj[39] ;
+  wire \la_data_out_mprj[3] ;
+  wire \la_data_out_mprj[40] ;
+  wire \la_data_out_mprj[41] ;
+  wire \la_data_out_mprj[42] ;
+  wire \la_data_out_mprj[43] ;
+  wire \la_data_out_mprj[44] ;
+  wire \la_data_out_mprj[45] ;
+  wire \la_data_out_mprj[46] ;
+  wire \la_data_out_mprj[47] ;
+  wire \la_data_out_mprj[48] ;
+  wire \la_data_out_mprj[49] ;
+  wire \la_data_out_mprj[4] ;
+  wire \la_data_out_mprj[50] ;
+  wire \la_data_out_mprj[51] ;
+  wire \la_data_out_mprj[52] ;
+  wire \la_data_out_mprj[53] ;
+  wire \la_data_out_mprj[54] ;
+  wire \la_data_out_mprj[55] ;
+  wire \la_data_out_mprj[56] ;
+  wire \la_data_out_mprj[57] ;
+  wire \la_data_out_mprj[58] ;
+  wire \la_data_out_mprj[59] ;
+  wire \la_data_out_mprj[5] ;
+  wire \la_data_out_mprj[60] ;
+  wire \la_data_out_mprj[61] ;
+  wire \la_data_out_mprj[62] ;
+  wire \la_data_out_mprj[63] ;
+  wire \la_data_out_mprj[64] ;
+  wire \la_data_out_mprj[65] ;
+  wire \la_data_out_mprj[66] ;
+  wire \la_data_out_mprj[67] ;
+  wire \la_data_out_mprj[68] ;
+  wire \la_data_out_mprj[69] ;
+  wire \la_data_out_mprj[6] ;
+  wire \la_data_out_mprj[70] ;
+  wire \la_data_out_mprj[71] ;
+  wire \la_data_out_mprj[72] ;
+  wire \la_data_out_mprj[73] ;
+  wire \la_data_out_mprj[74] ;
+  wire \la_data_out_mprj[75] ;
+  wire \la_data_out_mprj[76] ;
+  wire \la_data_out_mprj[77] ;
+  wire \la_data_out_mprj[78] ;
+  wire \la_data_out_mprj[79] ;
+  wire \la_data_out_mprj[7] ;
+  wire \la_data_out_mprj[80] ;
+  wire \la_data_out_mprj[81] ;
+  wire \la_data_out_mprj[82] ;
+  wire \la_data_out_mprj[83] ;
+  wire \la_data_out_mprj[84] ;
+  wire \la_data_out_mprj[85] ;
+  wire \la_data_out_mprj[86] ;
+  wire \la_data_out_mprj[87] ;
+  wire \la_data_out_mprj[88] ;
+  wire \la_data_out_mprj[89] ;
+  wire \la_data_out_mprj[8] ;
+  wire \la_data_out_mprj[90] ;
+  wire \la_data_out_mprj[91] ;
+  wire \la_data_out_mprj[92] ;
+  wire \la_data_out_mprj[93] ;
+  wire \la_data_out_mprj[94] ;
+  wire \la_data_out_mprj[95] ;
+  wire \la_data_out_mprj[96] ;
+  wire \la_data_out_mprj[97] ;
+  wire \la_data_out_mprj[98] ;
+  wire \la_data_out_mprj[99] ;
+  wire \la_data_out_mprj[9] ;
+  wire \la_data_out_user[0] ;
+  wire \la_data_out_user[100] ;
+  wire \la_data_out_user[101] ;
+  wire \la_data_out_user[102] ;
+  wire \la_data_out_user[103] ;
+  wire \la_data_out_user[104] ;
+  wire \la_data_out_user[105] ;
+  wire \la_data_out_user[106] ;
+  wire \la_data_out_user[107] ;
+  wire \la_data_out_user[108] ;
+  wire \la_data_out_user[109] ;
+  wire \la_data_out_user[10] ;
+  wire \la_data_out_user[110] ;
+  wire \la_data_out_user[111] ;
+  wire \la_data_out_user[112] ;
+  wire \la_data_out_user[113] ;
+  wire \la_data_out_user[114] ;
+  wire \la_data_out_user[115] ;
+  wire \la_data_out_user[116] ;
+  wire \la_data_out_user[117] ;
+  wire \la_data_out_user[118] ;
+  wire \la_data_out_user[119] ;
+  wire \la_data_out_user[11] ;
+  wire \la_data_out_user[120] ;
+  wire \la_data_out_user[121] ;
+  wire \la_data_out_user[122] ;
+  wire \la_data_out_user[123] ;
+  wire \la_data_out_user[124] ;
+  wire \la_data_out_user[125] ;
+  wire \la_data_out_user[126] ;
+  wire \la_data_out_user[127] ;
+  wire \la_data_out_user[12] ;
+  wire \la_data_out_user[13] ;
+  wire \la_data_out_user[14] ;
+  wire \la_data_out_user[15] ;
+  wire \la_data_out_user[16] ;
+  wire \la_data_out_user[17] ;
+  wire \la_data_out_user[18] ;
+  wire \la_data_out_user[19] ;
+  wire \la_data_out_user[1] ;
+  wire \la_data_out_user[20] ;
+  wire \la_data_out_user[21] ;
+  wire \la_data_out_user[22] ;
+  wire \la_data_out_user[23] ;
+  wire \la_data_out_user[24] ;
+  wire \la_data_out_user[25] ;
+  wire \la_data_out_user[26] ;
+  wire \la_data_out_user[27] ;
+  wire \la_data_out_user[28] ;
+  wire \la_data_out_user[29] ;
+  wire \la_data_out_user[2] ;
+  wire \la_data_out_user[30] ;
+  wire \la_data_out_user[31] ;
+  wire \la_data_out_user[32] ;
+  wire \la_data_out_user[33] ;
+  wire \la_data_out_user[34] ;
+  wire \la_data_out_user[35] ;
+  wire \la_data_out_user[36] ;
+  wire \la_data_out_user[37] ;
+  wire \la_data_out_user[38] ;
+  wire \la_data_out_user[39] ;
+  wire \la_data_out_user[3] ;
+  wire \la_data_out_user[40] ;
+  wire \la_data_out_user[41] ;
+  wire \la_data_out_user[42] ;
+  wire \la_data_out_user[43] ;
+  wire \la_data_out_user[44] ;
+  wire \la_data_out_user[45] ;
+  wire \la_data_out_user[46] ;
+  wire \la_data_out_user[47] ;
+  wire \la_data_out_user[48] ;
+  wire \la_data_out_user[49] ;
+  wire \la_data_out_user[4] ;
+  wire \la_data_out_user[50] ;
+  wire \la_data_out_user[51] ;
+  wire \la_data_out_user[52] ;
+  wire \la_data_out_user[53] ;
+  wire \la_data_out_user[54] ;
+  wire \la_data_out_user[55] ;
+  wire \la_data_out_user[56] ;
+  wire \la_data_out_user[57] ;
+  wire \la_data_out_user[58] ;
+  wire \la_data_out_user[59] ;
+  wire \la_data_out_user[5] ;
+  wire \la_data_out_user[60] ;
+  wire \la_data_out_user[61] ;
+  wire \la_data_out_user[62] ;
+  wire \la_data_out_user[63] ;
+  wire \la_data_out_user[64] ;
+  wire \la_data_out_user[65] ;
+  wire \la_data_out_user[66] ;
+  wire \la_data_out_user[67] ;
+  wire \la_data_out_user[68] ;
+  wire \la_data_out_user[69] ;
+  wire \la_data_out_user[6] ;
+  wire \la_data_out_user[70] ;
+  wire \la_data_out_user[71] ;
+  wire \la_data_out_user[72] ;
+  wire \la_data_out_user[73] ;
+  wire \la_data_out_user[74] ;
+  wire \la_data_out_user[75] ;
+  wire \la_data_out_user[76] ;
+  wire \la_data_out_user[77] ;
+  wire \la_data_out_user[78] ;
+  wire \la_data_out_user[79] ;
+  wire \la_data_out_user[7] ;
+  wire \la_data_out_user[80] ;
+  wire \la_data_out_user[81] ;
+  wire \la_data_out_user[82] ;
+  wire \la_data_out_user[83] ;
+  wire \la_data_out_user[84] ;
+  wire \la_data_out_user[85] ;
+  wire \la_data_out_user[86] ;
+  wire \la_data_out_user[87] ;
+  wire \la_data_out_user[88] ;
+  wire \la_data_out_user[89] ;
+  wire \la_data_out_user[8] ;
+  wire \la_data_out_user[90] ;
+  wire \la_data_out_user[91] ;
+  wire \la_data_out_user[92] ;
+  wire \la_data_out_user[93] ;
+  wire \la_data_out_user[94] ;
+  wire \la_data_out_user[95] ;
+  wire \la_data_out_user[96] ;
+  wire \la_data_out_user[97] ;
+  wire \la_data_out_user[98] ;
+  wire \la_data_out_user[99] ;
+  wire \la_data_out_user[9] ;
+  wire \la_iena_mprj[0] ;
+  wire \la_iena_mprj[100] ;
+  wire \la_iena_mprj[101] ;
+  wire \la_iena_mprj[102] ;
+  wire \la_iena_mprj[103] ;
+  wire \la_iena_mprj[104] ;
+  wire \la_iena_mprj[105] ;
+  wire \la_iena_mprj[106] ;
+  wire \la_iena_mprj[107] ;
+  wire \la_iena_mprj[108] ;
+  wire \la_iena_mprj[109] ;
+  wire \la_iena_mprj[10] ;
+  wire \la_iena_mprj[110] ;
+  wire \la_iena_mprj[111] ;
+  wire \la_iena_mprj[112] ;
+  wire \la_iena_mprj[113] ;
+  wire \la_iena_mprj[114] ;
+  wire \la_iena_mprj[115] ;
+  wire \la_iena_mprj[116] ;
+  wire \la_iena_mprj[117] ;
+  wire \la_iena_mprj[118] ;
+  wire \la_iena_mprj[119] ;
+  wire \la_iena_mprj[11] ;
+  wire \la_iena_mprj[120] ;
+  wire \la_iena_mprj[121] ;
+  wire \la_iena_mprj[122] ;
+  wire \la_iena_mprj[123] ;
+  wire \la_iena_mprj[124] ;
+  wire \la_iena_mprj[125] ;
+  wire \la_iena_mprj[126] ;
+  wire \la_iena_mprj[127] ;
+  wire \la_iena_mprj[12] ;
+  wire \la_iena_mprj[13] ;
+  wire \la_iena_mprj[14] ;
+  wire \la_iena_mprj[15] ;
+  wire \la_iena_mprj[16] ;
+  wire \la_iena_mprj[17] ;
+  wire \la_iena_mprj[18] ;
+  wire \la_iena_mprj[19] ;
+  wire \la_iena_mprj[1] ;
+  wire \la_iena_mprj[20] ;
+  wire \la_iena_mprj[21] ;
+  wire \la_iena_mprj[22] ;
+  wire \la_iena_mprj[23] ;
+  wire \la_iena_mprj[24] ;
+  wire \la_iena_mprj[25] ;
+  wire \la_iena_mprj[26] ;
+  wire \la_iena_mprj[27] ;
+  wire \la_iena_mprj[28] ;
+  wire \la_iena_mprj[29] ;
+  wire \la_iena_mprj[2] ;
+  wire \la_iena_mprj[30] ;
+  wire \la_iena_mprj[31] ;
+  wire \la_iena_mprj[32] ;
+  wire \la_iena_mprj[33] ;
+  wire \la_iena_mprj[34] ;
+  wire \la_iena_mprj[35] ;
+  wire \la_iena_mprj[36] ;
+  wire \la_iena_mprj[37] ;
+  wire \la_iena_mprj[38] ;
+  wire \la_iena_mprj[39] ;
+  wire \la_iena_mprj[3] ;
+  wire \la_iena_mprj[40] ;
+  wire \la_iena_mprj[41] ;
+  wire \la_iena_mprj[42] ;
+  wire \la_iena_mprj[43] ;
+  wire \la_iena_mprj[44] ;
+  wire \la_iena_mprj[45] ;
+  wire \la_iena_mprj[46] ;
+  wire \la_iena_mprj[47] ;
+  wire \la_iena_mprj[48] ;
+  wire \la_iena_mprj[49] ;
+  wire \la_iena_mprj[4] ;
+  wire \la_iena_mprj[50] ;
+  wire \la_iena_mprj[51] ;
+  wire \la_iena_mprj[52] ;
+  wire \la_iena_mprj[53] ;
+  wire \la_iena_mprj[54] ;
+  wire \la_iena_mprj[55] ;
+  wire \la_iena_mprj[56] ;
+  wire \la_iena_mprj[57] ;
+  wire \la_iena_mprj[58] ;
+  wire \la_iena_mprj[59] ;
+  wire \la_iena_mprj[5] ;
+  wire \la_iena_mprj[60] ;
+  wire \la_iena_mprj[61] ;
+  wire \la_iena_mprj[62] ;
+  wire \la_iena_mprj[63] ;
+  wire \la_iena_mprj[64] ;
+  wire \la_iena_mprj[65] ;
+  wire \la_iena_mprj[66] ;
+  wire \la_iena_mprj[67] ;
+  wire \la_iena_mprj[68] ;
+  wire \la_iena_mprj[69] ;
+  wire \la_iena_mprj[6] ;
+  wire \la_iena_mprj[70] ;
+  wire \la_iena_mprj[71] ;
+  wire \la_iena_mprj[72] ;
+  wire \la_iena_mprj[73] ;
+  wire \la_iena_mprj[74] ;
+  wire \la_iena_mprj[75] ;
+  wire \la_iena_mprj[76] ;
+  wire \la_iena_mprj[77] ;
+  wire \la_iena_mprj[78] ;
+  wire \la_iena_mprj[79] ;
+  wire \la_iena_mprj[7] ;
+  wire \la_iena_mprj[80] ;
+  wire \la_iena_mprj[81] ;
+  wire \la_iena_mprj[82] ;
+  wire \la_iena_mprj[83] ;
+  wire \la_iena_mprj[84] ;
+  wire \la_iena_mprj[85] ;
+  wire \la_iena_mprj[86] ;
+  wire \la_iena_mprj[87] ;
+  wire \la_iena_mprj[88] ;
+  wire \la_iena_mprj[89] ;
+  wire \la_iena_mprj[8] ;
+  wire \la_iena_mprj[90] ;
+  wire \la_iena_mprj[91] ;
+  wire \la_iena_mprj[92] ;
+  wire \la_iena_mprj[93] ;
+  wire \la_iena_mprj[94] ;
+  wire \la_iena_mprj[95] ;
+  wire \la_iena_mprj[96] ;
+  wire \la_iena_mprj[97] ;
+  wire \la_iena_mprj[98] ;
+  wire \la_iena_mprj[99] ;
+  wire \la_iena_mprj[9] ;
+  wire \la_oenb_mprj[0] ;
+  wire \la_oenb_mprj[100] ;
+  wire \la_oenb_mprj[101] ;
+  wire \la_oenb_mprj[102] ;
+  wire \la_oenb_mprj[103] ;
+  wire \la_oenb_mprj[104] ;
+  wire \la_oenb_mprj[105] ;
+  wire \la_oenb_mprj[106] ;
+  wire \la_oenb_mprj[107] ;
+  wire \la_oenb_mprj[108] ;
+  wire \la_oenb_mprj[109] ;
+  wire \la_oenb_mprj[10] ;
+  wire \la_oenb_mprj[110] ;
+  wire \la_oenb_mprj[111] ;
+  wire \la_oenb_mprj[112] ;
+  wire \la_oenb_mprj[113] ;
+  wire \la_oenb_mprj[114] ;
+  wire \la_oenb_mprj[115] ;
+  wire \la_oenb_mprj[116] ;
+  wire \la_oenb_mprj[117] ;
+  wire \la_oenb_mprj[118] ;
+  wire \la_oenb_mprj[119] ;
+  wire \la_oenb_mprj[11] ;
+  wire \la_oenb_mprj[120] ;
+  wire \la_oenb_mprj[121] ;
+  wire \la_oenb_mprj[122] ;
+  wire \la_oenb_mprj[123] ;
+  wire \la_oenb_mprj[124] ;
+  wire \la_oenb_mprj[125] ;
+  wire \la_oenb_mprj[126] ;
+  wire \la_oenb_mprj[127] ;
+  wire \la_oenb_mprj[12] ;
+  wire \la_oenb_mprj[13] ;
+  wire \la_oenb_mprj[14] ;
+  wire \la_oenb_mprj[15] ;
+  wire \la_oenb_mprj[16] ;
+  wire \la_oenb_mprj[17] ;
+  wire \la_oenb_mprj[18] ;
+  wire \la_oenb_mprj[19] ;
+  wire \la_oenb_mprj[1] ;
+  wire \la_oenb_mprj[20] ;
+  wire \la_oenb_mprj[21] ;
+  wire \la_oenb_mprj[22] ;
+  wire \la_oenb_mprj[23] ;
+  wire \la_oenb_mprj[24] ;
+  wire \la_oenb_mprj[25] ;
+  wire \la_oenb_mprj[26] ;
+  wire \la_oenb_mprj[27] ;
+  wire \la_oenb_mprj[28] ;
+  wire \la_oenb_mprj[29] ;
+  wire \la_oenb_mprj[2] ;
+  wire \la_oenb_mprj[30] ;
+  wire \la_oenb_mprj[31] ;
+  wire \la_oenb_mprj[32] ;
+  wire \la_oenb_mprj[33] ;
+  wire \la_oenb_mprj[34] ;
+  wire \la_oenb_mprj[35] ;
+  wire \la_oenb_mprj[36] ;
+  wire \la_oenb_mprj[37] ;
+  wire \la_oenb_mprj[38] ;
+  wire \la_oenb_mprj[39] ;
+  wire \la_oenb_mprj[3] ;
+  wire \la_oenb_mprj[40] ;
+  wire \la_oenb_mprj[41] ;
+  wire \la_oenb_mprj[42] ;
+  wire \la_oenb_mprj[43] ;
+  wire \la_oenb_mprj[44] ;
+  wire \la_oenb_mprj[45] ;
+  wire \la_oenb_mprj[46] ;
+  wire \la_oenb_mprj[47] ;
+  wire \la_oenb_mprj[48] ;
+  wire \la_oenb_mprj[49] ;
+  wire \la_oenb_mprj[4] ;
+  wire \la_oenb_mprj[50] ;
+  wire \la_oenb_mprj[51] ;
+  wire \la_oenb_mprj[52] ;
+  wire \la_oenb_mprj[53] ;
+  wire \la_oenb_mprj[54] ;
+  wire \la_oenb_mprj[55] ;
+  wire \la_oenb_mprj[56] ;
+  wire \la_oenb_mprj[57] ;
+  wire \la_oenb_mprj[58] ;
+  wire \la_oenb_mprj[59] ;
+  wire \la_oenb_mprj[5] ;
+  wire \la_oenb_mprj[60] ;
+  wire \la_oenb_mprj[61] ;
+  wire \la_oenb_mprj[62] ;
+  wire \la_oenb_mprj[63] ;
+  wire \la_oenb_mprj[64] ;
+  wire \la_oenb_mprj[65] ;
+  wire \la_oenb_mprj[66] ;
+  wire \la_oenb_mprj[67] ;
+  wire \la_oenb_mprj[68] ;
+  wire \la_oenb_mprj[69] ;
+  wire \la_oenb_mprj[6] ;
+  wire \la_oenb_mprj[70] ;
+  wire \la_oenb_mprj[71] ;
+  wire \la_oenb_mprj[72] ;
+  wire \la_oenb_mprj[73] ;
+  wire \la_oenb_mprj[74] ;
+  wire \la_oenb_mprj[75] ;
+  wire \la_oenb_mprj[76] ;
+  wire \la_oenb_mprj[77] ;
+  wire \la_oenb_mprj[78] ;
+  wire \la_oenb_mprj[79] ;
+  wire \la_oenb_mprj[7] ;
+  wire \la_oenb_mprj[80] ;
+  wire \la_oenb_mprj[81] ;
+  wire \la_oenb_mprj[82] ;
+  wire \la_oenb_mprj[83] ;
+  wire \la_oenb_mprj[84] ;
+  wire \la_oenb_mprj[85] ;
+  wire \la_oenb_mprj[86] ;
+  wire \la_oenb_mprj[87] ;
+  wire \la_oenb_mprj[88] ;
+  wire \la_oenb_mprj[89] ;
+  wire \la_oenb_mprj[8] ;
+  wire \la_oenb_mprj[90] ;
+  wire \la_oenb_mprj[91] ;
+  wire \la_oenb_mprj[92] ;
+  wire \la_oenb_mprj[93] ;
+  wire \la_oenb_mprj[94] ;
+  wire \la_oenb_mprj[95] ;
+  wire \la_oenb_mprj[96] ;
+  wire \la_oenb_mprj[97] ;
+  wire \la_oenb_mprj[98] ;
+  wire \la_oenb_mprj[99] ;
+  wire \la_oenb_mprj[9] ;
+  wire \la_oenb_user[0] ;
+  wire \la_oenb_user[100] ;
+  wire \la_oenb_user[101] ;
+  wire \la_oenb_user[102] ;
+  wire \la_oenb_user[103] ;
+  wire \la_oenb_user[104] ;
+  wire \la_oenb_user[105] ;
+  wire \la_oenb_user[106] ;
+  wire \la_oenb_user[107] ;
+  wire \la_oenb_user[108] ;
+  wire \la_oenb_user[109] ;
+  wire \la_oenb_user[10] ;
+  wire \la_oenb_user[110] ;
+  wire \la_oenb_user[111] ;
+  wire \la_oenb_user[112] ;
+  wire \la_oenb_user[113] ;
+  wire \la_oenb_user[114] ;
+  wire \la_oenb_user[115] ;
+  wire \la_oenb_user[116] ;
+  wire \la_oenb_user[117] ;
+  wire \la_oenb_user[118] ;
+  wire \la_oenb_user[119] ;
+  wire \la_oenb_user[11] ;
+  wire \la_oenb_user[120] ;
+  wire \la_oenb_user[121] ;
+  wire \la_oenb_user[122] ;
+  wire \la_oenb_user[123] ;
+  wire \la_oenb_user[124] ;
+  wire \la_oenb_user[125] ;
+  wire \la_oenb_user[126] ;
+  wire \la_oenb_user[127] ;
+  wire \la_oenb_user[12] ;
+  wire \la_oenb_user[13] ;
+  wire \la_oenb_user[14] ;
+  wire \la_oenb_user[15] ;
+  wire \la_oenb_user[16] ;
+  wire \la_oenb_user[17] ;
+  wire \la_oenb_user[18] ;
+  wire \la_oenb_user[19] ;
+  wire \la_oenb_user[1] ;
+  wire \la_oenb_user[20] ;
+  wire \la_oenb_user[21] ;
+  wire \la_oenb_user[22] ;
+  wire \la_oenb_user[23] ;
+  wire \la_oenb_user[24] ;
+  wire \la_oenb_user[25] ;
+  wire \la_oenb_user[26] ;
+  wire \la_oenb_user[27] ;
+  wire \la_oenb_user[28] ;
+  wire \la_oenb_user[29] ;
+  wire \la_oenb_user[2] ;
+  wire \la_oenb_user[30] ;
+  wire \la_oenb_user[31] ;
+  wire \la_oenb_user[32] ;
+  wire \la_oenb_user[33] ;
+  wire \la_oenb_user[34] ;
+  wire \la_oenb_user[35] ;
+  wire \la_oenb_user[36] ;
+  wire \la_oenb_user[37] ;
+  wire \la_oenb_user[38] ;
+  wire \la_oenb_user[39] ;
+  wire \la_oenb_user[3] ;
+  wire \la_oenb_user[40] ;
+  wire \la_oenb_user[41] ;
+  wire \la_oenb_user[42] ;
+  wire \la_oenb_user[43] ;
+  wire \la_oenb_user[44] ;
+  wire \la_oenb_user[45] ;
+  wire \la_oenb_user[46] ;
+  wire \la_oenb_user[47] ;
+  wire \la_oenb_user[48] ;
+  wire \la_oenb_user[49] ;
+  wire \la_oenb_user[4] ;
+  wire \la_oenb_user[50] ;
+  wire \la_oenb_user[51] ;
+  wire \la_oenb_user[52] ;
+  wire \la_oenb_user[53] ;
+  wire \la_oenb_user[54] ;
+  wire \la_oenb_user[55] ;
+  wire \la_oenb_user[56] ;
+  wire \la_oenb_user[57] ;
+  wire \la_oenb_user[58] ;
+  wire \la_oenb_user[59] ;
+  wire \la_oenb_user[5] ;
+  wire \la_oenb_user[60] ;
+  wire \la_oenb_user[61] ;
+  wire \la_oenb_user[62] ;
+  wire \la_oenb_user[63] ;
+  wire \la_oenb_user[64] ;
+  wire \la_oenb_user[65] ;
+  wire \la_oenb_user[66] ;
+  wire \la_oenb_user[67] ;
+  wire \la_oenb_user[68] ;
+  wire \la_oenb_user[69] ;
+  wire \la_oenb_user[6] ;
+  wire \la_oenb_user[70] ;
+  wire \la_oenb_user[71] ;
+  wire \la_oenb_user[72] ;
+  wire \la_oenb_user[73] ;
+  wire \la_oenb_user[74] ;
+  wire \la_oenb_user[75] ;
+  wire \la_oenb_user[76] ;
+  wire \la_oenb_user[77] ;
+  wire \la_oenb_user[78] ;
+  wire \la_oenb_user[79] ;
+  wire \la_oenb_user[7] ;
+  wire \la_oenb_user[80] ;
+  wire \la_oenb_user[81] ;
+  wire \la_oenb_user[82] ;
+  wire \la_oenb_user[83] ;
+  wire \la_oenb_user[84] ;
+  wire \la_oenb_user[85] ;
+  wire \la_oenb_user[86] ;
+  wire \la_oenb_user[87] ;
+  wire \la_oenb_user[88] ;
+  wire \la_oenb_user[89] ;
+  wire \la_oenb_user[8] ;
+  wire \la_oenb_user[90] ;
+  wire \la_oenb_user[91] ;
+  wire \la_oenb_user[92] ;
+  wire \la_oenb_user[93] ;
+  wire \la_oenb_user[94] ;
+  wire \la_oenb_user[95] ;
+  wire \la_oenb_user[96] ;
+  wire \la_oenb_user[97] ;
+  wire \la_oenb_user[98] ;
+  wire \la_oenb_user[99] ;
+  wire \la_oenb_user[9] ;
+  wire \mask_rev[0] ;
+  wire \mask_rev[10] ;
+  wire \mask_rev[11] ;
+  wire \mask_rev[12] ;
+  wire \mask_rev[13] ;
+  wire \mask_rev[14] ;
+  wire \mask_rev[15] ;
+  wire \mask_rev[16] ;
+  wire \mask_rev[17] ;
+  wire \mask_rev[18] ;
+  wire \mask_rev[19] ;
+  wire \mask_rev[1] ;
+  wire \mask_rev[20] ;
+  wire \mask_rev[21] ;
+  wire \mask_rev[22] ;
+  wire \mask_rev[23] ;
+  wire \mask_rev[24] ;
+  wire \mask_rev[25] ;
+  wire \mask_rev[26] ;
+  wire \mask_rev[27] ;
+  wire \mask_rev[28] ;
+  wire \mask_rev[29] ;
+  wire \mask_rev[2] ;
+  wire \mask_rev[30] ;
+  wire \mask_rev[31] ;
+  wire \mask_rev[3] ;
+  wire \mask_rev[4] ;
+  wire \mask_rev[5] ;
+  wire \mask_rev[6] ;
+  wire \mask_rev[7] ;
+  wire \mask_rev[8] ;
+  wire \mask_rev[9] ;
+  wire \mgmt_io_in[0] ;
+  wire \mgmt_io_in[10] ;
+  wire \mgmt_io_in[11] ;
+  wire \mgmt_io_in[12] ;
+  wire \mgmt_io_in[13] ;
+  wire \mgmt_io_in[14] ;
+  wire \mgmt_io_in[15] ;
+  wire \mgmt_io_in[16] ;
+  wire \mgmt_io_in[17] ;
+  wire \mgmt_io_in[18] ;
+  wire \mgmt_io_in[19] ;
+  wire \mgmt_io_in[1] ;
+  wire \mgmt_io_in[20] ;
+  wire \mgmt_io_in[21] ;
+  wire \mgmt_io_in[22] ;
+  wire \mgmt_io_in[23] ;
+  wire \mgmt_io_in[24] ;
+  wire \mgmt_io_in[25] ;
+  wire \mgmt_io_in[26] ;
+  wire \mgmt_io_in[27] ;
+  wire \mgmt_io_in[28] ;
+  wire \mgmt_io_in[29] ;
+  wire \mgmt_io_in[2] ;
+  wire \mgmt_io_in[30] ;
+  wire \mgmt_io_in[31] ;
+  wire \mgmt_io_in[32] ;
+  wire \mgmt_io_in[33] ;
+  wire \mgmt_io_in[34] ;
+  wire \mgmt_io_in[35] ;
+  wire \mgmt_io_in[36] ;
+  wire \mgmt_io_in[37] ;
+  wire \mgmt_io_in[3] ;
+  wire \mgmt_io_in[4] ;
+  wire \mgmt_io_in[5] ;
+  wire \mgmt_io_in[6] ;
+  wire \mgmt_io_in[7] ;
+  wire \mgmt_io_in[8] ;
+  wire \mgmt_io_in[9] ;
+  wire \mgmt_io_in_hk[0] ;
+  wire \mgmt_io_in_hk[10] ;
+  wire \mgmt_io_in_hk[11] ;
+  wire \mgmt_io_in_hk[12] ;
+  wire \mgmt_io_in_hk[13] ;
+  wire \mgmt_io_in_hk[14] ;
+  wire \mgmt_io_in_hk[15] ;
+  wire \mgmt_io_in_hk[16] ;
+  wire \mgmt_io_in_hk[17] ;
+  wire \mgmt_io_in_hk[18] ;
+  wire \mgmt_io_in_hk[19] ;
+  wire \mgmt_io_in_hk[1] ;
+  wire \mgmt_io_in_hk[20] ;
+  wire \mgmt_io_in_hk[21] ;
+  wire \mgmt_io_in_hk[22] ;
+  wire \mgmt_io_in_hk[23] ;
+  wire \mgmt_io_in_hk[24] ;
+  wire \mgmt_io_in_hk[25] ;
+  wire \mgmt_io_in_hk[26] ;
+  wire \mgmt_io_in_hk[27] ;
+  wire \mgmt_io_in_hk[28] ;
+  wire \mgmt_io_in_hk[29] ;
+  wire \mgmt_io_in_hk[2] ;
+  wire \mgmt_io_in_hk[30] ;
+  wire \mgmt_io_in_hk[31] ;
+  wire \mgmt_io_in_hk[32] ;
+  wire \mgmt_io_in_hk[33] ;
+  wire \mgmt_io_in_hk[34] ;
+  wire \mgmt_io_in_hk[35] ;
+  wire \mgmt_io_in_hk[36] ;
+  wire \mgmt_io_in_hk[37] ;
+  wire \mgmt_io_in_hk[3] ;
+  wire \mgmt_io_in_hk[4] ;
+  wire \mgmt_io_in_hk[5] ;
+  wire \mgmt_io_in_hk[6] ;
+  wire \mgmt_io_in_hk[7] ;
+  wire \mgmt_io_in_hk[8] ;
+  wire \mgmt_io_in_hk[9] ;
+  wire \mgmt_io_oeb[0] ;
+  wire \mgmt_io_oeb[10] ;
+  wire \mgmt_io_oeb[11] ;
+  wire \mgmt_io_oeb[12] ;
+  wire \mgmt_io_oeb[13] ;
+  wire \mgmt_io_oeb[14] ;
+  wire \mgmt_io_oeb[15] ;
+  wire \mgmt_io_oeb[16] ;
+  wire \mgmt_io_oeb[17] ;
+  wire \mgmt_io_oeb[18] ;
+  wire \mgmt_io_oeb[19] ;
+  wire \mgmt_io_oeb[1] ;
+  wire \mgmt_io_oeb[20] ;
+  wire \mgmt_io_oeb[21] ;
+  wire \mgmt_io_oeb[22] ;
+  wire \mgmt_io_oeb[23] ;
+  wire \mgmt_io_oeb[24] ;
+  wire \mgmt_io_oeb[25] ;
+  wire \mgmt_io_oeb[26] ;
+  wire \mgmt_io_oeb[27] ;
+  wire \mgmt_io_oeb[28] ;
+  wire \mgmt_io_oeb[29] ;
+  wire \mgmt_io_oeb[2] ;
+  wire \mgmt_io_oeb[30] ;
+  wire \mgmt_io_oeb[31] ;
+  wire \mgmt_io_oeb[32] ;
+  wire \mgmt_io_oeb[33] ;
+  wire \mgmt_io_oeb[34] ;
+  wire \mgmt_io_oeb[35] ;
+  wire \mgmt_io_oeb[36] ;
+  wire \mgmt_io_oeb[37] ;
+  wire \mgmt_io_oeb[3] ;
+  wire \mgmt_io_oeb[4] ;
+  wire \mgmt_io_oeb[5] ;
+  wire \mgmt_io_oeb[6] ;
+  wire \mgmt_io_oeb[7] ;
+  wire \mgmt_io_oeb[8] ;
+  wire \mgmt_io_oeb[9] ;
+  wire \mgmt_io_oeb_hk[0] ;
+  wire \mgmt_io_oeb_hk[10] ;
+  wire \mgmt_io_oeb_hk[11] ;
+  wire \mgmt_io_oeb_hk[12] ;
+  wire \mgmt_io_oeb_hk[13] ;
+  wire \mgmt_io_oeb_hk[14] ;
+  wire \mgmt_io_oeb_hk[15] ;
+  wire \mgmt_io_oeb_hk[16] ;
+  wire \mgmt_io_oeb_hk[17] ;
+  wire \mgmt_io_oeb_hk[18] ;
+  wire \mgmt_io_oeb_hk[19] ;
+  wire \mgmt_io_oeb_hk[1] ;
+  wire \mgmt_io_oeb_hk[20] ;
+  wire \mgmt_io_oeb_hk[21] ;
+  wire \mgmt_io_oeb_hk[22] ;
+  wire \mgmt_io_oeb_hk[23] ;
+  wire \mgmt_io_oeb_hk[24] ;
+  wire \mgmt_io_oeb_hk[25] ;
+  wire \mgmt_io_oeb_hk[26] ;
+  wire \mgmt_io_oeb_hk[27] ;
+  wire \mgmt_io_oeb_hk[28] ;
+  wire \mgmt_io_oeb_hk[29] ;
+  wire \mgmt_io_oeb_hk[2] ;
+  wire \mgmt_io_oeb_hk[30] ;
+  wire \mgmt_io_oeb_hk[31] ;
+  wire \mgmt_io_oeb_hk[32] ;
+  wire \mgmt_io_oeb_hk[33] ;
+  wire \mgmt_io_oeb_hk[34] ;
+  wire \mgmt_io_oeb_hk[35] ;
+  wire \mgmt_io_oeb_hk[36] ;
+  wire \mgmt_io_oeb_hk[37] ;
+  wire \mgmt_io_oeb_hk[3] ;
+  wire \mgmt_io_oeb_hk[4] ;
+  wire \mgmt_io_oeb_hk[5] ;
+  wire \mgmt_io_oeb_hk[6] ;
+  wire \mgmt_io_oeb_hk[7] ;
+  wire \mgmt_io_oeb_hk[8] ;
+  wire \mgmt_io_oeb_hk[9] ;
+  wire \mgmt_io_out[0] ;
+  wire \mgmt_io_out[10] ;
+  wire \mgmt_io_out[11] ;
+  wire \mgmt_io_out[12] ;
+  wire \mgmt_io_out[13] ;
+  wire \mgmt_io_out[14] ;
+  wire \mgmt_io_out[15] ;
+  wire \mgmt_io_out[16] ;
+  wire \mgmt_io_out[17] ;
+  wire \mgmt_io_out[18] ;
+  wire \mgmt_io_out[19] ;
+  wire \mgmt_io_out[1] ;
+  wire \mgmt_io_out[20] ;
+  wire \mgmt_io_out[21] ;
+  wire \mgmt_io_out[22] ;
+  wire \mgmt_io_out[23] ;
+  wire \mgmt_io_out[24] ;
+  wire \mgmt_io_out[25] ;
+  wire \mgmt_io_out[26] ;
+  wire \mgmt_io_out[27] ;
+  wire \mgmt_io_out[28] ;
+  wire \mgmt_io_out[29] ;
+  wire \mgmt_io_out[2] ;
+  wire \mgmt_io_out[30] ;
+  wire \mgmt_io_out[31] ;
+  wire \mgmt_io_out[32] ;
+  wire \mgmt_io_out[33] ;
+  wire \mgmt_io_out[34] ;
+  wire \mgmt_io_out[35] ;
+  wire \mgmt_io_out[36] ;
+  wire \mgmt_io_out[37] ;
+  wire \mgmt_io_out[3] ;
+  wire \mgmt_io_out[4] ;
+  wire \mgmt_io_out[5] ;
+  wire \mgmt_io_out[6] ;
+  wire \mgmt_io_out[7] ;
+  wire \mgmt_io_out[8] ;
+  wire \mgmt_io_out[9] ;
+  wire \mgmt_io_out_hk[0] ;
+  wire \mgmt_io_out_hk[10] ;
+  wire \mgmt_io_out_hk[11] ;
+  wire \mgmt_io_out_hk[12] ;
+  wire \mgmt_io_out_hk[13] ;
+  wire \mgmt_io_out_hk[14] ;
+  wire \mgmt_io_out_hk[15] ;
+  wire \mgmt_io_out_hk[16] ;
+  wire \mgmt_io_out_hk[17] ;
+  wire \mgmt_io_out_hk[18] ;
+  wire \mgmt_io_out_hk[19] ;
+  wire \mgmt_io_out_hk[1] ;
+  wire \mgmt_io_out_hk[20] ;
+  wire \mgmt_io_out_hk[21] ;
+  wire \mgmt_io_out_hk[22] ;
+  wire \mgmt_io_out_hk[23] ;
+  wire \mgmt_io_out_hk[24] ;
+  wire \mgmt_io_out_hk[25] ;
+  wire \mgmt_io_out_hk[26] ;
+  wire \mgmt_io_out_hk[27] ;
+  wire \mgmt_io_out_hk[28] ;
+  wire \mgmt_io_out_hk[29] ;
+  wire \mgmt_io_out_hk[2] ;
+  wire \mgmt_io_out_hk[30] ;
+  wire \mgmt_io_out_hk[31] ;
+  wire \mgmt_io_out_hk[32] ;
+  wire \mgmt_io_out_hk[33] ;
+  wire \mgmt_io_out_hk[34] ;
+  wire \mgmt_io_out_hk[35] ;
+  wire \mgmt_io_out_hk[36] ;
+  wire \mgmt_io_out_hk[37] ;
+  wire \mgmt_io_out_hk[3] ;
+  wire \mgmt_io_out_hk[4] ;
+  wire \mgmt_io_out_hk[5] ;
+  wire \mgmt_io_out_hk[6] ;
+  wire \mgmt_io_out_hk[7] ;
+  wire \mgmt_io_out_hk[8] ;
+  wire \mgmt_io_out_hk[9] ;
+  wire mprj2_vcc_pwrgood;
+  wire mprj2_vdd_pwrgood;
+  wire mprj_ack_i_core;
+  wire mprj_ack_i_user;
+  wire \mprj_adr_o_core[0] ;
+  wire \mprj_adr_o_core[10] ;
+  wire \mprj_adr_o_core[11] ;
+  wire \mprj_adr_o_core[12] ;
+  wire \mprj_adr_o_core[13] ;
+  wire \mprj_adr_o_core[14] ;
+  wire \mprj_adr_o_core[15] ;
+  wire \mprj_adr_o_core[16] ;
+  wire \mprj_adr_o_core[17] ;
+  wire \mprj_adr_o_core[18] ;
+  wire \mprj_adr_o_core[19] ;
+  wire \mprj_adr_o_core[1] ;
+  wire \mprj_adr_o_core[20] ;
+  wire \mprj_adr_o_core[21] ;
+  wire \mprj_adr_o_core[22] ;
+  wire \mprj_adr_o_core[23] ;
+  wire \mprj_adr_o_core[24] ;
+  wire \mprj_adr_o_core[25] ;
+  wire \mprj_adr_o_core[26] ;
+  wire \mprj_adr_o_core[27] ;
+  wire \mprj_adr_o_core[28] ;
+  wire \mprj_adr_o_core[29] ;
+  wire \mprj_adr_o_core[2] ;
+  wire \mprj_adr_o_core[30] ;
+  wire \mprj_adr_o_core[31] ;
+  wire \mprj_adr_o_core[3] ;
+  wire \mprj_adr_o_core[4] ;
+  wire \mprj_adr_o_core[5] ;
+  wire \mprj_adr_o_core[6] ;
+  wire \mprj_adr_o_core[7] ;
+  wire \mprj_adr_o_core[8] ;
+  wire \mprj_adr_o_core[9] ;
+  wire \mprj_adr_o_user[0] ;
+  wire \mprj_adr_o_user[10] ;
+  wire \mprj_adr_o_user[11] ;
+  wire \mprj_adr_o_user[12] ;
+  wire \mprj_adr_o_user[13] ;
+  wire \mprj_adr_o_user[14] ;
+  wire \mprj_adr_o_user[15] ;
+  wire \mprj_adr_o_user[16] ;
+  wire \mprj_adr_o_user[17] ;
+  wire \mprj_adr_o_user[18] ;
+  wire \mprj_adr_o_user[19] ;
+  wire \mprj_adr_o_user[1] ;
+  wire \mprj_adr_o_user[20] ;
+  wire \mprj_adr_o_user[21] ;
+  wire \mprj_adr_o_user[22] ;
+  wire \mprj_adr_o_user[23] ;
+  wire \mprj_adr_o_user[24] ;
+  wire \mprj_adr_o_user[25] ;
+  wire \mprj_adr_o_user[26] ;
+  wire \mprj_adr_o_user[27] ;
+  wire \mprj_adr_o_user[28] ;
+  wire \mprj_adr_o_user[29] ;
+  wire \mprj_adr_o_user[2] ;
+  wire \mprj_adr_o_user[30] ;
+  wire \mprj_adr_o_user[31] ;
+  wire \mprj_adr_o_user[3] ;
+  wire \mprj_adr_o_user[4] ;
+  wire \mprj_adr_o_user[5] ;
+  wire \mprj_adr_o_user[6] ;
+  wire \mprj_adr_o_user[7] ;
+  wire \mprj_adr_o_user[8] ;
+  wire \mprj_adr_o_user[9] ;
+  wire mprj_clock;
+  wire mprj_clock2;
+  wire mprj_cyc_o_core;
+  wire mprj_cyc_o_user;
+  wire \mprj_dat_i_core[0] ;
+  wire \mprj_dat_i_core[10] ;
+  wire \mprj_dat_i_core[11] ;
+  wire \mprj_dat_i_core[12] ;
+  wire \mprj_dat_i_core[13] ;
+  wire \mprj_dat_i_core[14] ;
+  wire \mprj_dat_i_core[15] ;
+  wire \mprj_dat_i_core[16] ;
+  wire \mprj_dat_i_core[17] ;
+  wire \mprj_dat_i_core[18] ;
+  wire \mprj_dat_i_core[19] ;
+  wire \mprj_dat_i_core[1] ;
+  wire \mprj_dat_i_core[20] ;
+  wire \mprj_dat_i_core[21] ;
+  wire \mprj_dat_i_core[22] ;
+  wire \mprj_dat_i_core[23] ;
+  wire \mprj_dat_i_core[24] ;
+  wire \mprj_dat_i_core[25] ;
+  wire \mprj_dat_i_core[26] ;
+  wire \mprj_dat_i_core[27] ;
+  wire \mprj_dat_i_core[28] ;
+  wire \mprj_dat_i_core[29] ;
+  wire \mprj_dat_i_core[2] ;
+  wire \mprj_dat_i_core[30] ;
+  wire \mprj_dat_i_core[31] ;
+  wire \mprj_dat_i_core[3] ;
+  wire \mprj_dat_i_core[4] ;
+  wire \mprj_dat_i_core[5] ;
+  wire \mprj_dat_i_core[6] ;
+  wire \mprj_dat_i_core[7] ;
+  wire \mprj_dat_i_core[8] ;
+  wire \mprj_dat_i_core[9] ;
+  wire \mprj_dat_i_user[0] ;
+  wire \mprj_dat_i_user[10] ;
+  wire \mprj_dat_i_user[11] ;
+  wire \mprj_dat_i_user[12] ;
+  wire \mprj_dat_i_user[13] ;
+  wire \mprj_dat_i_user[14] ;
+  wire \mprj_dat_i_user[15] ;
+  wire \mprj_dat_i_user[16] ;
+  wire \mprj_dat_i_user[17] ;
+  wire \mprj_dat_i_user[18] ;
+  wire \mprj_dat_i_user[19] ;
+  wire \mprj_dat_i_user[1] ;
+  wire \mprj_dat_i_user[20] ;
+  wire \mprj_dat_i_user[21] ;
+  wire \mprj_dat_i_user[22] ;
+  wire \mprj_dat_i_user[23] ;
+  wire \mprj_dat_i_user[24] ;
+  wire \mprj_dat_i_user[25] ;
+  wire \mprj_dat_i_user[26] ;
+  wire \mprj_dat_i_user[27] ;
+  wire \mprj_dat_i_user[28] ;
+  wire \mprj_dat_i_user[29] ;
+  wire \mprj_dat_i_user[2] ;
+  wire \mprj_dat_i_user[30] ;
+  wire \mprj_dat_i_user[31] ;
+  wire \mprj_dat_i_user[3] ;
+  wire \mprj_dat_i_user[4] ;
+  wire \mprj_dat_i_user[5] ;
+  wire \mprj_dat_i_user[6] ;
+  wire \mprj_dat_i_user[7] ;
+  wire \mprj_dat_i_user[8] ;
+  wire \mprj_dat_i_user[9] ;
+  wire \mprj_dat_o_core[0] ;
+  wire \mprj_dat_o_core[10] ;
+  wire \mprj_dat_o_core[11] ;
+  wire \mprj_dat_o_core[12] ;
+  wire \mprj_dat_o_core[13] ;
+  wire \mprj_dat_o_core[14] ;
+  wire \mprj_dat_o_core[15] ;
+  wire \mprj_dat_o_core[16] ;
+  wire \mprj_dat_o_core[17] ;
+  wire \mprj_dat_o_core[18] ;
+  wire \mprj_dat_o_core[19] ;
+  wire \mprj_dat_o_core[1] ;
+  wire \mprj_dat_o_core[20] ;
+  wire \mprj_dat_o_core[21] ;
+  wire \mprj_dat_o_core[22] ;
+  wire \mprj_dat_o_core[23] ;
+  wire \mprj_dat_o_core[24] ;
+  wire \mprj_dat_o_core[25] ;
+  wire \mprj_dat_o_core[26] ;
+  wire \mprj_dat_o_core[27] ;
+  wire \mprj_dat_o_core[28] ;
+  wire \mprj_dat_o_core[29] ;
+  wire \mprj_dat_o_core[2] ;
+  wire \mprj_dat_o_core[30] ;
+  wire \mprj_dat_o_core[31] ;
+  wire \mprj_dat_o_core[3] ;
+  wire \mprj_dat_o_core[4] ;
+  wire \mprj_dat_o_core[5] ;
+  wire \mprj_dat_o_core[6] ;
+  wire \mprj_dat_o_core[7] ;
+  wire \mprj_dat_o_core[8] ;
+  wire \mprj_dat_o_core[9] ;
+  wire \mprj_dat_o_user[0] ;
+  wire \mprj_dat_o_user[10] ;
+  wire \mprj_dat_o_user[11] ;
+  wire \mprj_dat_o_user[12] ;
+  wire \mprj_dat_o_user[13] ;
+  wire \mprj_dat_o_user[14] ;
+  wire \mprj_dat_o_user[15] ;
+  wire \mprj_dat_o_user[16] ;
+  wire \mprj_dat_o_user[17] ;
+  wire \mprj_dat_o_user[18] ;
+  wire \mprj_dat_o_user[19] ;
+  wire \mprj_dat_o_user[1] ;
+  wire \mprj_dat_o_user[20] ;
+  wire \mprj_dat_o_user[21] ;
+  wire \mprj_dat_o_user[22] ;
+  wire \mprj_dat_o_user[23] ;
+  wire \mprj_dat_o_user[24] ;
+  wire \mprj_dat_o_user[25] ;
+  wire \mprj_dat_o_user[26] ;
+  wire \mprj_dat_o_user[27] ;
+  wire \mprj_dat_o_user[28] ;
+  wire \mprj_dat_o_user[29] ;
+  wire \mprj_dat_o_user[2] ;
+  wire \mprj_dat_o_user[30] ;
+  wire \mprj_dat_o_user[31] ;
+  wire \mprj_dat_o_user[3] ;
+  wire \mprj_dat_o_user[4] ;
+  wire \mprj_dat_o_user[5] ;
+  wire \mprj_dat_o_user[6] ;
+  wire \mprj_dat_o_user[7] ;
+  wire \mprj_dat_o_user[8] ;
+  wire \mprj_dat_o_user[9] ;
+  wire mprj_iena_wb;
+  inout [37:0] mprj_io;
+  wire \mprj_io_analog_en[0] ;
+  wire \mprj_io_analog_en[10] ;
+  wire \mprj_io_analog_en[11] ;
+  wire \mprj_io_analog_en[12] ;
+  wire \mprj_io_analog_en[13] ;
+  wire \mprj_io_analog_en[14] ;
+  wire \mprj_io_analog_en[15] ;
+  wire \mprj_io_analog_en[16] ;
+  wire \mprj_io_analog_en[17] ;
+  wire \mprj_io_analog_en[18] ;
+  wire \mprj_io_analog_en[19] ;
+  wire \mprj_io_analog_en[1] ;
+  wire \mprj_io_analog_en[20] ;
+  wire \mprj_io_analog_en[21] ;
+  wire \mprj_io_analog_en[22] ;
+  wire \mprj_io_analog_en[23] ;
+  wire \mprj_io_analog_en[24] ;
+  wire \mprj_io_analog_en[25] ;
+  wire \mprj_io_analog_en[26] ;
+  wire \mprj_io_analog_en[27] ;
+  wire \mprj_io_analog_en[28] ;
+  wire \mprj_io_analog_en[29] ;
+  wire \mprj_io_analog_en[2] ;
+  wire \mprj_io_analog_en[30] ;
+  wire \mprj_io_analog_en[31] ;
+  wire \mprj_io_analog_en[32] ;
+  wire \mprj_io_analog_en[33] ;
+  wire \mprj_io_analog_en[34] ;
+  wire \mprj_io_analog_en[35] ;
+  wire \mprj_io_analog_en[36] ;
+  wire \mprj_io_analog_en[37] ;
+  wire \mprj_io_analog_en[3] ;
+  wire \mprj_io_analog_en[4] ;
+  wire \mprj_io_analog_en[5] ;
+  wire \mprj_io_analog_en[6] ;
+  wire \mprj_io_analog_en[7] ;
+  wire \mprj_io_analog_en[8] ;
+  wire \mprj_io_analog_en[9] ;
+  wire \mprj_io_analog_pol[0] ;
+  wire \mprj_io_analog_pol[10] ;
+  wire \mprj_io_analog_pol[11] ;
+  wire \mprj_io_analog_pol[12] ;
+  wire \mprj_io_analog_pol[13] ;
+  wire \mprj_io_analog_pol[14] ;
+  wire \mprj_io_analog_pol[15] ;
+  wire \mprj_io_analog_pol[16] ;
+  wire \mprj_io_analog_pol[17] ;
+  wire \mprj_io_analog_pol[18] ;
+  wire \mprj_io_analog_pol[19] ;
+  wire \mprj_io_analog_pol[1] ;
+  wire \mprj_io_analog_pol[20] ;
+  wire \mprj_io_analog_pol[21] ;
+  wire \mprj_io_analog_pol[22] ;
+  wire \mprj_io_analog_pol[23] ;
+  wire \mprj_io_analog_pol[24] ;
+  wire \mprj_io_analog_pol[25] ;
+  wire \mprj_io_analog_pol[26] ;
+  wire \mprj_io_analog_pol[27] ;
+  wire \mprj_io_analog_pol[28] ;
+  wire \mprj_io_analog_pol[29] ;
+  wire \mprj_io_analog_pol[2] ;
+  wire \mprj_io_analog_pol[30] ;
+  wire \mprj_io_analog_pol[31] ;
+  wire \mprj_io_analog_pol[32] ;
+  wire \mprj_io_analog_pol[33] ;
+  wire \mprj_io_analog_pol[34] ;
+  wire \mprj_io_analog_pol[35] ;
+  wire \mprj_io_analog_pol[36] ;
+  wire \mprj_io_analog_pol[37] ;
+  wire \mprj_io_analog_pol[3] ;
+  wire \mprj_io_analog_pol[4] ;
+  wire \mprj_io_analog_pol[5] ;
+  wire \mprj_io_analog_pol[6] ;
+  wire \mprj_io_analog_pol[7] ;
+  wire \mprj_io_analog_pol[8] ;
+  wire \mprj_io_analog_pol[9] ;
+  wire \mprj_io_analog_sel[0] ;
+  wire \mprj_io_analog_sel[10] ;
+  wire \mprj_io_analog_sel[11] ;
+  wire \mprj_io_analog_sel[12] ;
+  wire \mprj_io_analog_sel[13] ;
+  wire \mprj_io_analog_sel[14] ;
+  wire \mprj_io_analog_sel[15] ;
+  wire \mprj_io_analog_sel[16] ;
+  wire \mprj_io_analog_sel[17] ;
+  wire \mprj_io_analog_sel[18] ;
+  wire \mprj_io_analog_sel[19] ;
+  wire \mprj_io_analog_sel[1] ;
+  wire \mprj_io_analog_sel[20] ;
+  wire \mprj_io_analog_sel[21] ;
+  wire \mprj_io_analog_sel[22] ;
+  wire \mprj_io_analog_sel[23] ;
+  wire \mprj_io_analog_sel[24] ;
+  wire \mprj_io_analog_sel[25] ;
+  wire \mprj_io_analog_sel[26] ;
+  wire \mprj_io_analog_sel[27] ;
+  wire \mprj_io_analog_sel[28] ;
+  wire \mprj_io_analog_sel[29] ;
+  wire \mprj_io_analog_sel[2] ;
+  wire \mprj_io_analog_sel[30] ;
+  wire \mprj_io_analog_sel[31] ;
+  wire \mprj_io_analog_sel[32] ;
+  wire \mprj_io_analog_sel[33] ;
+  wire \mprj_io_analog_sel[34] ;
+  wire \mprj_io_analog_sel[35] ;
+  wire \mprj_io_analog_sel[36] ;
+  wire \mprj_io_analog_sel[37] ;
+  wire \mprj_io_analog_sel[3] ;
+  wire \mprj_io_analog_sel[4] ;
+  wire \mprj_io_analog_sel[5] ;
+  wire \mprj_io_analog_sel[6] ;
+  wire \mprj_io_analog_sel[7] ;
+  wire \mprj_io_analog_sel[8] ;
+  wire \mprj_io_analog_sel[9] ;
+  wire \mprj_io_dm[0] ;
+  wire \mprj_io_dm[100] ;
+  wire \mprj_io_dm[101] ;
+  wire \mprj_io_dm[102] ;
+  wire \mprj_io_dm[103] ;
+  wire \mprj_io_dm[104] ;
+  wire \mprj_io_dm[105] ;
+  wire \mprj_io_dm[106] ;
+  wire \mprj_io_dm[107] ;
+  wire \mprj_io_dm[108] ;
+  wire \mprj_io_dm[109] ;
+  wire \mprj_io_dm[10] ;
+  wire \mprj_io_dm[110] ;
+  wire \mprj_io_dm[111] ;
+  wire \mprj_io_dm[112] ;
+  wire \mprj_io_dm[113] ;
+  wire \mprj_io_dm[11] ;
+  wire \mprj_io_dm[12] ;
+  wire \mprj_io_dm[13] ;
+  wire \mprj_io_dm[14] ;
+  wire \mprj_io_dm[15] ;
+  wire \mprj_io_dm[16] ;
+  wire \mprj_io_dm[17] ;
+  wire \mprj_io_dm[18] ;
+  wire \mprj_io_dm[19] ;
+  wire \mprj_io_dm[1] ;
+  wire \mprj_io_dm[20] ;
+  wire \mprj_io_dm[21] ;
+  wire \mprj_io_dm[22] ;
+  wire \mprj_io_dm[23] ;
+  wire \mprj_io_dm[24] ;
+  wire \mprj_io_dm[25] ;
+  wire \mprj_io_dm[26] ;
+  wire \mprj_io_dm[27] ;
+  wire \mprj_io_dm[28] ;
+  wire \mprj_io_dm[29] ;
+  wire \mprj_io_dm[2] ;
+  wire \mprj_io_dm[30] ;
+  wire \mprj_io_dm[31] ;
+  wire \mprj_io_dm[32] ;
+  wire \mprj_io_dm[33] ;
+  wire \mprj_io_dm[34] ;
+  wire \mprj_io_dm[35] ;
+  wire \mprj_io_dm[36] ;
+  wire \mprj_io_dm[37] ;
+  wire \mprj_io_dm[38] ;
+  wire \mprj_io_dm[39] ;
+  wire \mprj_io_dm[3] ;
+  wire \mprj_io_dm[40] ;
+  wire \mprj_io_dm[41] ;
+  wire \mprj_io_dm[42] ;
+  wire \mprj_io_dm[43] ;
+  wire \mprj_io_dm[44] ;
+  wire \mprj_io_dm[45] ;
+  wire \mprj_io_dm[46] ;
+  wire \mprj_io_dm[47] ;
+  wire \mprj_io_dm[48] ;
+  wire \mprj_io_dm[49] ;
+  wire \mprj_io_dm[4] ;
+  wire \mprj_io_dm[50] ;
+  wire \mprj_io_dm[51] ;
+  wire \mprj_io_dm[52] ;
+  wire \mprj_io_dm[53] ;
+  wire \mprj_io_dm[54] ;
+  wire \mprj_io_dm[55] ;
+  wire \mprj_io_dm[56] ;
+  wire \mprj_io_dm[57] ;
+  wire \mprj_io_dm[58] ;
+  wire \mprj_io_dm[59] ;
+  wire \mprj_io_dm[5] ;
+  wire \mprj_io_dm[60] ;
+  wire \mprj_io_dm[61] ;
+  wire \mprj_io_dm[62] ;
+  wire \mprj_io_dm[63] ;
+  wire \mprj_io_dm[64] ;
+  wire \mprj_io_dm[65] ;
+  wire \mprj_io_dm[66] ;
+  wire \mprj_io_dm[67] ;
+  wire \mprj_io_dm[68] ;
+  wire \mprj_io_dm[69] ;
+  wire \mprj_io_dm[6] ;
+  wire \mprj_io_dm[70] ;
+  wire \mprj_io_dm[71] ;
+  wire \mprj_io_dm[72] ;
+  wire \mprj_io_dm[73] ;
+  wire \mprj_io_dm[74] ;
+  wire \mprj_io_dm[75] ;
+  wire \mprj_io_dm[76] ;
+  wire \mprj_io_dm[77] ;
+  wire \mprj_io_dm[78] ;
+  wire \mprj_io_dm[79] ;
+  wire \mprj_io_dm[7] ;
+  wire \mprj_io_dm[80] ;
+  wire \mprj_io_dm[81] ;
+  wire \mprj_io_dm[82] ;
+  wire \mprj_io_dm[83] ;
+  wire \mprj_io_dm[84] ;
+  wire \mprj_io_dm[85] ;
+  wire \mprj_io_dm[86] ;
+  wire \mprj_io_dm[87] ;
+  wire \mprj_io_dm[88] ;
+  wire \mprj_io_dm[89] ;
+  wire \mprj_io_dm[8] ;
+  wire \mprj_io_dm[90] ;
+  wire \mprj_io_dm[91] ;
+  wire \mprj_io_dm[92] ;
+  wire \mprj_io_dm[93] ;
+  wire \mprj_io_dm[94] ;
+  wire \mprj_io_dm[95] ;
+  wire \mprj_io_dm[96] ;
+  wire \mprj_io_dm[97] ;
+  wire \mprj_io_dm[98] ;
+  wire \mprj_io_dm[99] ;
+  wire \mprj_io_dm[9] ;
+  wire \mprj_io_holdover[0] ;
+  wire \mprj_io_holdover[10] ;
+  wire \mprj_io_holdover[11] ;
+  wire \mprj_io_holdover[12] ;
+  wire \mprj_io_holdover[13] ;
+  wire \mprj_io_holdover[14] ;
+  wire \mprj_io_holdover[15] ;
+  wire \mprj_io_holdover[16] ;
+  wire \mprj_io_holdover[17] ;
+  wire \mprj_io_holdover[18] ;
+  wire \mprj_io_holdover[19] ;
+  wire \mprj_io_holdover[1] ;
+  wire \mprj_io_holdover[20] ;
+  wire \mprj_io_holdover[21] ;
+  wire \mprj_io_holdover[22] ;
+  wire \mprj_io_holdover[23] ;
+  wire \mprj_io_holdover[24] ;
+  wire \mprj_io_holdover[25] ;
+  wire \mprj_io_holdover[26] ;
+  wire \mprj_io_holdover[27] ;
+  wire \mprj_io_holdover[28] ;
+  wire \mprj_io_holdover[29] ;
+  wire \mprj_io_holdover[2] ;
+  wire \mprj_io_holdover[30] ;
+  wire \mprj_io_holdover[31] ;
+  wire \mprj_io_holdover[32] ;
+  wire \mprj_io_holdover[33] ;
+  wire \mprj_io_holdover[34] ;
+  wire \mprj_io_holdover[35] ;
+  wire \mprj_io_holdover[36] ;
+  wire \mprj_io_holdover[37] ;
+  wire \mprj_io_holdover[3] ;
+  wire \mprj_io_holdover[4] ;
+  wire \mprj_io_holdover[5] ;
+  wire \mprj_io_holdover[6] ;
+  wire \mprj_io_holdover[7] ;
+  wire \mprj_io_holdover[8] ;
+  wire \mprj_io_holdover[9] ;
+  wire \mprj_io_ib_mode_sel[0] ;
+  wire \mprj_io_ib_mode_sel[10] ;
+  wire \mprj_io_ib_mode_sel[11] ;
+  wire \mprj_io_ib_mode_sel[12] ;
+  wire \mprj_io_ib_mode_sel[13] ;
+  wire \mprj_io_ib_mode_sel[14] ;
+  wire \mprj_io_ib_mode_sel[15] ;
+  wire \mprj_io_ib_mode_sel[16] ;
+  wire \mprj_io_ib_mode_sel[17] ;
+  wire \mprj_io_ib_mode_sel[18] ;
+  wire \mprj_io_ib_mode_sel[19] ;
+  wire \mprj_io_ib_mode_sel[1] ;
+  wire \mprj_io_ib_mode_sel[20] ;
+  wire \mprj_io_ib_mode_sel[21] ;
+  wire \mprj_io_ib_mode_sel[22] ;
+  wire \mprj_io_ib_mode_sel[23] ;
+  wire \mprj_io_ib_mode_sel[24] ;
+  wire \mprj_io_ib_mode_sel[25] ;
+  wire \mprj_io_ib_mode_sel[26] ;
+  wire \mprj_io_ib_mode_sel[27] ;
+  wire \mprj_io_ib_mode_sel[28] ;
+  wire \mprj_io_ib_mode_sel[29] ;
+  wire \mprj_io_ib_mode_sel[2] ;
+  wire \mprj_io_ib_mode_sel[30] ;
+  wire \mprj_io_ib_mode_sel[31] ;
+  wire \mprj_io_ib_mode_sel[32] ;
+  wire \mprj_io_ib_mode_sel[33] ;
+  wire \mprj_io_ib_mode_sel[34] ;
+  wire \mprj_io_ib_mode_sel[35] ;
+  wire \mprj_io_ib_mode_sel[36] ;
+  wire \mprj_io_ib_mode_sel[37] ;
+  wire \mprj_io_ib_mode_sel[3] ;
+  wire \mprj_io_ib_mode_sel[4] ;
+  wire \mprj_io_ib_mode_sel[5] ;
+  wire \mprj_io_ib_mode_sel[6] ;
+  wire \mprj_io_ib_mode_sel[7] ;
+  wire \mprj_io_ib_mode_sel[8] ;
+  wire \mprj_io_ib_mode_sel[9] ;
+  wire \mprj_io_in[0] ;
+  wire \mprj_io_in[10] ;
+  wire \mprj_io_in[11] ;
+  wire \mprj_io_in[12] ;
+  wire \mprj_io_in[13] ;
+  wire \mprj_io_in[14] ;
+  wire \mprj_io_in[15] ;
+  wire \mprj_io_in[16] ;
+  wire \mprj_io_in[17] ;
+  wire \mprj_io_in[18] ;
+  wire \mprj_io_in[19] ;
+  wire \mprj_io_in[1] ;
+  wire \mprj_io_in[20] ;
+  wire \mprj_io_in[21] ;
+  wire \mprj_io_in[22] ;
+  wire \mprj_io_in[23] ;
+  wire \mprj_io_in[24] ;
+  wire \mprj_io_in[25] ;
+  wire \mprj_io_in[26] ;
+  wire \mprj_io_in[27] ;
+  wire \mprj_io_in[28] ;
+  wire \mprj_io_in[29] ;
+  wire \mprj_io_in[2] ;
+  wire \mprj_io_in[30] ;
+  wire \mprj_io_in[31] ;
+  wire \mprj_io_in[32] ;
+  wire \mprj_io_in[33] ;
+  wire \mprj_io_in[34] ;
+  wire \mprj_io_in[35] ;
+  wire \mprj_io_in[36] ;
+  wire \mprj_io_in[37] ;
+  wire \mprj_io_in[3] ;
+  wire \mprj_io_in[4] ;
+  wire \mprj_io_in[5] ;
+  wire \mprj_io_in[6] ;
+  wire \mprj_io_in[7] ;
+  wire \mprj_io_in[8] ;
+  wire \mprj_io_in[9] ;
+  wire \mprj_io_inp_dis[0] ;
+  wire \mprj_io_inp_dis[10] ;
+  wire \mprj_io_inp_dis[11] ;
+  wire \mprj_io_inp_dis[12] ;
+  wire \mprj_io_inp_dis[13] ;
+  wire \mprj_io_inp_dis[14] ;
+  wire \mprj_io_inp_dis[15] ;
+  wire \mprj_io_inp_dis[16] ;
+  wire \mprj_io_inp_dis[17] ;
+  wire \mprj_io_inp_dis[18] ;
+  wire \mprj_io_inp_dis[19] ;
+  wire \mprj_io_inp_dis[1] ;
+  wire \mprj_io_inp_dis[20] ;
+  wire \mprj_io_inp_dis[21] ;
+  wire \mprj_io_inp_dis[22] ;
+  wire \mprj_io_inp_dis[23] ;
+  wire \mprj_io_inp_dis[24] ;
+  wire \mprj_io_inp_dis[25] ;
+  wire \mprj_io_inp_dis[26] ;
+  wire \mprj_io_inp_dis[27] ;
+  wire \mprj_io_inp_dis[28] ;
+  wire \mprj_io_inp_dis[29] ;
+  wire \mprj_io_inp_dis[2] ;
+  wire \mprj_io_inp_dis[30] ;
+  wire \mprj_io_inp_dis[31] ;
+  wire \mprj_io_inp_dis[32] ;
+  wire \mprj_io_inp_dis[33] ;
+  wire \mprj_io_inp_dis[34] ;
+  wire \mprj_io_inp_dis[35] ;
+  wire \mprj_io_inp_dis[36] ;
+  wire \mprj_io_inp_dis[37] ;
+  wire \mprj_io_inp_dis[3] ;
+  wire \mprj_io_inp_dis[4] ;
+  wire \mprj_io_inp_dis[5] ;
+  wire \mprj_io_inp_dis[6] ;
+  wire \mprj_io_inp_dis[7] ;
+  wire \mprj_io_inp_dis[8] ;
+  wire \mprj_io_inp_dis[9] ;
+  wire mprj_io_loader_clock;
+  wire mprj_io_loader_clock_buf;
+  wire mprj_io_loader_data_1;
+  wire mprj_io_loader_data_2;
+  wire mprj_io_loader_data_2_buf;
+  wire mprj_io_loader_resetn;
+  wire mprj_io_loader_resetn_buf;
+  wire mprj_io_loader_strobe;
+  wire mprj_io_loader_strobe_buf;
+  wire \mprj_io_oeb[0] ;
+  wire \mprj_io_oeb[10] ;
+  wire \mprj_io_oeb[11] ;
+  wire \mprj_io_oeb[12] ;
+  wire \mprj_io_oeb[13] ;
+  wire \mprj_io_oeb[14] ;
+  wire \mprj_io_oeb[15] ;
+  wire \mprj_io_oeb[16] ;
+  wire \mprj_io_oeb[17] ;
+  wire \mprj_io_oeb[18] ;
+  wire \mprj_io_oeb[19] ;
+  wire \mprj_io_oeb[1] ;
+  wire \mprj_io_oeb[20] ;
+  wire \mprj_io_oeb[21] ;
+  wire \mprj_io_oeb[22] ;
+  wire \mprj_io_oeb[23] ;
+  wire \mprj_io_oeb[24] ;
+  wire \mprj_io_oeb[25] ;
+  wire \mprj_io_oeb[26] ;
+  wire \mprj_io_oeb[27] ;
+  wire \mprj_io_oeb[28] ;
+  wire \mprj_io_oeb[29] ;
+  wire \mprj_io_oeb[2] ;
+  wire \mprj_io_oeb[30] ;
+  wire \mprj_io_oeb[31] ;
+  wire \mprj_io_oeb[32] ;
+  wire \mprj_io_oeb[33] ;
+  wire \mprj_io_oeb[34] ;
+  wire \mprj_io_oeb[35] ;
+  wire \mprj_io_oeb[36] ;
+  wire \mprj_io_oeb[37] ;
+  wire \mprj_io_oeb[3] ;
+  wire \mprj_io_oeb[4] ;
+  wire \mprj_io_oeb[5] ;
+  wire \mprj_io_oeb[6] ;
+  wire \mprj_io_oeb[7] ;
+  wire \mprj_io_oeb[8] ;
+  wire \mprj_io_oeb[9] ;
+  wire \mprj_io_one[0] ;
+  wire \mprj_io_one[10] ;
+  wire \mprj_io_one[11] ;
+  wire \mprj_io_one[12] ;
+  wire \mprj_io_one[13] ;
+  wire \mprj_io_one[14] ;
+  wire \mprj_io_one[15] ;
+  wire \mprj_io_one[16] ;
+  wire \mprj_io_one[17] ;
+  wire \mprj_io_one[18] ;
+  wire \mprj_io_one[19] ;
+  wire \mprj_io_one[1] ;
+  wire \mprj_io_one[20] ;
+  wire \mprj_io_one[21] ;
+  wire \mprj_io_one[22] ;
+  wire \mprj_io_one[23] ;
+  wire \mprj_io_one[24] ;
+  wire \mprj_io_one[25] ;
+  wire \mprj_io_one[26] ;
+  wire \mprj_io_one[27] ;
+  wire \mprj_io_one[28] ;
+  wire \mprj_io_one[29] ;
+  wire \mprj_io_one[2] ;
+  wire \mprj_io_one[30] ;
+  wire \mprj_io_one[31] ;
+  wire \mprj_io_one[32] ;
+  wire \mprj_io_one[33] ;
+  wire \mprj_io_one[34] ;
+  wire \mprj_io_one[35] ;
+  wire \mprj_io_one[36] ;
+  wire \mprj_io_one[37] ;
+  wire \mprj_io_one[3] ;
+  wire \mprj_io_one[4] ;
+  wire \mprj_io_one[5] ;
+  wire \mprj_io_one[6] ;
+  wire \mprj_io_one[7] ;
+  wire \mprj_io_one[8] ;
+  wire \mprj_io_one[9] ;
+  wire \mprj_io_out[0] ;
+  wire \mprj_io_out[10] ;
+  wire \mprj_io_out[11] ;
+  wire \mprj_io_out[12] ;
+  wire \mprj_io_out[13] ;
+  wire \mprj_io_out[14] ;
+  wire \mprj_io_out[15] ;
+  wire \mprj_io_out[16] ;
+  wire \mprj_io_out[17] ;
+  wire \mprj_io_out[18] ;
+  wire \mprj_io_out[19] ;
+  wire \mprj_io_out[1] ;
+  wire \mprj_io_out[20] ;
+  wire \mprj_io_out[21] ;
+  wire \mprj_io_out[22] ;
+  wire \mprj_io_out[23] ;
+  wire \mprj_io_out[24] ;
+  wire \mprj_io_out[25] ;
+  wire \mprj_io_out[26] ;
+  wire \mprj_io_out[27] ;
+  wire \mprj_io_out[28] ;
+  wire \mprj_io_out[29] ;
+  wire \mprj_io_out[2] ;
+  wire \mprj_io_out[30] ;
+  wire \mprj_io_out[31] ;
+  wire \mprj_io_out[32] ;
+  wire \mprj_io_out[33] ;
+  wire \mprj_io_out[34] ;
+  wire \mprj_io_out[35] ;
+  wire \mprj_io_out[36] ;
+  wire \mprj_io_out[37] ;
+  wire \mprj_io_out[3] ;
+  wire \mprj_io_out[4] ;
+  wire \mprj_io_out[5] ;
+  wire \mprj_io_out[6] ;
+  wire \mprj_io_out[7] ;
+  wire \mprj_io_out[8] ;
+  wire \mprj_io_out[9] ;
+  wire \mprj_io_slow_sel[0] ;
+  wire \mprj_io_slow_sel[10] ;
+  wire \mprj_io_slow_sel[11] ;
+  wire \mprj_io_slow_sel[12] ;
+  wire \mprj_io_slow_sel[13] ;
+  wire \mprj_io_slow_sel[14] ;
+  wire \mprj_io_slow_sel[15] ;
+  wire \mprj_io_slow_sel[16] ;
+  wire \mprj_io_slow_sel[17] ;
+  wire \mprj_io_slow_sel[18] ;
+  wire \mprj_io_slow_sel[19] ;
+  wire \mprj_io_slow_sel[1] ;
+  wire \mprj_io_slow_sel[20] ;
+  wire \mprj_io_slow_sel[21] ;
+  wire \mprj_io_slow_sel[22] ;
+  wire \mprj_io_slow_sel[23] ;
+  wire \mprj_io_slow_sel[24] ;
+  wire \mprj_io_slow_sel[25] ;
+  wire \mprj_io_slow_sel[26] ;
+  wire \mprj_io_slow_sel[27] ;
+  wire \mprj_io_slow_sel[28] ;
+  wire \mprj_io_slow_sel[29] ;
+  wire \mprj_io_slow_sel[2] ;
+  wire \mprj_io_slow_sel[30] ;
+  wire \mprj_io_slow_sel[31] ;
+  wire \mprj_io_slow_sel[32] ;
+  wire \mprj_io_slow_sel[33] ;
+  wire \mprj_io_slow_sel[34] ;
+  wire \mprj_io_slow_sel[35] ;
+  wire \mprj_io_slow_sel[36] ;
+  wire \mprj_io_slow_sel[37] ;
+  wire \mprj_io_slow_sel[3] ;
+  wire \mprj_io_slow_sel[4] ;
+  wire \mprj_io_slow_sel[5] ;
+  wire \mprj_io_slow_sel[6] ;
+  wire \mprj_io_slow_sel[7] ;
+  wire \mprj_io_slow_sel[8] ;
+  wire \mprj_io_slow_sel[9] ;
+  wire \mprj_io_vtrip_sel[0] ;
+  wire \mprj_io_vtrip_sel[10] ;
+  wire \mprj_io_vtrip_sel[11] ;
+  wire \mprj_io_vtrip_sel[12] ;
+  wire \mprj_io_vtrip_sel[13] ;
+  wire \mprj_io_vtrip_sel[14] ;
+  wire \mprj_io_vtrip_sel[15] ;
+  wire \mprj_io_vtrip_sel[16] ;
+  wire \mprj_io_vtrip_sel[17] ;
+  wire \mprj_io_vtrip_sel[18] ;
+  wire \mprj_io_vtrip_sel[19] ;
+  wire \mprj_io_vtrip_sel[1] ;
+  wire \mprj_io_vtrip_sel[20] ;
+  wire \mprj_io_vtrip_sel[21] ;
+  wire \mprj_io_vtrip_sel[22] ;
+  wire \mprj_io_vtrip_sel[23] ;
+  wire \mprj_io_vtrip_sel[24] ;
+  wire \mprj_io_vtrip_sel[25] ;
+  wire \mprj_io_vtrip_sel[26] ;
+  wire \mprj_io_vtrip_sel[27] ;
+  wire \mprj_io_vtrip_sel[28] ;
+  wire \mprj_io_vtrip_sel[29] ;
+  wire \mprj_io_vtrip_sel[2] ;
+  wire \mprj_io_vtrip_sel[30] ;
+  wire \mprj_io_vtrip_sel[31] ;
+  wire \mprj_io_vtrip_sel[32] ;
+  wire \mprj_io_vtrip_sel[33] ;
+  wire \mprj_io_vtrip_sel[34] ;
+  wire \mprj_io_vtrip_sel[35] ;
+  wire \mprj_io_vtrip_sel[36] ;
+  wire \mprj_io_vtrip_sel[37] ;
+  wire \mprj_io_vtrip_sel[3] ;
+  wire \mprj_io_vtrip_sel[4] ;
+  wire \mprj_io_vtrip_sel[5] ;
+  wire \mprj_io_vtrip_sel[6] ;
+  wire \mprj_io_vtrip_sel[7] ;
+  wire \mprj_io_vtrip_sel[8] ;
+  wire \mprj_io_vtrip_sel[9] ;
+  wire mprj_reset;
+  wire \mprj_sel_o_core[0] ;
+  wire \mprj_sel_o_core[1] ;
+  wire \mprj_sel_o_core[2] ;
+  wire \mprj_sel_o_core[3] ;
+  wire \mprj_sel_o_user[0] ;
+  wire \mprj_sel_o_user[1] ;
+  wire \mprj_sel_o_user[2] ;
+  wire \mprj_sel_o_user[3] ;
+  wire mprj_stb_o_core;
+  wire mprj_stb_o_user;
+  wire mprj_vcc_pwrgood;
+  wire mprj_vdd_pwrgood;
+  wire mprj_we_o_core;
+  wire mprj_we_o_user;
+  wire pll_clk;
+  wire pll_clk90;
+  wire por_l;
+  wire por_l_buf;
+  wire porb_h;
+  wire porb_h_buf;
+  wire porb_h_in_nc;
+  wire porb_h_out_nc;
+  wire porb_l;
+  wire \pwr_ctrl_nc[0] ;
+  wire \pwr_ctrl_nc[1] ;
+  wire \pwr_ctrl_nc[2] ;
+  wire \pwr_ctrl_nc[3] ;
+  wire qspi_enabled;
+  input resetb;
+  wire resetn_passthru;
+  wire rstb_h;
+  wire rstb_l;
+  wire rstb_l_buf;
+  wire ser_rx;
+  wire ser_tx;
+  wire \spare_xfq_nc[0] ;
+  wire \spare_xfq_nc[1] ;
+  wire \spare_xfq_nc[2] ;
+  wire \spare_xfq_nc[3] ;
+  wire \spare_xfq_nc[4] ;
+  wire \spare_xfq_nc[5] ;
+  wire \spare_xfq_nc[6] ;
+  wire \spare_xfq_nc[7] ;
+  wire \spare_xfqn_nc[0] ;
+  wire \spare_xfqn_nc[1] ;
+  wire \spare_xfqn_nc[2] ;
+  wire \spare_xfqn_nc[3] ;
+  wire \spare_xfqn_nc[4] ;
+  wire \spare_xfqn_nc[5] ;
+  wire \spare_xfqn_nc[6] ;
+  wire \spare_xfqn_nc[7] ;
+  wire \spare_xi_nc[0] ;
+  wire \spare_xi_nc[10] ;
+  wire \spare_xi_nc[11] ;
+  wire \spare_xi_nc[12] ;
+  wire \spare_xi_nc[13] ;
+  wire \spare_xi_nc[14] ;
+  wire \spare_xi_nc[15] ;
+  wire \spare_xi_nc[1] ;
+  wire \spare_xi_nc[2] ;
+  wire \spare_xi_nc[3] ;
+  wire \spare_xi_nc[4] ;
+  wire \spare_xi_nc[5] ;
+  wire \spare_xi_nc[6] ;
+  wire \spare_xi_nc[7] ;
+  wire \spare_xi_nc[8] ;
+  wire \spare_xi_nc[9] ;
+  wire \spare_xib_nc[0] ;
+  wire \spare_xib_nc[1] ;
+  wire \spare_xib_nc[2] ;
+  wire \spare_xib_nc[3] ;
+  wire \spare_xmx_nc[0] ;
+  wire \spare_xmx_nc[1] ;
+  wire \spare_xmx_nc[2] ;
+  wire \spare_xmx_nc[3] ;
+  wire \spare_xmx_nc[4] ;
+  wire \spare_xmx_nc[5] ;
+  wire \spare_xmx_nc[6] ;
+  wire \spare_xmx_nc[7] ;
+  wire \spare_xna_nc[0] ;
+  wire \spare_xna_nc[1] ;
+  wire \spare_xna_nc[2] ;
+  wire \spare_xna_nc[3] ;
+  wire \spare_xna_nc[4] ;
+  wire \spare_xna_nc[5] ;
+  wire \spare_xna_nc[6] ;
+  wire \spare_xna_nc[7] ;
+  wire \spare_xno_nc[0] ;
+  wire \spare_xno_nc[1] ;
+  wire \spare_xno_nc[2] ;
+  wire \spare_xno_nc[3] ;
+  wire \spare_xno_nc[4] ;
+  wire \spare_xno_nc[5] ;
+  wire \spare_xno_nc[6] ;
+  wire \spare_xno_nc[7] ;
+  wire \spare_xz_nc[0] ;
+  wire \spare_xz_nc[100] ;
+  wire \spare_xz_nc[101] ;
+  wire \spare_xz_nc[102] ;
+  wire \spare_xz_nc[103] ;
+  wire \spare_xz_nc[104] ;
+  wire \spare_xz_nc[105] ;
+  wire \spare_xz_nc[106] ;
+  wire \spare_xz_nc[107] ;
+  wire \spare_xz_nc[10] ;
+  wire \spare_xz_nc[11] ;
+  wire \spare_xz_nc[12] ;
+  wire \spare_xz_nc[13] ;
+  wire \spare_xz_nc[14] ;
+  wire \spare_xz_nc[15] ;
+  wire \spare_xz_nc[16] ;
+  wire \spare_xz_nc[17] ;
+  wire \spare_xz_nc[18] ;
+  wire \spare_xz_nc[19] ;
+  wire \spare_xz_nc[1] ;
+  wire \spare_xz_nc[20] ;
+  wire \spare_xz_nc[21] ;
+  wire \spare_xz_nc[22] ;
+  wire \spare_xz_nc[23] ;
+  wire \spare_xz_nc[24] ;
+  wire \spare_xz_nc[25] ;
+  wire \spare_xz_nc[26] ;
+  wire \spare_xz_nc[27] ;
+  wire \spare_xz_nc[28] ;
+  wire \spare_xz_nc[29] ;
+  wire \spare_xz_nc[2] ;
+  wire \spare_xz_nc[30] ;
+  wire \spare_xz_nc[31] ;
+  wire \spare_xz_nc[32] ;
+  wire \spare_xz_nc[33] ;
+  wire \spare_xz_nc[34] ;
+  wire \spare_xz_nc[35] ;
+  wire \spare_xz_nc[36] ;
+  wire \spare_xz_nc[37] ;
+  wire \spare_xz_nc[38] ;
+  wire \spare_xz_nc[39] ;
+  wire \spare_xz_nc[3] ;
+  wire \spare_xz_nc[40] ;
+  wire \spare_xz_nc[41] ;
+  wire \spare_xz_nc[42] ;
+  wire \spare_xz_nc[43] ;
+  wire \spare_xz_nc[44] ;
+  wire \spare_xz_nc[45] ;
+  wire \spare_xz_nc[46] ;
+  wire \spare_xz_nc[47] ;
+  wire \spare_xz_nc[48] ;
+  wire \spare_xz_nc[49] ;
+  wire \spare_xz_nc[4] ;
+  wire \spare_xz_nc[50] ;
+  wire \spare_xz_nc[51] ;
+  wire \spare_xz_nc[52] ;
+  wire \spare_xz_nc[53] ;
+  wire \spare_xz_nc[54] ;
+  wire \spare_xz_nc[55] ;
+  wire \spare_xz_nc[56] ;
+  wire \spare_xz_nc[57] ;
+  wire \spare_xz_nc[58] ;
+  wire \spare_xz_nc[59] ;
+  wire \spare_xz_nc[5] ;
+  wire \spare_xz_nc[60] ;
+  wire \spare_xz_nc[61] ;
+  wire \spare_xz_nc[62] ;
+  wire \spare_xz_nc[63] ;
+  wire \spare_xz_nc[64] ;
+  wire \spare_xz_nc[65] ;
+  wire \spare_xz_nc[66] ;
+  wire \spare_xz_nc[67] ;
+  wire \spare_xz_nc[68] ;
+  wire \spare_xz_nc[69] ;
+  wire \spare_xz_nc[6] ;
+  wire \spare_xz_nc[70] ;
+  wire \spare_xz_nc[71] ;
+  wire \spare_xz_nc[72] ;
+  wire \spare_xz_nc[73] ;
+  wire \spare_xz_nc[74] ;
+  wire \spare_xz_nc[75] ;
+  wire \spare_xz_nc[76] ;
+  wire \spare_xz_nc[77] ;
+  wire \spare_xz_nc[78] ;
+  wire \spare_xz_nc[79] ;
+  wire \spare_xz_nc[7] ;
+  wire \spare_xz_nc[80] ;
+  wire \spare_xz_nc[81] ;
+  wire \spare_xz_nc[82] ;
+  wire \spare_xz_nc[83] ;
+  wire \spare_xz_nc[84] ;
+  wire \spare_xz_nc[85] ;
+  wire \spare_xz_nc[86] ;
+  wire \spare_xz_nc[87] ;
+  wire \spare_xz_nc[88] ;
+  wire \spare_xz_nc[89] ;
+  wire \spare_xz_nc[8] ;
+  wire \spare_xz_nc[90] ;
+  wire \spare_xz_nc[91] ;
+  wire \spare_xz_nc[92] ;
+  wire \spare_xz_nc[93] ;
+  wire \spare_xz_nc[94] ;
+  wire \spare_xz_nc[95] ;
+  wire \spare_xz_nc[96] ;
+  wire \spare_xz_nc[97] ;
+  wire \spare_xz_nc[98] ;
+  wire \spare_xz_nc[99] ;
+  wire \spare_xz_nc[9] ;
+  wire spi_csb;
+  wire spi_enabled;
+  wire \spi_pll90_sel[0] ;
+  wire \spi_pll90_sel[1] ;
+  wire \spi_pll90_sel[2] ;
+  wire spi_pll_dco_ena;
+  wire \spi_pll_div[0] ;
+  wire \spi_pll_div[1] ;
+  wire \spi_pll_div[2] ;
+  wire \spi_pll_div[3] ;
+  wire \spi_pll_div[4] ;
+  wire spi_pll_ena;
+  wire \spi_pll_sel[0] ;
+  wire \spi_pll_sel[1] ;
+  wire \spi_pll_sel[2] ;
+  wire \spi_pll_trim[0] ;
+  wire \spi_pll_trim[10] ;
+  wire \spi_pll_trim[11] ;
+  wire \spi_pll_trim[12] ;
+  wire \spi_pll_trim[13] ;
+  wire \spi_pll_trim[14] ;
+  wire \spi_pll_trim[15] ;
+  wire \spi_pll_trim[16] ;
+  wire \spi_pll_trim[17] ;
+  wire \spi_pll_trim[18] ;
+  wire \spi_pll_trim[19] ;
+  wire \spi_pll_trim[1] ;
+  wire \spi_pll_trim[20] ;
+  wire \spi_pll_trim[21] ;
+  wire \spi_pll_trim[22] ;
+  wire \spi_pll_trim[23] ;
+  wire \spi_pll_trim[24] ;
+  wire \spi_pll_trim[25] ;
+  wire \spi_pll_trim[2] ;
+  wire \spi_pll_trim[3] ;
+  wire \spi_pll_trim[4] ;
+  wire \spi_pll_trim[5] ;
+  wire \spi_pll_trim[6] ;
+  wire \spi_pll_trim[7] ;
+  wire \spi_pll_trim[8] ;
+  wire \spi_pll_trim[9] ;
+  wire spi_sck;
+  wire spi_sdi;
+  wire spi_sdo;
+  wire spi_sdoenb;
+  wire trap;
+  wire uart_enabled;
+  wire \user_analog_io[0] ;
+  wire \user_analog_io[10] ;
+  wire \user_analog_io[11] ;
+  wire \user_analog_io[12] ;
+  wire \user_analog_io[13] ;
+  wire \user_analog_io[14] ;
+  wire \user_analog_io[15] ;
+  wire \user_analog_io[16] ;
+  wire \user_analog_io[17] ;
+  wire \user_analog_io[18] ;
+  wire \user_analog_io[19] ;
+  wire \user_analog_io[1] ;
+  wire \user_analog_io[20] ;
+  wire \user_analog_io[21] ;
+  wire \user_analog_io[22] ;
+  wire \user_analog_io[23] ;
+  wire \user_analog_io[24] ;
+  wire \user_analog_io[25] ;
+  wire \user_analog_io[26] ;
+  wire \user_analog_io[27] ;
+  wire \user_analog_io[28] ;
+  wire \user_analog_io[2] ;
+  wire \user_analog_io[3] ;
+  wire \user_analog_io[4] ;
+  wire \user_analog_io[5] ;
+  wire \user_analog_io[6] ;
+  wire \user_analog_io[7] ;
+  wire \user_analog_io[8] ;
+  wire \user_analog_io[9] ;
+  wire \user_io_in[0] ;
+  wire \user_io_in[10] ;
+  wire \user_io_in[11] ;
+  wire \user_io_in[12] ;
+  wire \user_io_in[13] ;
+  wire \user_io_in[14] ;
+  wire \user_io_in[15] ;
+  wire \user_io_in[16] ;
+  wire \user_io_in[17] ;
+  wire \user_io_in[18] ;
+  wire \user_io_in[19] ;
+  wire \user_io_in[1] ;
+  wire \user_io_in[20] ;
+  wire \user_io_in[21] ;
+  wire \user_io_in[22] ;
+  wire \user_io_in[23] ;
+  wire \user_io_in[24] ;
+  wire \user_io_in[25] ;
+  wire \user_io_in[26] ;
+  wire \user_io_in[27] ;
+  wire \user_io_in[28] ;
+  wire \user_io_in[29] ;
+  wire \user_io_in[2] ;
+  wire \user_io_in[30] ;
+  wire \user_io_in[31] ;
+  wire \user_io_in[32] ;
+  wire \user_io_in[33] ;
+  wire \user_io_in[34] ;
+  wire \user_io_in[35] ;
+  wire \user_io_in[36] ;
+  wire \user_io_in[37] ;
+  wire \user_io_in[3] ;
+  wire \user_io_in[4] ;
+  wire \user_io_in[5] ;
+  wire \user_io_in[6] ;
+  wire \user_io_in[7] ;
+  wire \user_io_in[8] ;
+  wire \user_io_in[9] ;
+  wire \user_io_oeb[0] ;
+  wire \user_io_oeb[10] ;
+  wire \user_io_oeb[11] ;
+  wire \user_io_oeb[12] ;
+  wire \user_io_oeb[13] ;
+  wire \user_io_oeb[14] ;
+  wire \user_io_oeb[15] ;
+  wire \user_io_oeb[16] ;
+  wire \user_io_oeb[17] ;
+  wire \user_io_oeb[18] ;
+  wire \user_io_oeb[19] ;
+  wire \user_io_oeb[1] ;
+  wire \user_io_oeb[20] ;
+  wire \user_io_oeb[21] ;
+  wire \user_io_oeb[22] ;
+  wire \user_io_oeb[23] ;
+  wire \user_io_oeb[24] ;
+  wire \user_io_oeb[25] ;
+  wire \user_io_oeb[26] ;
+  wire \user_io_oeb[27] ;
+  wire \user_io_oeb[28] ;
+  wire \user_io_oeb[29] ;
+  wire \user_io_oeb[2] ;
+  wire \user_io_oeb[30] ;
+  wire \user_io_oeb[31] ;
+  wire \user_io_oeb[32] ;
+  wire \user_io_oeb[33] ;
+  wire \user_io_oeb[34] ;
+  wire \user_io_oeb[35] ;
+  wire \user_io_oeb[36] ;
+  wire \user_io_oeb[37] ;
+  wire \user_io_oeb[3] ;
+  wire \user_io_oeb[4] ;
+  wire \user_io_oeb[5] ;
+  wire \user_io_oeb[6] ;
+  wire \user_io_oeb[7] ;
+  wire \user_io_oeb[8] ;
+  wire \user_io_oeb[9] ;
+  wire \user_io_out[0] ;
+  wire \user_io_out[10] ;
+  wire \user_io_out[11] ;
+  wire \user_io_out[12] ;
+  wire \user_io_out[13] ;
+  wire \user_io_out[14] ;
+  wire \user_io_out[15] ;
+  wire \user_io_out[16] ;
+  wire \user_io_out[17] ;
+  wire \user_io_out[18] ;
+  wire \user_io_out[19] ;
+  wire \user_io_out[1] ;
+  wire \user_io_out[20] ;
+  wire \user_io_out[21] ;
+  wire \user_io_out[22] ;
+  wire \user_io_out[23] ;
+  wire \user_io_out[24] ;
+  wire \user_io_out[25] ;
+  wire \user_io_out[26] ;
+  wire \user_io_out[27] ;
+  wire \user_io_out[28] ;
+  wire \user_io_out[29] ;
+  wire \user_io_out[2] ;
+  wire \user_io_out[30] ;
+  wire \user_io_out[31] ;
+  wire \user_io_out[32] ;
+  wire \user_io_out[33] ;
+  wire \user_io_out[34] ;
+  wire \user_io_out[35] ;
+  wire \user_io_out[36] ;
+  wire \user_io_out[37] ;
+  wire \user_io_out[3] ;
+  wire \user_io_out[4] ;
+  wire \user_io_out[5] ;
+  wire \user_io_out[6] ;
+  wire \user_io_out[7] ;
+  wire \user_io_out[8] ;
+  wire \user_io_out[9] ;
+  wire \user_irq[0] ;
+  wire \user_irq[1] ;
+  wire \user_irq[2] ;
+  wire \user_irq_core[0] ;
+  wire \user_irq_core[1] ;
+  wire \user_irq_core[2] ;
+  wire \user_irq_ena[0] ;
+  wire \user_irq_ena[1] ;
+  wire \user_irq_ena[2] ;
+  inout vccd;
+  inout vccd1;
+  wire vccd1_core;
+  inout vccd2;
+  wire vccd2_core;
+  wire vccd_core;
+  inout vdda;
+  inout vdda1;
+  inout vdda1_2;
+  wire vdda1_core;
+  inout vdda2;
+  wire vdda2_core;
+  wire vdda_core;
+  inout vddio;
+  inout vddio_2;
+  wire vddio_core;
+  inout vssa;
+  inout vssa1;
+  inout vssa1_2;
+  wire vssa1_core;
+  inout vssa2;
+  wire vssa2_core;
+  wire vssa_core;
+  inout vssd;
+  inout vssd1;
+  wire vssd1_core;
+  inout vssd2;
+  wire vssd2_core;
+  wire vssd_core;
+  inout vssio;
+  inout vssio_2;
+  wire vssio_core;
+  caravel_clocking clock_ctrl (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .core_clk(caravel_clk),
+    .ext_clk(clock_core_buf),
+    .ext_clk_sel(ext_clk_sel),
+    .ext_reset(ext_reset),
+    .pll_clk(pll_clk),
+    .pll_clk90(pll_clk90),
+    .resetb(rstb_l_buf),
+    .resetb_sync(caravel_rstn),
+    .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .user_clk(caravel_clk2)
+  );
+  buff_flash_clkrst flash_clkrst_buffers (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .in_n({ caravel_clk, caravel_rstn, flash_clk_frame, flash_csb_frame, flash_clk_oeb, flash_csb_oeb, flash_io0_oeb, flash_io1_oeb, flash_io0_ieb, flash_io1_ieb, flash_io0_do, flash_io1_do }),
+    .in_s({ clock_core, flash_io1_di, flash_io0_di }),
+    .out_n({ clock_core_buf, flash_io1_di_buf, flash_io0_di_buf }),
+    .out_s({ caravel_clk_buf, caravel_rstn_buf, flash_clk_frame_buf, flash_csb_frame_buf, flash_clk_oeb_buf, flash_csb_oeb_buf, flash_io0_oeb_buf, flash_io1_oeb_buf, flash_io0_ieb_buf, flash_io1_ieb_buf, flash_io0_do_buf, flash_io1_do_buf })
+  );
+  gpio_control_block \gpio_control_bidir_1[0]  (
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  }),
+    .mgmt_gpio_in(\mgmt_io_in[0] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[0] ),
+    .mgmt_gpio_out(\mgmt_io_out[0] ),
+    .one(\mprj_io_one[0] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+    .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[0] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+    .pad_gpio_in(\mprj_io_in[0] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+    .pad_gpio_out(\mprj_io_out[0] ),
+    .pad_gpio_outenb(\mprj_io_oeb[0] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+    .resetn(\gpio_resetn_1_shifted[0] ),
+    .resetn_out(\gpio_resetn_1[0] ),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_clock_out(\gpio_clock_1[0] ),
+    .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_out(\gpio_serial_link_1[0] ),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_load_out(\gpio_load_1[0] ),
+    .user_gpio_in(\user_io_in[0] ),
+    .user_gpio_oeb(\user_io_oeb[0] ),
+    .user_gpio_out(\user_io_out[0] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_1[1]  (
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  }),
+    .mgmt_gpio_in(\mgmt_io_in[1] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[1] ),
+    .mgmt_gpio_out(\mgmt_io_out[1] ),
+    .one(\mprj_io_one[1] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+    .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[1] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+    .pad_gpio_in(\mprj_io_in[1] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+    .pad_gpio_out(\mprj_io_out[1] ),
+    .pad_gpio_outenb(\mprj_io_oeb[1] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+    .resetn(\gpio_resetn_1[0] ),
+    .resetn_out(\gpio_resetn_1[1] ),
+    .serial_clock(\gpio_clock_1[0] ),
+    .serial_clock_out(\gpio_clock_1[1] ),
+    .serial_data_in(\gpio_serial_link_1[0] ),
+    .serial_data_out(\gpio_serial_link_1[1] ),
+    .serial_load(\gpio_load_1[0] ),
+    .serial_load_out(\gpio_load_1[1] ),
+    .user_gpio_in(\user_io_in[1] ),
+    .user_gpio_oeb(\user_io_oeb[1] ),
+    .user_gpio_out(\user_io_out[1] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[0]  (
+    .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  }),
+    .mgmt_gpio_in(\mgmt_io_in[35] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[35] ),
+    .mgmt_gpio_out(\mgmt_io_out[35] ),
+    .one(\mprj_io_one[35] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[35] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[35] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[35] ),
+    .pad_gpio_dm({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[35] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[35] ),
+    .pad_gpio_in(\mprj_io_in[35] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[35] ),
+    .pad_gpio_out(\mprj_io_out[35] ),
+    .pad_gpio_outenb(\mprj_io_oeb[35] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[35] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[35] ),
+    .resetn(\gpio_resetn_2[17] ),
+    .resetn_out(\gpio_resetn_2[16] ),
+    .serial_clock(\gpio_clock_2[17] ),
+    .serial_clock_out(\gpio_clock_2[16] ),
+    .serial_data_in(\gpio_serial_link_2[17] ),
+    .serial_data_out(\gpio_serial_link_2[16] ),
+    .serial_load(\gpio_load_2[17] ),
+    .serial_load_out(\gpio_load_2[16] ),
+    .user_gpio_in(\user_io_in[35] ),
+    .user_gpio_oeb(\user_io_oeb[35] ),
+    .user_gpio_out(\user_io_out[35] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[1]  (
+    .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  }),
+    .mgmt_gpio_in(\mgmt_io_in[36] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[36] ),
+    .mgmt_gpio_out(\mgmt_io_out[36] ),
+    .one(\mprj_io_one[36] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[36] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[36] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[36] ),
+    .pad_gpio_dm({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[36] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[36] ),
+    .pad_gpio_in(\mprj_io_in[36] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[36] ),
+    .pad_gpio_out(\mprj_io_out[36] ),
+    .pad_gpio_outenb(\mprj_io_oeb[36] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[36] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[36] ),
+    .resetn(\gpio_resetn_2[18] ),
+    .resetn_out(\gpio_resetn_2[17] ),
+    .serial_clock(\gpio_clock_2[18] ),
+    .serial_clock_out(\gpio_clock_2[17] ),
+    .serial_data_in(\gpio_serial_link_2[18] ),
+    .serial_data_out(\gpio_serial_link_2[17] ),
+    .serial_load(\gpio_load_2[18] ),
+    .serial_load_out(\gpio_load_2[17] ),
+    .user_gpio_in(\user_io_in[36] ),
+    .user_gpio_oeb(\user_io_oeb[36] ),
+    .user_gpio_out(\user_io_out[36] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_bidir_2[2]  (
+    .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  }),
+    .mgmt_gpio_in(\mgmt_io_in[37] ),
+    .mgmt_gpio_oeb(\mgmt_io_oeb[37] ),
+    .mgmt_gpio_out(\mgmt_io_out[37] ),
+    .one(\mprj_io_one[37] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[37] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[37] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[37] ),
+    .pad_gpio_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[37] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[37] ),
+    .pad_gpio_in(\mprj_io_in[37] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[37] ),
+    .pad_gpio_out(\mprj_io_out[37] ),
+    .pad_gpio_outenb(\mprj_io_oeb[37] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[37] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[37] ),
+    .resetn(\gpio_resetn_2_shifted[18] ),
+    .resetn_out(\gpio_resetn_2[18] ),
+    .serial_clock(\gpio_clock_2_shifted[18] ),
+    .serial_clock_out(\gpio_clock_2[18] ),
+    .serial_data_in(\gpio_serial_link_2_shifted[18] ),
+    .serial_data_out(\gpio_serial_link_2[18] ),
+    .serial_load(\gpio_load_2_shifted[18] ),
+    .serial_load_out(\gpio_load_2[18] ),
+    .user_gpio_in(\user_io_in[37] ),
+    .user_gpio_oeb(\user_io_oeb[37] ),
+    .user_gpio_out(\user_io_out[37] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[0]  (
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  }),
+    .mgmt_gpio_in(\mgmt_io_in[8] ),
+    .mgmt_gpio_oeb(\mprj_io_one[8] ),
+    .mgmt_gpio_out(\mgmt_io_out[8] ),
+    .one(\mprj_io_one[8] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+    .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[8] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+    .pad_gpio_in(\mprj_io_in[8] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+    .pad_gpio_out(\mprj_io_out[8] ),
+    .pad_gpio_outenb(\mprj_io_oeb[8] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+    .resetn(\gpio_resetn_1[7] ),
+    .resetn_out(\gpio_resetn_1[8] ),
+    .serial_clock(\gpio_clock_1[7] ),
+    .serial_clock_out(\gpio_clock_1[8] ),
+    .serial_data_in(\gpio_serial_link_1[7] ),
+    .serial_data_out(\gpio_serial_link_1[8] ),
+    .serial_load(\gpio_load_1[7] ),
+    .serial_load_out(\gpio_load_1[8] ),
+    .user_gpio_in(\user_io_in[8] ),
+    .user_gpio_oeb(\user_io_oeb[8] ),
+    .user_gpio_out(\user_io_out[8] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[10]  (
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  }),
+    .mgmt_gpio_in(\mgmt_io_in[18] ),
+    .mgmt_gpio_oeb(\mprj_io_one[18] ),
+    .mgmt_gpio_out(\mgmt_io_out[18] ),
+    .one(\mprj_io_one[18] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+    .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[18] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+    .pad_gpio_in(\mprj_io_in[18] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+    .pad_gpio_out(\mprj_io_out[18] ),
+    .pad_gpio_outenb(\mprj_io_oeb[18] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+    .resetn(\gpio_resetn_1[17] ),
+    .resetn_out(\gpio_resetn_1[18] ),
+    .serial_clock(\gpio_clock_1[17] ),
+    .serial_clock_out(\gpio_clock_1[18] ),
+    .serial_data_in(\gpio_serial_link_1[17] ),
+    .serial_data_out(\gpio_serial_link_1[18] ),
+    .serial_load(\gpio_load_1[17] ),
+    .serial_load_out(\gpio_load_1[18] ),
+    .user_gpio_in(\user_io_in[18] ),
+    .user_gpio_oeb(\user_io_oeb[18] ),
+    .user_gpio_out(\user_io_out[18] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[1]  (
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  }),
+    .mgmt_gpio_in(\mgmt_io_in[9] ),
+    .mgmt_gpio_oeb(\mprj_io_one[9] ),
+    .mgmt_gpio_out(\mgmt_io_out[9] ),
+    .one(\mprj_io_one[9] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+    .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[9] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+    .pad_gpio_in(\mprj_io_in[9] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+    .pad_gpio_out(\mprj_io_out[9] ),
+    .pad_gpio_outenb(\mprj_io_oeb[9] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+    .resetn(\gpio_resetn_1[8] ),
+    .resetn_out(\gpio_resetn_1[9] ),
+    .serial_clock(\gpio_clock_1[8] ),
+    .serial_clock_out(\gpio_clock_1[9] ),
+    .serial_data_in(\gpio_serial_link_1[8] ),
+    .serial_data_out(\gpio_serial_link_1[9] ),
+    .serial_load(\gpio_load_1[8] ),
+    .serial_load_out(\gpio_load_1[9] ),
+    .user_gpio_in(\user_io_in[9] ),
+    .user_gpio_oeb(\user_io_oeb[9] ),
+    .user_gpio_out(\user_io_out[9] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[2]  (
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  }),
+    .mgmt_gpio_in(\mgmt_io_in[10] ),
+    .mgmt_gpio_oeb(\mprj_io_one[10] ),
+    .mgmt_gpio_out(\mgmt_io_out[10] ),
+    .one(\mprj_io_one[10] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+    .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[10] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+    .pad_gpio_in(\mprj_io_in[10] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+    .pad_gpio_out(\mprj_io_out[10] ),
+    .pad_gpio_outenb(\mprj_io_oeb[10] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+    .resetn(\gpio_resetn_1[9] ),
+    .resetn_out(\gpio_resetn_1[10] ),
+    .serial_clock(\gpio_clock_1[9] ),
+    .serial_clock_out(\gpio_clock_1[10] ),
+    .serial_data_in(\gpio_serial_link_1[9] ),
+    .serial_data_out(\gpio_serial_link_1[10] ),
+    .serial_load(\gpio_load_1[9] ),
+    .serial_load_out(\gpio_load_1[10] ),
+    .user_gpio_in(\user_io_in[10] ),
+    .user_gpio_oeb(\user_io_oeb[10] ),
+    .user_gpio_out(\user_io_out[10] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[3]  (
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  }),
+    .mgmt_gpio_in(\mgmt_io_in[11] ),
+    .mgmt_gpio_oeb(\mprj_io_one[11] ),
+    .mgmt_gpio_out(\mgmt_io_out[11] ),
+    .one(\mprj_io_one[11] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+    .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[11] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+    .pad_gpio_in(\mprj_io_in[11] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+    .pad_gpio_out(\mprj_io_out[11] ),
+    .pad_gpio_outenb(\mprj_io_oeb[11] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+    .resetn(\gpio_resetn_1[10] ),
+    .resetn_out(\gpio_resetn_1[11] ),
+    .serial_clock(\gpio_clock_1[10] ),
+    .serial_clock_out(\gpio_clock_1[11] ),
+    .serial_data_in(\gpio_serial_link_1[10] ),
+    .serial_data_out(\gpio_serial_link_1[11] ),
+    .serial_load(\gpio_load_1[10] ),
+    .serial_load_out(\gpio_load_1[11] ),
+    .user_gpio_in(\user_io_in[11] ),
+    .user_gpio_oeb(\user_io_oeb[11] ),
+    .user_gpio_out(\user_io_out[11] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[4]  (
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  }),
+    .mgmt_gpio_in(\mgmt_io_in[12] ),
+    .mgmt_gpio_oeb(\mprj_io_one[12] ),
+    .mgmt_gpio_out(\mgmt_io_out[12] ),
+    .one(\mprj_io_one[12] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+    .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[12] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+    .pad_gpio_in(\mprj_io_in[12] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+    .pad_gpio_out(\mprj_io_out[12] ),
+    .pad_gpio_outenb(\mprj_io_oeb[12] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+    .resetn(\gpio_resetn_1[11] ),
+    .resetn_out(\gpio_resetn_1[12] ),
+    .serial_clock(\gpio_clock_1[11] ),
+    .serial_clock_out(\gpio_clock_1[12] ),
+    .serial_data_in(\gpio_serial_link_1[11] ),
+    .serial_data_out(\gpio_serial_link_1[12] ),
+    .serial_load(\gpio_load_1[11] ),
+    .serial_load_out(\gpio_load_1[12] ),
+    .user_gpio_in(\user_io_in[12] ),
+    .user_gpio_oeb(\user_io_oeb[12] ),
+    .user_gpio_out(\user_io_out[12] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[5]  (
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  }),
+    .mgmt_gpio_in(\mgmt_io_in[13] ),
+    .mgmt_gpio_oeb(\mprj_io_one[13] ),
+    .mgmt_gpio_out(\mgmt_io_out[13] ),
+    .one(\mprj_io_one[13] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+    .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[13] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+    .pad_gpio_in(\mprj_io_in[13] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+    .pad_gpio_out(\mprj_io_out[13] ),
+    .pad_gpio_outenb(\mprj_io_oeb[13] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+    .resetn(\gpio_resetn_1[12] ),
+    .resetn_out(\gpio_resetn_1[13] ),
+    .serial_clock(\gpio_clock_1[12] ),
+    .serial_clock_out(\gpio_clock_1[13] ),
+    .serial_data_in(\gpio_serial_link_1[12] ),
+    .serial_data_out(\gpio_serial_link_1[13] ),
+    .serial_load(\gpio_load_1[12] ),
+    .serial_load_out(\gpio_load_1[13] ),
+    .user_gpio_in(\user_io_in[13] ),
+    .user_gpio_oeb(\user_io_oeb[13] ),
+    .user_gpio_out(\user_io_out[13] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[6]  (
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  }),
+    .mgmt_gpio_in(\mgmt_io_in[14] ),
+    .mgmt_gpio_oeb(\mprj_io_one[14] ),
+    .mgmt_gpio_out(\mgmt_io_out[14] ),
+    .one(\mprj_io_one[14] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+    .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[14] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+    .pad_gpio_in(\mprj_io_in[14] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+    .pad_gpio_out(\mprj_io_out[14] ),
+    .pad_gpio_outenb(\mprj_io_oeb[14] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+    .resetn(\gpio_resetn_1[13] ),
+    .resetn_out(\gpio_resetn_1[14] ),
+    .serial_clock(\gpio_clock_1[13] ),
+    .serial_clock_out(\gpio_clock_1[14] ),
+    .serial_data_in(\gpio_serial_link_1[13] ),
+    .serial_data_out(\gpio_serial_link_1[14] ),
+    .serial_load(\gpio_load_1[13] ),
+    .serial_load_out(\gpio_load_1[14] ),
+    .user_gpio_in(\user_io_in[14] ),
+    .user_gpio_oeb(\user_io_oeb[14] ),
+    .user_gpio_out(\user_io_out[14] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[7]  (
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  }),
+    .mgmt_gpio_in(\mgmt_io_in[15] ),
+    .mgmt_gpio_oeb(\mprj_io_one[15] ),
+    .mgmt_gpio_out(\mgmt_io_out[15] ),
+    .one(\mprj_io_one[15] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+    .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[15] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+    .pad_gpio_in(\mprj_io_in[15] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+    .pad_gpio_out(\mprj_io_out[15] ),
+    .pad_gpio_outenb(\mprj_io_oeb[15] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+    .resetn(\gpio_resetn_1[14] ),
+    .resetn_out(\gpio_resetn_1[15] ),
+    .serial_clock(\gpio_clock_1[14] ),
+    .serial_clock_out(\gpio_clock_1[15] ),
+    .serial_data_in(\gpio_serial_link_1[14] ),
+    .serial_data_out(\gpio_serial_link_1[15] ),
+    .serial_load(\gpio_load_1[14] ),
+    .serial_load_out(\gpio_load_1[15] ),
+    .user_gpio_in(\user_io_in[15] ),
+    .user_gpio_oeb(\user_io_oeb[15] ),
+    .user_gpio_out(\user_io_out[15] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[8]  (
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  }),
+    .mgmt_gpio_in(\mgmt_io_in[16] ),
+    .mgmt_gpio_oeb(\mprj_io_one[16] ),
+    .mgmt_gpio_out(\mgmt_io_out[16] ),
+    .one(\mprj_io_one[16] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+    .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[16] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+    .pad_gpio_in(\mprj_io_in[16] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+    .pad_gpio_out(\mprj_io_out[16] ),
+    .pad_gpio_outenb(\mprj_io_oeb[16] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+    .resetn(\gpio_resetn_1[15] ),
+    .resetn_out(\gpio_resetn_1[16] ),
+    .serial_clock(\gpio_clock_1[15] ),
+    .serial_clock_out(\gpio_clock_1[16] ),
+    .serial_data_in(\gpio_serial_link_1[15] ),
+    .serial_data_out(\gpio_serial_link_1[16] ),
+    .serial_load(\gpio_load_1[15] ),
+    .serial_load_out(\gpio_load_1[16] ),
+    .user_gpio_in(\user_io_in[16] ),
+    .user_gpio_oeb(\user_io_oeb[16] ),
+    .user_gpio_out(\user_io_out[16] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1[9]  (
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  }),
+    .mgmt_gpio_in(\mgmt_io_in[17] ),
+    .mgmt_gpio_oeb(\mprj_io_one[17] ),
+    .mgmt_gpio_out(\mgmt_io_out[17] ),
+    .one(\mprj_io_one[17] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+    .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[17] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+    .pad_gpio_in(\mprj_io_in[17] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+    .pad_gpio_out(\mprj_io_out[17] ),
+    .pad_gpio_outenb(\mprj_io_oeb[17] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+    .resetn(\gpio_resetn_1[16] ),
+    .resetn_out(\gpio_resetn_1[17] ),
+    .serial_clock(\gpio_clock_1[16] ),
+    .serial_clock_out(\gpio_clock_1[17] ),
+    .serial_data_in(\gpio_serial_link_1[16] ),
+    .serial_data_out(\gpio_serial_link_1[17] ),
+    .serial_load(\gpio_load_1[16] ),
+    .serial_load_out(\gpio_load_1[17] ),
+    .user_gpio_in(\user_io_in[17] ),
+    .user_gpio_oeb(\user_io_oeb[17] ),
+    .user_gpio_out(\user_io_out[17] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[0]  (
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  }),
+    .mgmt_gpio_in(\mgmt_io_in[2] ),
+    .mgmt_gpio_oeb(\mprj_io_one[2] ),
+    .mgmt_gpio_out(\mgmt_io_out[2] ),
+    .one(\mprj_io_one[2] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+    .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[2] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+    .pad_gpio_in(\mprj_io_in[2] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+    .pad_gpio_out(\mprj_io_out[2] ),
+    .pad_gpio_outenb(\mprj_io_oeb[2] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+    .resetn(\gpio_resetn_1[1] ),
+    .resetn_out(\gpio_resetn_1[2] ),
+    .serial_clock(\gpio_clock_1[1] ),
+    .serial_clock_out(\gpio_clock_1[2] ),
+    .serial_data_in(\gpio_serial_link_1[1] ),
+    .serial_data_out(\gpio_serial_link_1[2] ),
+    .serial_load(\gpio_load_1[1] ),
+    .serial_load_out(\gpio_load_1[2] ),
+    .user_gpio_in(\user_io_in[2] ),
+    .user_gpio_oeb(\user_io_oeb[2] ),
+    .user_gpio_out(\user_io_out[2] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[1]  (
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  }),
+    .mgmt_gpio_in(\mgmt_io_in[3] ),
+    .mgmt_gpio_oeb(\mprj_io_one[3] ),
+    .mgmt_gpio_out(\mgmt_io_out[3] ),
+    .one(\mprj_io_one[3] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+    .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[3] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+    .pad_gpio_in(\mprj_io_in[3] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+    .pad_gpio_out(\mprj_io_out[3] ),
+    .pad_gpio_outenb(\mprj_io_oeb[3] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+    .resetn(\gpio_resetn_1[2] ),
+    .resetn_out(\gpio_resetn_1[3] ),
+    .serial_clock(\gpio_clock_1[2] ),
+    .serial_clock_out(\gpio_clock_1[3] ),
+    .serial_data_in(\gpio_serial_link_1[2] ),
+    .serial_data_out(\gpio_serial_link_1[3] ),
+    .serial_load(\gpio_load_1[2] ),
+    .serial_load_out(\gpio_load_1[3] ),
+    .user_gpio_in(\user_io_in[3] ),
+    .user_gpio_oeb(\user_io_oeb[3] ),
+    .user_gpio_out(\user_io_out[3] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[2]  (
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  }),
+    .mgmt_gpio_in(\mgmt_io_in[4] ),
+    .mgmt_gpio_oeb(\mprj_io_one[4] ),
+    .mgmt_gpio_out(\mgmt_io_out[4] ),
+    .one(\mprj_io_one[4] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+    .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[4] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+    .pad_gpio_in(\mprj_io_in[4] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+    .pad_gpio_out(\mprj_io_out[4] ),
+    .pad_gpio_outenb(\mprj_io_oeb[4] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+    .resetn(\gpio_resetn_1[3] ),
+    .resetn_out(\gpio_resetn_1[4] ),
+    .serial_clock(\gpio_clock_1[3] ),
+    .serial_clock_out(\gpio_clock_1[4] ),
+    .serial_data_in(\gpio_serial_link_1[3] ),
+    .serial_data_out(\gpio_serial_link_1[4] ),
+    .serial_load(\gpio_load_1[3] ),
+    .serial_load_out(\gpio_load_1[4] ),
+    .user_gpio_in(\user_io_in[4] ),
+    .user_gpio_oeb(\user_io_oeb[4] ),
+    .user_gpio_out(\user_io_out[4] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[3]  (
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  }),
+    .mgmt_gpio_in(\mgmt_io_in[5] ),
+    .mgmt_gpio_oeb(\mprj_io_one[5] ),
+    .mgmt_gpio_out(\mgmt_io_out[5] ),
+    .one(\mprj_io_one[5] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+    .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[5] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+    .pad_gpio_in(\mprj_io_in[5] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+    .pad_gpio_out(\mprj_io_out[5] ),
+    .pad_gpio_outenb(\mprj_io_oeb[5] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+    .resetn(\gpio_resetn_1[4] ),
+    .resetn_out(\gpio_resetn_1[5] ),
+    .serial_clock(\gpio_clock_1[4] ),
+    .serial_clock_out(\gpio_clock_1[5] ),
+    .serial_data_in(\gpio_serial_link_1[4] ),
+    .serial_data_out(\gpio_serial_link_1[5] ),
+    .serial_load(\gpio_load_1[4] ),
+    .serial_load_out(\gpio_load_1[5] ),
+    .user_gpio_in(\user_io_in[5] ),
+    .user_gpio_oeb(\user_io_oeb[5] ),
+    .user_gpio_out(\user_io_out[5] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[4]  (
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  }),
+    .mgmt_gpio_in(\mgmt_io_in[6] ),
+    .mgmt_gpio_oeb(\mprj_io_one[6] ),
+    .mgmt_gpio_out(\mgmt_io_out[6] ),
+    .one(\mprj_io_one[6] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+    .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[6] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+    .pad_gpio_in(\mprj_io_in[6] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+    .pad_gpio_out(\mprj_io_out[6] ),
+    .pad_gpio_outenb(\mprj_io_oeb[6] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+    .resetn(\gpio_resetn_1[5] ),
+    .resetn_out(\gpio_resetn_1[6] ),
+    .serial_clock(\gpio_clock_1[5] ),
+    .serial_clock_out(\gpio_clock_1[6] ),
+    .serial_data_in(\gpio_serial_link_1[5] ),
+    .serial_data_out(\gpio_serial_link_1[6] ),
+    .serial_load(\gpio_load_1[5] ),
+    .serial_load_out(\gpio_load_1[6] ),
+    .user_gpio_in(\user_io_in[6] ),
+    .user_gpio_oeb(\user_io_oeb[6] ),
+    .user_gpio_out(\user_io_out[6] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_1a[5]  (
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  }),
+    .mgmt_gpio_in(\mgmt_io_in[7] ),
+    .mgmt_gpio_oeb(\mprj_io_one[7] ),
+    .mgmt_gpio_out(\mgmt_io_out[7] ),
+    .one(\mprj_io_one[7] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+    .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[7] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+    .pad_gpio_in(\mprj_io_in[7] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+    .pad_gpio_out(\mprj_io_out[7] ),
+    .pad_gpio_outenb(\mprj_io_oeb[7] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+    .resetn(\gpio_resetn_1[6] ),
+    .resetn_out(\gpio_resetn_1[7] ),
+    .serial_clock(\gpio_clock_1[6] ),
+    .serial_clock_out(\gpio_clock_1[7] ),
+    .serial_data_in(\gpio_serial_link_1[6] ),
+    .serial_data_out(\gpio_serial_link_1[7] ),
+    .serial_load(\gpio_load_1[6] ),
+    .serial_load_out(\gpio_load_1[7] ),
+    .user_gpio_in(\user_io_in[7] ),
+    .user_gpio_oeb(\user_io_oeb[7] ),
+    .user_gpio_out(\user_io_out[7] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[0]  (
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  }),
+    .mgmt_gpio_in(\mgmt_io_in[19] ),
+    .mgmt_gpio_oeb(\mprj_io_one[19] ),
+    .mgmt_gpio_out(\mgmt_io_out[19] ),
+    .one(\mprj_io_one[19] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+    .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[19] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+    .pad_gpio_in(\mprj_io_in[19] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+    .pad_gpio_out(\mprj_io_out[19] ),
+    .pad_gpio_outenb(\mprj_io_oeb[19] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+    .resetn(\gpio_resetn_2[1] ),
+    .resetn_out(\gpio_resetn_2[0] ),
+    .serial_clock(\gpio_clock_2[1] ),
+    .serial_clock_out(\gpio_clock_2[0] ),
+    .serial_data_in(\gpio_serial_link_2[1] ),
+    .serial_data_out(\gpio_serial_link_2[0] ),
+    .serial_load(\gpio_load_2[1] ),
+    .serial_load_out(\gpio_load_2[0] ),
+    .user_gpio_in(\user_io_in[19] ),
+    .user_gpio_oeb(\user_io_oeb[19] ),
+    .user_gpio_out(\user_io_out[19] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[10]  (
+    .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  }),
+    .mgmt_gpio_in(\mgmt_io_in[29] ),
+    .mgmt_gpio_oeb(\mprj_io_one[29] ),
+    .mgmt_gpio_out(\mgmt_io_out[29] ),
+    .one(\mprj_io_one[29] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[29] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[29] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[29] ),
+    .pad_gpio_dm({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[29] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[29] ),
+    .pad_gpio_in(\mprj_io_in[29] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[29] ),
+    .pad_gpio_out(\mprj_io_out[29] ),
+    .pad_gpio_outenb(\mprj_io_oeb[29] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[29] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[29] ),
+    .resetn(\gpio_resetn_2[11] ),
+    .resetn_out(\gpio_resetn_2[10] ),
+    .serial_clock(\gpio_clock_2[11] ),
+    .serial_clock_out(\gpio_clock_2[10] ),
+    .serial_data_in(\gpio_serial_link_2[11] ),
+    .serial_data_out(\gpio_serial_link_2[10] ),
+    .serial_load(\gpio_load_2[11] ),
+    .serial_load_out(\gpio_load_2[10] ),
+    .user_gpio_in(\user_io_in[29] ),
+    .user_gpio_oeb(\user_io_oeb[29] ),
+    .user_gpio_out(\user_io_out[29] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[11]  (
+    .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  }),
+    .mgmt_gpio_in(\mgmt_io_in[30] ),
+    .mgmt_gpio_oeb(\mprj_io_one[30] ),
+    .mgmt_gpio_out(\mgmt_io_out[30] ),
+    .one(\mprj_io_one[30] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[30] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[30] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[30] ),
+    .pad_gpio_dm({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[30] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[30] ),
+    .pad_gpio_in(\mprj_io_in[30] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[30] ),
+    .pad_gpio_out(\mprj_io_out[30] ),
+    .pad_gpio_outenb(\mprj_io_oeb[30] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[30] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[30] ),
+    .resetn(\gpio_resetn_2[12] ),
+    .resetn_out(\gpio_resetn_2[11] ),
+    .serial_clock(\gpio_clock_2[12] ),
+    .serial_clock_out(\gpio_clock_2[11] ),
+    .serial_data_in(\gpio_serial_link_2[12] ),
+    .serial_data_out(\gpio_serial_link_2[11] ),
+    .serial_load(\gpio_load_2[12] ),
+    .serial_load_out(\gpio_load_2[11] ),
+    .user_gpio_in(\user_io_in[30] ),
+    .user_gpio_oeb(\user_io_oeb[30] ),
+    .user_gpio_out(\user_io_out[30] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[12]  (
+    .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  }),
+    .mgmt_gpio_in(\mgmt_io_in[31] ),
+    .mgmt_gpio_oeb(\mprj_io_one[31] ),
+    .mgmt_gpio_out(\mgmt_io_out[31] ),
+    .one(\mprj_io_one[31] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[31] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[31] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[31] ),
+    .pad_gpio_dm({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[31] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[31] ),
+    .pad_gpio_in(\mprj_io_in[31] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[31] ),
+    .pad_gpio_out(\mprj_io_out[31] ),
+    .pad_gpio_outenb(\mprj_io_oeb[31] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[31] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[31] ),
+    .resetn(\gpio_resetn_2[13] ),
+    .resetn_out(\gpio_resetn_2[12] ),
+    .serial_clock(\gpio_clock_2[13] ),
+    .serial_clock_out(\gpio_clock_2[12] ),
+    .serial_data_in(\gpio_serial_link_2[13] ),
+    .serial_data_out(\gpio_serial_link_2[12] ),
+    .serial_load(\gpio_load_2[13] ),
+    .serial_load_out(\gpio_load_2[12] ),
+    .user_gpio_in(\user_io_in[31] ),
+    .user_gpio_oeb(\user_io_oeb[31] ),
+    .user_gpio_out(\user_io_out[31] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[13]  (
+    .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  }),
+    .mgmt_gpio_in(\mgmt_io_in[32] ),
+    .mgmt_gpio_oeb(\mprj_io_one[32] ),
+    .mgmt_gpio_out(\mgmt_io_out[32] ),
+    .one(\mprj_io_one[32] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[32] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[32] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[32] ),
+    .pad_gpio_dm({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[32] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[32] ),
+    .pad_gpio_in(\mprj_io_in[32] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[32] ),
+    .pad_gpio_out(\mprj_io_out[32] ),
+    .pad_gpio_outenb(\mprj_io_oeb[32] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[32] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[32] ),
+    .resetn(\gpio_resetn_2[14] ),
+    .resetn_out(\gpio_resetn_2[13] ),
+    .serial_clock(\gpio_clock_2[14] ),
+    .serial_clock_out(\gpio_clock_2[13] ),
+    .serial_data_in(\gpio_serial_link_2[14] ),
+    .serial_data_out(\gpio_serial_link_2[13] ),
+    .serial_load(\gpio_load_2[14] ),
+    .serial_load_out(\gpio_load_2[13] ),
+    .user_gpio_in(\user_io_in[32] ),
+    .user_gpio_oeb(\user_io_oeb[32] ),
+    .user_gpio_out(\user_io_out[32] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[14]  (
+    .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  }),
+    .mgmt_gpio_in(\mgmt_io_in[33] ),
+    .mgmt_gpio_oeb(\mprj_io_one[33] ),
+    .mgmt_gpio_out(\mgmt_io_out[33] ),
+    .one(\mprj_io_one[33] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[33] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[33] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[33] ),
+    .pad_gpio_dm({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[33] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[33] ),
+    .pad_gpio_in(\mprj_io_in[33] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[33] ),
+    .pad_gpio_out(\mprj_io_out[33] ),
+    .pad_gpio_outenb(\mprj_io_oeb[33] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[33] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[33] ),
+    .resetn(\gpio_resetn_2[15] ),
+    .resetn_out(\gpio_resetn_2[14] ),
+    .serial_clock(\gpio_clock_2[15] ),
+    .serial_clock_out(\gpio_clock_2[14] ),
+    .serial_data_in(\gpio_serial_link_2[15] ),
+    .serial_data_out(\gpio_serial_link_2[14] ),
+    .serial_load(\gpio_load_2[15] ),
+    .serial_load_out(\gpio_load_2[14] ),
+    .user_gpio_in(\user_io_in[33] ),
+    .user_gpio_oeb(\user_io_oeb[33] ),
+    .user_gpio_out(\user_io_out[33] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[15]  (
+    .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  }),
+    .mgmt_gpio_in(\mgmt_io_in[34] ),
+    .mgmt_gpio_oeb(\mprj_io_one[34] ),
+    .mgmt_gpio_out(\mgmt_io_out[34] ),
+    .one(\mprj_io_one[34] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[34] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[34] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[34] ),
+    .pad_gpio_dm({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[34] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[34] ),
+    .pad_gpio_in(\mprj_io_in[34] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[34] ),
+    .pad_gpio_out(\mprj_io_out[34] ),
+    .pad_gpio_outenb(\mprj_io_oeb[34] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[34] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[34] ),
+    .resetn(\gpio_resetn_2[16] ),
+    .resetn_out(\gpio_resetn_2[15] ),
+    .serial_clock(\gpio_clock_2[16] ),
+    .serial_clock_out(\gpio_clock_2[15] ),
+    .serial_data_in(\gpio_serial_link_2[16] ),
+    .serial_data_out(\gpio_serial_link_2[15] ),
+    .serial_load(\gpio_load_2[16] ),
+    .serial_load_out(\gpio_load_2[15] ),
+    .user_gpio_in(\user_io_in[34] ),
+    .user_gpio_oeb(\user_io_oeb[34] ),
+    .user_gpio_out(\user_io_out[34] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[1]  (
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  }),
+    .mgmt_gpio_in(\mgmt_io_in[20] ),
+    .mgmt_gpio_oeb(\mprj_io_one[20] ),
+    .mgmt_gpio_out(\mgmt_io_out[20] ),
+    .one(\mprj_io_one[20] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+    .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[20] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+    .pad_gpio_in(\mprj_io_in[20] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+    .pad_gpio_out(\mprj_io_out[20] ),
+    .pad_gpio_outenb(\mprj_io_oeb[20] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+    .resetn(\gpio_resetn_2[2] ),
+    .resetn_out(\gpio_resetn_2[1] ),
+    .serial_clock(\gpio_clock_2[2] ),
+    .serial_clock_out(\gpio_clock_2[1] ),
+    .serial_data_in(\gpio_serial_link_2[2] ),
+    .serial_data_out(\gpio_serial_link_2[1] ),
+    .serial_load(\gpio_load_2[2] ),
+    .serial_load_out(\gpio_load_2[1] ),
+    .user_gpio_in(\user_io_in[20] ),
+    .user_gpio_oeb(\user_io_oeb[20] ),
+    .user_gpio_out(\user_io_out[20] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[2]  (
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  }),
+    .mgmt_gpio_in(\mgmt_io_in[21] ),
+    .mgmt_gpio_oeb(\mprj_io_one[21] ),
+    .mgmt_gpio_out(\mgmt_io_out[21] ),
+    .one(\mprj_io_one[21] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+    .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[21] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+    .pad_gpio_in(\mprj_io_in[21] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+    .pad_gpio_out(\mprj_io_out[21] ),
+    .pad_gpio_outenb(\mprj_io_oeb[21] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+    .resetn(\gpio_resetn_2[3] ),
+    .resetn_out(\gpio_resetn_2[2] ),
+    .serial_clock(\gpio_clock_2[3] ),
+    .serial_clock_out(\gpio_clock_2[2] ),
+    .serial_data_in(\gpio_serial_link_2[3] ),
+    .serial_data_out(\gpio_serial_link_2[2] ),
+    .serial_load(\gpio_load_2[3] ),
+    .serial_load_out(\gpio_load_2[2] ),
+    .user_gpio_in(\user_io_in[21] ),
+    .user_gpio_oeb(\user_io_oeb[21] ),
+    .user_gpio_out(\user_io_out[21] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[3]  (
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  }),
+    .mgmt_gpio_in(\mgmt_io_in[22] ),
+    .mgmt_gpio_oeb(\mprj_io_one[22] ),
+    .mgmt_gpio_out(\mgmt_io_out[22] ),
+    .one(\mprj_io_one[22] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+    .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[22] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+    .pad_gpio_in(\mprj_io_in[22] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+    .pad_gpio_out(\mprj_io_out[22] ),
+    .pad_gpio_outenb(\mprj_io_oeb[22] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+    .resetn(\gpio_resetn_2[4] ),
+    .resetn_out(\gpio_resetn_2[3] ),
+    .serial_clock(\gpio_clock_2[4] ),
+    .serial_clock_out(\gpio_clock_2[3] ),
+    .serial_data_in(\gpio_serial_link_2[4] ),
+    .serial_data_out(\gpio_serial_link_2[3] ),
+    .serial_load(\gpio_load_2[4] ),
+    .serial_load_out(\gpio_load_2[3] ),
+    .user_gpio_in(\user_io_in[22] ),
+    .user_gpio_oeb(\user_io_oeb[22] ),
+    .user_gpio_out(\user_io_out[22] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[4]  (
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  }),
+    .mgmt_gpio_in(\mgmt_io_in[23] ),
+    .mgmt_gpio_oeb(\mprj_io_one[23] ),
+    .mgmt_gpio_out(\mgmt_io_out[23] ),
+    .one(\mprj_io_one[23] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+    .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[23] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+    .pad_gpio_in(\mprj_io_in[23] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+    .pad_gpio_out(\mprj_io_out[23] ),
+    .pad_gpio_outenb(\mprj_io_oeb[23] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+    .resetn(\gpio_resetn_2[5] ),
+    .resetn_out(\gpio_resetn_2[4] ),
+    .serial_clock(\gpio_clock_2[5] ),
+    .serial_clock_out(\gpio_clock_2[4] ),
+    .serial_data_in(\gpio_serial_link_2[5] ),
+    .serial_data_out(\gpio_serial_link_2[4] ),
+    .serial_load(\gpio_load_2[5] ),
+    .serial_load_out(\gpio_load_2[4] ),
+    .user_gpio_in(\user_io_in[23] ),
+    .user_gpio_oeb(\user_io_oeb[23] ),
+    .user_gpio_out(\user_io_out[23] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[5]  (
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  }),
+    .mgmt_gpio_in(\mgmt_io_in[24] ),
+    .mgmt_gpio_oeb(\mprj_io_one[24] ),
+    .mgmt_gpio_out(\mgmt_io_out[24] ),
+    .one(\mprj_io_one[24] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+    .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[24] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+    .pad_gpio_in(\mprj_io_in[24] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+    .pad_gpio_out(\mprj_io_out[24] ),
+    .pad_gpio_outenb(\mprj_io_oeb[24] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+    .resetn(\gpio_resetn_2[6] ),
+    .resetn_out(\gpio_resetn_2[5] ),
+    .serial_clock(\gpio_clock_2[6] ),
+    .serial_clock_out(\gpio_clock_2[5] ),
+    .serial_data_in(\gpio_serial_link_2[6] ),
+    .serial_data_out(\gpio_serial_link_2[5] ),
+    .serial_load(\gpio_load_2[6] ),
+    .serial_load_out(\gpio_load_2[5] ),
+    .user_gpio_in(\user_io_in[24] ),
+    .user_gpio_oeb(\user_io_oeb[24] ),
+    .user_gpio_out(\user_io_out[24] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[6]  (
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  }),
+    .mgmt_gpio_in(\mgmt_io_in[25] ),
+    .mgmt_gpio_oeb(\mprj_io_one[25] ),
+    .mgmt_gpio_out(\mgmt_io_out[25] ),
+    .one(\mprj_io_one[25] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+    .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[25] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+    .pad_gpio_in(\mprj_io_in[25] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+    .pad_gpio_out(\mprj_io_out[25] ),
+    .pad_gpio_outenb(\mprj_io_oeb[25] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+    .resetn(\gpio_resetn_2[7] ),
+    .resetn_out(\gpio_resetn_2[6] ),
+    .serial_clock(\gpio_clock_2[7] ),
+    .serial_clock_out(\gpio_clock_2[6] ),
+    .serial_data_in(\gpio_serial_link_2[7] ),
+    .serial_data_out(\gpio_serial_link_2[6] ),
+    .serial_load(\gpio_load_2[7] ),
+    .serial_load_out(\gpio_load_2[6] ),
+    .user_gpio_in(\user_io_in[25] ),
+    .user_gpio_oeb(\user_io_oeb[25] ),
+    .user_gpio_out(\user_io_out[25] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[7]  (
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  }),
+    .mgmt_gpio_in(\mgmt_io_in[26] ),
+    .mgmt_gpio_oeb(\mprj_io_one[26] ),
+    .mgmt_gpio_out(\mgmt_io_out[26] ),
+    .one(\mprj_io_one[26] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+    .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[26] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+    .pad_gpio_in(\mprj_io_in[26] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+    .pad_gpio_out(\mprj_io_out[26] ),
+    .pad_gpio_outenb(\mprj_io_oeb[26] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+    .resetn(\gpio_resetn_2[8] ),
+    .resetn_out(\gpio_resetn_2[7] ),
+    .serial_clock(\gpio_clock_2[8] ),
+    .serial_clock_out(\gpio_clock_2[7] ),
+    .serial_data_in(\gpio_serial_link_2[8] ),
+    .serial_data_out(\gpio_serial_link_2[7] ),
+    .serial_load(\gpio_load_2[8] ),
+    .serial_load_out(\gpio_load_2[7] ),
+    .user_gpio_in(\user_io_in[26] ),
+    .user_gpio_oeb(\user_io_oeb[26] ),
+    .user_gpio_out(\user_io_out[26] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[8]  (
+    .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  }),
+    .mgmt_gpio_in(\mgmt_io_in[27] ),
+    .mgmt_gpio_oeb(\mprj_io_one[27] ),
+    .mgmt_gpio_out(\mgmt_io_out[27] ),
+    .one(\mprj_io_one[27] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[27] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[27] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[27] ),
+    .pad_gpio_dm({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[27] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[27] ),
+    .pad_gpio_in(\mprj_io_in[27] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[27] ),
+    .pad_gpio_out(\mprj_io_out[27] ),
+    .pad_gpio_outenb(\mprj_io_oeb[27] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[27] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[27] ),
+    .resetn(\gpio_resetn_2[9] ),
+    .resetn_out(\gpio_resetn_2[8] ),
+    .serial_clock(\gpio_clock_2[9] ),
+    .serial_clock_out(\gpio_clock_2[8] ),
+    .serial_data_in(\gpio_serial_link_2[9] ),
+    .serial_data_out(\gpio_serial_link_2[8] ),
+    .serial_load(\gpio_load_2[9] ),
+    .serial_load_out(\gpio_load_2[8] ),
+    .user_gpio_in(\user_io_in[27] ),
+    .user_gpio_oeb(\user_io_oeb[27] ),
+    .user_gpio_out(\user_io_out[27] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_control_block \gpio_control_in_2[9]  (
+    .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  }),
+    .mgmt_gpio_in(\mgmt_io_in[28] ),
+    .mgmt_gpio_oeb(\mprj_io_one[28] ),
+    .mgmt_gpio_out(\mgmt_io_out[28] ),
+    .one(\mprj_io_one[28] ),
+    .pad_gpio_ana_en(\mprj_io_analog_en[28] ),
+    .pad_gpio_ana_pol(\mprj_io_analog_pol[28] ),
+    .pad_gpio_ana_sel(\mprj_io_analog_sel[28] ),
+    .pad_gpio_dm({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84]  }),
+    .pad_gpio_holdover(\mprj_io_holdover[28] ),
+    .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[28] ),
+    .pad_gpio_in(\mprj_io_in[28] ),
+    .pad_gpio_inenb(\mprj_io_inp_dis[28] ),
+    .pad_gpio_out(\mprj_io_out[28] ),
+    .pad_gpio_outenb(\mprj_io_oeb[28] ),
+    .pad_gpio_slow_sel(\mprj_io_slow_sel[28] ),
+    .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[28] ),
+    .resetn(\gpio_resetn_2[10] ),
+    .resetn_out(\gpio_resetn_2[9] ),
+    .serial_clock(\gpio_clock_2[10] ),
+    .serial_clock_out(\gpio_clock_2[9] ),
+    .serial_data_in(\gpio_serial_link_2[10] ),
+    .serial_data_out(\gpio_serial_link_2[9] ),
+    .serial_load(\gpio_load_2[10] ),
+    .serial_load_out(\gpio_load_2[9] ),
+    .user_gpio_in(\user_io_in[28] ),
+    .user_gpio_oeb(\user_io_oeb[28] ),
+    .user_gpio_out(\user_io_out[28] ),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .zero()
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_0 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0]  })
+  );
+  gpio_defaults_block_1803 gpio_defaults_block_1 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_10 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_11 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_12 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_13 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_14 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_15 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_16 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_17 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_18 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_19 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_2 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_20 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_21 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_22 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_23 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_24 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_25 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_26 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_27 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_28 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_29 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  })
+  );
+  gpio_defaults_block_0801 gpio_defaults_block_3 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_30 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_31 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_32 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_33 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_34 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_35 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_36 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_37 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  })
+  );
+  gpio_defaults_block_0403 gpio_defaults_block_4 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_5 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_6 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_7 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_8 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  })
+  );
+  gpio_defaults_block_1800 gpio_defaults_block_9 (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  })
+  );
+  housekeeping housekeeping (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0]  }),
+    .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  }),
+    .mgmt_gpio_in({ \mgmt_io_in_hk[37] , \mgmt_io_in_hk[36] , \mgmt_io_in_hk[35] , \mgmt_io_in_hk[34] , \mgmt_io_in_hk[33] , \mgmt_io_in_hk[32] , \mgmt_io_in_hk[31] , \mgmt_io_in_hk[30] , \mgmt_io_in_hk[29] , \mgmt_io_in_hk[28] , \mgmt_io_in_hk[27] , \mgmt_io_in_hk[26] , \mgmt_io_in_hk[25] , \mgmt_io_in_hk[24] , \mgmt_io_in_hk[23] , \mgmt_io_in_hk[22] , \mgmt_io_in_hk[21] , \mgmt_io_in_hk[20] , \mgmt_io_in_hk[19] , \mgmt_io_in_hk[18] , \mgmt_io_in_hk[17] , \mgmt_io_in_hk[16] , \mgmt_io_in_hk[15] , \mgmt_io_in_hk[14] , \mgmt_io_in_hk[13] , \mgmt_io_in_hk[12] , \mgmt_io_in_hk[11] , \mgmt_io_in_hk[10] , \mgmt_io_in_hk[9] , \mgmt_io_in_hk[8] , \mgmt_io_in_hk[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0]  }),
+    .mgmt_gpio_oeb({ \mgmt_io_oeb_hk[37] , \mgmt_io_oeb_hk[36] , \mgmt_io_oeb_hk[35] , \mgmt_io_oeb[34] , \mgmt_io_oeb[33] , \mgmt_io_oeb[32] , \mgmt_io_oeb[31] , \mgmt_io_oeb[30] , \mgmt_io_oeb[29] , \mgmt_io_oeb[28] , \mgmt_io_oeb[27] , \mgmt_io_oeb[26] , \mgmt_io_oeb[25] , \mgmt_io_oeb[24] , \mgmt_io_oeb[23] , \mgmt_io_oeb[22] , \mgmt_io_oeb[21] , \mgmt_io_oeb[20] , \mgmt_io_oeb[19] , \mgmt_io_oeb[18] , \mgmt_io_oeb[17] , \mgmt_io_oeb[16] , \mgmt_io_oeb[15] , \mgmt_io_oeb[14] , \mgmt_io_oeb[13] , \mgmt_io_oeb[12] , \mgmt_io_oeb[11] , \mgmt_io_oeb[10] , \mgmt_io_oeb[9] , \mgmt_io_oeb[8] , \mgmt_io_oeb[7] , \mgmt_io_oeb[6] , \mgmt_io_oeb[5] , \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0]  }),
+    .mgmt_gpio_out({ \mgmt_io_out_hk[37] , \mgmt_io_out_hk[36] , \mgmt_io_out_hk[35] , \mgmt_io_out_hk[34] , \mgmt_io_out_hk[33] , \mgmt_io_out_hk[32] , \mgmt_io_out_hk[31] , \mgmt_io_out_hk[30] , \mgmt_io_out_hk[29] , \mgmt_io_out_hk[28] , \mgmt_io_out_hk[27] , \mgmt_io_out_hk[26] , \mgmt_io_out_hk[25] , \mgmt_io_out_hk[24] , \mgmt_io_out_hk[23] , \mgmt_io_out_hk[22] , \mgmt_io_out_hk[21] , \mgmt_io_out_hk[20] , \mgmt_io_out_hk[19] , \mgmt_io_out_hk[18] , \mgmt_io_out_hk[17] , \mgmt_io_out_hk[16] , \mgmt_io_out_hk[15] , \mgmt_io_out_hk[14] , \mgmt_io_out_hk[13] , \mgmt_io_out_hk[12] , \mgmt_io_out_hk[11] , \mgmt_io_out_hk[10] , \mgmt_io_out_hk[9] , \mgmt_io_out_hk[8] , \mgmt_io_out_hk[7] , \mgmt_io_out[6] , \mgmt_io_out[5] , \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_out[1] , \mgmt_io_out[0]  }),
+    .pad_flash_clk(flash_clk_frame),
+    .pad_flash_clk_oeb(flash_clk_oeb),
+    .pad_flash_csb(flash_csb_frame),
+    .pad_flash_csb_oeb(flash_csb_oeb),
+    .pad_flash_io0_di(flash_io0_di_buf),
+    .pad_flash_io0_do(flash_io0_do),
+    .pad_flash_io0_ieb(flash_io0_ieb),
+    .pad_flash_io0_oeb(flash_io0_oeb),
+    .pad_flash_io1_di(flash_io1_di_buf),
+    .pad_flash_io1_do(flash_io1_do),
+    .pad_flash_io1_ieb(flash_io1_ieb),
+    .pad_flash_io1_oeb(flash_io1_oeb),
+    .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0]  }),
+    .pll_bypass(ext_clk_sel),
+    .pll_dco_ena(spi_pll_dco_ena),
+    .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .pll_ena(spi_pll_ena),
+    .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0]  }),
+    .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .porb(porb_l),
+    .pwr_ctrl_out({ \pwr_ctrl_nc[3] , \pwr_ctrl_nc[2] , \pwr_ctrl_nc[1] , \pwr_ctrl_nc[0]  }),
+    .qspi_enabled(qspi_enabled),
+    .reset(ext_reset),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .serial_clock(\gpio_clock_1_shifted[0] ),
+    .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+    .serial_data_2(mprj_io_loader_data_2),
+    .serial_load(\gpio_load_1_shifted[0] ),
+    .serial_resetn(\gpio_resetn_1_shifted[0] ),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .spimemio_flash_clk(flash_clk_core),
+    .spimemio_flash_csb(flash_csb_core),
+    .spimemio_flash_io0_di(flash_io0_di_core),
+    .spimemio_flash_io0_do(flash_io0_do_core),
+    .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+    .spimemio_flash_io1_di(flash_io1_di_core),
+    .spimemio_flash_io1_do(flash_io1_do_core),
+    .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+    .spimemio_flash_io2_di(flash_io2_di_core),
+    .spimemio_flash_io2_do(flash_io2_do_core),
+    .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+    .spimemio_flash_io3_di(flash_io3_di_core),
+    .spimemio_flash_io3_do(flash_io3_do_core),
+    .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_clock(caravel_clk2),
+    .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+    .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+    .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+    .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+    .wb_ack_o(hk_ack_i),
+    .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .wb_clk_i(caravel_clk),
+    .wb_cyc_i(hk_cyc_o),
+    .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .wb_rstn_i(caravel_rstn),
+    .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .wb_stb_i(hk_stb_o),
+    .wb_we_i(mprj_we_o_core)
+  );
+  mgmt_protect mgmt_buffers (
+    .caravel_clk(clk_passthru),
+    .caravel_clk2(caravel_clk2),
+    .caravel_rstn(resetn_passthru),
+    .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .mprj_ack_i_core(mprj_ack_i_core),
+    .mprj_ack_i_user(mprj_ack_i_user),
+    .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .mprj_cyc_o_core(mprj_cyc_o_core),
+    .mprj_cyc_o_user(mprj_cyc_o_user),
+    .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .mprj_iena_wb(mprj_iena_wb),
+    .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .mprj_stb_o_core(mprj_stb_o_core),
+    .mprj_stb_o_user(mprj_stb_o_user),
+    .mprj_we_o_core(mprj_we_o_core),
+    .mprj_we_o_user(mprj_we_o_user),
+    .user1_vcc_powergood(mprj_vcc_pwrgood),
+    .user1_vdd_powergood(mprj_vdd_pwrgood),
+    .user2_vcc_powergood(mprj2_vcc_pwrgood),
+    .user2_vdd_powergood(mprj2_vdd_pwrgood),
+    .user_clock(mprj_clock),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  }),
+    .user_reset(mprj_reset),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core)
+  );
+  user_project_wrapper mprj (
+    .analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0]  }),
+    .io_in({ \user_io_in[37] , \user_io_in[36] , \user_io_in[35] , \user_io_in[34] , \user_io_in[33] , \user_io_in[32] , \user_io_in[31] , \user_io_in[30] , \user_io_in[29] , \user_io_in[28] , \user_io_in[27] , \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0]  }),
+    .io_oeb({ \user_io_oeb[37] , \user_io_oeb[36] , \user_io_oeb[35] , \user_io_oeb[34] , \user_io_oeb[33] , \user_io_oeb[32] , \user_io_oeb[31] , \user_io_oeb[30] , \user_io_oeb[29] , \user_io_oeb[28] , \user_io_oeb[27] , \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0]  }),
+    .io_out({ \user_io_out[37] , \user_io_out[36] , \user_io_out[35] , \user_io_out[34] , \user_io_out[33] , \user_io_out[32] , \user_io_out[31] , \user_io_out[30] , \user_io_out[29] , \user_io_out[28] , \user_io_out[27] , \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0]  }),
+    .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0]  }),
+    .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0]  }),
+    .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0]  }),
+    .user_clock2(mprj_clock2),
+    .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0]  }),
+    .vccd1(vccd1_core),
+    .vccd2(vccd2_core),
+    .vdda1(vdda1_core),
+    .vdda2(vdda2_core),
+    .vssa1(vssa1_core),
+    .vssa2(vssa2_core),
+    .vssd1(vssd1_core),
+    .vssd2(vssd2_core),
+    .wb_clk_i(mprj_clock),
+    .wb_rst_i(mprj_reset),
+    .wbs_ack_o(mprj_ack_i_user),
+    .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0]  }),
+    .wbs_cyc_i(mprj_cyc_o_user),
+    .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0]  }),
+    .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0]  }),
+    .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0]  }),
+    .wbs_stb_i(mprj_stb_o_user),
+    .wbs_we_i(mprj_we_o_user)
+  );
+  chip_io padframe (
+    .clock(clock),
+    .clock_core(clock_core),
+    .flash_clk(flash_clk),
+    .flash_clk_core(flash_clk_frame_buf),
+    .flash_clk_oeb_core(flash_clk_oeb_buf),
+    .flash_csb(flash_csb),
+    .flash_csb_core(flash_csb_frame_buf),
+    .flash_csb_oeb_core(flash_csb_oeb_buf),
+    .flash_io0(flash_io0),
+    .flash_io0_di_core(flash_io0_di),
+    .flash_io0_do_core(flash_io0_do_buf),
+    .flash_io0_ieb_core(flash_io0_ieb_buf),
+    .flash_io0_oeb_core(flash_io0_oeb_buf),
+    .flash_io1(flash_io1),
+    .flash_io1_di_core(flash_io1_di),
+    .flash_io1_do_core(flash_io1_do_buf),
+    .flash_io1_ieb_core(flash_io1_ieb_buf),
+    .flash_io1_oeb_core(flash_io1_oeb_buf),
+    .gpio(gpio),
+    .gpio_in_core(gpio_in_core),
+    .gpio_inenb_core(gpio_inenb_core),
+    .gpio_mode0_core(gpio_mode0_core),
+    .gpio_mode1_core(gpio_mode1_core),
+    .gpio_out_core(gpio_out_core),
+    .gpio_outenb_core(gpio_outenb_core),
+    .mprj_analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0]  }),
+    .mprj_io(mprj_io),
+    .mprj_io_analog_en({ \mprj_io_analog_en[37] , \mprj_io_analog_en[36] , \mprj_io_analog_en[35] , \mprj_io_analog_en[34] , \mprj_io_analog_en[33] , \mprj_io_analog_en[32] , \mprj_io_analog_en[31] , \mprj_io_analog_en[30] , \mprj_io_analog_en[29] , \mprj_io_analog_en[28] , \mprj_io_analog_en[27] , \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0]  }),
+    .mprj_io_analog_pol({ \mprj_io_analog_pol[37] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0]  }),
+    .mprj_io_analog_sel({ \mprj_io_analog_sel[37] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0]  }),
+    .mprj_io_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] , \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] , \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] , \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] , \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] , \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] , \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] , \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] , \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] , \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] , \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] , \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .mprj_io_holdover({ \mprj_io_holdover[37] , \mprj_io_holdover[36] , \mprj_io_holdover[35] , \mprj_io_holdover[34] , \mprj_io_holdover[33] , \mprj_io_holdover[32] , \mprj_io_holdover[31] , \mprj_io_holdover[30] , \mprj_io_holdover[29] , \mprj_io_holdover[28] , \mprj_io_holdover[27] , \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0]  }),
+    .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[37] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0]  }),
+    .mprj_io_in({ \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0]  }),
+    .mprj_io_inp_dis({ \mprj_io_inp_dis[37] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0]  }),
+    .mprj_io_oeb({ \mprj_io_oeb[37] , \mprj_io_oeb[36] , \mprj_io_oeb[35] , \mprj_io_oeb[34] , \mprj_io_oeb[33] , \mprj_io_oeb[32] , \mprj_io_oeb[31] , \mprj_io_oeb[30] , \mprj_io_oeb[29] , \mprj_io_oeb[28] , \mprj_io_oeb[27] , \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0]  }),
+    .mprj_io_one({ \mprj_io_one[37] , \mprj_io_one[36] , \mprj_io_one[35] , \mprj_io_one[34] , \mprj_io_one[33] , \mprj_io_one[32] , \mprj_io_one[31] , \mprj_io_one[30] , \mprj_io_one[29] , \mprj_io_one[28] , \mprj_io_one[27] , \mprj_io_one[26] , \mprj_io_one[25] , \mprj_io_one[24] , \mprj_io_one[23] , \mprj_io_one[22] , \mprj_io_one[21] , \mprj_io_one[20] , \mprj_io_one[19] , \mprj_io_one[18] , \mprj_io_one[17] , \mprj_io_one[16] , \mprj_io_one[15] , \mprj_io_one[14] , \mprj_io_one[13] , \mprj_io_one[12] , \mprj_io_one[11] , \mprj_io_one[10] , \mprj_io_one[9] , \mprj_io_one[8] , \mprj_io_one[7] , \mprj_io_one[6] , \mprj_io_one[5] , \mprj_io_one[4] , \mprj_io_one[3] , \mprj_io_one[2] , \mprj_io_one[1] , \mprj_io_one[0]  }),
+    .mprj_io_out({ \mprj_io_out[37] , \mprj_io_out[36] , \mprj_io_out[35] , \mprj_io_out[34] , \mprj_io_out[33] , \mprj_io_out[32] , \mprj_io_out[31] , \mprj_io_out[30] , \mprj_io_out[29] , \mprj_io_out[28] , \mprj_io_out[27] , \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0]  }),
+    .mprj_io_slow_sel({ \mprj_io_slow_sel[37] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0]  }),
+    .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[37] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0]  }),
+    .por(por_l_buf),
+    .porb_h(porb_h),
+    .resetb(resetb),
+    .resetb_core_h(rstb_h),
+    .vccd(vccd_core),
+    .vccd1(vccd1_core),
+    .vccd1_pad(vccd1),
+    .vccd2(vccd2_core),
+    .vccd2_pad(vccd2),
+    .vccd_pad(vccd),
+    .vdda(vdda_core),
+    .vdda1(vdda1_core),
+    .vdda1_pad(vdda1),
+    .vdda1_pad2(vdda1_2),
+    .vdda2(vdda2_core),
+    .vdda2_pad(vdda2),
+    .vdda_pad(vdda),
+    .vddio(vddio_core),
+    .vddio_pad(vddio),
+    .vddio_pad2(vddio_2),
+    .vssa(vssa_core),
+    .vssa1(vssa1_core),
+    .vssa1_pad(vssa1),
+    .vssa1_pad2(vssa1_2),
+    .vssa2(vssa2_core),
+    .vssa2_pad(vssa2),
+    .vssa_pad(vssa),
+    .vssd(vssd_core),
+    .vssd1(vssd1_core),
+    .vssd1_pad(vssd1),
+    .vssd2(vssd2_core),
+    .vssd2_pad(vssd2),
+    .vssd_pad(vssd),
+    .vssio(vssio_core),
+    .vssio_pad(vssio),
+    .vssio_pad2(vssio_2)
+  );
+  digital_pll pll (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .clockp({ pll_clk, pll_clk90 }),
+    .dco(spi_pll_dco_ena),
+    .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0]  }),
+    .enable(spi_pll_ena),
+    .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0]  }),
+    .osc(clock_core_buf),
+    .resetb(rstb_l_buf)
+  );
+  simple_por por (
+    .por_l(por_l),
+    .porb_h(porb_h),
+    .porb_l(porb_l),
+    .vdd1v8(vccd_core),
+    .vdd3v3(vddio_core),
+    .vss1v8(vssd_core),
+    .vss3v3(vssio_core)
+  );
+  xres_buf rstb_level (
+    .A(rstb_h),
+    .LVGND(vssd_core),
+    .LVPWR(vccd_core),
+    .VGND(vssio_core),
+    .VPWR(vddio_core),
+    .X(rstb_l)
+  );
+  gpio_signal_buffering sigbuf (
+    .mgmt_io_in_buf({ \mgmt_io_in_hk[37] , \mgmt_io_in_hk[36] , \mgmt_io_in_hk[35] , \mgmt_io_in_hk[34] , \mgmt_io_in_hk[33] , \mgmt_io_in_hk[32] , \mgmt_io_in_hk[31] , \mgmt_io_in_hk[30] , \mgmt_io_in_hk[29] , \mgmt_io_in_hk[28] , \mgmt_io_in_hk[27] , \mgmt_io_in_hk[26] , \mgmt_io_in_hk[25] , \mgmt_io_in_hk[24] , \mgmt_io_in_hk[23] , \mgmt_io_in_hk[22] , \mgmt_io_in_hk[21] , \mgmt_io_in_hk[20] , \mgmt_io_in_hk[19] , \mgmt_io_in_hk[18] , \mgmt_io_in_hk[17] , \mgmt_io_in_hk[16] , \mgmt_io_in_hk[15] , \mgmt_io_in_hk[14] , \mgmt_io_in_hk[13] , \mgmt_io_in_hk[12] , \mgmt_io_in_hk[11] , \mgmt_io_in_hk[10] , \mgmt_io_in_hk[9] , \mgmt_io_in_hk[8] , \mgmt_io_in_hk[7]  }),
+    .mgmt_io_in_unbuf({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7]  }),
+    .mgmt_io_oeb_buf({ \mgmt_io_oeb[37] , \mgmt_io_oeb[36] , \mgmt_io_oeb[35]  }),
+    .mgmt_io_oeb_unbuf({ \mgmt_io_oeb_hk[37] , \mgmt_io_oeb_hk[36] , \mgmt_io_oeb_hk[35]  }),
+    .mgmt_io_out_buf({ \mgmt_io_out[37] , \mgmt_io_out[36] , \mgmt_io_out[35] , \mgmt_io_out[34] , \mgmt_io_out[33] , \mgmt_io_out[32] , \mgmt_io_out[31] , \mgmt_io_out[30] , \mgmt_io_out[29] , \mgmt_io_out[28] , \mgmt_io_out[27] , \mgmt_io_out[26] , \mgmt_io_out[25] , \mgmt_io_out[24] , \mgmt_io_out[23] , \mgmt_io_out[22] , \mgmt_io_out[21] , \mgmt_io_out[20] , \mgmt_io_out[19] , \mgmt_io_out[18] , \mgmt_io_out[17] , \mgmt_io_out[16] , \mgmt_io_out[15] , \mgmt_io_out[14] , \mgmt_io_out[13] , \mgmt_io_out[12] , \mgmt_io_out[11] , \mgmt_io_out[10] , \mgmt_io_out[9] , \mgmt_io_out[8] , \mgmt_io_out[7]  }),
+    .mgmt_io_out_unbuf({ \mgmt_io_out_hk[37] , \mgmt_io_out_hk[36] , \mgmt_io_out_hk[35] , \mgmt_io_out_hk[34] , \mgmt_io_out_hk[33] , \mgmt_io_out_hk[32] , \mgmt_io_out_hk[31] , \mgmt_io_out_hk[30] , \mgmt_io_out_hk[29] , \mgmt_io_out_hk[28] , \mgmt_io_out_hk[27] , \mgmt_io_out_hk[26] , \mgmt_io_out_hk[25] , \mgmt_io_out_hk[24] , \mgmt_io_out_hk[23] , \mgmt_io_out_hk[22] , \mgmt_io_out_hk[21] , \mgmt_io_out_hk[20] , \mgmt_io_out_hk[19] , \mgmt_io_out_hk[18] , \mgmt_io_out_hk[17] , \mgmt_io_out_hk[16] , \mgmt_io_out_hk[15] , \mgmt_io_out_hk[14] , \mgmt_io_out_hk[13] , \mgmt_io_out_hk[12] , \mgmt_io_out_hk[11] , \mgmt_io_out_hk[10] , \mgmt_io_out_hk[9] , \mgmt_io_out_hk[8] , \mgmt_io_out_hk[7]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  mgmt_core_wrapper soc (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .clk_in(caravel_clk_buf),
+    .clk_out(clk_passthru),
+    .core_clk(caravel_clk_buf),
+    .core_rstn(caravel_rstn_buf),
+    .debug_in(debug_in),
+    .debug_mode(debug_mode),
+    .debug_oeb(debug_oeb),
+    .debug_out(debug_out),
+    .flash_clk(flash_clk_core),
+    .flash_csb(flash_csb_core),
+    .flash_io0_di(flash_io0_di_core),
+    .flash_io0_do(flash_io0_do_core),
+    .flash_io0_oeb(flash_io0_oeb_core),
+    .flash_io1_di(flash_io1_di_core),
+    .flash_io1_do(flash_io1_do_core),
+    .flash_io1_oeb(flash_io1_oeb_core),
+    .flash_io2_di(flash_io2_di_core),
+    .flash_io2_do(flash_io2_do_core),
+    .flash_io2_oeb(flash_io2_oeb_core),
+    .flash_io3_di(flash_io3_di_core),
+    .flash_io3_do(flash_io3_do_core),
+    .flash_io3_oeb(flash_io3_oeb_core),
+    .gpio_in_pad(gpio_in_core),
+    .gpio_inenb_pad(gpio_inenb_core),
+    .gpio_mode0_pad(gpio_mode0_core),
+    .gpio_mode1_pad(gpio_mode1_core),
+    .gpio_out_pad(gpio_out_core),
+    .gpio_outenb_pad(gpio_outenb_core),
+    .hk_ack_i(hk_ack_i),
+    .hk_cyc_o(hk_cyc_o),
+    .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0]  }),
+    .hk_stb_o(hk_stb_o),
+    .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0]  }),
+    .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0]  }),
+    .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0]  }),
+    .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0]  }),
+    .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0]  }),
+    .mprj_ack_i(mprj_ack_i_core),
+    .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0]  }),
+    .mprj_cyc_o(mprj_cyc_o_core),
+    .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0]  }),
+    .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0]  }),
+    .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0]  }),
+    .mprj_stb_o(mprj_stb_o_core),
+    .mprj_wb_iena(mprj_iena_wb),
+    .mprj_we_o(mprj_we_o_core),
+    .por_l_in(por_l),
+    .por_l_out(por_l_buf),
+    .porb_h_in(por_l),
+    .porb_h_out(porb_h_out_nc),
+    .qspi_enabled(qspi_enabled),
+    .resetn_in(caravel_rstn_buf),
+    .resetn_out(resetn_passthru),
+    .rstb_l_in(rstb_l),
+    .rstb_l_out(rstb_l_buf),
+    .ser_rx(ser_rx),
+    .ser_tx(ser_tx),
+    .serial_clock_in(\gpio_clock_1_shifted[0] ),
+    .serial_clock_out(\gpio_clock_2_shifted[18] ),
+    .serial_data_2_in(mprj_io_loader_data_2),
+    .serial_data_2_out(\gpio_serial_link_2_shifted[18] ),
+    .serial_load_in(\gpio_load_1_shifted[0] ),
+    .serial_load_out(\gpio_load_2_shifted[18] ),
+    .serial_resetn_in(\gpio_resetn_1_shifted[0] ),
+    .serial_resetn_out(\gpio_resetn_2_shifted[18] ),
+    .spi_csb(spi_csb),
+    .spi_enabled(spi_enabled),
+    .spi_sck(spi_sck),
+    .spi_sdi(spi_sdi),
+    .spi_sdo(spi_sdo),
+    .spi_sdoenb(spi_sdoenb),
+    .trap(trap),
+    .uart_enabled(uart_enabled),
+    .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0]  })
+  );
+  spare_logic_block \spare_logic[0]  (
+    .spare_xfq({ \spare_xfq_nc[1] , \spare_xfq_nc[0]  }),
+    .spare_xfqn({ \spare_xfqn_nc[1] , \spare_xfqn_nc[0]  }),
+    .spare_xi({ \spare_xi_nc[3] , \spare_xi_nc[2] , \spare_xi_nc[1] , \spare_xi_nc[0]  }),
+    .spare_xib(\spare_xib_nc[0] ),
+    .spare_xmx({ \spare_xmx_nc[1] , \spare_xmx_nc[0]  }),
+    .spare_xna({ \spare_xna_nc[1] , \spare_xna_nc[0]  }),
+    .spare_xno({ \spare_xno_nc[1] , \spare_xno_nc[0]  }),
+    .spare_xz({ \spare_xz_nc[26] , \spare_xz_nc[25] , \spare_xz_nc[24] , \spare_xz_nc[23] , \spare_xz_nc[22] , \spare_xz_nc[21] , \spare_xz_nc[20] , \spare_xz_nc[19] , \spare_xz_nc[18] , \spare_xz_nc[17] , \spare_xz_nc[16] , \spare_xz_nc[15] , \spare_xz_nc[14] , \spare_xz_nc[13] , \spare_xz_nc[12] , \spare_xz_nc[11] , \spare_xz_nc[10] , \spare_xz_nc[9] , \spare_xz_nc[8] , \spare_xz_nc[7] , \spare_xz_nc[6] , \spare_xz_nc[5] , \spare_xz_nc[4] , \spare_xz_nc[3] , \spare_xz_nc[2] , \spare_xz_nc[1] , \spare_xz_nc[0]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  spare_logic_block \spare_logic[1]  (
+    .spare_xfq({ \spare_xfq_nc[3] , \spare_xfq_nc[2]  }),
+    .spare_xfqn({ \spare_xfqn_nc[3] , \spare_xfqn_nc[2]  }),
+    .spare_xi({ \spare_xi_nc[7] , \spare_xi_nc[6] , \spare_xi_nc[5] , \spare_xi_nc[4]  }),
+    .spare_xib(\spare_xib_nc[1] ),
+    .spare_xmx({ \spare_xmx_nc[3] , \spare_xmx_nc[2]  }),
+    .spare_xna({ \spare_xna_nc[3] , \spare_xna_nc[2]  }),
+    .spare_xno({ \spare_xno_nc[3] , \spare_xno_nc[2]  }),
+    .spare_xz({ \spare_xz_nc[53] , \spare_xz_nc[52] , \spare_xz_nc[51] , \spare_xz_nc[50] , \spare_xz_nc[49] , \spare_xz_nc[48] , \spare_xz_nc[47] , \spare_xz_nc[46] , \spare_xz_nc[45] , \spare_xz_nc[44] , \spare_xz_nc[43] , \spare_xz_nc[42] , \spare_xz_nc[41] , \spare_xz_nc[40] , \spare_xz_nc[39] , \spare_xz_nc[38] , \spare_xz_nc[37] , \spare_xz_nc[36] , \spare_xz_nc[35] , \spare_xz_nc[34] , \spare_xz_nc[33] , \spare_xz_nc[32] , \spare_xz_nc[31] , \spare_xz_nc[30] , \spare_xz_nc[29] , \spare_xz_nc[28] , \spare_xz_nc[27]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  spare_logic_block \spare_logic[2]  (
+    .spare_xfq({ \spare_xfq_nc[5] , \spare_xfq_nc[4]  }),
+    .spare_xfqn({ \spare_xfqn_nc[5] , \spare_xfqn_nc[4]  }),
+    .spare_xi({ \spare_xi_nc[11] , \spare_xi_nc[10] , \spare_xi_nc[9] , \spare_xi_nc[8]  }),
+    .spare_xib(\spare_xib_nc[2] ),
+    .spare_xmx({ \spare_xmx_nc[5] , \spare_xmx_nc[4]  }),
+    .spare_xna({ \spare_xna_nc[5] , \spare_xna_nc[4]  }),
+    .spare_xno({ \spare_xno_nc[5] , \spare_xno_nc[4]  }),
+    .spare_xz({ \spare_xz_nc[80] , \spare_xz_nc[79] , \spare_xz_nc[78] , \spare_xz_nc[77] , \spare_xz_nc[76] , \spare_xz_nc[75] , \spare_xz_nc[74] , \spare_xz_nc[73] , \spare_xz_nc[72] , \spare_xz_nc[71] , \spare_xz_nc[70] , \spare_xz_nc[69] , \spare_xz_nc[68] , \spare_xz_nc[67] , \spare_xz_nc[66] , \spare_xz_nc[65] , \spare_xz_nc[64] , \spare_xz_nc[63] , \spare_xz_nc[62] , \spare_xz_nc[61] , \spare_xz_nc[60] , \spare_xz_nc[59] , \spare_xz_nc[58] , \spare_xz_nc[57] , \spare_xz_nc[56] , \spare_xz_nc[55] , \spare_xz_nc[54]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  spare_logic_block \spare_logic[3]  (
+    .spare_xfq({ \spare_xfq_nc[7] , \spare_xfq_nc[6]  }),
+    .spare_xfqn({ \spare_xfqn_nc[7] , \spare_xfqn_nc[6]  }),
+    .spare_xi({ \spare_xi_nc[15] , \spare_xi_nc[14] , \spare_xi_nc[13] , \spare_xi_nc[12]  }),
+    .spare_xib(\spare_xib_nc[3] ),
+    .spare_xmx({ \spare_xmx_nc[7] , \spare_xmx_nc[6]  }),
+    .spare_xna({ \spare_xna_nc[7] , \spare_xna_nc[6]  }),
+    .spare_xno({ \spare_xno_nc[7] , \spare_xno_nc[6]  }),
+    .spare_xz({ \spare_xz_nc[107] , \spare_xz_nc[106] , \spare_xz_nc[105] , \spare_xz_nc[104] , \spare_xz_nc[103] , \spare_xz_nc[102] , \spare_xz_nc[101] , \spare_xz_nc[100] , \spare_xz_nc[99] , \spare_xz_nc[98] , \spare_xz_nc[97] , \spare_xz_nc[96] , \spare_xz_nc[95] , \spare_xz_nc[94] , \spare_xz_nc[93] , \spare_xz_nc[92] , \spare_xz_nc[91] , \spare_xz_nc[90] , \spare_xz_nc[89] , \spare_xz_nc[88] , \spare_xz_nc[87] , \spare_xz_nc[86] , \spare_xz_nc[85] , \spare_xz_nc[84] , \spare_xz_nc[83] , \spare_xz_nc[82] , \spare_xz_nc[81]  }),
+    .vccd(vccd_core),
+    .vssd(vssd_core)
+  );
+  user_id_programming user_id_value (
+    .VGND(vssd_core),
+    .VPWR(vccd_core),
+    .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0]  })
+  );
+  assign \gpio_serial_link_1_shifted[18]  = \gpio_serial_link_1[17] ;
+  assign \gpio_serial_link_1_shifted[17]  = \gpio_serial_link_1[16] ;
+  assign \gpio_serial_link_1_shifted[16]  = \gpio_serial_link_1[15] ;
+  assign \gpio_serial_link_1_shifted[15]  = \gpio_serial_link_1[14] ;
+  assign \gpio_serial_link_1_shifted[14]  = \gpio_serial_link_1[13] ;
+  assign \gpio_serial_link_1_shifted[13]  = \gpio_serial_link_1[12] ;
+  assign \gpio_serial_link_1_shifted[12]  = \gpio_serial_link_1[11] ;
+  assign \gpio_serial_link_1_shifted[11]  = \gpio_serial_link_1[10] ;
+  assign \gpio_serial_link_1_shifted[10]  = \gpio_serial_link_1[9] ;
+  assign \gpio_serial_link_1_shifted[9]  = \gpio_serial_link_1[8] ;
+  assign \gpio_serial_link_1_shifted[8]  = \gpio_serial_link_1[7] ;
+  assign \gpio_serial_link_1_shifted[7]  = \gpio_serial_link_1[6] ;
+  assign \gpio_serial_link_1_shifted[6]  = \gpio_serial_link_1[5] ;
+  assign \gpio_serial_link_1_shifted[5]  = \gpio_serial_link_1[4] ;
+  assign \gpio_serial_link_1_shifted[4]  = \gpio_serial_link_1[3] ;
+  assign \gpio_serial_link_1_shifted[3]  = \gpio_serial_link_1[2] ;
+  assign \gpio_serial_link_1_shifted[2]  = \gpio_serial_link_1[1] ;
+  assign \gpio_serial_link_1_shifted[1]  = \gpio_serial_link_1[0] ;
+  assign \gpio_load_2_shifted[17]  = \gpio_load_2[18] ;
+  assign \gpio_load_2_shifted[16]  = \gpio_load_2[17] ;
+  assign \gpio_load_2_shifted[15]  = \gpio_load_2[16] ;
+  assign \gpio_load_2_shifted[14]  = \gpio_load_2[15] ;
+  assign \gpio_load_2_shifted[13]  = \gpio_load_2[14] ;
+  assign \gpio_load_2_shifted[12]  = \gpio_load_2[13] ;
+  assign \gpio_load_2_shifted[11]  = \gpio_load_2[12] ;
+  assign \gpio_load_2_shifted[10]  = \gpio_load_2[11] ;
+  assign \gpio_load_2_shifted[9]  = \gpio_load_2[10] ;
+  assign \gpio_load_2_shifted[8]  = \gpio_load_2[9] ;
+  assign \gpio_load_2_shifted[7]  = \gpio_load_2[8] ;
+  assign \gpio_load_2_shifted[6]  = \gpio_load_2[7] ;
+  assign \gpio_load_2_shifted[5]  = \gpio_load_2[6] ;
+  assign \gpio_load_2_shifted[4]  = \gpio_load_2[5] ;
+  assign \gpio_load_2_shifted[3]  = \gpio_load_2[4] ;
+  assign \gpio_load_2_shifted[2]  = \gpio_load_2[3] ;
+  assign \gpio_load_2_shifted[1]  = \gpio_load_2[2] ;
+  assign \gpio_load_2_shifted[0]  = \gpio_load_2[1] ;
+  assign \gpio_clock_1_shifted[18]  = \gpio_clock_1[17] ;
+  assign \gpio_clock_1_shifted[17]  = \gpio_clock_1[16] ;
+  assign \gpio_clock_1_shifted[16]  = \gpio_clock_1[15] ;
+  assign \gpio_clock_1_shifted[15]  = \gpio_clock_1[14] ;
+  assign \gpio_clock_1_shifted[14]  = \gpio_clock_1[13] ;
+  assign \gpio_clock_1_shifted[13]  = \gpio_clock_1[12] ;
+  assign \gpio_clock_1_shifted[12]  = \gpio_clock_1[11] ;
+  assign \gpio_clock_1_shifted[11]  = \gpio_clock_1[10] ;
+  assign \gpio_clock_1_shifted[10]  = \gpio_clock_1[9] ;
+  assign \gpio_clock_1_shifted[9]  = \gpio_clock_1[8] ;
+  assign \gpio_clock_1_shifted[8]  = \gpio_clock_1[7] ;
+  assign \gpio_clock_1_shifted[7]  = \gpio_clock_1[6] ;
+  assign \gpio_clock_1_shifted[6]  = \gpio_clock_1[5] ;
+  assign \gpio_clock_1_shifted[5]  = \gpio_clock_1[4] ;
+  assign \gpio_clock_1_shifted[4]  = \gpio_clock_1[3] ;
+  assign \gpio_clock_1_shifted[3]  = \gpio_clock_1[2] ;
+  assign \gpio_clock_1_shifted[2]  = \gpio_clock_1[1] ;
+  assign \gpio_clock_1_shifted[1]  = \gpio_clock_1[0] ;
+  assign \gpio_resetn_1_shifted[18]  = \gpio_resetn_1[17] ;
+  assign \gpio_resetn_1_shifted[17]  = \gpio_resetn_1[16] ;
+  assign \gpio_resetn_1_shifted[16]  = \gpio_resetn_1[15] ;
+  assign \gpio_resetn_1_shifted[15]  = \gpio_resetn_1[14] ;
+  assign \gpio_resetn_1_shifted[14]  = \gpio_resetn_1[13] ;
+  assign \gpio_resetn_1_shifted[13]  = \gpio_resetn_1[12] ;
+  assign \gpio_resetn_1_shifted[12]  = \gpio_resetn_1[11] ;
+  assign \gpio_resetn_1_shifted[11]  = \gpio_resetn_1[10] ;
+  assign \gpio_resetn_1_shifted[10]  = \gpio_resetn_1[9] ;
+  assign \gpio_resetn_1_shifted[9]  = \gpio_resetn_1[8] ;
+  assign \gpio_resetn_1_shifted[8]  = \gpio_resetn_1[7] ;
+  assign \gpio_resetn_1_shifted[7]  = \gpio_resetn_1[6] ;
+  assign \gpio_resetn_1_shifted[6]  = \gpio_resetn_1[5] ;
+  assign \gpio_resetn_1_shifted[5]  = \gpio_resetn_1[4] ;
+  assign \gpio_resetn_1_shifted[4]  = \gpio_resetn_1[3] ;
+  assign \gpio_resetn_1_shifted[3]  = \gpio_resetn_1[2] ;
+  assign \gpio_resetn_1_shifted[2]  = \gpio_resetn_1[1] ;
+  assign \gpio_resetn_1_shifted[1]  = \gpio_resetn_1[0] ;
+  assign \gpio_clock_2_shifted[17]  = \gpio_clock_2[18] ;
+  assign \gpio_clock_2_shifted[16]  = \gpio_clock_2[17] ;
+  assign \gpio_clock_2_shifted[15]  = \gpio_clock_2[16] ;
+  assign \gpio_clock_2_shifted[14]  = \gpio_clock_2[15] ;
+  assign \gpio_clock_2_shifted[13]  = \gpio_clock_2[14] ;
+  assign \gpio_clock_2_shifted[12]  = \gpio_clock_2[13] ;
+  assign \gpio_clock_2_shifted[11]  = \gpio_clock_2[12] ;
+  assign \gpio_clock_2_shifted[10]  = \gpio_clock_2[11] ;
+  assign \gpio_clock_2_shifted[9]  = \gpio_clock_2[10] ;
+  assign \gpio_clock_2_shifted[8]  = \gpio_clock_2[9] ;
+  assign \gpio_clock_2_shifted[7]  = \gpio_clock_2[8] ;
+  assign \gpio_clock_2_shifted[6]  = \gpio_clock_2[7] ;
+  assign \gpio_clock_2_shifted[5]  = \gpio_clock_2[6] ;
+  assign \gpio_clock_2_shifted[4]  = \gpio_clock_2[5] ;
+  assign \gpio_clock_2_shifted[3]  = \gpio_clock_2[4] ;
+  assign \gpio_clock_2_shifted[2]  = \gpio_clock_2[3] ;
+  assign \gpio_clock_2_shifted[1]  = \gpio_clock_2[2] ;
+  assign \gpio_clock_2_shifted[0]  = \gpio_clock_2[1] ;
+  assign \gpio_load_1_shifted[18]  = \gpio_load_1[17] ;
+  assign \gpio_load_1_shifted[17]  = \gpio_load_1[16] ;
+  assign \gpio_load_1_shifted[16]  = \gpio_load_1[15] ;
+  assign \gpio_load_1_shifted[15]  = \gpio_load_1[14] ;
+  assign \gpio_load_1_shifted[14]  = \gpio_load_1[13] ;
+  assign \gpio_load_1_shifted[13]  = \gpio_load_1[12] ;
+  assign \gpio_load_1_shifted[12]  = \gpio_load_1[11] ;
+  assign \gpio_load_1_shifted[11]  = \gpio_load_1[10] ;
+  assign \gpio_load_1_shifted[10]  = \gpio_load_1[9] ;
+  assign \gpio_load_1_shifted[9]  = \gpio_load_1[8] ;
+  assign \gpio_load_1_shifted[8]  = \gpio_load_1[7] ;
+  assign \gpio_load_1_shifted[7]  = \gpio_load_1[6] ;
+  assign \gpio_load_1_shifted[6]  = \gpio_load_1[5] ;
+  assign \gpio_load_1_shifted[5]  = \gpio_load_1[4] ;
+  assign \gpio_load_1_shifted[4]  = \gpio_load_1[3] ;
+  assign \gpio_load_1_shifted[3]  = \gpio_load_1[2] ;
+  assign \gpio_load_1_shifted[2]  = \gpio_load_1[1] ;
+  assign \gpio_load_1_shifted[1]  = \gpio_load_1[0] ;
+  assign \gpio_serial_link_2_shifted[17]  = \gpio_serial_link_2[18] ;
+  assign \gpio_serial_link_2_shifted[16]  = \gpio_serial_link_2[17] ;
+  assign \gpio_serial_link_2_shifted[15]  = \gpio_serial_link_2[16] ;
+  assign \gpio_serial_link_2_shifted[14]  = \gpio_serial_link_2[15] ;
+  assign \gpio_serial_link_2_shifted[13]  = \gpio_serial_link_2[14] ;
+  assign \gpio_serial_link_2_shifted[12]  = \gpio_serial_link_2[13] ;
+  assign \gpio_serial_link_2_shifted[11]  = \gpio_serial_link_2[12] ;
+  assign \gpio_serial_link_2_shifted[10]  = \gpio_serial_link_2[11] ;
+  assign \gpio_serial_link_2_shifted[9]  = \gpio_serial_link_2[10] ;
+  assign \gpio_serial_link_2_shifted[8]  = \gpio_serial_link_2[9] ;
+  assign \gpio_serial_link_2_shifted[7]  = \gpio_serial_link_2[8] ;
+  assign \gpio_serial_link_2_shifted[6]  = \gpio_serial_link_2[7] ;
+  assign \gpio_serial_link_2_shifted[5]  = \gpio_serial_link_2[6] ;
+  assign \gpio_serial_link_2_shifted[4]  = \gpio_serial_link_2[5] ;
+  assign \gpio_serial_link_2_shifted[3]  = \gpio_serial_link_2[4] ;
+  assign \gpio_serial_link_2_shifted[2]  = \gpio_serial_link_2[3] ;
+  assign \gpio_serial_link_2_shifted[1]  = \gpio_serial_link_2[2] ;
+  assign \gpio_serial_link_2_shifted[0]  = \gpio_serial_link_2[1] ;
+  assign \gpio_resetn_2_shifted[17]  = \gpio_resetn_2[18] ;
+  assign \gpio_resetn_2_shifted[16]  = \gpio_resetn_2[17] ;
+  assign \gpio_resetn_2_shifted[15]  = \gpio_resetn_2[16] ;
+  assign \gpio_resetn_2_shifted[14]  = \gpio_resetn_2[15] ;
+  assign \gpio_resetn_2_shifted[13]  = \gpio_resetn_2[14] ;
+  assign \gpio_resetn_2_shifted[12]  = \gpio_resetn_2[13] ;
+  assign \gpio_resetn_2_shifted[11]  = \gpio_resetn_2[12] ;
+  assign \gpio_resetn_2_shifted[10]  = \gpio_resetn_2[11] ;
+  assign \gpio_resetn_2_shifted[9]  = \gpio_resetn_2[10] ;
+  assign \gpio_resetn_2_shifted[8]  = \gpio_resetn_2[9] ;
+  assign \gpio_resetn_2_shifted[7]  = \gpio_resetn_2[8] ;
+  assign \gpio_resetn_2_shifted[6]  = \gpio_resetn_2[7] ;
+  assign \gpio_resetn_2_shifted[5]  = \gpio_resetn_2[6] ;
+  assign \gpio_resetn_2_shifted[4]  = \gpio_resetn_2[5] ;
+  assign \gpio_resetn_2_shifted[3]  = \gpio_resetn_2[4] ;
+  assign \gpio_resetn_2_shifted[2]  = \gpio_resetn_2[3] ;
+  assign \gpio_resetn_2_shifted[1]  = \gpio_resetn_2[2] ;
+  assign \gpio_resetn_2_shifted[0]  = \gpio_resetn_2[1] ;
+  assign \mgmt_io_in_hk[6]  = \mgmt_io_in[6] ;
+  assign \mgmt_io_in_hk[5]  = \mgmt_io_in[5] ;
+  assign \mgmt_io_in_hk[4]  = \mgmt_io_in[4] ;
+  assign \mgmt_io_in_hk[3]  = \mgmt_io_in[3] ;
+  assign \mgmt_io_in_hk[2]  = \mgmt_io_in[2] ;
+  assign \mgmt_io_in_hk[1]  = \mgmt_io_in[1] ;
+  assign \mgmt_io_in_hk[0]  = \mgmt_io_in[0] ;
+  assign \mgmt_io_out_hk[6]  = \mgmt_io_out[6] ;
+  assign \mgmt_io_out_hk[5]  = \mgmt_io_out[5] ;
+  assign \mgmt_io_out_hk[4]  = \mgmt_io_out[4] ;
+  assign \mgmt_io_out_hk[3]  = \mgmt_io_out[3] ;
+  assign \mgmt_io_out_hk[2]  = \mgmt_io_out[2] ;
+  assign \mgmt_io_out_hk[1]  = \mgmt_io_out[1] ;
+  assign \mgmt_io_out_hk[0]  = \mgmt_io_out[0] ;
+  assign \mgmt_io_oeb_hk[34]  = \mgmt_io_oeb[34] ;
+  assign \mgmt_io_oeb_hk[33]  = \mgmt_io_oeb[33] ;
+  assign \mgmt_io_oeb_hk[32]  = \mgmt_io_oeb[32] ;
+  assign \mgmt_io_oeb_hk[31]  = \mgmt_io_oeb[31] ;
+  assign \mgmt_io_oeb_hk[30]  = \mgmt_io_oeb[30] ;
+  assign \mgmt_io_oeb_hk[29]  = \mgmt_io_oeb[29] ;
+  assign \mgmt_io_oeb_hk[28]  = \mgmt_io_oeb[28] ;
+  assign \mgmt_io_oeb_hk[27]  = \mgmt_io_oeb[27] ;
+  assign \mgmt_io_oeb_hk[26]  = \mgmt_io_oeb[26] ;
+  assign \mgmt_io_oeb_hk[25]  = \mgmt_io_oeb[25] ;
+  assign \mgmt_io_oeb_hk[24]  = \mgmt_io_oeb[24] ;
+  assign \mgmt_io_oeb_hk[23]  = \mgmt_io_oeb[23] ;
+  assign \mgmt_io_oeb_hk[22]  = \mgmt_io_oeb[22] ;
+  assign \mgmt_io_oeb_hk[21]  = \mgmt_io_oeb[21] ;
+  assign \mgmt_io_oeb_hk[20]  = \mgmt_io_oeb[20] ;
+  assign \mgmt_io_oeb_hk[19]  = \mgmt_io_oeb[19] ;
+  assign \mgmt_io_oeb_hk[18]  = \mgmt_io_oeb[18] ;
+  assign \mgmt_io_oeb_hk[17]  = \mgmt_io_oeb[17] ;
+  assign \mgmt_io_oeb_hk[16]  = \mgmt_io_oeb[16] ;
+  assign \mgmt_io_oeb_hk[15]  = \mgmt_io_oeb[15] ;
+  assign \mgmt_io_oeb_hk[14]  = \mgmt_io_oeb[14] ;
+  assign \mgmt_io_oeb_hk[13]  = \mgmt_io_oeb[13] ;
+  assign \mgmt_io_oeb_hk[12]  = \mgmt_io_oeb[12] ;
+  assign \mgmt_io_oeb_hk[11]  = \mgmt_io_oeb[11] ;
+  assign \mgmt_io_oeb_hk[10]  = \mgmt_io_oeb[10] ;
+  assign \mgmt_io_oeb_hk[9]  = \mgmt_io_oeb[9] ;
+  assign \mgmt_io_oeb_hk[8]  = \mgmt_io_oeb[8] ;
+  assign \mgmt_io_oeb_hk[7]  = \mgmt_io_oeb[7] ;
+  assign \mgmt_io_oeb_hk[6]  = \mgmt_io_oeb[6] ;
+  assign \mgmt_io_oeb_hk[5]  = \mgmt_io_oeb[5] ;
+  assign \mgmt_io_oeb_hk[4]  = \mgmt_io_oeb[4] ;
+  assign \mgmt_io_oeb_hk[3]  = \mgmt_io_oeb[3] ;
+  assign \mgmt_io_oeb_hk[2]  = \mgmt_io_oeb[2] ;
+  assign \mgmt_io_oeb_hk[1]  = \mgmt_io_oeb[1] ;
+  assign \mgmt_io_oeb_hk[0]  = \mgmt_io_oeb[0] ;
+  assign mprj_io_loader_data_2_buf = \gpio_serial_link_2_shifted[18] ;
+  assign mprj_io_loader_resetn_buf = \gpio_resetn_2_shifted[18] ;
+  assign mprj_io_loader_strobe_buf = \gpio_load_2_shifted[18] ;
+  assign mprj_io_loader_clock_buf = \gpio_clock_2_shifted[18] ;
+  assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+  assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+  assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+  assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v
new file mode 100644
index 0000000..33fbfde
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0403 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_high[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_low[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v
new file mode 100644
index 0000000..379ba1c
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0801 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_1800.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_1800.v
new file mode 100644
index 0000000..bdb0ae2
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_1800.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1800 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_low[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v
new file mode 100644
index 0000000..13ad29a
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1803 (VGND,
+    VPWR,
+    gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0]  (.HI(\gpio_defaults_high[0] ),
+    .LO(\gpio_defaults_low[0] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10]  (.HI(\gpio_defaults_high[10] ),
+    .LO(\gpio_defaults_low[10] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11]  (.HI(\gpio_defaults_high[11] ),
+    .LO(\gpio_defaults_low[11] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12]  (.HI(\gpio_defaults_high[12] ),
+    .LO(\gpio_defaults_low[12] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1]  (.HI(\gpio_defaults_high[1] ),
+    .LO(\gpio_defaults_low[1] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2]  (.HI(\gpio_defaults_high[2] ),
+    .LO(\gpio_defaults_low[2] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3]  (.HI(\gpio_defaults_high[3] ),
+    .LO(\gpio_defaults_low[3] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4]  (.HI(\gpio_defaults_high[4] ),
+    .LO(\gpio_defaults_low[4] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5]  (.HI(\gpio_defaults_high[5] ),
+    .LO(\gpio_defaults_low[5] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6]  (.HI(\gpio_defaults_high[6] ),
+    .LO(\gpio_defaults_low[6] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7]  (.HI(\gpio_defaults_high[7] ),
+    .LO(\gpio_defaults_low[7] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8]  (.HI(\gpio_defaults_high[8] ),
+    .LO(\gpio_defaults_low[8] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9]  (.HI(\gpio_defaults_high[9] ),
+    .LO(\gpio_defaults_low[9] ),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/user_id_programming.v b/tapeout/outputs/verilog/gl/user_id_programming.v
new file mode 100644
index 0000000..6c98126
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/user_id_programming.v
@@ -0,0 +1,786 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module user_id_programming(VPWR, VGND, mask_rev);
+  input VGND;
+  input VPWR;
+  output [31:0] mask_rev;
+  wire \user_proj_id_high[0] ;
+  wire \user_proj_id_high[10] ;
+  wire \user_proj_id_high[11] ;
+  wire \user_proj_id_high[12] ;
+  wire \user_proj_id_low[13] ;
+  wire \user_proj_id_low[14] ;
+  wire \user_proj_id_low[15] ;
+  wire \user_proj_id_high[16] ;
+  wire \user_proj_id_high[17] ;
+  wire \user_proj_id_high[18] ;
+  wire \user_proj_id_low[19] ;
+  wire \user_proj_id_high[1] ;
+  wire \user_proj_id_high[20] ;
+  wire \user_proj_id_high[21] ;
+  wire \user_proj_id_high[22] ;
+  wire \user_proj_id_high[23] ;
+  wire \user_proj_id_low[24] ;
+  wire \user_proj_id_low[25] ;
+  wire \user_proj_id_high[26] ;
+  wire \user_proj_id_low[27] ;
+  wire \user_proj_id_high[28] ;
+  wire \user_proj_id_low[29] ;
+  wire \user_proj_id_high[2] ;
+  wire \user_proj_id_low[30] ;
+  wire \user_proj_id_high[31] ;
+  wire \user_proj_id_high[3] ;
+  wire \user_proj_id_high[4] ;
+  wire \user_proj_id_high[5] ;
+  wire \user_proj_id_high[6] ;
+  wire \user_proj_id_high[7] ;
+  wire \user_proj_id_high[8] ;
+  wire \user_proj_id_high[9] ;
+  sky130_fd_sc_hd__decap_3 FILLER_0_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_0_21 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_0_29 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_0_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_0_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_0_39 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_0_47 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_0_7 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_1_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_1_20 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_1_24 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_1_33 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_1_45 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_1_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_2_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_2_27 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_2_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_2_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_2_44 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_3_18 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_3_30 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_3_42 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_3_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_4_10 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_4_14 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_4_18 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_4_26 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_4_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_4_30 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_4_35 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_4_41 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_4_46 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_5_11 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_5_23 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_5_31 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_5_40 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_5_49 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_5_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_6_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_6_20 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_6_24 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 FILLER_6_28 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_6_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_6_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_6_36 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_8 FILLER_6_40 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_2 FILLER_6_48 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_7_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_7_27 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_7_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_7_36 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__fill_1 FILLER_7_42 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_7_46 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_8_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_4 FILLER_8_27 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_8_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_12 FILLER_8_32 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_6 FILLER_8_44 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_0 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_1 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_10 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_11 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_13 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_14 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_16 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_17 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_2 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22 (
+    .VGND(VGND),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_3 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_4 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_5 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_7 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_8 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__decap_3 PHY_9 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[0]  (
+    .HI(\user_proj_id_high[0] ),
+    .LO(mask_rev[0]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[10]  (
+    .HI(\user_proj_id_high[10] ),
+    .LO(mask_rev[10]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[11]  (
+    .HI(\user_proj_id_high[11] ),
+    .LO(mask_rev[11]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[12]  (
+    .HI(\user_proj_id_high[12] ),
+    .LO(mask_rev[12]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[13]  (
+    .LO(\user_proj_id_low[13] ),
+    .HI(mask_rev[13]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[14]  (
+    .LO(\user_proj_id_low[14] ),
+    .HI(mask_rev[14]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[15]  (
+    .LO(\user_proj_id_low[15] ),
+    .HI(mask_rev[15]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[16]  (
+    .HI(\user_proj_id_high[16] ),
+    .LO(mask_rev[16]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[17]  (
+    .HI(\user_proj_id_high[17] ),
+    .LO(mask_rev[17]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[18]  (
+    .HI(\user_proj_id_high[18] ),
+    .LO(mask_rev[18]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[19]  (
+    .LO(\user_proj_id_low[19] ),
+    .HI(mask_rev[19]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[1]  (
+    .HI(\user_proj_id_high[1] ),
+    .LO(mask_rev[1]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[20]  (
+    .HI(\user_proj_id_high[20] ),
+    .LO(mask_rev[20]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[21]  (
+    .HI(\user_proj_id_high[21] ),
+    .LO(mask_rev[21]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[22]  (
+    .HI(\user_proj_id_high[22] ),
+    .LO(mask_rev[22]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[23]  (
+    .HI(\user_proj_id_high[23] ),
+    .LO(mask_rev[23]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[24]  (
+    .LO(\user_proj_id_low[24] ),
+    .HI(mask_rev[24]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[25]  (
+    .LO(\user_proj_id_low[25] ),
+    .HI(mask_rev[25]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[26]  (
+    .HI(\user_proj_id_high[26] ),
+    .LO(mask_rev[26]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[27]  (
+    .LO(\user_proj_id_low[27] ),
+    .HI(mask_rev[27]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[28]  (
+    .HI(\user_proj_id_high[28] ),
+    .LO(mask_rev[28]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[29]  (
+    .LO(\user_proj_id_low[29] ),
+    .HI(mask_rev[29]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[2]  (
+    .HI(\user_proj_id_high[2] ),
+    .LO(mask_rev[2]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[30]  (
+    .LO(\user_proj_id_low[30] ),
+    .HI(mask_rev[30]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[31]  (
+    .HI(\user_proj_id_high[31] ),
+    .LO(mask_rev[31]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[3]  (
+    .HI(\user_proj_id_high[3] ),
+    .LO(mask_rev[3]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[4]  (
+    .HI(\user_proj_id_high[4] ),
+    .LO(mask_rev[4]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[5]  (
+    .HI(\user_proj_id_high[5] ),
+    .LO(mask_rev[5]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[6]  (
+    .HI(\user_proj_id_high[6] ),
+    .LO(mask_rev[6]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[7]  (
+    .HI(\user_proj_id_high[7] ),
+    .LO(mask_rev[7]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[8]  (
+    .HI(\user_proj_id_high[8] ),
+    .LO(mask_rev[8]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hd__conb_1 \mask_rev_value[9]  (
+    .HI(\user_proj_id_high[9] ),
+    .LO(mask_rev[9]),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+endmodule
diff --git a/tapeout/outputs/verilog/rtl/caravel.v b/tapeout/outputs/verilog/rtl/caravel.v
new file mode 100644
index 0000000..a3c533c
--- /dev/null
+++ b/tapeout/outputs/verilog/rtl/caravel.v
@@ -0,0 +1,1635 @@
+ `ifdef SIM
+ `default_nettype wire
+ `endif
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130	*/
+/* fabrication process and open source PDK			*/
+/*                                                          	*/
+/* Copyright 2020 efabless, Inc.                            	*/
+/* Written by Tim Edwards, December 2019                    	*/
+/* and Mohamed Shalan, August 2020			    	*/
+/* This file is open source hardware released under the     	*/
+/* Apache 2.0 license.  See file LICENSE.                   	*/
+/*								*/
+/* Updated 10/15/2021:  Revised using the housekeeping module	*/
+/* from housekeeping.v (refactoring a number of functions from	*/
+/* the management SoC).						*/
+/*                                                          	*/
+/*--------------------------------------------------------------*/
+
+module caravel (
+
+    // All top-level I/O are package-facing pins
+
+    inout vddio,	// Common 3.3V padframe/ESD power
+    inout vddio_2,	// Common 3.3V padframe/ESD power
+    inout vssio,	// Common padframe/ESD ground
+    inout vssio_2,	// Common padframe/ESD ground
+    inout vdda,		// Management 3.3V power
+    inout vssa,		// Common analog ground
+    inout vccd,		// Management/Common 1.8V power
+    inout vssd,		// Common digital ground
+    inout vdda1,	// User area 1 3.3V power
+    inout vdda1_2,	// User area 1 3.3V power
+    inout vdda2,	// User area 2 3.3V power
+    inout vssa1,	// User area 1 analog ground
+    inout vssa1_2,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V power
+    inout vccd2,	// User area 2 1.8V power
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+
+    inout gpio,		// Used for external LDO control
+    inout [`MPRJ_IO_PADS-1:0] mprj_io,
+    input clock,    	// CMOS core clock input, not a crystal
+    input resetb,	// Reset input (sense inverted)
+
+    // Note that only two flash data pins are dedicated to the
+    // management SoC wrapper.  The management SoC exports the
+    // quad SPI mode status to make use of the top two mprj_io
+    // pins for io2 and io3.
+
+    output flash_csb,
+    output flash_clk,
+    output flash_io0,
+    output flash_io1
+);
+
+    //------------------------------------------------------------
+    // This value is uniquely defined for each user project.
+    //------------------------------------------------------------
+    parameter USER_PROJECT_ID = 32'h000710d6;
+
+    /*
+     *--------------------------------------------------------------------
+     *
+     * These pins are overlaid on mprj_io space.  They have the function
+     * below when the management processor is in reset, or in the default
+     * configuration.  They are assigned to uses in the user space by the
+     * configuration program running off of the SPI flash.  Note that even
+     * when the user has taken control of these pins, they can be restored
+     * to the original use by setting the resetb pin low.  The SPI pins and
+     * UART pins can be connected directly to an FTDI chip as long as the
+     * FTDI chip sets these lines to high impedence (input function) at
+     * all times except when holding the chip in reset.
+     *
+     * JTAG       = mprj_io[0]		(inout)
+     * SDO 	  = mprj_io[1]		(output)
+     * SDI 	  = mprj_io[2]		(input)
+     * CSB 	  = mprj_io[3]		(input)
+     * SCK	  = mprj_io[4]		(input)
+     * ser_rx     = mprj_io[5]		(input)
+     * ser_tx     = mprj_io[6]		(output)
+     * irq 	  = mprj_io[7]		(input)
+     *
+     * spi_sck    = mprj_io[32]		(output)
+     * spi_csb    = mprj_io[33]		(output)
+     * spi_sdi    = mprj_io[34]		(input)
+     * spi_sdo    = mprj_io[35]		(output)
+     * flash_io2  = mprj_io[36]		(inout) 
+     * flash_io3  = mprj_io[37]		(inout) 
+     *
+     * These pins are reserved for any project that wants to incorporate
+     * its own processor and flash controller.  While a user project can
+     * technically use any available I/O pins for the purpose, these
+     * four pins connect to a pass-through mode from the SPI slave (pins
+     * 1-4 above) so that any SPI flash connected to these specific pins
+     * can be accessed through the SPI slave even when the processor is in
+     * reset.
+     *
+     * user_flash_csb = mprj_io[8]
+     * user_flash_sck = mprj_io[9]
+     * user_flash_io0 = mprj_io[10]
+     * user_flash_io1 = mprj_io[11]
+     *
+     *--------------------------------------------------------------------
+     */
+
+    // One-bit GPIO dedicated to management SoC (outside of user control)
+    wire gpio_out_core;
+    wire gpio_in_core;
+    wire gpio_mode0_core;
+    wire gpio_mode1_core;
+    wire gpio_outenb_core;
+    wire gpio_inenb_core;
+
+    // User Project Control (pad-facing)
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+    wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_one;
+
+    // User Project Control (user-facing)
+    wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+    wire [`MPRJ_IO_PADS-1:0] user_io_in;
+    wire [`MPRJ_IO_PADS-1:0] user_io_out;
+    wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+    /* Padframe control signals */
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+    wire mprj_io_loader_resetn;
+    wire mprj_io_loader_clock;
+    wire mprj_io_loader_strobe;
+    wire mprj_io_loader_data_1;		/* user1 side serial loader */
+    wire mprj_io_loader_data_2;		/* user2 side serial loader */
+
+    // User Project Control management I/O
+    // There are two types of GPIO connections:
+    // (1) Full Bidirectional: Management connects to in, out, and oeb
+    //     Uses:  JTAG and SDO
+    // (2) Selectable bidirectional:  Management connects to in and out,
+    //	   which are tied together.  oeb is grounded (oeb from the
+    //	   configuration is used)
+
+    // SDI 	 = mprj_io[2]		(input)
+    // CSB 	 = mprj_io[3]		(input)
+    // SCK	 = mprj_io[4]		(input)
+    // ser_rx    = mprj_io[5]		(input)
+    // ser_tx    = mprj_io[6]		(output)
+    // irq 	 = mprj_io[7]		(input)
+
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;	/* two- and three-pin data in	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_out;	/* two- and three-pin data out	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb;	/* output enable, used only by	*/
+						/* the three-pin interfaces	*/
+    wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc;	/* no-connects */
+
+    /* Buffers are placed between housekeeping and gpio_control_block		*/
+    /* instances to mitigate timing issues on very long (> 1.5mm) wires.	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_in_hk;	/* mgmt_io_in at housekeeping	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_out_hk;	/* mgmt_io_out at housekeeping	*/
+    wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb_hk;	/* mgmt_io_oeb at housekeeping	*/
+    
+    wire clock_core;
+
+    // Power-on-reset signal.  The reset pad generates the sense-inverted
+    // reset at 3.3V.  The 1.8V signal and the inverted 1.8V signal are
+    // derived.
+
+    wire porb_h;
+    wire porb_l;
+    wire por_l;
+
+    wire rstb_h;
+    wire rstb_l;
+
+    // Flash SPI communication (management SoC to housekeeping)
+    wire flash_clk_core,     flash_csb_core;
+    wire flash_clk_oeb_core, flash_csb_oeb_core;
+    wire flash_io0_oeb_core, flash_io1_oeb_core;
+    wire flash_io2_oeb_core, flash_io3_oeb_core;
+    wire flash_io0_ieb_core, flash_io1_ieb_core;
+    wire flash_io2_ieb_core, flash_io3_ieb_core;
+    wire flash_io0_do_core,  flash_io1_do_core;
+    wire flash_io2_do_core,  flash_io3_do_core;
+    wire flash_io0_di_core,  flash_io1_di_core;
+    wire flash_io2_di_core,  flash_io3_di_core;
+
+    // Flash SPI communication (
+    wire flash_clk_frame;
+    wire flash_csb_frame;
+    wire flash_clk_oeb, flash_csb_oeb;
+    wire flash_clk_ieb, flash_csb_ieb;
+    wire flash_io0_oeb, flash_io1_oeb;
+    wire flash_io0_ieb, flash_io1_ieb;
+    wire flash_io0_do,  flash_io1_do;
+    wire flash_io0_di,  flash_io1_di;
+
+	// Flash buffered signals
+    wire flash_clk_frame_buf;
+    wire flash_csb_frame_buf;
+    wire flash_clk_ieb_buf, flash_csb_ieb_buf;
+    wire flash_io0_oeb_buf, flash_io1_oeb_buf;
+    wire flash_io0_ieb_buf, flash_io1_ieb_buf;
+    wire flash_io0_do_buf,  flash_io1_do_buf;
+    wire flash_io0_di_buf,  flash_io1_di_buf;
+	
+	// Clock and reset buffered signals
+	wire caravel_clk_buf;
+	wire caravel_rstn_buf;
+	wire clock_core_buf;
+
+	// SoC pass through buffered signals
+	wire mprj_io_loader_clock_buf;
+	wire mprj_io_loader_strobe_buf;
+	wire mprj_io_loader_resetn_buf;
+	wire mprj_io_loader_data_2_buf;
+	wire rstb_l_buf;
+	wire por_l_buf;
+	wire porb_h_buf;
+	
+
+    // SoC core
+    wire caravel_clk;
+    wire caravel_clk2;
+    wire caravel_rstn;
+	
+	// top-level buffers
+	buff_flash_clkrst flash_clkrst_buffers (
+	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+	`endif
+	.in_n({
+		caravel_clk,
+		caravel_rstn,
+		flash_clk_frame, 
+		flash_csb_frame, 
+		flash_clk_oeb, 
+		flash_csb_oeb, 
+		flash_io0_oeb, 
+		flash_io1_oeb,
+		flash_io0_ieb, 
+		flash_io1_ieb,
+		flash_io0_do,  
+		flash_io1_do }), 
+	.in_s({
+		clock_core,
+		flash_io1_di, 
+		flash_io0_di }),
+	.out_s({ 
+		caravel_clk_buf,
+		caravel_rstn_buf,
+		flash_clk_frame_buf, 
+		flash_csb_frame_buf, 
+		flash_clk_oeb_buf, 
+		flash_csb_oeb_buf, 
+		flash_io0_oeb_buf, 
+		flash_io1_oeb_buf,
+		flash_io0_ieb_buf, 
+		flash_io1_ieb_buf,
+		flash_io0_do_buf,  
+		flash_io1_do_buf }), 
+	.out_n({
+		clock_core_buf,
+		flash_io1_di_buf, 
+		flash_io0_di_buf })
+	);
+
+	`ifdef NO_TOP_LEVEL_BUFFERING
+		assign mgmt_io_in_hk = mgmt_io_in;
+		assign mgmt_io_out = mgmt_io_out_hk;
+		assign mgmt_io_oeb = mgmt_io_oeb_hk;
+	`else
+
+		/* NOTE: The first 7 GPIO are unbuffered, and all
+		 * OEB lines except the last three are unbuffered
+		 * (most of these end up being no-connects from
+		 * housekeeping).
+		 */
+		assign mgmt_io_in_hk[6:0] = mgmt_io_in[6:0];
+		assign mgmt_io_out[6:0] = mgmt_io_out_hk[6:0];
+		assign mgmt_io_oeb[34:0] = mgmt_io_oeb_hk[34:0];
+
+		gpio_signal_buffering sigbuf (
+		`ifdef USE_POWER_PINS
+			.vccd(vccd_core),
+			.vssd(vssd_core),
+		`endif
+		.mgmt_io_in_unbuf(mgmt_io_in[37:7]),
+		.mgmt_io_out_unbuf(mgmt_io_out_hk[37:7]),
+		.mgmt_io_oeb_unbuf(mgmt_io_oeb_hk[37:35]),
+		.mgmt_io_in_buf(mgmt_io_in_hk[37:7]),
+		.mgmt_io_out_buf(mgmt_io_out[37:7]),
+		.mgmt_io_oeb_buf(mgmt_io_oeb[37:35])
+		);
+	`endif
+
+	chip_io padframe(
+	`ifndef TOP_ROUTING
+		// Package Pins
+		.vddio_pad	(vddio),		// Common padframe/ESD supply
+		.vddio_pad2	(vddio_2),
+		.vssio_pad	(vssio),		// Common padframe/ESD ground
+		.vssio_pad2	(vssio_2),
+		.vccd_pad	(vccd),			// Common 1.8V supply
+		.vssd_pad	(vssd),			// Common digital ground
+		.vdda_pad	(vdda),			// Management analog 3.3V supply
+		.vssa_pad	(vssa),			// Management analog ground
+		.vdda1_pad	(vdda1),		// User area 1 3.3V supply
+		.vdda1_pad2	(vdda1_2),		
+		.vdda2_pad	(vdda2),		// User area 2 3.3V supply
+		.vssa1_pad	(vssa1),		// User area 1 analog ground
+		.vssa1_pad2	(vssa1_2),
+		.vssa2_pad	(vssa2),		// User area 2 analog ground
+		.vccd1_pad	(vccd1),		// User area 1 1.8V supply
+		.vccd2_pad	(vccd2),		// User area 2 1.8V supply
+		.vssd1_pad	(vssd1),		// User area 1 digital ground
+		.vssd2_pad	(vssd2),		// User area 2 digital ground
+        .vddio	(vddio_core),
+        .vssio	(vssio_core),
+        .vdda	(vdda_core),
+        .vssa	(vssa_core),
+        .vccd	(vccd_core),
+        .vssd	(vssd_core),
+        .vdda1	(vdda1_core),
+        .vdda2	(vdda2_core),
+        .vssa1	(vssa1_core),
+        .vssa2	(vssa2_core),
+        .vccd1	(vccd1_core),
+        .vccd2	(vccd2_core),
+        .vssd1	(vssd1_core),
+        .vssd2	(vssd2_core),
+	`endif
+	// Core Side Pins
+	.gpio(gpio),
+	.mprj_io(mprj_io),
+	.clock(clock),
+	.resetb(resetb),
+	.flash_csb(flash_csb),
+	.flash_clk(flash_clk),
+	.flash_io0(flash_io0),
+	.flash_io1(flash_io1),
+	// SoC Core Interface
+	.porb_h(porb_h),
+	.por(por_l_buf),
+	.resetb_core_h(rstb_h),
+	.clock_core(clock_core),
+	.gpio_out_core(gpio_out_core),
+	.gpio_in_core(gpio_in_core),
+	.gpio_mode0_core(gpio_mode0_core),
+	.gpio_mode1_core(gpio_mode1_core),
+	.gpio_outenb_core(gpio_outenb_core),
+	.gpio_inenb_core(gpio_inenb_core),
+	.flash_csb_core(flash_csb_frame_buf),
+	.flash_clk_core(flash_clk_frame_buf),
+	.flash_csb_oeb_core(flash_csb_oeb_buf),
+	.flash_clk_oeb_core(flash_clk_oeb_buf),
+	.flash_io0_oeb_core(flash_io0_oeb_buf),
+	.flash_io1_oeb_core(flash_io1_oeb_buf),
+	.flash_io0_ieb_core(flash_io0_ieb_buf),
+	.flash_io1_ieb_core(flash_io1_ieb_buf),
+	.flash_io0_do_core(flash_io0_do_buf),
+	.flash_io1_do_core(flash_io1_do_buf),
+	.flash_io0_di_core(flash_io0_di),
+	.flash_io1_di_core(flash_io1_di),
+	.mprj_io_one(mprj_io_one),
+	.mprj_io_in(mprj_io_in),
+	.mprj_io_out(mprj_io_out),
+	.mprj_io_oeb(mprj_io_oeb),
+	.mprj_io_inp_dis(mprj_io_inp_dis),
+	.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+	.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+	.mprj_io_slow_sel(mprj_io_slow_sel),
+	.mprj_io_holdover(mprj_io_holdover),
+	.mprj_io_analog_en(mprj_io_analog_en),
+	.mprj_io_analog_sel(mprj_io_analog_sel),
+	.mprj_io_analog_pol(mprj_io_analog_pol),
+	.mprj_io_dm(mprj_io_dm),
+	.mprj_analog_io(user_analog_io)
+    );
+
+
+    // Logic analyzer signals
+    wire [127:0] la_data_in_user;  // From CPU to MPRJ
+    wire [127:0] la_data_in_mprj;  // From MPRJ to CPU
+    wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+    wire [127:0] la_data_out_user; // From MPRJ to CPU
+    wire [127:0] la_oenb_user;     // From CPU to MPRJ
+    wire [127:0] la_oenb_mprj;     // From CPU to MPRJ
+    wire [127:0] la_iena_mprj;     // From CPU only
+
+    wire [2:0]   user_irq;	  // From MRPJ to CPU
+    wire [2:0]   user_irq_core;
+    wire [2:0]   user_irq_ena;
+    wire [2:0]	 irq_spi;	  // From SPI and external pins
+
+    // Exported Wishbone Bus (processor facing)
+    wire mprj_iena_wb;
+    wire mprj_cyc_o_core;
+    wire mprj_stb_o_core;
+    wire mprj_we_o_core;
+    wire [3:0] mprj_sel_o_core;
+    wire [31:0] mprj_adr_o_core;
+    wire [31:0] mprj_dat_o_core;
+    wire mprj_ack_i_core;
+    wire [31:0] mprj_dat_i_core;
+
+    wire [31:0] hk_dat_i;
+    wire hk_ack_i;
+    wire hk_stb_o;
+    wire hk_cyc_o;
+
+    // Exported Wishbone Bus (user area facing)
+    wire 	mprj_cyc_o_user;
+    wire 	mprj_stb_o_user;
+    wire 	mprj_we_o_user;
+    wire [3:0]  mprj_sel_o_user;
+    wire [31:0] mprj_adr_o_user;
+    wire [31:0] mprj_dat_o_user;
+    wire [31:0] mprj_dat_i_user;
+    wire	mprj_ack_i_user;
+
+    // Mask revision
+    wire [31:0] mask_rev;
+
+    wire 	mprj_clock;
+    wire 	mprj_clock2;
+    wire 	mprj_reset;
+
+    // Power monitoring 
+    wire	mprj_vcc_pwrgood;
+    wire	mprj2_vcc_pwrgood;
+    wire	mprj_vdd_pwrgood;
+    wire	mprj2_vdd_pwrgood;
+
+`ifdef USE_SRAM_RO_INTERFACE
+    // SRAM read-only access from housekeeping
+    wire 	hkspi_sram_clk;
+    wire 	hkspi_sram_csb;
+    wire [7:0]	hkspi_sram_addr;
+    wire [31:0]	hkspi_sram_data;
+`endif
+
+    // Management processor (wrapper).  Any management core
+    // implementation must match this pinout.
+
+    // Pass thru clock and reset
+    wire 	clk_passthru;
+    wire 	resetn_passthru;
+
+	// NC passthru signal porb_h 
+	wire porb_h_in_nc;
+	wire porb_h_out_nc;
+
+    mgmt_core_wrapper soc (
+	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+	`endif
+
+	// SoC pass through buffered signals
+	.serial_clock_in(mprj_io_loader_clock),
+	.serial_clock_out(mprj_io_loader_clock_buf),
+	.serial_load_in(mprj_io_loader_strobe),
+	.serial_load_out(mprj_io_loader_strobe_buf),
+	.serial_resetn_in(mprj_io_loader_resetn),
+	.serial_resetn_out(mprj_io_loader_resetn_buf),
+	.serial_data_2_in(mprj_io_loader_data_2),
+	.serial_data_2_out(mprj_io_loader_data_2_buf),
+	.rstb_l_in(rstb_l),
+	.rstb_l_out(rstb_l_buf),
+	.porb_h_in(porb_h_in_nc),
+	.porb_h_out(porb_h_out_nc),
+	.por_l_in(por_l),
+	.por_l_out(por_l_buf),
+
+	// Clock and reset
+	.core_clk(caravel_clk_buf),
+	.core_rstn(caravel_rstn_buf),
+
+    // Pass thru Clock and reset
+	.clk_in(caravel_clk_buf),
+	.resetn_in(caravel_rstn_buf),
+	.clk_out(clk_passthru),
+	.resetn_out(resetn_passthru),
+
+	// GPIO (1 pin)
+	.gpio_out_pad(gpio_out_core),
+	.gpio_in_pad(gpio_in_core),
+	.gpio_mode0_pad(gpio_mode0_core),
+	.gpio_mode1_pad(gpio_mode1_core),
+	.gpio_outenb_pad(gpio_outenb_core),
+	.gpio_inenb_pad(gpio_inenb_core),
+
+	// Primary SPI flash controller
+	.flash_csb(flash_csb_core),
+	.flash_clk(flash_clk_core),
+	.flash_io0_oeb(flash_io0_oeb_core),
+	.flash_io0_di(flash_io0_di_core),
+	.flash_io0_do(flash_io0_do_core),
+	.flash_io1_oeb(flash_io1_oeb_core),
+	.flash_io1_di(flash_io1_di_core),
+	.flash_io1_do(flash_io1_do_core),
+	.flash_io2_oeb(flash_io2_oeb_core),
+	.flash_io2_di(flash_io2_di_core),
+	.flash_io2_do(flash_io2_do_core),
+	.flash_io3_oeb(flash_io3_oeb_core),
+	.flash_io3_di(flash_io3_di_core),
+	.flash_io3_do(flash_io3_do_core),
+
+	// Exported Wishbone Bus
+	.mprj_wb_iena(mprj_iena_wb),
+	.mprj_cyc_o(mprj_cyc_o_core),
+	.mprj_stb_o(mprj_stb_o_core),
+	.mprj_we_o(mprj_we_o_core),
+	.mprj_sel_o(mprj_sel_o_core),
+	.mprj_adr_o(mprj_adr_o_core),
+	.mprj_dat_o(mprj_dat_o_core),
+	.mprj_ack_i(mprj_ack_i_core),
+	.mprj_dat_i(mprj_dat_i_core),
+
+	.hk_stb_o(hk_stb_o),
+	.hk_cyc_o(hk_cyc_o),
+	.hk_dat_i(hk_dat_i),
+	.hk_ack_i(hk_ack_i),
+
+	// IRQ
+	.irq({irq_spi, user_irq}),
+	.user_irq_ena(user_irq_ena),
+
+	// Module status (these may or may not be implemented)
+	.qspi_enabled(qspi_enabled),
+	.uart_enabled(uart_enabled),
+	.spi_enabled(spi_enabled),
+	.debug_mode(debug_mode),
+
+	// Module I/O (these may or may not be implemented)
+	// UART
+	.ser_tx(ser_tx),
+	.ser_rx(ser_rx),
+	// SPI master
+	.spi_sdi(spi_sdi),
+	.spi_csb(spi_csb),
+	.spi_sck(spi_sck),
+	.spi_sdo(spi_sdo),
+	.spi_sdoenb(spi_sdoenb),
+	// Debug
+	.debug_in(debug_in),
+	.debug_out(debug_out),
+	.debug_oeb(debug_oeb),
+	// Logic analyzer
+	.la_input(la_data_in_mprj),
+	.la_output(la_data_out_mprj),
+	.la_oenb(la_oenb_mprj),
+	.la_iena(la_iena_mprj),
+
+`ifdef USE_SRAM_RO_INTERFACE
+	// SRAM Read-only access from housekeeping
+	.sram_ro_clk(hkspi_sram_clk),
+	.sram_ro_csb(hkspi_sram_csb),
+	.sram_ro_addr(hkspi_sram_addr),
+	.sram_ro_data(hkspi_sram_data),
+`endif
+
+	// Trap status
+	.trap(trap)
+    );
+
+    /* Clock and reset to user space are passed through a tristate	*/
+    /* buffer like the above, but since they are intended to be		*/
+    /* always active, connect the enable to the logic-1 output from	*/
+    /* the vccd1 domain.						*/
+
+    mgmt_protect mgmt_buffers (
+	`ifdef USE_POWER_PINS
+ 	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+	    .vccd2(vccd2_core),
+	    .vssd2(vssd2_core),
+	    .vdda1(vdda1_core),
+	    .vssa1(vssa1_core),
+	    .vdda2(vdda2_core),
+	    .vssa2(vssa2_core),
+	`endif
+	.caravel_clk(clk_passthru),
+	.caravel_clk2(caravel_clk2),
+	.caravel_rstn(resetn_passthru),
+	.mprj_iena_wb(mprj_iena_wb),
+	.mprj_cyc_o_core(mprj_cyc_o_core),
+	.mprj_stb_o_core(mprj_stb_o_core),
+	.mprj_we_o_core(mprj_we_o_core),
+	.mprj_sel_o_core(mprj_sel_o_core),
+	.mprj_adr_o_core(mprj_adr_o_core),
+	.mprj_dat_o_core(mprj_dat_o_core),
+	.mprj_ack_i_core(mprj_ack_i_core),
+	.mprj_dat_i_core(mprj_dat_i_core),
+	.user_irq_core(user_irq_core),
+	.user_irq_ena(user_irq_ena),
+	.la_data_out_core(la_data_out_user),
+	.la_data_out_mprj(la_data_out_mprj),
+	.la_data_in_core(la_data_in_user),
+	.la_data_in_mprj(la_data_in_mprj),
+	.la_oenb_mprj(la_oenb_mprj),
+	.la_oenb_core(la_oenb_user),
+	.la_iena_mprj(la_iena_mprj),
+
+	.user_clock(mprj_clock),
+	.user_clock2(mprj_clock2),
+	.user_reset(mprj_reset),
+	.mprj_cyc_o_user(mprj_cyc_o_user),
+	.mprj_stb_o_user(mprj_stb_o_user),
+	.mprj_we_o_user(mprj_we_o_user),
+	.mprj_sel_o_user(mprj_sel_o_user),
+	.mprj_adr_o_user(mprj_adr_o_user),
+	.mprj_dat_o_user(mprj_dat_o_user),
+	.mprj_dat_i_user(mprj_dat_i_user),
+	.mprj_ack_i_user(mprj_ack_i_user),
+	.user_irq(user_irq),
+	.user1_vcc_powergood(mprj_vcc_pwrgood),
+	.user2_vcc_powergood(mprj2_vcc_pwrgood),
+	.user1_vdd_powergood(mprj_vdd_pwrgood),
+	.user2_vdd_powergood(mprj2_vdd_pwrgood)
+    );
+
+    /*--------------------------------------------------*/
+    /* Wrapper module around the user project 		*/
+    /*--------------------------------------------------*/
+
+    user_project_wrapper mprj ( 
+        `ifdef USE_POWER_PINS
+	    .vdda1(vdda1_core),		// User area 1 3.3V power
+	    .vdda2(vdda2_core),		// User area 2 3.3V power
+	    .vssa1(vssa1_core),		// User area 1 analog ground
+	    .vssa2(vssa2_core),		// User area 2 analog ground
+	    .vccd1(vccd1_core),		// User area 1 1.8V power
+	    .vccd2(vccd2_core),		// User area 2 1.8V power
+	    .vssd1(vssd1_core),		// User area 1 digital ground
+	    .vssd2(vssd2_core),		// User area 2 digital ground
+    	`endif
+
+    	.wb_clk_i(mprj_clock),
+    	.wb_rst_i(mprj_reset),
+
+	// Management SoC Wishbone bus (exported)
+	.wbs_cyc_i(mprj_cyc_o_user),
+	.wbs_stb_i(mprj_stb_o_user),
+	.wbs_we_i(mprj_we_o_user),
+	.wbs_sel_i(mprj_sel_o_user),
+	.wbs_adr_i(mprj_adr_o_user),
+	.wbs_dat_i(mprj_dat_o_user),
+	.wbs_ack_o(mprj_ack_i_user),
+	.wbs_dat_o(mprj_dat_i_user),
+
+	// GPIO pad 3-pin interface (plus analog)
+	.io_in (user_io_in),
+    	.io_out(user_io_out),
+    	.io_oeb(user_io_oeb),
+	.analog_io(user_analog_io),
+
+	// Logic analyzer
+	.la_data_in(la_data_in_user),
+	.la_data_out(la_data_out_user),
+	.la_oenb(la_oenb_user),
+
+	// Independent clock
+	.user_clock2(mprj_clock2),
+
+	// IRQ
+	.user_irq(user_irq_core)
+    );
+
+    /*------------------------------------------*/
+    /* End user project instantiation		*/
+    /*------------------------------------------*/
+
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+    assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_data_1};
+    // Note that serial_link_2 is backwards compared to serial_link_1, so it
+    // shifts in the other direction.
+    assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2_buf,
+					 gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+    // Propagating clock and reset to mitigate timing and fanout issues
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+    wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1_shifted;
+    wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2_shifted;
+
+    assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_clock};
+    assign gpio_clock_2_shifted = {mprj_io_loader_clock_buf,
+					gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+    assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_resetn};
+    assign gpio_resetn_2_shifted = {mprj_io_loader_resetn_buf,
+					gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+    assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0],
+					 mprj_io_loader_strobe};
+    assign gpio_load_2_shifted = {mprj_io_loader_strobe_buf,
+					gpio_load_2[`MPRJ_IO_PADS_2-1:1]};
+
+    wire [2:0] spi_pll_sel;
+    wire [2:0] spi_pll90_sel;
+    wire [4:0] spi_pll_div;
+    wire [25:0] spi_pll_trim;
+
+    // Clocking control
+
+    caravel_clocking clock_ctrl (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+        .ext_clk_sel(ext_clk_sel),
+        .ext_clk(clock_core_buf),
+        .pll_clk(pll_clk),
+        .pll_clk90(pll_clk90),
+        .resetb(rstb_l_buf),
+        .sel(spi_pll_sel),
+        .sel2(spi_pll90_sel),
+        .ext_reset(ext_reset),  // From housekeeping SPI
+        .core_clk(caravel_clk),
+        .user_clk(caravel_clk2),
+        .resetb_sync(caravel_rstn)
+    );
+
+    // DCO/Digital Locked Loop
+
+    digital_pll pll (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+        .resetb(rstb_l_buf),
+        .enable(spi_pll_ena),
+        .osc(clock_core_buf),
+        .clockp({pll_clk, pll_clk90}),
+        .div(spi_pll_div),
+        .dco(spi_pll_dco_ena),
+        .ext_trim(spi_pll_trim)
+    );
+
+    // Housekeeping interface
+
+    housekeeping housekeeping (
+    `ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+    `endif
+
+        .wb_clk_i(caravel_clk),
+        .wb_rstn_i(caravel_rstn),
+
+        .wb_adr_i(mprj_adr_o_core),
+        .wb_dat_i(mprj_dat_o_core),
+        .wb_sel_i(mprj_sel_o_core),
+        .wb_we_i(mprj_we_o_core),
+        .wb_cyc_i(hk_cyc_o),
+        .wb_stb_i(hk_stb_o),
+        .wb_ack_o(hk_ack_i),
+        .wb_dat_o(hk_dat_i),
+
+        .porb(porb_l),
+
+        .pll_ena(spi_pll_ena),
+        .pll_dco_ena(spi_pll_dco_ena),
+        .pll_div(spi_pll_div),
+        .pll_sel(spi_pll_sel),
+        .pll90_sel(spi_pll90_sel),
+        .pll_trim(spi_pll_trim),
+        .pll_bypass(ext_clk_sel),
+
+	.qspi_enabled(qspi_enabled),
+	.uart_enabled(uart_enabled),
+	.spi_enabled(spi_enabled),
+	.debug_mode(debug_mode),
+
+	.ser_tx(ser_tx),
+	.ser_rx(ser_rx),
+
+	.spi_sdi(spi_sdi),
+	.spi_csb(spi_csb),
+	.spi_sck(spi_sck),
+	.spi_sdo(spi_sdo),
+	.spi_sdoenb(spi_sdoenb),
+
+	.debug_in(debug_in),
+	.debug_out(debug_out),
+	.debug_oeb(debug_oeb),
+
+        .irq(irq_spi),
+        .reset(ext_reset),
+
+        .serial_clock(mprj_io_loader_clock),
+        .serial_load(mprj_io_loader_strobe),
+        .serial_resetn(mprj_io_loader_resetn),
+        .serial_data_1(mprj_io_loader_data_1),
+        .serial_data_2(mprj_io_loader_data_2),
+
+	.mgmt_gpio_in(mgmt_io_in_hk),
+	.mgmt_gpio_out(mgmt_io_out_hk),
+	.mgmt_gpio_oeb(mgmt_io_oeb_hk),
+
+	.pwr_ctrl_out(pwr_ctrl_nc),	/* Not used in this version */
+
+        .trap(trap),
+
+	.user_clock(caravel_clk2),
+
+        .mask_rev_in(mask_rev),
+
+	.spimemio_flash_csb(flash_csb_core),
+	.spimemio_flash_clk(flash_clk_core),
+	.spimemio_flash_io0_oeb(flash_io0_oeb_core),
+	.spimemio_flash_io1_oeb(flash_io1_oeb_core),
+	.spimemio_flash_io2_oeb(flash_io2_oeb_core),
+	.spimemio_flash_io3_oeb(flash_io3_oeb_core),
+	.spimemio_flash_io0_do(flash_io0_do_core),
+	.spimemio_flash_io1_do(flash_io1_do_core),
+	.spimemio_flash_io2_do(flash_io2_do_core),
+	.spimemio_flash_io3_do(flash_io3_do_core),
+	.spimemio_flash_io0_di(flash_io0_di_core),
+	.spimemio_flash_io1_di(flash_io1_di_core),
+	.spimemio_flash_io2_di(flash_io2_di_core),
+	.spimemio_flash_io3_di(flash_io3_di_core),
+
+	.pad_flash_csb(flash_csb_frame),
+	.pad_flash_csb_oeb(flash_csb_oeb),
+	.pad_flash_clk(flash_clk_frame),
+	.pad_flash_clk_oeb(flash_clk_oeb),
+	.pad_flash_io0_oeb(flash_io0_oeb),
+	.pad_flash_io1_oeb(flash_io1_oeb),
+	.pad_flash_io0_ieb(flash_io0_ieb),
+	.pad_flash_io1_ieb(flash_io1_ieb),
+	.pad_flash_io0_do(flash_io0_do),
+	.pad_flash_io1_do(flash_io1_do),
+	.pad_flash_io0_di(flash_io0_di_buf),
+	.pad_flash_io1_di(flash_io1_di_buf),
+
+`ifdef USE_SRAM_RO_INTERFACE
+	.sram_ro_clk(hkspi_sram_clk),
+	.sram_ro_csb(hkspi_sram_csb),
+	.sram_ro_addr(hkspi_sram_addr),
+	.sram_ro_data(hkspi_sram_data),
+`endif
+
+	.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+	.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+	.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+	.usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+    );
+
+    /* GPIO defaults (via programmed) */
+    wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
+
+    /* Fixed defaults for the first 5 GPIO pins */
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h1803)
+    ) gpio_defaults_block_0 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[12:0])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h1803)
+    ) gpio_defaults_block_1 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[25:13])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0403)
+    ) gpio_defaults_block_2 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[38:26])
+    );
+
+    // CSB pin is set as an internal pull-up
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0801)
+    ) gpio_defaults_block_3 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[51:39])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(13'h0403)
+    ) gpio_defaults_block_4 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[64:52])
+    );
+
+    /* Via-programmable defaults for the rest of the GPIO pins */
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+    ) gpio_defaults_block_5 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[77:65])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+    ) gpio_defaults_block_6 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[90:78])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+    ) gpio_defaults_block_7 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[103:91])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+    ) gpio_defaults_block_8 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[116:104])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+    ) gpio_defaults_block_9 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[129:117])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+    ) gpio_defaults_block_10 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[142:130])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+    ) gpio_defaults_block_11 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[155:143])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+    ) gpio_defaults_block_12 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[168:156])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+    ) gpio_defaults_block_13 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[181:169])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+    ) gpio_defaults_block_14 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[194:182])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
+    ) gpio_defaults_block_15 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[207:195])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
+    ) gpio_defaults_block_16 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[220:208])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
+    ) gpio_defaults_block_17 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[233:221])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
+    ) gpio_defaults_block_18 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[246:234])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
+    ) gpio_defaults_block_19 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[259:247])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
+    ) gpio_defaults_block_20 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[272:260])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
+    ) gpio_defaults_block_21 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[285:273])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
+    ) gpio_defaults_block_22 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[298:286])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
+    ) gpio_defaults_block_23 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[311:299])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
+    ) gpio_defaults_block_24 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[324:312])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
+    ) gpio_defaults_block_25 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[337:325])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+    ) gpio_defaults_block_26 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[350:338])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+    ) gpio_defaults_block_27 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[363:351])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+    ) gpio_defaults_block_28 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[376:364])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+    ) gpio_defaults_block_29 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[389:377])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+    ) gpio_defaults_block_30 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[402:390])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+    ) gpio_defaults_block_31 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[415:403])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+    ) gpio_defaults_block_32 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[428:416])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+    ) gpio_defaults_block_33 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[441:429])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+    ) gpio_defaults_block_34 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[454:442])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+    ) gpio_defaults_block_35 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[467:455])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+    ) gpio_defaults_block_36 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[480:468])
+    );
+
+    gpio_defaults_block #(
+	.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+    ) gpio_defaults_block_37 (
+    	`ifdef USE_POWER_PINS
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
+        `endif
+	.gpio_defaults(gpio_defaults[493:481])
+    );
+
+    // Each control block sits next to an I/O pad in the user area.
+    // It gets input through a serial chain from the previous control
+    // block and passes it to the next control block.  Due to the nature
+    // of the shift register, bits are presented in reverse, as the first
+    // bit in ends up as the last bit of the last I/O pad control block.
+
+    // There are two types of block;  the first two and the last two
+    // are configured to be full bidirectional under control of the
+    // management Soc (JTAG and SDO for the first two;  flash_io2 and
+    // flash_io3 for the last two).  The rest are configured to be default
+    // (input).  Note that the first two and last two are the ones closest
+    // to the management SoC on either side, which minimizes the wire length
+    // of the extra signals those pads need.
+
+    /* First two GPIOs (JTAG and SDO) */
+
+    gpio_control_block gpio_control_bidir_1 [1:0] (
+    	`ifdef USE_POWER_PINS
+	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[25:0]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[1:0]),
+    	.serial_clock(gpio_clock_1_shifted[1:0]),
+    	.serial_load(gpio_load_1_shifted[1:0]),
+
+    	.resetn_out(gpio_resetn_1[1:0]),
+    	.serial_clock_out(gpio_clock_1[1:0]),
+    	.serial_load_out(gpio_load_1[1:0]),
+
+    	.mgmt_gpio_in(mgmt_io_in[1:0]),
+	.mgmt_gpio_out(mgmt_io_out[1:0]),
+	.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
+
+        .one(mprj_io_one[1:0]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[1:0]),
+    	.serial_data_out(gpio_serial_link_1[1:0]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[1:0]),
+    	.user_gpio_oeb(user_io_oeb[1:0]),
+    	.user_gpio_in(user_io_in[1:0]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+    	.pad_gpio_holdover(mprj_io_holdover[1:0]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+    	.pad_gpio_dm(mprj_io_dm[5:0]),
+    	.pad_gpio_outenb(mprj_io_oeb[1:0]),
+    	.pad_gpio_out(mprj_io_out[1:0]),
+    	.pad_gpio_in(mprj_io_in[1:0])
+    );
+
+    /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+    gpio_control_block gpio_control_in_1a [5:0] (
+        `ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[103:26]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[7:2]),
+    	.serial_clock(gpio_clock_1_shifted[7:2]),
+    	.serial_load(gpio_load_1_shifted[7:2]),
+
+    	.resetn_out(gpio_resetn_1[7:2]),
+    	.serial_clock_out(gpio_clock_1[7:2]),
+    	.serial_load_out(gpio_load_1[7:2]),
+
+	.mgmt_gpio_in(mgmt_io_in[7:2]),
+	.mgmt_gpio_out(mgmt_io_out[7:2]),
+	.mgmt_gpio_oeb(mprj_io_one[7:2]),
+
+        .one(mprj_io_one[7:2]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[7:2]),
+    	.serial_data_out(gpio_serial_link_1[7:2]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[7:2]),
+    	.user_gpio_oeb(user_io_oeb[7:2]),
+    	.user_gpio_in(user_io_in[7:2]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+    	.pad_gpio_holdover(mprj_io_holdover[7:2]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+    	.pad_gpio_dm(mprj_io_dm[23:6]),
+    	.pad_gpio_outenb(mprj_io_oeb[7:2]),
+    	.pad_gpio_out(mprj_io_out[7:2]),
+    	.pad_gpio_in(mprj_io_in[7:2])
+    );
+
+    /* Section 1 GPIOs (GPIO 8 to 18) */
+
+    gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
+        `ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+
+    	.resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
+
+	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+	.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS_1-1):8]),
+	.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
+  
+        .one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+    	.serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
+    );
+
+    /* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
+
+    gpio_control_block gpio_control_bidir_2 [2:0] (
+    	`ifdef USE_POWER_PINS
+	    .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+	.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+	.mgmt_gpio_oeb(mgmt_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+        .one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+    	.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
+    );
+
+    /* Section 2 GPIOs (GPIO 19 to 34) */
+
+    gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
+    	`ifdef USE_POWER_PINS
+            .vccd(vccd_core),
+	    .vssd(vssd_core),
+	    .vccd1(vccd1_core),
+	    .vssd1(vssd1_core),
+        `endif
+
+	.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
+
+    	// Management Soc-facing signals
+
+    	.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+
+    	.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
+
+	.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+	.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+	.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+
+        .one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+        .zero(),
+
+    	// Serial data chain for pad configuration
+    	.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+    	.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
+
+    	// User-facing signals
+    	.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+    	// Pad-facing signals (Pad GPIOv2)
+    	.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
+    	.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+    	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
+    );
+
+    user_id_programming #(
+	.USER_PROJECT_ID(USER_PROJECT_ID)
+    ) user_id_value (
+	`ifdef USE_POWER_PINS
+		.VPWR(vccd_core),
+		.VGND(vssd_core),
+	`endif
+	.mask_rev(mask_rev)
+    );
+
+    // Power-on-reset circuit
+    simple_por por (
+	`ifdef USE_POWER_PINS
+		.vdd3v3(vddio_core),
+		.vdd1v8(vccd_core),
+		.vss3v3(vssio_core),
+		.vss1v8(vssd_core),
+	`endif
+		.porb_h(porb_h),
+		.porb_l(porb_l),
+		.por_l(por_l)
+    );
+
+    // XRES (chip input pin reset) reset level converter
+    xres_buf rstb_level (
+	`ifdef USE_POWER_PINS
+		.VPWR(vddio_core),
+		.LVPWR(vccd_core),
+		.LVGND(vssd_core),
+		.VGND(vssio_core),
+	`endif
+		.A(rstb_h),
+		.X(rstb_l)
+    );
+
+    /* Spare logic for metal mask fixes */
+    // `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
+    `define NUM_SPARE_BLOCKS 4
+
+    wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
+    wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
+    wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
+
+    // Four spare logic blocks above the processor and one per GPIO
+    // control block.
+    spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
+	`ifdef USE_POWER_PINS
+		.vccd(vccd_core),
+		.vssd(vssd_core),
+	`endif
+		.spare_xz(spare_xz_nc),
+		.spare_xi(spare_xi_nc),
+		.spare_xib(spare_xib_nc),
+		.spare_xna(spare_xna_nc),
+		.spare_xno(spare_xno_nc),
+		.spare_xmx(spare_xmx_nc),
+		.spare_xfq(spare_xfq_nc),
+		.spare_xfqn(spare_xfqn_nc)
+    );
+
+    `ifdef TOP_ROUTING
+    caravel_power_routing caravel_power_routing();
+    copyright_block copyright_block();
+    caravel_logo caravel_logo();
+    caravel_motto caravel_motto();
+    open_source open_source();
+    user_id_textblock user_id_textblock();
+    `endif
+
+endmodule
+// `default_nettype wire