diff --git a/Makefile b/Makefile
index 2d433bf..a54eedb 100644
--- a/Makefile
+++ b/Makefile
@@ -324,6 +324,6 @@
 .PHONY: caravel-sta
 caravel-sta: ./env/spef-mapping.tcl
 	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
-#	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
-#	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
 	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/README.md b/README.md
index eb1352d..05a57bf 100644
--- a/README.md
+++ b/README.md
@@ -27,6 +27,7 @@
 - [Repository contents](#repository-contents)
 - [Prerequisites](#prerequisites)
 - [Tests preparation](#tests-preparation)
+    - [Test Cases](#test-cases)
     - [Running Simuation](#running-simulation)
 - [Tool sets](#tool-sets)
 - [News](#news)
@@ -193,41 +194,41 @@
   <tr align="center"> <td> ATMGA328 Pin No</td> <td> Functionality           </td> <td> Arudino Pin Name</td> <td> Carvel Pin Mapping                   </td></tr>
   <tr align="center"> <td> Pin-1           </td> <td> PC6/RESET              </td> <td>                 </td> <td> digital_io[5]                        </td></tr>
   <tr align="center"> <td> Pin-2           </td> <td> PD0/RXD[0]             </td> <td>  D0             </td> <td> digital_io[6]                        </td></tr>
-  <tr align="center"> <td> Pin-3           </td> <td> PD1/TXD[0]             </td> <td>  D1             </td> <td> digital_io[7]                        </td></tr>
-  <tr align="center"> <td> Pin-4           </td> <td> PD2/RXD[1]/INT0        </td> <td>  D2             </td> <td> digital_io[8]                        </td></tr>
-  <tr align="center"> <td> Pin-5           </td> <td> PD3/INT1/OC2B(PWM0)    </td> <td>  D3             </td> <td> digital_io[9]                        </td></tr>
-  <tr align="center"> <td> Pin-6           </td> <td> PD4/TXD[1]             </td> <td>  D4             </td> <td> digital_io[10]                        </td></tr>
+  <tr align="center"> <td> Pin-3           </td> <td> PD1/TXD[0]             </td> <td>  D1             </td> <td> digital_io[7]/analog_io[0]           </td></tr>
+  <tr align="center"> <td> Pin-4           </td> <td> PD2/RXD[1]/INT0        </td> <td>  D2             </td> <td> digital_io[8]/analog_io[1]           </td></tr>
+  <tr align="center"> <td> Pin-5           </td> <td> PD3/INT1/OC2B(PWM0)    </td> <td>  D3             </td> <td> digital_io[9]/analog_io[2]           </td></tr>
+  <tr align="center"> <td> Pin-6           </td> <td> PD4/TXD[1]             </td> <td>  D4             </td> <td> digital_io[10]/analog_io[3]          </td></tr>
   <tr align="center"> <td> Pin-7           </td> <td> VCC                    </td> <td>                 </td> <td>  -                                   </td></tr>
   <tr align="center"> <td> Pin-8           </td> <td> GND                    </td> <td>                 </td> <td>  -                                   </td></tr>
-  <tr align="center"> <td> Pin-9           </td> <td> PB6/XTAL1/TOSC1        </td> <td>                 </td> <td> digital_io[11]                        </td></tr>
-  <tr align="center"> <td> Pin-10          </td> <td> PB7/XTAL2/TOSC2        </td> <td>                 </td> <td> digital_io[12]                        </td></tr>
-  <tr align="center"> <td> Pin-11          </td> <td> PD5/SS[3]/OC0B(PWM1)/T1      </td> <td> D5        </td> <td> digital_io[13]                        </td></tr>
-  <tr align="center"> <td> Pin-12          </td> <td> PD6/SS[2]/OC0A(PWM2)/AIN0    </td> <td> D6        </td> <td> digital_io[14] /analog_io[2]          </td></tr>
-  <tr align="center"> <td> Pin-13          </td> <td> PD7/A1N1               </td> <td> D7              </td> <td> digital_io[15]/analog_io[3]          </td></tr>
-  <tr align="center"> <td> Pin-14          </td> <td> PB0/CLKO/ICP1          </td> <td> D8              </td> <td> digital_io[16]                       </td></tr>
-  <tr align="center"> <td> Pin-15          </td> <td> PB1/SS[1]OC1A(PWM3)         </td> <td> D9         </td> <td> digital_io[17]                       </td></tr>
-  <tr align="center"> <td> Pin-16          </td> <td> PB2/SS[0]/OC1B(PWM4)      </td> <td> D10          </td> <td> digital_io[18]                       </td></tr>
-  <tr align="center"> <td> Pin-17          </td> <td> PB3/MOSI/OC2A(PWM5)    </td> <td> D11             </td> <td> digital_io[19]                       </td></tr>
-  <tr align="center"> <td> Pin-18          </td> <td> PB4/MISO               </td> <td> D12             </td> <td> digital_io[20]                       </td></tr>
-  <tr align="center"> <td> Pin-19          </td> <td> PB5/SCK                </td> <td> D13             </td> <td> digital_io[21]                       </td></tr>
+  <tr align="center"> <td> Pin-9           </td> <td> PB6/XTAL1/TOSC1        </td> <td>                 </td> <td> digital_io[11]/analog_io[4]          </td></tr>
+  <tr align="center"> <td> Pin-10          </td> <td> PB7/XTAL2/TOSC2        </td> <td>                 </td> <td> digital_io[12]/analog_io[5]          </td></tr>
+  <tr align="center"> <td> Pin-11          </td> <td> PD5/SS[3]/OC0B(PWM1)/T1      </td> <td> D5        </td> <td> digital_io[13]/analog_io[6]          </td></tr>
+  <tr align="center"> <td> Pin-12          </td> <td> PD6/SS[2]/OC0A(PWM2)/AIN0    </td> <td> D6        </td> <td> digital_io[14]/analog_io[7]          </td></tr>
+  <tr align="center"> <td> Pin-13          </td> <td> PD7/A1N1               </td> <td> D7              </td> <td> digital_io[15]/analog_io[8]          </td></tr>
+  <tr align="center"> <td> Pin-14          </td> <td> PB0/CLKO/ICP1          </td> <td> D8              </td> <td> digital_io[16]/analog_io[9]          </td></tr>
+  <tr align="center"> <td> Pin-15          </td> <td> PB1/SS[1]OC1A(PWM3)         </td> <td> D9         </td> <td> digital_io[17]/analog_io[10]         </td></tr>
+  <tr align="center"> <td> Pin-16          </td> <td> PB2/SS[0]/OC1B(PWM4)      </td> <td> D10          </td> <td> digital_io[18]/analog_io[11]         </td></tr>
+  <tr align="center"> <td> Pin-17          </td> <td> PB3/MOSI/OC2A(PWM5)    </td> <td> D11             </td> <td> digital_io[19]/analog_io[12]         </td></tr>
+  <tr align="center"> <td> Pin-18          </td> <td> PB4/MISO               </td> <td> D12             </td> <td> digital_io[20]/analog_io[13]         </td></tr>
+  <tr align="center"> <td> Pin-19          </td> <td> PB5/SCK                </td> <td> D13             </td> <td> digital_io[21]/analog_io[14]         </td></tr>
   <tr align="center"> <td> Pin-20          </td> <td> AVCC                   </td> <td>                 </td> <td> -                                    </td></tr>
-  <tr align="center"> <td> Pin-21          </td> <td> AREF                   </td> <td>                 </td> <td> analog_io[10]                        </td></tr>
+  <tr align="center"> <td> Pin-21          </td> <td> AREF                   </td> <td>                 </td> <td> analog_io[23]                        </td></tr>
   <tr align="center"> <td> Pin-22          </td> <td> GND                    </td> <td>                 </td> <td> -                                    </td></tr>
-  <tr align="center"> <td> Pin-23          </td> <td> PC0/uartm_rxd/ADC0     </td> <td>  A0             </td> <td> digital_io[22]/analog_io[11]         </td></tr>
-  <tr align="center"> <td> Pin-24          </td> <td> PC1/uartm/ADC1         </td> <td>  A1             </td> <td> digital_io[23]/analog_io[12]         </td></tr>
-  <tr align="center"> <td> Pin-25          </td> <td> PC2/usb_dp/ADC2        </td> <td>  A2             </td> <td> digital_io[24]/analog_io[13]         </td></tr>
-  <tr align="center"> <td> Pin-26          </td> <td> PC3/usb_dn/ADC3        </td> <td>  A3             </td> <td> digital_io[25]/analog_io[14]         </td></tr>
-  <tr align="center"> <td> Pin-27          </td> <td> PC4/ADC4/SDA           </td> <td>  A4             </td> <td> digital_io[26]/analog_io[15]         </td></tr>
-  <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[27]/analog_io[16]         </td></tr>
+  <tr align="center"> <td> Pin-23          </td> <td> PC0/uartm_rxd/ADC0     </td> <td>  A0             </td> <td> digital_io[22]/analog_io[15]         </td></tr>
+  <tr align="center"> <td> Pin-24          </td> <td> PC1/uartm/ADC1         </td> <td>  A1             </td> <td> digital_io[23]/analog_io[16]         </td></tr>
+  <tr align="center"> <td> Pin-25          </td> <td> PC2/usb_dp/ADC2        </td> <td>  A2             </td> <td> digital_io[24]/analog_io[17]         </td></tr>
+  <tr align="center"> <td> Pin-26          </td> <td> PC3/usb_dn/ADC3        </td> <td>  A3             </td> <td> digital_io[25]/analog_io[18]         </td></tr>
+  <tr align="center"> <td> Pin-27          </td> <td> PC4/ADC4/SDA           </td> <td>  A4             </td> <td> digital_io[26]/analog_io[19]         </td></tr>
+  <tr align="center"> <td> Pin-28          </td> <td> PC5/ADC5/SCL           </td> <td>  A5             </td> <td> digital_io[27]/analog_io[20]         </td></tr>
   <tr align="center"> <td colspan="4">   Additional Pad used for Externam ROM/RAM/USB </td></tr>
-  <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[28]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[29]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1             </td> <td>                 </td> <td> digital_io[30]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[31]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[32]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[33]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[34]                       </td></tr>
-  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[35]                       </td></tr>
+  <tr align="center"> <td> Sflash          </td> <td> sflash_sck             </td> <td>                 </td> <td> digital_io[28]/Analog[21]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss0             </td> <td>                 </td> <td> digital_io[29]/Analog[22]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss1/AREF        </td> <td>                 </td> <td> digital_io[30]/Analog[23]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss2             </td> <td>                 </td> <td> digital_io[31]/Analog[24]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_ss3             </td> <td>                 </td> <td> digital_io[32]/Analog[25]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io0             </td> <td>                 </td> <td> digital_io[33]/Analog[26]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io1             </td> <td>                 </td> <td> digital_io[34]/Analog[27]            </td></tr>
+  <tr align="center"> <td> SFlash          </td> <td> sflash_io2             </td> <td>                 </td> <td> digital_io[35]/Analog[28]            </td></tr>
   <tr align="center"> <td> SFlash          </td> <td> sflash_io3             </td> <td>                 </td> <td> digital_io[36]                       </td></tr>
   <tr align="center"> <td> DEBUG           </td> <td> dbg_clk_mon            </td> <td>                 </td> <td> digital_io[37]                       </td></tr>
   <tr align="center"> <td> SPARE           </td> <td> PA0                    </td> <td>                 </td> <td> digital_io[0]                       </td></tr>
@@ -557,6 +558,67 @@
    make user_project_wrapper
 ```
 
+#Timing Analysis
+## Timing Analysis setup
+   
+``` sh
+   make setup-timing-scripts
+   make install
+   make install_mcw
+```
+his will update Caravel design files and install the scripts for running timing.
+
+## Running Timing Analysis
+
+``` sh
+make extract-parasitics
+make create-spef-mapping
+make caravel-sta
+```
+#Other Miscellaneous Targets
+The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow.
+
+Run make help to display available targets.
+
+Run lvs on the mag view,
+
+``` sh
+make lvs-<macro_name>
+```
+
+Run lvs on the gds,
+
+``` sh
+make lvs-gds-<macro_name>
+```
+
+Run lvs on the maglef,
+
+``` sh
+make lvs-maglef-<macro_name>
+```
+
+Run drc using magic,
+
+``` sh
+make drc-<macro_name>
+```
+
+Run antenna check using magic,
+
+``` sh
+make antenna-<macro_name>
+```
+
+Run XOR check,
+
+``` sh
+make xor-wrapper
+```
+
+
+
+
 # Tool Sets
 
 Riscduino Soc flow uses Openlane tool sets.
diff --git a/deps/timing-scripts/scripts/openroad/timing_top.tcl b/deps/timing-scripts/scripts/openroad/timing_top.tcl
index 46bd876..03082ff 100644
--- a/deps/timing-scripts/scripts/openroad/timing_top.tcl
+++ b/deps/timing-scripts/scripts/openroad/timing_top.tcl
@@ -64,7 +64,7 @@
     -format full_clock_expanded \\
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
-    -group_count 10000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -endpoint_count 10 \\
@@ -77,7 +77,7 @@
     -format full_clock_expanded \\
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
-    -group_count 10000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -endpoint_count 10 \\
@@ -91,7 +91,7 @@
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
     -path_group hk_serial_clk \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -105,7 +105,7 @@
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
     -path_group hk_serial_clk \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -118,7 +118,7 @@
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
     -path_group hkspi_clk \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -131,7 +131,7 @@
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
     -path_group hkspi_clk \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -144,7 +144,7 @@
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
     -path_group clk \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -157,7 +157,7 @@
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
     -path_group clk \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -170,7 +170,7 @@
     -format full_clock_expanded \\
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -183,7 +183,7 @@
     -format full_clock_expanded \\
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 10 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -196,7 +196,7 @@
     -format full_clock_expanded \\
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 40 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
@@ -209,7 +209,7 @@
     -format full_clock_expanded \\
     -fields {slew cap input_pins nets fanout} \\
     -no_line_splits \\
-    -group_count 1000 \\
+    -group_count 100 \\
     -slack_max 40 \\
     -digits 4 \\
     -unique_paths_to_endpoint \\
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index a9eaeb9..1334cec 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index a35e7d6..fc30bce 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/pinmux_top/base.sdc b/openlane/pinmux_top/base.sdc
index 9c22d9c..e642e15 100644
--- a/openlane/pinmux_top/base.sdc
+++ b/openlane/pinmux_top/base.sdc
@@ -7,7 +7,32 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name mclk -period 10.0000 [get_ports {mclk}]
-set_propagated_clock [get_clocks {mclk}]
+create_clock -name user_clock1 -period 10.0000 [get_ports {user_clock1}]
+create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}]
+create_clock -name int_pll_clock -period 5.0000  [get_pins {int_pll_clock}]
+create_clock -name rtc_ref_clk -period 50.0000  [get_pins {u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk     -period 50.0000  [get_pins {u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+create_clock -name usb_ref_clk -period 5.0000   [get_pins {u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+
+set_clock_groups \
+   -name clock_group \
+   -logically_exclusive \
+   -group [get_clocks {mclk}]\
+   -group [get_clocks {user_clock1}]\
+   -group [get_clocks {user_clock2}]\
+   -group [get_clocks {int_pll_clock}]\
+   -group [get_clocks {rtc_ref_clk}]\
+   -group [get_clocks {rtc_clk}]\
+   -group [get_clocks {usb_ref_clk}]\
+   -group [get_clocks {dbg_ref_clk}]\
+   -comment {Async Clock group}
+
+
+
+set_propagated_clock [all_clocks]
+
 
 set_clock_transition 0.1500 [all_clocks]
 set_clock_uncertainty -setup 0.5000 [all_clocks]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 8329788..960f746 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -93,7 +93,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 520 850"
+set ::env(DIE_AREA) "0 0 520 900"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -103,9 +103,9 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.38"
+set ::env(PL_TARGET_DENSITY) "0.35"
 set ::env(CELL_PAD) "8"
-set ::env(GRT_ADJUSTMENT) {0.2}
+#set ::env(GRT_ADJUSTMENT) {0.2}
 
 
 ######################################################################################
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2c_usb_spi_top/base.sdc
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/base.sdc
rename to openlane/uart_i2c_usb_spi_top/base.sdc
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2c_usb_spi_top/config.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/config.tcl
rename to openlane/uart_i2c_usb_spi_top/config.tcl
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/uart_i2c_usb_spi_top/pdn.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/pdn.tcl
rename to openlane/uart_i2c_usb_spi_top/pdn.tcl
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/pin_order.cfg
rename to openlane/uart_i2c_usb_spi_top/pin_order.cfg
diff --git a/openlane/uart_i2cm_usb_spi_top/sta.tcl b/openlane/uart_i2c_usb_spi_top/sta.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/sta.tcl
rename to openlane/uart_i2c_usb_spi_top/sta.tcl
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 8a06191..e1f03c7 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -107,6 +107,7 @@
 	$gds_root/ycr2_iconnect.gds \
 	$gds_root/dg_pll.gds \
 	$gds_root/dac_top.gds \
+	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
 	$gds_root/aes_top.gds \
 	$gds_root/fpu_wrapper.gds \
 	"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index b4c0b35..c654abd 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -85,7 +85,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 425"
+set ::env(DIE_AREA) "0 0 425 425"
 
 set ::env(GRT_OBS) "                              \
 	                met4  0 0 400 425"
@@ -121,7 +121,7 @@
 
 
 #LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_EXT_USE_GDS) {1}
 
 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8c93e59..8ac589d 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -3,12 +3,6 @@
 #MANUAL_PLACE
 
 
-#W
-
-cpu_clk               0100 0 2
-
-
-
 #S
 user_clock2         0000 0  2
 user_clock1     
@@ -158,16 +152,8 @@
 
 
 #N
-cfg_clk_skew_ctrl2\[31\]   0000 0 2 
-cfg_clk_skew_ctrl2\[30\]
-cfg_clk_skew_ctrl2\[29\]
-cfg_clk_skew_ctrl2\[28\]
-cfg_clk_skew_ctrl2\[27\]
-cfg_clk_skew_ctrl2\[26\]
-cfg_clk_skew_ctrl2\[25\]
-cfg_clk_skew_ctrl2\[24\]
 
-cfg_clk_skew_ctrl1\[31\]
+cfg_clk_skew_ctrl1\[31\]   0000 0 2
 cfg_clk_skew_ctrl1\[30\]
 cfg_clk_skew_ctrl1\[29\]
 cfg_clk_skew_ctrl1\[28\]
@@ -181,7 +167,9 @@
 cfg_clk_skew_ctrl1\[4\]
 cfg_cska_wh\[0\]
 
-wbd_int_rst_n              0100 0 2
+cpu_clk                    0100 0 2
+
+wbd_int_rst_n              0120 0 2
 cfg_clk_skew_ctrl2\[23\]
 cfg_clk_skew_ctrl2\[22\]
 cfg_clk_skew_ctrl2\[21\]
@@ -347,7 +335,16 @@
 wbs_cyc_o      
 
 
-strap_sticky\[31\] 325 0 2
+cfg_clk_skew_ctrl2\[31\]   325 0 2 
+cfg_clk_skew_ctrl2\[30\]
+cfg_clk_skew_ctrl2\[29\]
+cfg_clk_skew_ctrl2\[28\]
+cfg_clk_skew_ctrl2\[27\]
+cfg_clk_skew_ctrl2\[26\]
+cfg_clk_skew_ctrl2\[25\]
+cfg_clk_skew_ctrl2\[24\]
+
+strap_sticky\[31\] 
 strap_sticky\[30\]
 strap_sticky\[29\]
 strap_sticky\[28\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index dffa9f4..f169b0e 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -30,6 +30,8 @@
 set ::env(CLOCK_NET) "clk_i"
 
 set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
 
 ## CTS BUFFER
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
@@ -51,7 +53,7 @@
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=14\
 	                 CH_DATA_WD=154 \
 			 "
 
@@ -102,7 +104,7 @@
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000"
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 7038097..e2344a5 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,7 +3,19 @@
 #MANUAL_PLACE
 
 #S
-rst_n                000  0 2
+ch_clk_in\[13\]  000 0 2
+ch_clk_in\[12\]
+ch_clk_in\[11\]
+ch_clk_in\[10\]
+ch_clk_in\[9\]
+ch_clk_in\[8\]
+ch_clk_in\[7\]
+ch_clk_in\[6\]
+ch_clk_in\[5\]
+ch_clk_in\[4\]
+
+
+rst_n                020  0 2
 ch_data_in\[43\]
 ch_data_in\[42\]
 ch_data_in\[41\]
@@ -260,6 +272,7 @@
 ch_data_out\[22\] 
 ch_data_out\[21\] 
 ch_data_out\[20\] 
+ch_clk_out\[4\]
 
 ch_data_out\[3\]   050 0 2
 ch_data_out\[2\]
@@ -587,19 +600,28 @@
 ch_data_out\[42\] 
 ch_data_out\[41\] 
 ch_data_out\[40\] 
+ch_clk_out\[9\]
+
 ch_data_out\[39\] 
 ch_data_out\[38\] 
 ch_data_out\[37\] 
 ch_data_out\[36\] 
+ch_clk_out\[8\]
+
 ch_data_out\[35\] 
 ch_data_out\[34\] 
 ch_data_out\[33\] 
 ch_data_out\[32\] 
+
+ch_clk_out\[7\]
+
 ch_data_out\[31\] 
 ch_data_out\[30\] 
 ch_data_out\[29\] 
 ch_data_out\[28\] 
 
+ch_clk_out\[6\]
+
 ch_data_out\[76\]   1600 0 2
 ch_data_out\[75\] 
 ch_data_out\[74\] 
@@ -638,16 +660,19 @@
 ch_data_out\[26\] 
 ch_data_out\[25\] 
 ch_data_out\[24\] 
+ch_clk_out\[5\]
 
-ch_data_out\[153\]  1700 0 2
-ch_data_out\[152\]  
-ch_data_out\[151\]  
-ch_data_out\[150\]  
-
-ch_data_out\[149\]  
+ch_data_out\[149\]  1700 0 2
 ch_data_out\[148\]  
 ch_data_out\[147\]  
 ch_data_out\[146\]  
+ch_clk_out\[10\]
+
+ch_data_out\[153\]  1750 0 2
+ch_data_out\[152\]  
+ch_data_out\[151\]  
+ch_data_out\[150\]  
+ch_clk_out\[11\]
 
 #E
 ch_data_out\[19\]   0000 0  2  
@@ -1064,4 +1089,6 @@
 s2_wbd_ack_i        
 s2_wbd_cyc_o        
 
+ch_clk_out\[12\]
+ch_clk_out\[13\]
 
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl
index b1a49b0..b1f625e 100644
--- a/openlane/ycr2_iconnect/config.tcl
+++ b/openlane/ycr2_iconnect/config.tcl
@@ -23,7 +23,7 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "core_clk rtc_clk"
+set ::env(CLOCK_PORT) "u_cclk_cts.genblk1.u_mux/X rtc_clk"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 679443f..70129d1 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -13,30 +13,30 @@
 set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 
 #IMEM Constraints
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
 
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
 
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
 
 #DMEM Constraints
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
-set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
 
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
@@ -44,9 +44,9 @@
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
 
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 7.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
 
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
 set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index 222f71f..f3daaa8 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,6 +1,21 @@
 #BUS_SORT
 #MANUAL_PLACE
 #E
+pwrup_rst_n       
+rst_n
+
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+
+clk
+clk_o
+core_rst_n_o
+core_rdc_qlfy_o
+
 core_uid\[1\]              0200 00 2
 core_uid\[0\]   
 imem2core_req_ack_i
@@ -331,19 +346,3 @@
 core_irq_soft_i
 cpu_rst_n
 
-#S
-pwrup_rst_n       
-rst_n
-
-
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-
-clk
-clk_o
-core_rst_n_o
-core_rdc_qlfy_o
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
index b321d37..fabca1a 100644
--- a/signoff/pinmux_top/OPENLANE_VERSION
+++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 9949f5d5f55749dc4b98648a25d355836895dc37
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
index 59f6ae6..ef91c87 100644
--- a/signoff/pinmux_top/PDK_SOURCES
+++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index b321d37..fabca1a 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 9949f5d5f55749dc4b98648a25d355836895dc37
+OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index 59f6ae6..ef91c87 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f
+open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 639e350..6f91eae 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -165,7 +165,7 @@
                 tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
                                                uart_stick_parity, uart_timeout, uart_divisor);
 
-                repeat (5000) @(posedge clock);  // wait for Processor Get Ready
+                repeat (8000) @(posedge clock);  // wait for Processor Get Ready
 	        flag  = 1;
                 
                 
diff --git a/verilog/dv/common/agents/caravel_task.sv b/verilog/dv/common/agents/caravel_task.sv
index 70ff764..3937734 100644
--- a/verilog/dv/common/agents/caravel_task.sv
+++ b/verilog/dv/common/agents/caravel_task.sv
@@ -13,9 +13,9 @@
 ****/
 
 `ifdef RISC_BOOT // RISCV Based Test case
-parameter bit  [15:0] PAD_STRAP = 16'b0000_0001_1011_0000;
+parameter bit  [15:0] PAD_STRAP = 16'b0000_0001_1010_0000;
 `else
-parameter bit  [15:0] PAD_STRAP = 16'b0000_0000_1011_0000;
+parameter bit  [15:0] PAD_STRAP = 16'b0000_0000_1010_0000;
 `endif
 
 /***********************************************
diff --git a/verilog/dv/common/agents/usb_agents.v b/verilog/dv/common/agents/usb_agents.v
index c266567..4d144d0 100644
--- a/verilog/dv/common/agents/usb_agents.v
+++ b/verilog/dv/common/agents/usb_agents.v
@@ -274,7 +274,7 @@
 input [15:0] value; 
 input [15:0] index; 
 input [15:0] length;
-output       status;
+output[7:0]  status;
 reg   [7:0]  status;
 integer idx;
 begin
diff --git a/verilog/dv/common/bfm/bfm_spim.v b/verilog/dv/common/bfm/bfm_spim.v
index f04f8b9..2bf556f 100644
--- a/verilog/dv/common/bfm/bfm_spim.v
+++ b/verilog/dv/common/bfm/bfm_spim.v
@@ -172,8 +172,7 @@
 endtask
 // Write 4 Byte
 task send_dword;
-input dword;
-reg [31:0] dword;
+input [31:0] dword;
 begin
   send_word(dword[31:16]);
   send_word(dword[15:0]);
@@ -182,8 +181,7 @@
 
 // Write 2 Byte
 task send_word;
-input word;
-reg [15:0] word;
+input [15:0] word;
 begin
   send_byte(word[15:8]);
   send_byte(word[7:0]);
@@ -194,8 +192,7 @@
 
 // Write 1 Byte
 task send_byte;
-input data;
-reg [7:0] data;
+input [7:0] data;
 integer i;
 begin
 
@@ -217,7 +214,7 @@
 
 // READ 4 BYTE
 task receive_dword;
-output dword;
+output [31:0] dword;
 reg [31:0] dword;
 begin
   receive_word(dword[31:16]);
@@ -227,7 +224,7 @@
 
 // READ 2 BYTE
 task receive_word;
-output word;
+output [15:0] word;
 reg [15:0] word;
 begin
   receive_byte(word[15:8]);
@@ -239,7 +236,7 @@
 
 // READ 1 BYTE
 task receive_byte;
-output data;
+output [7:0] data;
 reg [7:0] data;
 integer i;
 begin
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index db9d549..758f0ed 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -165,11 +165,11 @@
 ## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+	iverilog -g2012 -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+	iverilog -g2012 -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 51bde45..ef56ee4 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -18,18 +18,17 @@
 ////                                                              ////
 ////  User Risc Core Boot Validation                              ////
 ////                                                              ////
-////  This file is part of the YIFive cores project               ////
-////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscuino.git               ////
+////  http://www.opencores.org/cores/riscuino/                    ////
 ////                                                              ////
 ////  Description                                                 ////
-////     1. User Risc core is booted using  compiled code of      ////
-////        user_risc_boot.hex                                    ////
-////     2. User Risc core uses Serial Flash and SDRAM to boot    ////
-////     3. After successful boot, Risc core will  write signature////
-////        in to  user register from 0x3000_0018 to 0x3000_002C  ////
-////     4. Through the External Wishbone Interface we read back  ////
-////         and validate the user register to declared pass fail ////
+////    1. Strap is set to RISC core auto Boot mode               ////
+////    2. With Reset removal from caravel, User core boot up     ////
+////    3. Risc-V firmware have UART Loop back mode               ////
+////    4. Any UART Data Transmited by testbench will be loop back////
+////    5. There are 40 Random char are transmited and compared   ////
+////       againt received data                                   ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -132,9 +131,10 @@
            $dumpfile("simx.vcd");
            $dumpvars(1,risc_boot_tb);
            //$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
-           $dumpvars(2,risc_boot_tb.u_top);
+           //$dumpvars(2,risc_boot_tb.u_top);
            $dumpvars(1,risc_boot_tb.u_top.mprj);
            $dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host);
+           $dumpvars(0,risc_boot_tb.u_top.mprj.u_pinmux);
            //$dumpvars(0,risc_boot_tb.tb_uart);
            //$dumpvars(0,risc_boot_tb.u_user_spiflash);
 	   $display("Waveform Dump started");
@@ -165,7 +165,7 @@
 
  $value$plusargs("risc_core_id=%d", d_risc_id);
 
-   init();
+         init();
 
            uart_data_bit           = 2'b11;
            uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
@@ -186,7 +186,7 @@
 					     uart_stick_parity, uart_timeout, uart_divisor);
 
 
-                wait_riscv_boot();
+        wait_riscv_boot();
 		repeat (50000) @(posedge clock);  
 
 		for (i=0; i<40; i=i+1)
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index d52ebf4..c3e3679 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -15,7 +15,7 @@
 
 export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 ## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
 GCC_PREFIX?=riscv64-unknown-elf
 
 
diff --git a/verilog/dv/uart_master_test2/uart_master_test2_tb.v b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
index 257363e..b757926 100644
--- a/verilog/dv/uart_master_test2/uart_master_test2_tb.v
+++ b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
@@ -19,7 +19,7 @@
 `include "uart_agent.v"
 
 `define TB_HEX "uart_master.hex"
-`define TB_TOP  uart_master_tb
+`define TB_TOP  uart_master_test2
 module `TB_TOP;
 	reg clock;
 	reg RSTB;
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index c4b27a9..5b52174 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -68,7 +68,7 @@
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "i2c_slave_model.v"
 
-module tb_top;
+module user_i2cm_tb;
 parameter real CLK1_PERIOD  = 20; // 50Mhz
 parameter real CLK2_PERIOD = 2.5;
 parameter real IPLL_PERIOD = 5.008;
@@ -88,7 +88,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(0, tb_top);
+	   	$dumpvars(0, user_i2cm_tb);
 	   end
        `endif
 
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 25cbfd3..57d6802 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -145,7 +145,7 @@
 	                          uart_stick_parity, uart_timeout, uart_divisor);
 
 
-    tb_master_uart.write_char('\n'); // for uart baud auto detect purpose
+    tb_master_uart.write_char(8'h0A); // for uart baud auto detect purpose - New Line Character \n
    //$write ("\n(%t)Response:\n",$time);
    flag = 0;
    while(flag == 0)
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 2bc86d8..955a572 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -33,10 +33,20 @@
 int i = 0; 
 int clk = 0;
 
+void putdword(uint32_t Data)
+{
+	reg_uart_data = Data >> 24; // MSB [31:24];
+	reg_uart_data = Data >> 16; // MSB [23:16];
+	reg_uart_data = Data >> 8;  // MSB [15:8];
+	reg_uart_data = Data;       // MSB [7:0];
+}
+
+
 void main()
 {
 
 	int bFail = 0;
+    char DataIn[5];
 	/* 
 	IO Control Registers
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
@@ -127,4 +137,5 @@
     } else {
         reg_mprj_datal = 0xAB600000;
     }
+    putdword(reg_mprj_datal);
 }
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 28c2ee8..3dab8e7 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index d4ae6a0..ba50ccf 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2011_2022;
+parameter CHIP_RELEASE_DATE = 32'h2511_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0005_8000;
+parameter CHIP_REVISION   = 32'h0005_9000;
 
 parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_1100_1010_1010_1001_0011;
 parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0000_0000_0000_0000_0000_0111;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8a938e9..7a38583 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -285,6 +285,9 @@
 ////         B. FPU Integration                                   ////
 ////    5.8  Nov 20, 2022, Dinesh A                               ////
 ////         A. Pinmux - Double Sync added for usb & i2c inter    ////
+////    5.9  Nov 25, 2022, Dinesh A                               ////
+////         cpu_clk will be feed through wb_interconnect for     ////
+////         buffering purpose                                    ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -871,6 +874,19 @@
 
 wire   int_pll_clock       = pll_clk_out[0];
 
+//-------------------------------------
+// cpu clock repeater mapping
+//-------------------------------------
+wire [9:0] cpu_clk_rp;
+
+wire [5:0] cpu_clk_rp_risc   = cpu_clk_rp[5:0];
+wire       cpu_clk_rp_aes    = cpu_clk_rp[6];
+wire       cpu_clk_rp_fpu    = cpu_clk_rp[7];
+wire       cpu_clk_rp_pinmux = cpu_clk_rp[8];
+
+
+
+
 /***********************************************
  Wishbone HOST
 *************************************************/
@@ -994,7 +1010,7 @@
 	  .cfg_bypass_dcache       (cfg_bypass_dcache       ),
 
     // Clock
-          .core_clk_int            (cpu_clk                    ),
+          .core_clk_int            (cpu_clk_rp_risc            ),
           .cfg_ccska_riscv_intf    (cfg_ccska_riscv_intf_rp    ),
           .cfg_ccska_riscv_icon    (cfg_ccska_riscv_icon_rp    ),
           .cfg_ccska_riscv_core0   (cfg_ccska_riscv_core0_rp   ),
@@ -1222,15 +1238,15 @@
 *************************************************/
 aes_top u_aes (
 `ifdef USE_POWER_PINS
-    .vccd1                 (vdda1                  ),
-    .vssd1                 (vssa1                  ),
+    .vccd1                 (vdda1            ),
+    .vssd1                 (vssa1            ),
 `endif
 
     .mclk                  (cpu_clk_aes      ),
     .rst_n                 (cpu_intf_rst_n   ),
 
     .cfg_cska              (cfg_ccska_aes_rp ),
-    .wbd_clk_int           (cpu_clk          ),
+    .wbd_clk_int           (cpu_clk_rp_aes   ),
     .wbd_clk_out           (cpu_clk_aes      ),
 
     .dmem_req              (aes_dmem_req     ),
@@ -1256,7 +1272,7 @@
     .rst_n                 (cpu_intf_rst_n   ),
 
     .cfg_cska              (cfg_ccska_fpu_rp ),
-    .wbd_clk_int           (cpu_clk          ),
+    .wbd_clk_int           (cpu_clk_rp_fpu   ),
     .wbd_clk_out           (cpu_clk_fpu      ),
 
     .dmem_req              (fpu_dmem_req     ),
@@ -1328,7 +1344,7 @@
 
 wb_interconnect  #(
 	`ifndef SYNTHESIS
-          .CH_CLK_WD           (4                       ),
+          .CH_CLK_WD           (14                      ),
 	      .CH_DATA_WD          (154                     )
         `endif
 	) u_intercon (
@@ -1337,11 +1353,22 @@
           .vssd1                   (vssd1                   ),// User area 1 digital ground
 `endif
 	  .ch_clk_in               ({
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
+                                     cpu_clk,
                                      wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int}                  ),
 	  .ch_clk_out              ({
+                                     cpu_clk_rp,
                                      wbd_clk_pinmux_rp, 
                                      wbd_clk_uart_rp, 
                                      wbd_clk_qspi_rp, 
@@ -1583,7 +1610,7 @@
           .user_clock2             (user_clock2             ),
           .int_pll_clock           (int_pll_clock           ),
           .xtal_clk                (xtal_clk                ),
-          .cpu_clk                 (cpu_clk                 ),
+          .cpu_clk                 (cpu_clk_rp_pinmux       ),
 
 
           .rtc_clk                 (rtc_clk                 ),