diff --git a/verilog/dv/can_test_1/Makefile b/verilog/dv/can_test_1/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/can_test_1/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/can_test_1/YONGA_CAN_IP_regs.h b/verilog/dv/can_test_1/YONGA_CAN_IP_regs.h
new file mode 100644
index 0000000..89b992a
--- /dev/null
+++ b/verilog/dv/can_test_1/YONGA_CAN_IP_regs.h
@@ -0,0 +1,188 @@
+// -----------------------------------------------------------------------------
+// 'YONGA_CAN_IP' Register Definitions
+// Revision: 68
+// -----------------------------------------------------------------------------
+// Generated on 2022-09-07 at 10:18 (UTC) by airhdl version 2022.08.2-618538036
+// -----------------------------------------------------------------------------
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+// -----------------------------------------------------------------------------
+
+#ifndef YONGA_CAN_IP_REGS_H
+#define YONGA_CAN_IP_REGS_H
+
+/* Revision number of the 'YONGA_CAN_IP' register map */
+#define YONGA_CAN_IP_REVISION 68
+
+/* Default base address of the 'YONGA_CAN_IP' register map */
+#define YONGA_CAN_IP_DEFAULT_BASEADDR 0xA0000000
+
+/* Size of the 'YONGA_CAN_IP' register map, in bytes */
+#define YONGA_CAN_IP_RANGE_BYTES 28
+
+/* Register 'BAUD_RATE_CFG' */
+#define BAUD_RATE_CFG_OFFSET 0x00000000 /* address offset of the 'BAUD_RATE_CFG' register */
+
+/* Field  'BAUD_RATE_CFG.TSEG2' */
+#define BAUD_RATE_CFG_TSEG2_BIT_OFFSET 0 /* bit offset of the 'TSEG2' field */
+#define BAUD_RATE_CFG_TSEG2_BIT_WIDTH 9 /* bit width of the 'TSEG2' field */
+#define BAUD_RATE_CFG_TSEG2_BIT_MASK 0x000001FF /* bit mask of the 'TSEG2' field */
+#define BAUD_RATE_CFG_TSEG2_RESET 0x0 /* reset value of the 'TSEG2' field */
+
+/* Field  'BAUD_RATE_CFG.TSEG1' */
+#define BAUD_RATE_CFG_TSEG1_BIT_OFFSET 9 /* bit offset of the 'TSEG1' field */
+#define BAUD_RATE_CFG_TSEG1_BIT_WIDTH 9 /* bit width of the 'TSEG1' field */
+#define BAUD_RATE_CFG_TSEG1_BIT_MASK 0x0003FE00 /* bit mask of the 'TSEG1' field */
+#define BAUD_RATE_CFG_TSEG1_RESET 0x0 /* reset value of the 'TSEG1' field */
+
+/* Field  'BAUD_RATE_CFG.BRP' */
+#define BAUD_RATE_CFG_BRP_BIT_OFFSET 18 /* bit offset of the 'BRP' field */
+#define BAUD_RATE_CFG_BRP_BIT_WIDTH 9 /* bit width of the 'BRP' field */
+#define BAUD_RATE_CFG_BRP_BIT_MASK 0x07FC0000 /* bit mask of the 'BRP' field */
+#define BAUD_RATE_CFG_BRP_RESET 0x0 /* reset value of the 'BRP' field */
+
+/* Field  'BAUD_RATE_CFG.SJW' */
+#define BAUD_RATE_CFG_SJW_BIT_OFFSET 27 /* bit offset of the 'SJW' field */
+#define BAUD_RATE_CFG_SJW_BIT_WIDTH 5 /* bit width of the 'SJW' field */
+#define BAUD_RATE_CFG_SJW_BIT_MASK 0xF8000000 /* bit mask of the 'SJW' field */
+#define BAUD_RATE_CFG_SJW_RESET 0x0 /* reset value of the 'SJW' field */
+
+/* Register 'MSG_ID' */
+#define MSG_ID_OFFSET 0x00000004 /* address offset of the 'MSG_ID' register */
+
+/* Field  'MSG_ID.EID' */
+#define MSG_ID_EID_BIT_OFFSET 0 /* bit offset of the 'EID' field */
+#define MSG_ID_EID_BIT_WIDTH 18 /* bit width of the 'EID' field */
+#define MSG_ID_EID_BIT_MASK 0x0003FFFF /* bit mask of the 'EID' field */
+#define MSG_ID_EID_RESET 0x0 /* reset value of the 'EID' field */
+
+/* Field  'MSG_ID.IDE' */
+#define MSG_ID_IDE_BIT_OFFSET 18 /* bit offset of the 'IDE' field */
+#define MSG_ID_IDE_BIT_WIDTH 1 /* bit width of the 'IDE' field */
+#define MSG_ID_IDE_BIT_MASK 0x00040000 /* bit mask of the 'IDE' field */
+#define MSG_ID_IDE_RESET 0x0 /* reset value of the 'IDE' field */
+
+/* Field  'MSG_ID.SID' */
+#define MSG_ID_SID_BIT_OFFSET 19 /* bit offset of the 'SID' field */
+#define MSG_ID_SID_BIT_WIDTH 11 /* bit width of the 'SID' field */
+#define MSG_ID_SID_BIT_MASK 0x3FF80000 /* bit mask of the 'SID' field */
+#define MSG_ID_SID_RESET 0x0 /* reset value of the 'SID' field */
+
+/* Register 'MSG_CFG' */
+#define MSG_CFG_OFFSET 0x00000008 /* address offset of the 'MSG_CFG' register */
+
+/* Field  'MSG_CFG.DLC' */
+#define MSG_CFG_DLC_BIT_OFFSET 0 /* bit offset of the 'DLC' field */
+#define MSG_CFG_DLC_BIT_WIDTH 4 /* bit width of the 'DLC' field */
+#define MSG_CFG_DLC_BIT_MASK 0x0000000F /* bit mask of the 'DLC' field */
+#define MSG_CFG_DLC_RESET 0x0 /* reset value of the 'DLC' field */
+
+/* Field  'MSG_CFG.RTR' */
+#define MSG_CFG_RTR_BIT_OFFSET 4 /* bit offset of the 'RTR' field */
+#define MSG_CFG_RTR_BIT_WIDTH 1 /* bit width of the 'RTR' field */
+#define MSG_CFG_RTR_BIT_MASK 0x00000010 /* bit mask of the 'RTR' field */
+#define MSG_CFG_RTR_RESET 0x0 /* reset value of the 'RTR' field */
+
+/* Register 'DATA_REG1' */
+#define DATA_REG1_OFFSET 0x0000000C /* address offset of the 'DATA_REG1' register */
+
+/* Field  'DATA_REG1.DATA_BYTE_0' */
+#define DATA_REG1_DATA_BYTE_0_BIT_OFFSET 0 /* bit offset of the 'DATA_BYTE_0' field */
+#define DATA_REG1_DATA_BYTE_0_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_0' field */
+#define DATA_REG1_DATA_BYTE_0_BIT_MASK 0x000000FF /* bit mask of the 'DATA_BYTE_0' field */
+#define DATA_REG1_DATA_BYTE_0_RESET 0x0 /* reset value of the 'DATA_BYTE_0' field */
+
+/* Field  'DATA_REG1.DATA_BYTE_1' */
+#define DATA_REG1_DATA_BYTE_1_BIT_OFFSET 8 /* bit offset of the 'DATA_BYTE_1' field */
+#define DATA_REG1_DATA_BYTE_1_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_1' field */
+#define DATA_REG1_DATA_BYTE_1_BIT_MASK 0x0000FF00 /* bit mask of the 'DATA_BYTE_1' field */
+#define DATA_REG1_DATA_BYTE_1_RESET 0x0 /* reset value of the 'DATA_BYTE_1' field */
+
+/* Field  'DATA_REG1.DATA_BYTE_2' */
+#define DATA_REG1_DATA_BYTE_2_BIT_OFFSET 16 /* bit offset of the 'DATA_BYTE_2' field */
+#define DATA_REG1_DATA_BYTE_2_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_2' field */
+#define DATA_REG1_DATA_BYTE_2_BIT_MASK 0x00FF0000 /* bit mask of the 'DATA_BYTE_2' field */
+#define DATA_REG1_DATA_BYTE_2_RESET 0x0 /* reset value of the 'DATA_BYTE_2' field */
+
+/* Field  'DATA_REG1.DATA_BYTE_3' */
+#define DATA_REG1_DATA_BYTE_3_BIT_OFFSET 24 /* bit offset of the 'DATA_BYTE_3' field */
+#define DATA_REG1_DATA_BYTE_3_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_3' field */
+#define DATA_REG1_DATA_BYTE_3_BIT_MASK 0xFF000000 /* bit mask of the 'DATA_BYTE_3' field */
+#define DATA_REG1_DATA_BYTE_3_RESET 0x0 /* reset value of the 'DATA_BYTE_3' field */
+
+/* Register 'DATA_REG2' */
+#define DATA_REG2_OFFSET 0x00000010 /* address offset of the 'DATA_REG2' register */
+
+/* Field  'DATA_REG2.DATA_BYTE_4' */
+#define DATA_REG2_DATA_BYTE_4_BIT_OFFSET 0 /* bit offset of the 'DATA_BYTE_4' field */
+#define DATA_REG2_DATA_BYTE_4_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_4' field */
+#define DATA_REG2_DATA_BYTE_4_BIT_MASK 0x000000FF /* bit mask of the 'DATA_BYTE_4' field */
+#define DATA_REG2_DATA_BYTE_4_RESET 0x0 /* reset value of the 'DATA_BYTE_4' field */
+
+/* Field  'DATA_REG2.DATA_BYTE_5' */
+#define DATA_REG2_DATA_BYTE_5_BIT_OFFSET 8 /* bit offset of the 'DATA_BYTE_5' field */
+#define DATA_REG2_DATA_BYTE_5_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_5' field */
+#define DATA_REG2_DATA_BYTE_5_BIT_MASK 0x0000FF00 /* bit mask of the 'DATA_BYTE_5' field */
+#define DATA_REG2_DATA_BYTE_5_RESET 0x0 /* reset value of the 'DATA_BYTE_5' field */
+
+/* Field  'DATA_REG2.DATA_BYTE_6' */
+#define DATA_REG2_DATA_BYTE_6_BIT_OFFSET 16 /* bit offset of the 'DATA_BYTE_6' field */
+#define DATA_REG2_DATA_BYTE_6_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_6' field */
+#define DATA_REG2_DATA_BYTE_6_BIT_MASK 0x00FF0000 /* bit mask of the 'DATA_BYTE_6' field */
+#define DATA_REG2_DATA_BYTE_6_RESET 0x0 /* reset value of the 'DATA_BYTE_6' field */
+
+/* Field  'DATA_REG2.DATA_BYTE_7' */
+#define DATA_REG2_DATA_BYTE_7_BIT_OFFSET 24 /* bit offset of the 'DATA_BYTE_7' field */
+#define DATA_REG2_DATA_BYTE_7_BIT_WIDTH 8 /* bit width of the 'DATA_BYTE_7' field */
+#define DATA_REG2_DATA_BYTE_7_BIT_MASK 0xFF000000 /* bit mask of the 'DATA_BYTE_7' field */
+#define DATA_REG2_DATA_BYTE_7_RESET 0x0 /* reset value of the 'DATA_BYTE_7' field */
+
+/* Register 'SYS_CFG' */
+#define SYS_CFG_OFFSET 0x00000014 /* address offset of the 'SYS_CFG' register */
+
+/* Field  'SYS_CFG.MODE' */
+#define SYS_CFG_MODE_BIT_OFFSET 0 /* bit offset of the 'MODE' field */
+#define SYS_CFG_MODE_BIT_WIDTH 1 /* bit width of the 'MODE' field */
+#define SYS_CFG_MODE_BIT_MASK 0x00000001 /* bit mask of the 'MODE' field */
+#define SYS_CFG_MODE_RESET 0x0 /* reset value of the 'MODE' field */
+
+/* Enumerated values for field 'SYS_CFG.MODE' */
+#define SYS_CFG_MODE_BUS_MODE 0
+#define SYS_CFG_MODE_LOOPBACK_MODE 1
+
+/* Field  'SYS_CFG.ENABLE' */
+#define SYS_CFG_ENABLE_BIT_OFFSET 1 /* bit offset of the 'ENABLE' field */
+#define SYS_CFG_ENABLE_BIT_WIDTH 1 /* bit width of the 'ENABLE' field */
+#define SYS_CFG_ENABLE_BIT_MASK 0x00000002 /* bit mask of the 'ENABLE' field */
+#define SYS_CFG_ENABLE_RESET 0x0 /* reset value of the 'ENABLE' field */
+
+/* Register 'SYS_CTRL_STS' */
+#define SYS_CTRL_STS_OFFSET 0x00000018 /* address offset of the 'SYS_CTRL_STS' register */
+
+/* Field  'SYS_CTRL_STS.SEND' */
+#define SYS_CTRL_STS_SEND_BIT_OFFSET 0 /* bit offset of the 'SEND' field */
+#define SYS_CTRL_STS_SEND_BIT_WIDTH 1 /* bit width of the 'SEND' field */
+#define SYS_CTRL_STS_SEND_BIT_MASK 0x00000001 /* bit mask of the 'SEND' field */
+#define SYS_CTRL_STS_SEND_RESET 0x0 /* reset value of the 'SEND' field */
+
+/* Field  'SYS_CTRL_STS.STATUS_CODE' */
+#define SYS_CTRL_STS_STATUS_CODE_BIT_OFFSET 1 /* bit offset of the 'STATUS_CODE' field */
+#define SYS_CTRL_STS_STATUS_CODE_BIT_WIDTH 3 /* bit width of the 'STATUS_CODE' field */
+#define SYS_CTRL_STS_STATUS_CODE_BIT_MASK 0x0000000E /* bit mask of the 'STATUS_CODE' field */
+#define SYS_CTRL_STS_STATUS_CODE_RESET 0x0 /* reset value of the 'STATUS_CODE' field */
+
+/* Enumerated values for field 'SYS_CTRL_STS.STATUS_CODE' */
+#define SYS_CTRL_STS_STATUS_CODE_TX_FAILED 3
+#define SYS_CTRL_STS_STATUS_CODE_TX_SUCCESSFUL 1
+#define SYS_CTRL_STS_STATUS_CODE_ARBITRATION_LOST 2
+
+#endif  /* YONGA_CAN_IP_REGS_H */
diff --git a/verilog/dv/can_test_1/can_test1.c b/verilog/dv/can_test_1/can_test1.c
new file mode 100644
index 0000000..caf3e92
--- /dev/null
+++ b/verilog/dv/can_test_1/can_test1.c
@@ -0,0 +1,186 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+#include "YONGA_CAN_IP_regs.h"
+
+/*
+	CAN TX Transaction Test in Loopback Mode:
+		- Transmitted frame format: CAN BASE FORMAT
+*/
+
+#define BAUD_RATE_CFG_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + BAUD_RATE_CFG_OFFSET)
+#define MSG_ID_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + MSG_ID_OFFSET)
+#define MSG_CFG_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + MSG_CFG_OFFSET)
+#define DATA_REG1_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + DATA_REG1_OFFSET)
+#define DATA_REG2_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + DATA_REG2_OFFSET)
+#define SYS_CFG_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + SYS_CFG_OFFSET)
+#define SYS_CTRL_STS_REG (YONGA_CAN_IP_DEFAULT_BASEADDR + SYS_CTRL_STS_OFFSET)
+
+#define CONFIG_EN SYS_CFG_ENABLE_BIT_MASK
+#define LOOPBACK_EN SYS_CFG_MODE_BIT_MASK
+#define SEND SYS_CTRL_STS_SEND_BIT_MASK
+#define TX_SUCCESSFUL SYS_CTRL_STS_STATUS_CODE_TX_SUCCESSFUL
+
+#define WR_EN 0x20
+
+void device_register_write(uint32_t, uint32_t);
+
+uint32_t device_register_read(uint32_t);
+
+void main()
+{
+
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Configure LA probes [63:0] as outputs from the cpu
+    // Configure LA probes [127:64] as inputs to the cpu
+    // the output enable is active low, the input enable is active high
+    reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
+    reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+    reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+    reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
+
+    // Flag start of the test
+	reg_mprj_datal = 0xAB600000;
+
+    // Set configuration data
+    uint32_t TSEG2 = 0x8;
+    uint32_t TSEG1 = 0x10;
+    uint32_t BRP = 0x2;
+    uint32_t SID = 0xAB;
+    uint32_t DLC = 0x5;
+    uint32_t DATA_BYTE_0 = 0xEE;
+    uint32_t DATA_BYTE_1 = 0xEE;
+    uint32_t DATA_BYTE_2 = 0xFF;
+    uint32_t DATA_BYTE_3 = 0xCA;
+    uint32_t DATA_BYTE_4 = 0x30;
+    uint32_t DATA_BYTE_5 = 0xB0;
+    uint32_t DATA_BYTE_6 = 0x0A;
+    uint32_t DATA_BYTE_7 = 0xAB;
+
+    // Enable device configuration
+    device_register_write(SYS_CFG_REG, CONFIG_EN);
+
+    // Enable loopback mode
+    device_register_write(SYS_CFG_REG, (CONFIG_EN | LOOPBACK_EN));
+
+    // Apply configuration
+    device_register_write(BAUD_RATE_CFG_REG, ( \
+        (TSEG2 << BAUD_RATE_CFG_TSEG2_BIT_OFFSET) | \
+        (TSEG1 << BAUD_RATE_CFG_TSEG1_BIT_OFFSET) | \
+        (BRP << BAUD_RATE_CFG_BRP_BIT_OFFSET) \
+        ) \
+    );
+    device_register_write(MSG_ID_REG, (SID << MSG_ID_SID_BIT_OFFSET));
+    device_register_write(MSG_CFG_REG, (DLC << MSG_CFG_DLC_BIT_OFFSET));
+    device_register_write(DATA_REG1_REG, ( \
+        (DATA_BYTE_0 << DATA_REG1_DATA_BYTE_0_BIT_OFFSET) | \
+        (DATA_BYTE_1 << DATA_REG1_DATA_BYTE_1_BIT_OFFSET) | \
+        (DATA_BYTE_2 << DATA_REG1_DATA_BYTE_2_BIT_OFFSET) | \
+        (DATA_BYTE_3 << DATA_REG1_DATA_BYTE_3_BIT_OFFSET) \
+        ) \
+    );
+    device_register_write(DATA_REG2_REG, ( \
+        (DATA_BYTE_4 << DATA_REG2_DATA_BYTE_4_BIT_OFFSET) | \
+        (DATA_BYTE_5 << DATA_REG2_DATA_BYTE_5_BIT_OFFSET) | \
+        (DATA_BYTE_6 << DATA_REG2_DATA_BYTE_6_BIT_OFFSET) | \
+        (DATA_BYTE_7 << DATA_REG2_DATA_BYTE_7_BIT_OFFSET) \
+        ) \
+    );
+
+    // Disable device configuration
+    device_register_write(SYS_CFG_REG, (~CONFIG_EN | LOOPBACK_EN));
+
+    // Initiate CAN transfer
+    device_register_write(SYS_CTRL_STS_REG, SEND);
+
+    uint32_t tmp;
+    while (1) {
+      if (device_register_read(SYS_CTRL_STS_REG) & TX_SUCCESSFUL) break;
+    }
+
+}
+
+void device_register_write(uint32_t device_addr, uint32_t val){
+
+    reg_la0_data = WR_EN | device_addr;
+    reg_la1_data = val;
+
+    // send access request to the peripheral
+    reg_mprj_slave = 0x1;
+
+}
+
+uint32_t device_register_read(uint32_t device_addr){
+
+    reg_la0_data = device_addr;
+
+    // send access request to the peripheral
+    reg_mprj_slave = 0x1;
+
+    return reg_la2_data_in;
+
+}
diff --git a/verilog/dv/can_test_1/can_test1_tb.v b/verilog/dv/can_test_1/can_test1_tb.v
new file mode 100644
index 0000000..3ae4b20
--- /dev/null
+++ b/verilog/dv/can_test_1/can_test1_tb.v
@@ -0,0 +1,135 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module can_test1_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+
+	assign mprj_io[3] = 1'b1;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("can_test1.vcd");
+		$dumpvars(0, can_test1_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (200) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, GL simulation Finished");
+		`else
+			$display ("Monitor: Timeout, RTL simulation Finished");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#100000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3 = power1;
+	wire VDD1V8 = power2;
+	wire USER_VDD3V3 = power3;
+	wire USER_VDD1V8 = power4;
+	wire VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("can_test1.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire