)]}'
{
  "commit": "afb84ffb64c6045841abed02f21a674c4306bc24",
  "tree": "3aab35266d58d7a99ca2d8e234e7a03ed9b22835",
  "parents": [
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  "author": {
    "name": "okanyagiz",
    "email": "61591852+okanyagiz@users.noreply.github.com",
    "time": "Thu Nov 24 15:56:23 2022 +0300"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Nov 24 15:56:23 2022 +0300"
  },
  "message": "Add files via upload\n\nUpdate GPIO direction.",
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    {
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      "old_mode": 33188,
      "old_path": "verilog/rtl/user_defines.v",
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}