)]}'
{
  "commit": "45713ae38da32395dc6695c43efce094080baa74",
  "tree": "ee53343f2212c7342b75985aba9b11f1b5ab0141",
  "parents": [
    "83771d251d748d3368acc813b545a05bd7c97bd2"
  ],
  "author": {
    "name": "abdullahyildiz",
    "email": "abdullahyildiz@github.com",
    "time": "Tue Nov 22 16:03:30 2022 +0300"
  },
  "committer": {
    "name": "abdullahyildiz",
    "email": "abdullahyildiz@github.com",
    "time": "Tue Nov 22 16:03:30 2022 +0300"
  },
  "message": "Update verilog/dv/Makefile\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "43a41497160dbf0145ff5c638f085070f00715c9",
      "old_mode": 33188,
      "old_path": "verilog/dv/Makefile",
      "new_id": "76873b76f3a9e678a3e9b7d6c67a37dccba0fb4b",
      "new_mode": 33188,
      "new_path": "verilog/dv/Makefile"
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}