| { |
| "DESIGN_NAME": "user_project_wrapper", |
| |
| "CLOCK_PERIOD": 20, |
| "CLOCK_PORT": "user_clock2", |
| "CLOCK_NET": "user_clock2", |
| "BASE_SDC_FILE": "dir::base.sdc", |
| |
| "FP_PDN_VPITCH": 180, |
| "FP_PDN_HPITCH": 180, |
| "FP_PDN_VOFFSET": 5, |
| "FP_PDN_HOFFSET": 5, |
| |
| "MAGIC_ZEROIZE_ORIGIN": 0, |
| "FP_SIZING": "absolute", |
| |
| "UNIT": "2.4", |
| "FP_IO_VEXTEND": "expr::2 * $UNIT", |
| "FP_IO_HEXTEND": "expr::2 * $UNIT", |
| "FP_IO_VLENGTH": "ref::$UNIT", |
| "FP_IO_HLENGTH": "ref::$UNIT", |
| "FP_IO_VTHICKNESS_MULT": 4, |
| "FP_IO_HTHICKNESS_MULT": 4, |
| |
| "FP_PDN_CORE_RING": 1, |
| "FP_PDN_CORE_RING_VWIDTH": 3.1, |
| "FP_PDN_CORE_RING_HWIDTH": 3.1, |
| "FP_PDN_CORE_RING_VOFFSET": 12.45, |
| "FP_PDN_CORE_RING_HOFFSET": 12.45, |
| "FP_PDN_CORE_RING_VSPACING": 1.7, |
| "FP_PDN_CORE_RING_HSPACING": 1.7, |
| "FP_PDN_VWIDTH": 3.1, |
| "FP_PDN_HWIDTH": 3.1, |
| "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)", |
| "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)", |
| |
| "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS", |
| |
| "SYNTH_MAX_FANOUT": "10", |
| "SYNTH_STRATEGY": "DELAY 4", |
| |
| "FP_TAP_HORIZONTAL_HALO": "40", |
| "FP_PDN_HORIZONTAL_HALO": "40", |
| "FP_TAP_VERTICAL_HALO": "10", |
| "FP_PDN_VERTICAL_HALO": "10", |
| |
| "GPL_CELL_PADDING": "2", |
| "DPL_CELL_PADDING": "0", |
| "DIODE_PADDING": "0", |
| |
| "ROUTING_CORES": "24", |
| |
| "RUN_KLAYOUT": "0", |
| |
| "SYNTH_NO_FLAT": "0", |
| |
| "pdk::sky130*": { |
| "DIE_AREA": "0 0 2920 3520", |
| "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def", |
| |
| "MACRO_PLACEMENT_CFG": "dir::macro.cfg", |
| |
| "FP_PDN_MACRO_HOOKS": "microwatt_0.soc0.bram.bram0.ram_0.memory_0 vccd1 vssd1 VPWR VGND, microwatt_0.soc0.processor.dcache_0.rams:1.way.cache_ram_0 vccd1 vssd1 VPWR VGND, microwatt_0.soc0.processor.icache_0.rams:1.way.cache_ram_0 vccd1 vssd1 VPWR VGND, microwatt_0.soc0.processor.execute1_0.multiply_0.multiplier vccd1 vssd1 VPWR VGND, microwatt_0.soc0.processor.with_fpu.fpu_0.fpu_multiply_0.multiplier vccd1 vssd1 VPWR VGND, microwatt_0.soc0.processor.register_file_0.register_file_0 vccd1 vssd1 VPWR VGND", |
| |
| "VERILOG_FILES": [ |
| "dir::../../verilog/rtl/defines.v", |
| "dir::../../verilog/rtl/tap_top.v", |
| "dir::../../verilog/rtl/raminfr.v", |
| "dir::../../verilog/rtl/uart_defines.v", |
| "dir::../../verilog/rtl/uart_receiver.v", |
| "dir::../../verilog/rtl/uart_regs.v", |
| "dir::../../verilog/rtl/uart_rfifo.v", |
| "dir::../../verilog/rtl/uart_sync_flops.v", |
| "dir::../../verilog/rtl/uart_tfifo.v", |
| "dir::../../verilog/rtl/uart_top.v", |
| "dir::../../verilog/rtl/uart_transmitter.v", |
| "dir::../../verilog/rtl/uart_wb.v", |
| "dir::../../verilog/rtl/simplebus_host.v", |
| "dir::../../verilog/rtl/microwatt.v", |
| "dir::../../verilog/rtl/user_project_wrapper.v" |
| ], |
| |
| "VERILOG_FILES_BLACKBOX": [ |
| "dir::../../verilog/rtl/wrapper/RAM512.v", |
| "dir::../../verilog/rtl/wrapper/RAM32_1RW1R.v", |
| "dir::../../verilog/rtl/wrapper/Microwatt_FP_DFFRFile.v", |
| "dir::../../verilog/rtl/wrapper/multiply_add_64x64.v" |
| ], |
| |
| "EXTRA_LEFS": [ |
| "dir::../../lef/RAM512.lef", |
| "dir::../../lef/RAM32_1RW1R.lef", |
| "dir::../../lef/Microwatt_FP_DFFRFile.lef", |
| "dir::../../lef/multiply_add_64x64.lef" |
| ], |
| |
| "EXTRA_GDS_FILES": [ |
| "dir::../../gds/RAM512.gds", |
| "dir::../../gds/RAM32_1RW1R.gds", |
| "dir::../../gds/Microwatt_FP_DFFRFile.gds", |
| "dir::../../gds/multiply_add_64x64.gds" |
| ], |
| |
| "EXTRA_LIBS": [ |
| "dir::../../lib/RAM512.lib", |
| "dir::../../lib/RAM32_1RW1R.lib", |
| "dir::../../lib/Microwatt_FP_DFFRFile.lib", |
| "dir::../../lib/multiply_add_64x64.lib" |
| ], |
| |
| "VDD_NETS": ["vccd1", "vccd2", "vdda1", "vdda2"], |
| "GND_NETS": ["vssd1", "vssd2", "vssa1", "vssa2"], |
| |
| "PL_TARGET_DENSITY": "0.25", |
| "PL_RESIZER_HOLD_SLACK_MARGIN": "0.25", |
| "GRT_ADJUSTMENT": "0.2", |
| |
| "GRT_ANT_ITERS": "1", |
| |
| "CTS_CLK_BUFFER_LIST": ["sky130_fd_sc_hd__clkbuf_8", "sky130_fd_sc_hd__clkbuf_4", "sky130_fd_sc_hd__clkbuf_2"], |
| "CTS_DISABLE_POST_PROCESSING": "1", |
| "CTS_SINK_CLUSTERING_MAX_DIAMETER": "200", |
| "CTS_DISTANCE_BETWEEN_BUFFERS": "1000" |
| }, |
| "pdk::gf180mcuC": { |
| "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
| |
| "DIE_AREA": "0 0 3000 3000", |
| "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def", |
| |
| "MACRO_PLACEMENT_CFG": "dir::macro-gf180mcu.cfg", |
| |
| "FP_PDN_MACRO_HOOKS": "microwatt_0.soc0.bram.bram0.ram_0.ram0 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram1 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram2 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram3 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram4 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram5 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram6 vccd1 vssd1 VDD VSS, microwatt_0.soc0.bram.bram0.ram_0.ram7 vccd1 vssd1 VDD VSS, microwatt_0.soc0.processor.dcache_0.rams:1.way.cache_ram_0 vccd1 vssd1 VDD VSS, microwatt_0.soc0.processor.icache_0.rams:1.way.cache_ram_0 vccd1 vssd1 VDD VSS, microwatt_0.soc0.processor.execute1_0.multiply_0.multiplier vccd1 vssd1 VDD VSS, microwatt_0.soc0.processor.register_file_0.register_file_0 vccd1 vssd1 VDD VSS", |
| |
| "VERILOG_FILES": [ |
| "dir::../../verilog/rtl/defines.v", |
| "dir::../../verilog/rtl/RAM512-gf180.v", |
| "dir::../../verilog/rtl/tap_top.v", |
| "dir::../../verilog/rtl/raminfr.v", |
| "dir::../../verilog/rtl/uart_defines.v", |
| "dir::../../verilog/rtl/uart_receiver.v", |
| "dir::../../verilog/rtl/uart_regs.v", |
| "dir::../../verilog/rtl/uart_rfifo.v", |
| "dir::../../verilog/rtl/uart_sync_flops.v", |
| "dir::../../verilog/rtl/uart_tfifo.v", |
| "dir::../../verilog/rtl/uart_top.v", |
| "dir::../../verilog/rtl/uart_transmitter.v", |
| "dir::../../verilog/rtl/uart_wb.v", |
| "dir::../../verilog/rtl/simplebus_host.v", |
| "dir::../../verilog/rtl/microwatt.v", |
| "dir::../../verilog/rtl/user_project_wrapper.v" |
| ], |
| |
| "VERILOG_FILES_BLACKBOX": [ |
| "pdk_dir::libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v", |
| "dir::../../verilog/rtl/wrapper/RAM32_1RW1R.v", |
| "dir::../../verilog/rtl/wrapper/Microwatt_FP_DFFRFile.v", |
| "dir::../../verilog/rtl/wrapper/multiply_add_64x64.v" |
| ], |
| |
| "EXTRA_LEFS": [ |
| "pdk_dir::libs.ref/gf180mcu_fd_ip_sram/lef/gf180mcu_fd_ip_sram__sram512x8m8wm1.lef", |
| "dir::../../lef/RAM32_1RW1R.lef", |
| "dir::../../lef/Microwatt_FP_DFFRFile.lef", |
| "dir::../../lef/multiply_add_64x64.lef" |
| ], |
| |
| "EXTRA_GDS_FILES": [ |
| "pdk_dir::libs.ref/gf180mcu_fd_ip_sram/gds/gf180mcu_fd_ip_sram__sram512x8m8wm1.gds", |
| "dir::../../gds/RAM32_1RW1R.gds", |
| "dir::../../gds/Microwatt_FP_DFFRFile.gds", |
| "dir::../../gds/multiply_add_64x64.gds" |
| ], |
| |
| "EXTRA_LIBS": [ |
| "pdk_dir::libs.ref/gf180mcu_fd_ip_sram/liberty/gf180mcu_fd_ip_sram__sram512x8m8wm1__tt_025C_5v00.lib", |
| "dir::../../lib/RAM32_1RW1R.lib", |
| "dir::../../lib/Microwatt_FP_DFFRFile.lib", |
| "dir::../../lib/multiply_add_64x64.lib" |
| ], |
| |
| "VDD_NETS": ["vccd1"], |
| "GND_NETS": ["vssd1"], |
| |
| "PL_TARGET_DENSITY": "0.65", |
| |
| "CTS_DISABLE_POST_PROCESSING": "1", |
| "CTS_SINK_CLUSTERING_MAX_DIAMETER": "200", |
| "CTS_DISTANCE_BETWEEN_BUFFERS": "1000", |
| |
| "GRT_ADJUSTMENT": "0.1", |
| |
| "DIODE_INSERTION_STRATEGY": "0" |
| } |
| } |
