)]}'
{
  "commit": "6b8975c3759ea05781771482db5fcf4803d0d73b",
  "tree": "a1b95e20155423aa4a5dc62652e571d1af5399a2",
  "parents": [
    "1155805997baa4772489cb3839d1fdf74bf53466"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Mon Dec 05 11:07:53 2022 +1100"
  },
  "committer": {
    "name": "Anton Blanchard",
    "email": "anton@ozlabs.org",
    "time": "Mon Dec 05 11:07:53 2022 +1100"
  },
  "message": "Fix gate level sim\n\nmake gpio_defaults writes a modified caravel.v to the\ncaravel_user_project verilog/gl directory so we need to use that and not\nthe version in the caravel repo. We also need the gate level\nimplementations of the various gpio_defaults_block modules (only a few\nare created and referenced in the caravel repo).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ec00c93c4c0921d259820ef1424ef12ee9a43ea6",
      "old_mode": 33188,
      "old_path": "verilog/dv/microwatt/make.rules",
      "new_id": "1f52e2a961a3c21a7c224811877987c6cc0cb719",
      "new_mode": 33188,
      "new_path": "verilog/dv/microwatt/make.rules"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "343456e1a9a6ddfc7b28d011304ed7ae24327b44",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.gl.caravel"
    }
  ]
}