)]}'
{
  "commit": "5d6c7da2c75c888242890de14d19776ed79320aa",
  "tree": "45c9cebf893194150845eafa7a17545c36b51415",
  "parents": [
    "efd24903b39758fad3a834367fe394abdbd3e513"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Tue Sep 06 12:49:30 2022 +1000"
  },
  "committer": {
    "name": "Anton Blanchard",
    "email": "anton@ozlabs.org",
    "time": "Tue Sep 06 12:49:30 2022 +1000"
  },
  "message": "Resynthesize microwatt verilog\n\nSome recent GHDL updates result in significant changes to the\nsynthesized verilog, although there should be no functional changes.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e789a6f7ed0bdf267a8ed8089c8849827cead9f5",
      "old_mode": 33188,
      "old_path": "verilog/rtl/microwatt.v",
      "new_id": "9ff6a30282ba1145a84f13b7babe3c78ec84b5f2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/microwatt.v"
    }
  ]
}