)]}'
{
  "commit": "96d63c562290d91451adeef1ac030174e19a3da7",
  "tree": "c66e1ffffa8b76dc1dcbb48743487701e3f56269",
  "parents": [
    "51a109622b4580ce760a544cc2104ba5985dbf15"
  ],
  "author": {
    "name": "Marwan Abbas",
    "email": "marwaneltoukhy@aucegypt.edu",
    "time": "Sun Feb 13 19:13:03 2022 +0200"
  },
  "committer": {
    "name": "Marwan Abbas",
    "email": "marwaneltoukhy@aucegypt.edu",
    "time": "Sun Feb 13 19:13:03 2022 +0200"
  },
  "message": "litex integration iteration - only wb_port not working\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "793bf634c2c1b1af90be95fcd85688e869bfb667",
      "old_mode": 57344,
      "old_path": "caravel",
      "new_id": "e7ade8203d82c5604c7542d161765090838e5e7f",
      "new_mode": 57344,
      "new_path": "caravel"
    },
    {
      "type": "modify",
      "old_id": "e14258deccfff255d88a505fe9de76333b70ca25",
      "old_mode": 33188,
      "old_path": "verilog/dv/Makefile",
      "new_id": "be842fca05a87e19242328071ddc7b99c6e5d9a0",
      "new_mode": 33188,
      "new_path": "verilog/dv/Makefile"
    },
    {
      "type": "delete",
      "old_id": "a85a5eda3799377a5796672edd62b032a9b8eb52",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/RTL-io_ports.vcd",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "2515ebb46959a37dc7526b59f3eaae5fa2199ec0",
      "old_mode": 33261,
      "old_path": "verilog/dv/io_ports/io_ports.hex",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "66f66608388a9a4c9eac120b6bea6cbab442f0b2",
      "old_mode": 33261,
      "old_path": "verilog/dv/io_ports/io_ports.hexe",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "a7bd07394627598298a00f2737250557768a1c91",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports.lst",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "8da4873b94914691cdc51b1f9c067c2c9d3b5862",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports_tb.v",
      "new_id": "08843ceac5e0f75b1d9ae1d24659b8fce17c396e",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports_tb.v"
    },
    {
      "type": "modify",
      "old_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "ea1b0e07334ab65aa0259a33463e07c203acacbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "ea1b0e07334ab65aa0259a33463e07c203acacbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "2acf43d610c0f08dee912e70e3af58daf394d83a",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2_tb.v",
      "new_id": "168664b650f66188ddb3c7e8a004d8b8e269c3a9",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/la_test2_tb.v"
    },
    {
      "type": "modify",
      "old_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "ea1b0e07334ab65aa0259a33463e07c203acacbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/Makefile"
    },
    {
      "type": "modify",
      "old_id": "15d7849d31b37a95a4ddd141404ff225390ee9ad",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v",
      "new_id": "8088ecc8f19fe3b55041134fbff0914842483abf",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v"
    },
    {
      "type": "modify",
      "old_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "ea1b0e07334ab65aa0259a33463e07c203acacbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/Makefile"
    }
  ]
}