)]}'
{
  "commit": "f1045ab5d4fe35696908a0ab0d68b6832018a89d",
  "tree": "2579ad84fc13f648416df971fa078c76e02f52df",
  "parents": [
    "c01bf929d0c07aaa7b47e6db261eb7f13c666ce9"
  ],
  "author": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Fri Aug 26 13:56:15 2022 +0200"
  },
  "committer": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Fri Aug 26 13:56:15 2022 +0200"
  },
  "message": "wip for sim tb\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "426d6473176ab9867c8b80742206b257a3506239",
      "old_mode": 33261,
      "old_path": "configure.py",
      "new_id": "742dd0916509c5140e12b98eb90fb54f999b77bf",
      "new_mode": 33261,
      "new_path": "configure.py"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "46863076e386bd9b2ebb8377d08bb85f680f2412",
      "new_mode": 33188,
      "new_path": "verilog/dv/scan_controller/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8e9ecce83f90b203e7358fb0552ef51c4e2d93f2",
      "new_mode": 33188,
      "new_path": "verilog/dv/scan_controller/scan_wrapper.py"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a2d55ed57773adfe53cc9e209e62d3542183da08",
      "new_mode": 33188,
      "new_path": "verilog/dv/scan_controller/test_scan_controller.py"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b7d67c25746445764edca0c4a6007716167a86d8",
      "new_mode": 33188,
      "new_path": "verilog/dv/scan_controller/test_scan_controller_tb.v"
    },
    {
      "type": "modify",
      "old_id": "33c0eb3015c3416097e9f842ee591c6c2554cc79",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.rtl.caravel_user_project",
      "new_id": "37d192dbed986bc759d7239c1c343085f0dc0bfa",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.rtl.caravel_user_project"
    }
  ]
}
