diff --git a/verilog/rtl/scan_controller/scan_controller.v b/verilog/rtl/scan_controller/scan_controller.v
index e1d75a8..a28820c 100644
--- a/verilog/rtl/scan_controller/scan_controller.v
+++ b/verilog/rtl/scan_controller/scan_controller.v
@@ -326,7 +326,7 @@
     // Input
     always @(posedge clk)
         if (aio_input_ld)
-            aio_input_shift <= slow_clk_ena ? { aio_input_reg[PL-1:1], slow_clk } : aio_input_reg;
+            aio_input_shift <= slow_clk_ena ? { aio_input_reg[PL:1], slow_clk } : aio_input_reg;
         else if (aio_input_sh)
             aio_input_shift <= { aio_input_shift[PL-1:0], 1'b0 };