diff --git a/verilog/rtl/scan_controller/scan_controller.v b/verilog/rtl/scan_controller/scan_controller.v
index a28820c..f2a1cfa 100644
--- a/verilog/rtl/scan_controller/scan_controller.v
+++ b/verilog/rtl/scan_controller/scan_controller.v
@@ -2,7 +2,7 @@
 `default_nettype none
 
 module scan_controller #(
-    parameter integer NUM_DESIGNS = 8,
+    parameter integer NUM_DESIGNS = 498,
     parameter integer NUM_IOS     = 8,
 
     // auto-set