)]}'
{
  "commit": "b7dbaa4eb5d25169917c570ba12f9bd029d48dac",
  "tree": "b51a3c7bcbb6a326f162669137e7fa54e78d74e0",
  "parents": [
    "4ed41af6ae695e1fd2acf10c03dfd6b020a9d066"
  ],
  "author": {
    "name": "matt venn",
    "email": "matt@mattvenn.net",
    "time": "Wed Aug 31 23:00:37 2022 +0200"
  },
  "committer": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Thu Sep 01 12:44:37 2022 +0200"
  },
  "message": "remove the reset from clockdiv and update tb to reset so test passes\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/dv/scan_controller_int/scan_controller_int.gtkw",
      "new_id": "2007495bcc44f4d948aaade0dc2eee2dff4365a3",
      "new_mode": 33188,
      "new_path": "verilog/dv/scan_controller_int/scan_controller_int.gtkw"
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      "old_path": "verilog/rtl/scan_controller/scan_controller.v",
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      "new_path": "verilog/rtl/scan_controller/scan_controller.v"
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}