)]}'
{
  "commit": "afd5b8665bd1956188ad99c290015dbdb3196509",
  "tree": "3fa7cb60a6696a44edbf168a33f3695d961f12f1",
  "parents": [
    "f2993d11331b2bd3e81c08886c2529bc973b76dc"
  ],
  "author": {
    "name": "matt venn",
    "email": "matt@mattvenn.net",
    "time": "Sun Aug 28 04:42:48 2022 +0200"
  },
  "committer": {
    "name": "matt venn",
    "email": "matt@mattvenn.net",
    "time": "Sun Aug 28 04:42:48 2022 +0200"
  },
  "message": "formal mux proof\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "408fcf64cf4d5ae2128dfc02616a1bec5ab5ab90",
      "new_mode": 33188,
      "new_path": "verilog/rtl/scan_controller/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c104f6a990ba661ad0b9ae61de686c8d0acc1a97",
      "new_mode": 33188,
      "new_path": "verilog/rtl/scan_controller/properties.v"
    },
    {
      "type": "modify",
      "old_id": "60b366b6e795190232a2205fce07f747b5bfe7cb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/scan_controller/scan_controller.v",
      "new_id": "d9f8f96426372b9537ac67564fb4ed06ae98d57e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/scan_controller/scan_controller.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "57fe26424a7d3b108bb5589f2b00396f221dd052",
      "new_mode": 33188,
      "new_path": "verilog/rtl/scan_controller/scan_mux.sby"
    }
  ]
}
