# name must be valid verilog module name set in scan_wrapper.v
project_urls = [
            'https://github.com/mattvenn/wokwi-verilog-gds-test',
            'https://github.com/mattvenn/animation_tinytapeout_demo',
            'https://github.com/mattvenn/wokwi_inverters',
            'https://github.com/wokwi/tiny-tapeout-test-simple',
            'https://github.com/omerk/tinytapeout-demo1',
            'https://github.com/mattvenn/tinytapeout-7seg-decoder',
            'https://github.com/omerk/tinytapeout-verilog-test',
            'https://github.com/gregdavill/tinytapeout_spin0',
            'https://github.com/mole99/wokwi-1bit-alu',
            'https://github.com/ericsmi/tinytapeout_popcnt.git',
            'https://github.com/krasin/wokwi-guess-my-number',
            'https://github.com/mattvenn/tinytapeout-7seg-seconds-counter',
            'https://github.com/johshoff/barrelshifter-wokwi-gds',
            'https://github.com/pretentious7/tinytapeout',
            'https://github.com/GuzTech/wokwi-ripple-carry-adder',
            'https://github.com/kbeckmann/tinytapeout_kbeckmann1',
            'https://github.com/H-S-S-11/tinytapeout-verilog-test',
            'https://github.com/skerr92/tinytapeout_frequency_div',
            'https://github.com/argunda/tinytapeout_dualedgedetector',
    ]