)]}'
{
  "commit": "2e10e747c869afb5cf47a0b99e6f86fefab2f082",
  "tree": "e355fd7c5b22b05adaba2a557bcd5aad0112272e",
  "parents": [
    "5edb56f9d9900efefe04db854a70fb2358b2a226"
  ],
  "author": {
    "name": "Sylvain Munaut",
    "email": "tnt@246tNt.com",
    "time": "Thu Sep 01 09:37:00 2022 +0200"
  },
  "committer": {
    "name": "Sylvain Munaut",
    "email": "tnt@246tNt.com",
    "time": "Thu Sep 01 12:37:04 2022 +0200"
  },
  "message": "scan_controller: Use negedge for reset sync\n\nThis keeps the reset transition away from the clock edge\n\nSigned-off-by: Sylvain Munaut \u003ctnt@246tNt.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1b37af3fef7b7d2842e6edaac1683043b2a6ab54",
      "old_mode": 33188,
      "old_path": "verilog/rtl/scan_controller/scan_controller.v",
      "new_id": "93ec4b06746ef10a86abe89cba5309e71a61cb49",
      "new_mode": 33188,
      "new_path": "verilog/rtl/scan_controller/scan_controller.v"
    }
  ]
}