diff --git a/verilog/rtl/scan_controller/scan_controller.v b/verilog/rtl/scan_controller/scan_controller.v
index 1b37af3..93ec4b0 100644
--- a/verilog/rtl/scan_controller/scan_controller.v
+++ b/verilog/rtl/scan_controller/scan_controller.v
@@ -130,7 +130,7 @@
 
     // Generate our own reset, with de-assertion
     // synchronized to clock
-    always @(posedge clk or posedge reset)
+    always @(negedge clk or posedge reset)
         if (reset)
             rst_shift <= 3'b111;
         else