| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h35m55s0ms,0h32m6s0ms,22860.869565217392,0.46,11430.434782608696,9.82,1061.57,5258,0,0,0,0,0,0,0,-1,0,-1,-1,900638,55837,0.0,-2.26,-1,-1.76,-2.22,0.0,-101.82,-1,-197.22,-286.21,832828329.0,0.0,24.44,49.29,2.25,39.09,-1,1460,4695,237,3471,0,0,0,2321,146,4,12,55,280,29,6,550,919,860,20,1674,5873,0,7547,81.8330605564648,12.22,10,AREA 0,2,50,1,120,120,0.3,0,sky130_fd_sc_hd,4,4 |
