openlane/sar_adc/pin_order.cfg

#BUS_SORT
#MANUAL_PLACE

#S
reset_n          
pulse1m_mclk             

#W
clk                      000 0 2
reg_cs            
reg_wr           
reg_addr\[7\]    
reg_addr\[6\]    
reg_addr\[5\]    
reg_addr\[4\]    
reg_addr\[3\]    
reg_addr\[2\]    
reg_addr\[1\]    
reg_addr\[0\]    
reg_be\[3\]    
reg_be\[2\]    
reg_be\[1\]    
reg_be\[0\]    
reg_wdata\[31\]   
reg_wdata\[30\]   
reg_wdata\[29\]   
reg_wdata\[28\]   
reg_wdata\[27\]   
reg_wdata\[26\]   
reg_wdata\[25\]   
reg_wdata\[24\]   
reg_wdata\[23\]   
reg_wdata\[22\]   
reg_wdata\[21\]   
reg_wdata\[20\]   
reg_wdata\[19\]   
reg_wdata\[18\]   
reg_wdata\[17\]   
reg_wdata\[16\]   
reg_wdata\[15\]   
reg_wdata\[14\]   
reg_wdata\[13\]   
reg_wdata\[12\]  
reg_wdata\[11\]  
reg_wdata\[10\]  
reg_wdata\[9\]   
reg_wdata\[8\]   
reg_wdata\[7\]   
reg_wdata\[6\]   
reg_wdata\[5\]   
reg_wdata\[4\]   
reg_wdata\[3\]   
reg_wdata\[2\]   
reg_wdata\[1\]   
reg_wdata\[0\]   
reg_rdata\[31\]  
reg_rdata\[30\]  
reg_rdata\[29\]  
reg_rdata\[28\]  
reg_rdata\[27\]  
reg_rdata\[26\]  
reg_rdata\[25\]  
reg_rdata\[24\]  
reg_rdata\[23\]  
reg_rdata\[22\]  
reg_rdata\[21\]  
reg_rdata\[20\]  
reg_rdata\[19\]  
reg_rdata\[18\]  
reg_rdata\[17\]  
reg_rdata\[16\]  
reg_rdata\[15\]  
reg_rdata\[14\]  
reg_rdata\[13\]  
reg_rdata\[12\]  
reg_rdata\[11\]  
reg_rdata\[10\]  
reg_rdata\[9\]  
reg_rdata\[8\]  
reg_rdata\[7\]  
reg_rdata\[6\]  
reg_rdata\[5\]  
reg_rdata\[4\]  
reg_rdata\[3\]  
reg_rdata\[2\]  
reg_rdata\[1\]  
reg_rdata\[0\]  
reg_ack       


#N
sar2dac\[7\]
sar2dac\[6\]
sar2dac\[5\]
sar2dac\[4\]
sar2dac\[3\]
sar2dac\[2\]
sar2dac\[1\]
sar2dac\[0\]
analog_din\[5\]
analog_din\[4\]
analog_din\[3\]
analog_din\[2\]
analog_din\[1\]
analog_din\[0\]
analog_dac_out