| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m26s0ms,0h6m3s0ms,49511.11111111112,0.2475,24755.55555555556,29.5,953.26,6127,0,0,0,0,0,0,0,-1,0,-1,-1,477211,61100,-9.79,-17.05,-1,0.0,0.0,-11345.75,-19529.63,-1,0.0,0.0,377081144.0,0.0,62.96,48.49,30.58,23.07,-1,4058,9565,814,6321,0,0,0,4603,152,83,49,97,1014,154,18,287,1210,1172,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4 |
