| /root/optimised_strong_arm_latch/Makefile |
| /root/optimised_strong_arm_latch/docs/Makefile |
| /root/optimised_strong_arm_latch/docs/environment.yml |
| /root/optimised_strong_arm_latch/docs/source/conf.py |
| /root/optimised_strong_arm_latch/docs/source/index.rst |
| /root/optimised_strong_arm_latch/netgen/run_lvs_por.sh |
| /root/optimised_strong_arm_latch/netgen/run_lvs_wrapper_verilog.sh |
| /root/optimised_strong_arm_latch/netgen/run_lvs_wrapper_xschem.sh |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___07_11_48/logs/gds.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___07_11_48/logs/tools.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___08_35_25/logs/gds.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___08_35_25/logs/tools.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___08_42_48/logs/gds.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___08_42_48/logs/pdks.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___08_42_48/logs/tools.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/gds.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.total |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/pdks.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/logs/tools.info |
| /root/optimised_strong_arm_latch/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.drc.report |
| /root/optimised_strong_arm_latch/verilog/dv/Makefile |
| /root/optimised_strong_arm_latch/verilog/dv/mprj_por/Makefile |
| /root/optimised_strong_arm_latch/verilog/dv/mprj_por/mprj_por.c |
| /root/optimised_strong_arm_latch/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/optimised_strong_arm_latch/verilog/rtl/comparator.v |
| /root/optimised_strong_arm_latch/verilog/rtl/example_por.v |
| /root/optimised_strong_arm_latch/verilog/rtl/uprj_analog_netlists.v |
| /root/optimised_strong_arm_latch/verilog/rtl/user_analog_proj_example.v |
| /root/optimised_strong_arm_latch/verilog/rtl/user_analog_project_wrapper.v |
| /root/optimised_strong_arm_latch/xschem/.spiceinit |
| /root/optimised_strong_arm_latch/xschem/analog_wrapper_tb.sch |
| /root/optimised_strong_arm_latch/xschem/comparator.sch |
| /root/optimised_strong_arm_latch/xschem/comparator.sym |
| /root/optimised_strong_arm_latch/xschem/comparator_lvs.sch |
| /root/optimised_strong_arm_latch/xschem/comparator_tb.sch |
| /root/optimised_strong_arm_latch/xschem/user_analog_project_wrapper.sch |
| /root/optimised_strong_arm_latch/xschem/user_analog_project_wrapper.sym |
| /root/optimised_strong_arm_latch/xschem/xschemrc |
