)]}'
{
  "commit": "e82b9c4ca4ece655d8fcc72cc651aa62d4353e73",
  "tree": "b08f1ecdb150947116017eb3905adfbf909a4427",
  "parents": [
    "a194d0e9b5e7ba770762009efa68d6a57a594aaf"
  ],
  "author": {
    "name": "Ang Li",
    "email": "angl@princeton.edu",
    "time": "Fri May 20 22:31:50 2022 -0400"
  },
  "committer": {
    "name": "Ang Li",
    "email": "angl@princeton.edu",
    "time": "Fri May 20 22:31:50 2022 -0400"
  },
  "message": "[RTL] PRGA TB\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "63fe1a39cf9683f12390625c1cf7147b41faad6e",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/checker.v"
    },
    {
      "type": "modify",
      "old_id": "771af8d47466cee4c0fea7bd9e5cd8dba6b8f998",
      "old_mode": 33188,
      "old_path": "verilog/dv/prga/prga_bitstream_loader.v",
      "new_id": "50811e1f0fd13d0e6ce9c7cb0a8db9ad9f061b5e",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/prga_bitstream_loader.v"
    },
    {
      "type": "modify",
      "old_id": "735ee1c565e2ca3438be2742ec2f9ef701714768",
      "old_mode": 33188,
      "old_path": "verilog/dv/prga/prga_tb.v",
      "new_id": "1c327c420b0f9fc54dd34bc54209c7b422e055bf",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/prga_tb.v"
    },
    {
      "type": "modify",
      "old_id": "153f572435fadfd95cc6780ee898a3d68f3b72ab",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "56a1d3abea3cf6654721148d1b3f04e2dde7aa72",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}