)]}'
{
  "commit": "e20bfbc621a920ef56036eb4123f2f6415e0936f",
  "tree": "274c01e759798ec0df4424e012f789ec08eb1a56",
  "parents": [
    "d0aaeb4c9b651e26901def3a4b0a933a9b3e5ea1"
  ],
  "author": {
    "name": "Ang Li",
    "email": "angl@princeton.edu",
    "time": "Fri May 20 15:17:54 2022 -0400"
  },
  "committer": {
    "name": "Ang Li",
    "email": "angl@princeton.edu",
    "time": "Fri May 20 15:17:54 2022 -0400"
  },
  "message": "[C/RTL] Dummy test infra\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "70d7e916a6de255e709614796535328ec86b41a2",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/bcd2bin.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "065ef822fe149d4613ff77312a1c61fcb7baf979",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/bcd2bin_test_basic.v"
    },
    {
      "type": "modify",
      "old_id": "c316f0ddda0159cb2f0c16162493bbec5f59a4aa",
      "old_mode": 33188,
      "old_path": "verilog/dv/prga/prga.c",
      "new_id": "7557343b939164c0837ea7ce581ac5f61917a52c",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/prga.c"
    },
    {
      "type": "modify",
      "old_id": "ca03e76a45f6f27fccf1ead4e9d01c4984480871",
      "old_mode": 33188,
      "old_path": "verilog/dv/prga/prga_tb.v",
      "new_id": "9f7e95d275186f9afe2b28916328e22578f5e8bf",
      "new_mode": 33188,
      "new_path": "verilog/dv/prga/prga_tb.v"
    },
    {
      "type": "modify",
      "old_id": "017a499ee27225ac6d559c5ea787c9e94d6ac5cc",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
      "new_id": "057647f44383f264213d4fb15950369d5dc4d784",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v"
    }
  ]
}