)]}'
{
  "commit": "fab5f032d44174fa748b9cf91f089f05c9600f20",
  "tree": "73fdd96aa29b308378b92a83d06b06614e582ba5",
  "parents": [
    "0cd43a29593e58d98b939832fac201cfece40282"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Fri Jun 03 14:05:50 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Fri Jun 03 14:05:50 2022 +0100"
  },
  "message": "Fixed off by one error on the default PWM top compare value.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d9a43c9e1f852e924c0c7446047f699f5c9a5fe0",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/PWM/PWMDevice.v",
      "new_id": "d20a219c992f6132bf6da2b2489b43cfd5bd47e7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/PWM/PWMDevice.v"
    }
  ]
}