)]}'
{
  "commit": "f0597c4bfcd0ceb19a86db8c26be821ba03fdcc6",
  "tree": "ba3fa70afa7a47b63997a573102fd7af5ea94d19",
  "parents": [
    "546583cb32b25d4f7a99babaea878ae7133c79e4"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Thu Jun 02 14:43:45 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Thu Jun 02 14:43:45 2022 +0100"
  },
  "message": "Fixed branch and jump instructions not generating instruction address misalignment exceptions when jumping to a non word aligned address.\n",
  "tree_diff": [
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      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/CSR/CSR.v",
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      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/CSR/CSR.v"
    },
    {
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      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/CSR/Traps/Traps.v",
      "new_id": "e9f2d576f09180aba22805b377be829c7bdc2109",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/CSR/Traps/Traps.v"
    },
    {
      "type": "modify",
      "old_id": "3fb2c65bfeac3f690a3571757441f6ac35d972ae",
      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/RV32ICore.v",
      "new_id": "026380790c8847e0abe1d12a6e4ad2aa1f674353",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/RV32ICore.v"
    }
  ]
}