)]}'
{
  "commit": "e78d21187306967e0eaef7a1f77970daf925a0d0",
  "tree": "90a196e733ace333fe0db1ce634b7943669f1716",
  "parents": [
    "17641e27390956c21ae1c415c2d534e6a728bb40"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Mon May 30 00:12:22 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Mon May 30 00:12:22 2022 +0100"
  },
  "message": "Fixed arithmetic right shifts not sign extending correctly.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ef8d754fb3b7bc53a5dc065a9d1fcba722369961",
      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/RV32ICore.v",
      "new_id": "4017da8dbea658fc584402818bec67ddf71aeb03",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/RV32ICore.v"
    }
  ]
}