)]}'
{
  "commit": "c138fb0519ad778b4625b6f1d7391c7018ac14c5",
  "tree": "af9ac99468df85aa3347774fab6612b83a686292",
  "parents": [
    "951f5a34fb96c59e219de6851038767f211be617"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sun May 22 22:06:01 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sun May 22 22:06:01 2022 +0100"
  },
  "message": "Added core program counter test. Also fixed the core not putting any of the core in the macro. This was caused by the unimplemented JTAG device not sending a signal to the core management, preventing it from ever allowing the core to run, resulting it being optimised away.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "32fe57b4201243aa5d6f58e919fe149ea6827939",
      "old_mode": 33188,
      "old_path": "docs/Testing/Testing.md",
      "new_id": "1154da77e0cdf2f8f35dfba75c3f9bd52cf85d55",
      "new_mode": 33188,
      "new_path": "docs/Testing/Testing.md"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "new_mode": 33188,
      "new_path": "verilog/dv/corePC/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5f78d80e8e067f7a32184fae35b4d9afbfc25b38",
      "new_mode": 33188,
      "new_path": "verilog/dv/corePC/corePC.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a1d6de9a7676f08585ae4aa686bab18261513b42",
      "new_mode": 33188,
      "new_path": "verilog/dv/corePC/corePC_tb.v"
    },
    {
      "type": "modify",
      "old_id": "144efa71ea1fda36adff5687df737a8324abd493",
      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/JTAG.v",
      "new_id": "c959d009abb4bd2f2831c1b8e51ce975233f639d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/JTAG.v"
    },
    {
      "type": "modify",
      "old_id": "2f005be43a981e7c7e788a5237237b2dbe2e639c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/RV32ICore.v",
      "new_id": "fc9fd7d84f8fde107801574c619b9d29a5ed7b34",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/RV32ICore.v"
    }
  ]
}