)]}'
{
  "commit": "bedb595d4dfe22d088efac99de78eb4ddc23322d",
  "tree": "d8cf95d776f4f7dcd7a3f3abe5ba77c94c2e1bd3",
  "parents": [
    "2988523b0cc07f1a93ae7a88f831c5b933343150"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 19:09:15 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 19:09:15 2022 +0100"
  },
  "message": "Fixed N input mux not generating an output signal.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cf94a333f628686a4624fb932273c6aeba100595",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Utility/Mux.v",
      "new_id": "4fa8756c7bd60d098fcf74de8ac4d47fd634492c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Utility/Mux.v"
    }
  ]
}