)]}'
{
  "commit": "a56209ce3d9b40000c08c19dc0b88f7e94f46d52",
  "tree": "712abf767f5a0e1e442b3a798f2d419ee1ba4efa",
  "parents": [
    "c678a2e4fa47590c2b0b6f555275df724974152a"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sun May 29 22:36:34 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sun May 29 22:36:34 2022 +0100"
  },
  "message": "Fixed that address misalignment error bit could be set when not performing a load or store instruction. This means that some other instructions would trigger the core to lock, when performing valid instructions.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5319df1c15e0ca299b381dffedd9a232cf39aa84",
      "old_mode": 33188,
      "old_path": "verilog/rtl/ExperiarCore/RV32ICore.v",
      "new_id": "b43552443d21d3ac70ff843eb02b50f7b0f6a8f9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/ExperiarCore/RV32ICore.v"
    }
  ]
}