tree c643e99e321478b4480194edc90c2e0d1bbe2fd2
parent 626c8dc5099128794b80f564a62e13afb0d78460
author Charlie <charlie.david.smith@hotmail.co.uk> 1653774013 +0100
committer Charlie <charlie.david.smith@hotmail.co.uk> 1653774013 +0100

Fixed gpio not getting input connections (a bit more) due to verilog being dumb and not correctly parsing a mux inside a mux when performing syntheses, even though it works correctly in rtl simulation.