)]}'
{
  "commit": "9e727281760308b1e83e89e2b893f9bb717e36f9",
  "tree": "c643e99e321478b4480194edc90c2e0d1bbe2fd2",
  "parents": [
    "626c8dc5099128794b80f564a62e13afb0d78460"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 28 22:40:13 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 28 22:40:13 2022 +0100"
  },
  "message": "Fixed gpio not getting input connections (a bit more) due to verilog being dumb and not correctly parsing a mux inside a mux when performing syntheses, even though it works correctly in rtl simulation.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8e676365a2e0f90cbe57296ee82642c71b4b14d4",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheralsGPIO/peripheralsGPIO.c",
      "new_id": "d722d5bf39fd712ac0a460fce73686b79de21071",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsGPIO/peripheralsGPIO.c"
    },
    {
      "type": "modify",
      "old_id": "1abb9a160db6a59612e6f82036a1757bde573036",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py",
      "new_id": "1d58cb5fae7928aefbc742b8214113618cc194ab",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py"
    },
    {
      "type": "modify",
      "old_id": "c3d4edab077c24a889340f63b02d226f98978347",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v",
      "new_id": "48a5448961473418e888e0a34d79a81b3cdf4420",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v"
    }
  ]
}