diff --git a/verilog/dv/flash/Makefile b/verilog/dv/flash/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/flash/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/flash/flash.c b/verilog/dv/flash/flash.c
new file mode 100644
index 0000000..a3fedea
--- /dev/null
+++ b/verilog/dv/flash/flash.c
@@ -0,0 +1,191 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+#define GPIO0_OE_WRITE_ADDR ((uint32_t*)0x33031000)
+#define GPIO0_OE_SET_ADDR ((uint32_t*)0x33031004)
+#define GPIO0_OE_CLEAR_ADDR ((uint32_t*)0x33031008)
+#define GPIO0_OE_TOGGLE_ADDR ((uint32_t*)0x3303100C)
+#define GPIO0_OUTPUT_WRITE_ADDR ((uint32_t*)0x33031010)
+#define GPIO0_OUTPUT_SET_ADDR ((uint32_t*)0x33031014)
+#define GPIO0_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33031018)
+#define GPIO0_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303101C)
+#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031020)
+#define GPIO1_OE_WRITE_ADDR ((uint32_t*)0x33032000)
+#define GPIO1_OE_SET_ADDR ((uint32_t*)0x33032004)
+#define GPIO1_OE_CLEAR_ADDR ((uint32_t*)0x33032008)
+#define GPIO1_OE_TOGGLE_ADDR ((uint32_t*)0x3303200C)
+#define GPIO1_OUTPUT_WRITE_ADDR ((uint32_t*)0x33032010)
+#define GPIO1_OUTPUT_SET_ADDR ((uint32_t*)0x33032014)
+#define GPIO1_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33032018)
+#define GPIO1_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303201C)
+#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020)
+
+#define FLASH_DATA ((uint32_t*)0x3400000)
+#define FLASH_CONFIGURATION ((uint32_t*)0x34001000)
+#define FLASH_BASE_ADDRESS ((uint32_t*)0x34001004)
+#define FLASH_CACHED_ADDRESS ((uint32_t*)0x34001008)
+
+#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000)
+#define MPRJ_WB_DATA_LOCATION 0x30008000
+
+void wbWrite (uint32_t* location, uint32_t value)
+{
+	// Write the address
+	uint32_t locationData = (uint32_t)location;
+	MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+	// Write the data
+	uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+	*((volatile uint32_t*)writeAddress) = value;
+}
+
+uint32_t wbRead (uint32_t* location)
+{
+	// Write the address
+	uint32_t locationData = (uint32_t)location;
+	MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+	// Write the data
+	uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+	return *((volatile uint32_t*)writeAddress);
+}
+
+void nextTest (bool testPassing)
+{
+	if (testPassing)
+	{
+		wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+	}
+	else
+	{
+		wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+		wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+	}
+
+	wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
+}
+
+void main ()
+{
+	/*
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+
+
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+	// https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt
+
+	// Enable the wishbone bus
+	reg_wb_enable = 1;
+
+	// Enable GPIO
+	reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+	reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1) {}
+
+	// Setup test output
+	bool testPass = true;
+	wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x01000);
+	wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000);
+
+	// Enable
+	wbWrite (FLASH_CONFIGURATION, 0x1);
+	if (wbRead (FLASH_CONFIGURATION) != 0x1) testPass = false;
+	nextTest (testPass);
+
+	// Set the base address
+	// This will probably be the default value
+	wbWrite (FLASH_BASE_ADDRESS, 0x0);
+	if (wbRead (FLASH_BASE_ADDRESS) != 0x0) testPass = false;
+	nextTest (testPass);
+
+	// Check that data is marked as cached
+	uint32_t tries = 5;
+	while (tries > 0 && wbRead (FLASH_CACHED_ADDRESS) < 0x20) tries--;
+	if (tries == 0) testPass = false;
+	nextTest (testPass);
+
+	// Check that the cached data is correct
+	if (wbRead (FLASH_DATA) != 0x03020100) testPass = false;
+	nextTest (testPass);
+
+	if (wbRead (FLASH_DATA + 1) != 0xA2706054) testPass = false;
+	nextTest (testPass);
+
+	if (wbRead (FLASH_DATA + 2) != 0xD3C2B1A0) testPass = false;
+	nextTest (testPass);
+
+	if (wbRead (FLASH_DATA + 3) != 0x1706F5E4) testPass = false;
+	nextTest (testPass);
+
+	// Change to another location in flash
+	// Set the base address
+	// This will probably be the default value
+	wbWrite (FLASH_BASE_ADDRESS, 0xF000);
+	if (wbRead (FLASH_BASE_ADDRESS) != 0x0) testPass = false;
+	nextTest (testPass);
+
+	// Check that data is marked as cached
+	tries = 5;
+	while (tries > 0 && wbRead (FLASH_CACHED_ADDRESS) < 0x20) tries--;
+	if (tries == 0) testPass = false;
+	nextTest (testPass);
+
+	// Check that the cached data is correct
+	if (wbRead (FLASH_DATA) != 0xCB232C81) testPass = false;
+	nextTest (testPass);
+
+	if (wbRead (FLASH_DATA + 1) != 0xEFF0DFF6) testPass = false;
+	nextTest (testPass);
+
+	if (wbRead (FLASH_DATA + 2) != 0xFE23A0E7) testPass = false;
+	nextTest (testPass);
+
+	if (wbRead (FLASH_DATA + 3) != 0x13050588) testPass = false;
+
+	// Finish test
+	nextTest (testPass);
+}
diff --git a/verilog/dv/flash/flash_tb.v b/verilog/dv/flash/flash_tb.v
new file mode 100644
index 0000000..01cb8e9
--- /dev/null
+++ b/verilog/dv/flash/flash_tb.v
@@ -0,0 +1,226 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module flash_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+
+	wire succesOutput = mprj_io[12];
+	wire nextTestOutput = mprj_io[13];
+
+	wire user_flash_csb = mprj_io[8];
+	wire user_flash_clk = mprj_io[9];
+	wire user_flash_io0 = mprj_io[10];
+	wire user_flash_io1;
+	assign mprj_io[11] = user_flash_io1;
+
+	pullup(mprj_io[3]);
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+	always #12.5 clock <= (clock === 1'b0);
+
+	// Need to add pulls (can be up or down) to all unsed io so that input data is known
+	assign mprj_io[2:0] = 3'b0;
+	assign mprj_io[7:4] = 4'b0;
+	assign mprj_io[37:14] = 24'b0;
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("flash.vcd");
+
+`ifdef SIM
+		$dumpvars(0, flash_tb);
+`else
+		$dumpvars(1, flash_tb);
+		$dumpvars(2, flash_tb.uut.mprj);
+`endif
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (300) begin
+			repeat (1000) @(posedge clock);
+			//$display("+1000 cycles");
+		end
+		$display("%c[1;35m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Flash Test (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Flash Test (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		
+		// Enable
+		@(posedge nextTestOutput);
+
+		// Set the base address
+		@(posedge nextTestOutput);
+
+		// Check that data is marked as cached
+		@(posedge nextTestOutput);
+
+		// Check that the cached data is correct
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+
+		// Change to second location
+		// Set the base address
+		@(posedge nextTestOutput);
+
+		// Check that data is marked as cached
+		@(posedge nextTestOutput);
+
+		// Check that the cached data is correct
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+
+		// Wait for management core to output the final output test result
+		@(posedge nextTestOutput);
+		
+		if (succesOutput) begin
+			$display("%c[1;92m",27);
+			`ifdef GL
+				$display("Monitor: Flash Test (GL) Passed");
+			`else
+				$display("Monitor: Flash Test (RTL) Passed");
+			`endif
+			$display("%c[0m",27);
+		end else begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display ("Monitor: Flash Test (GL) Failed");
+			`else
+				$display ("Monitor: Flash Test (RTL) Failed");
+			`endif
+			$display("%c[0m",27);
+		end
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#300000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	always @(succesOutput, nextTestOutput) begin
+		#1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput);
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("flash.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	spiflash #(
+		.FILENAME("test.hex")
+	) testflash (
+		.csb(user_flash_csb),
+		.clk(user_flash_clk),
+		.io0(user_flash_io0),
+		.io1(user_flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire