)]}'
{
  "commit": "95c709cf81d88c4d5b3ce45c1c807ad6fb3af0e1",
  "tree": "38b8b622243cf84c38c13753548ff8add60595e0",
  "parents": [
    "933bd6bff9690856dbeba32f81145b45afa56adf"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Mon Jun 06 23:23:21 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Mon Jun 06 23:23:21 2022 +0100"
  },
  "message": "Fixed cores not being able to access the wishbone bus.\n",
  "tree_diff": [
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      "new_mode": 33188,
      "new_path": "verilog/dv/coreMemory/coreMemory.c"
    },
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      "new_path": "verilog/dv/memory/memory.c"
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      "old_path": "verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v",
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      "new_mode": 33188,
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      "old_mode": 33188,
      "old_path": "verilog/rtl/WishboneInterconnect/MasterArbiter.v",
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}