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# Created by write_sdc
# Mon Jun  6 23:19:14 2022
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current_design Flash
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# Timing Constraints
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create_clock -name clk -period 25.0000 
set_clock_uncertainty 0.2500 clk
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0_read}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1_read}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[0]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[10]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[11]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[12]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[13]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[14]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[15]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[16]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[17]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[18]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[19]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[1]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[20]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[21]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[22]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[23]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[24]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[25]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[26]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[27]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[28]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[29]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[2]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[30]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[31]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[3]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[4]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[5]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[6]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[7]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[8]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout0[9]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[0]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[10]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[11]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[12]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[13]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[14]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[15]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[16]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[17]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[18]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[19]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[1]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[20]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[21]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[22]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[23]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[24]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[25]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[26]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[27]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[28]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[29]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[2]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[30]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[31]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[3]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[4]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[5]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[6]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[7]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[8]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_dout1[9]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[0]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[10]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[11]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[12]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[13]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[14]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[15]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[16]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[17]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[18]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[19]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[1]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[20]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[21]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[22]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[23]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[2]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[3]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[4]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[5]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[6]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[7]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[8]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_adr_i[9]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_clk_i}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_cyc_i}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[0]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[10]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[11]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[12]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[13]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[14]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[15]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[16]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[17]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[18]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[19]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[1]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[20]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[21]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[22]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[23]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[24]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[25]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[26]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[27]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[28]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[29]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[2]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[30]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[31]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[3]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[4]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[5]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[6]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[7]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[8]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_i[9]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_rst_i}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_stb_i}]
set_input_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_we_i}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0_we}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0_write}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1_we}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1_write}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {flash_sck}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[0]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[1]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[2]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[3]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[4]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[5]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[6]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[7]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr0[8]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[0]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[1]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[2]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[3]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[4]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[5]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[6]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[7]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_addr1[8]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_clk0}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_clk1}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_csb0}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_csb1}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[0]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[10]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[11]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[12]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[13]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[14]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[15]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[16]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[17]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[18]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[19]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[1]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[20]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[21]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[22]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[23]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[24]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[25]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[26]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[27]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[28]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[29]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[2]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[30]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[31]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[3]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[4]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[5]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[6]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[7]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[8]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_din0[9]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_web0}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_wmask0[0]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_wmask0[1]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_wmask0[2]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {sram_wmask0[3]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_ack_o}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[0]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[10]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[11]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[12]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[13]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[14]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[15]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[16]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[17]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[18]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[19]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[1]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[20]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[21]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[22]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[23]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[24]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[25]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[26]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[27]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[28]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[29]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[2]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[30]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[31]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[3]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[4]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[5]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[6]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[7]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[8]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_data_o[9]}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_error_o}]
set_output_delay 5.0000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_stall_o}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {flash_csb}]
set_load -pin_load 0.0334 [get_ports {flash_io0_we}]
set_load -pin_load 0.0334 [get_ports {flash_io0_write}]
set_load -pin_load 0.0334 [get_ports {flash_io1_we}]
set_load -pin_load 0.0334 [get_ports {flash_io1_write}]
set_load -pin_load 0.0334 [get_ports {flash_sck}]
set_load -pin_load 0.0334 [get_ports {sram_clk0}]
set_load -pin_load 0.0334 [get_ports {sram_clk1}]
set_load -pin_load 0.0334 [get_ports {sram_csb0}]
set_load -pin_load 0.0334 [get_ports {sram_csb1}]
set_load -pin_load 0.0334 [get_ports {sram_web0}]
set_load -pin_load 0.0334 [get_ports {wb_ack_o}]
set_load -pin_load 0.0334 [get_ports {wb_error_o}]
set_load -pin_load 0.0334 [get_ports {wb_stall_o}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[8]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[7]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[6]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[5]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[4]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[0]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[8]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[7]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[6]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[5]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[4]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[3]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[2]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[1]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[0]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[31]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[30]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[29]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[28]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[27]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[26]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[25]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[24]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[23]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[22]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[21]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[20]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[19]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[18]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[17]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[16]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[15]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[14]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[13]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[12]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[11]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[10]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[9]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[8]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[7]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[6]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[5]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[4]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[0]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[0]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[31]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[30]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[29]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[28]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[27]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[26]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[25]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[24]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[23]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[22]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[21]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[20]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[19]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[18]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[17]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[16]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[15]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[14]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[13]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[12]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[11]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[10]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[9]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[8]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[7]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[6]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[5]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[4]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[3]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[2]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[1]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {flash_io0_read}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {flash_io1_read}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]