diff --git a/verilog/dv/.gitignore b/verilog/dv/.gitignore
new file mode 100644
index 0000000..eb9393f
--- /dev/null
+++ b/verilog/dv/.gitignore
@@ -0,0 +1,11 @@
+*.hex*
+*.lst
+*.vcd
+*.vcd.hier
+*.vvp
+*.gtkw
+coreArch/riscof/riscof_work/
+coreArch/riscof/sail_cSim/__pycache__/
+coreArch/riscof/ExperiarSoC/__pycache__/
+coreArch/DUT-ExperiarSoC.signature
+coreArch/coreArch.disass
\ No newline at end of file
diff --git a/verilog/dv/coreArch/Makefile b/verilog/dv/coreArch/Makefile
index 0d2b4a8..9993dce 100644
--- a/verilog/dv/coreArch/Makefile
+++ b/verilog/dv/coreArch/Makefile
@@ -24,12 +24,14 @@
 ## Caravel Verilog for Integration Tests
 #######################################################################
 
-export USER_PROJECT_VERILOG ?= /mnt/f/WSL/ASIC/ExperiarSoC/verilog
+export DESIGNS ?= /mnt/f/WSL/ASIC/ExperiarSoC
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 export CARAVEL_ROOT ?= /mnt/f/WSL/ASIC/ExperiarSoC/caravel
 export IVERILOG_DUMPER = fst
 
-GCC_PATH=/opt/riscv32i/bin
-GCC_PREFIX=riscv32-unknown-elf
+
+GCC_PATH?=/opt/riscv32i/bin
+GCC_PREFIX?=riscv32-unknown-elf
 
 # RTL/GL/GL_SDF
 SIM?=RTL
@@ -65,7 +67,7 @@
 
 ## GL
 ifeq ($(SIM),GL)
-	iiverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
 	-DSIGNATURE_START=$(SIGNATURE_START) -DSIGNATURE_END=$(SIGNATURE_END) -DCODE_END=$(CODE_END) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
 endif 
@@ -81,9 +83,11 @@
 coreArch.vcd: coreArch.vvp
 ifeq ($(SIM),RTL)
 	vvp  $<
+	 mv $@ RTL-$@
 endif
 ifeq ($(SIM),GL)
 	vvp  $<
+	 mv $@ GL-$@
 endif
 
 .PHONY: hex
diff --git a/verilog/dv/coreArch/coreArch.elf b/verilog/dv/coreArch/coreArch.elf
new file mode 100644
index 0000000..6c27364
--- /dev/null
+++ b/verilog/dv/coreArch/coreArch.elf
Binary files differ
diff --git a/verilog/dv/coreArch/runArchTest.py b/verilog/dv/coreArch/runArchTest.py
index 0046f5a..77ed256 100644
--- a/verilog/dv/coreArch/runArchTest.py
+++ b/verilog/dv/coreArch/runArchTest.py
@@ -21,7 +21,7 @@
 		makeFilePath = os.path.dirname(os.path.abspath(__file__))
 		shutil.copy2(os.path.join(makeFilePath, "coreArch_tb.v"), os.getcwd())
 		shutil.copy2(os.path.join(makeFilePath, "Makefile"), os.getcwd())
-		RunShellCommand(["make"])
+		RunShellCommand(["make"]) # , "SIM=GL"
 	except Exception as e:
 		print(e)