)]}'
{
  "commit": "7d7207a1eb188e3277ade12be54f319b78208ba1",
  "tree": "033f20c142362c0d6a457acfbb1ddcf4fc63bb24",
  "parents": [
    "e851b8afcd11bd89694aa53c39a0442f2c15ed60"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 18:43:37 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 18:43:37 2022 +0100"
  },
  "message": "Updated testing setup to remove example tests, and provide a proper GPIO test which passes when using verify rtl.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "223bdb13a78c3bf17096429be4d8dbcfde097a94",
      "old_mode": 33188,
      "old_path": "README.md",
      "new_id": "1ec2cf9f9d186745988b8e38be1ea75a9ff4a81f",
      "new_mode": 33188,
      "new_path": "README.md"
    },
    {
      "type": "modify",
      "old_id": "c97c5649057475c3cb7712c88c90919ea05af7be",
      "old_mode": 33188,
      "old_path": "docs/Testing/Testing.md",
      "new_id": "32fe57b4201243aa5d6f58e919fe149ea6827939",
      "new_mode": 33188,
      "new_path": "docs/Testing/Testing.md"
    },
    {
      "type": "delete",
      "old_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d204e4a11fd14a493ca6958b5d5c1f2459908a04",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "cf66d3fcb64d3199f987d0cadb1da38db0cc338b",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "cad69d115c70aa38b88d68e33c370a001b4bcce7",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "e0fff24b089cfcf94f2058c266cd4a39a51ee4cf",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "25fad481e188bd9c186b9706f140fff0f4ad9764",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "6ef965dbc3f2c33651edb55dbb1b6d6d841139dd",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d049848c8f04932337cabdb310e796ab28ba94d5",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "68addd0620b4184878d5e0a4e3bfe19fdcd60d52",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "01ef43ed0edb7fba3a8435e68f05e03f5199ebc2",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheral/peripheral.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "0ee9e44646f7fcfcadcc30ca8df144bd12b6d316",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheral/peripheral_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "rename",
      "old_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "old_mode": 33188,
      "old_path": "verilog/dv/peripheral/Makefile",
      "new_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsGPIO/Makefile",
      "score": 100
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1325ed66bb11a829388de1db734cde4301abc2b0",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsGPIO/peripheralsGPIO.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8734f36925ccb9d1af9fbdad1aac9610fa32357a",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v"
    },
    {
      "type": "delete",
      "old_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "4f590556cd345c9b720def558651055d677c06bc",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/wb_port.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d5c29830401d8c6858beda051fad63cc47e71edb",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/wb_port_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "b52322e300809c57c6466eae3c2c9078984916d0",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.gl+sdf.caravel_user_project",
      "new_id": "95e8af226da4181570d07057ccd370ddde95bc0e",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.gl+sdf.caravel_user_project"
    },
    {
      "type": "modify",
      "old_id": "4b8d988a84ed789a0eaa2d074a1f23e548def887",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.gl.caravel_user_project",
      "new_id": "a0fd648d12b4edceed3447cf0eb057a8d14a54b2",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.gl.caravel_user_project"
    }
  ]
}
