)]}'
{
  "commit": "7b09468ed11e245574c08155eb91f119ee34c11e",
  "tree": "dd9f8928f539b0960c2438ab454da500476c3d43",
  "parents": [
    "6ab7edd5e4f440579d74160af9dcb0304cffe5fb"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Thu May 26 17:59:36 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Thu May 26 17:59:36 2022 +0100"
  },
  "message": "Fixed VGA pixel data being misaligned with synchronisation signals.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "74421576d35c0c2e63bfea1d402b8052fb6eb974",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Video/VGA_top.v",
      "new_id": "31cea36c653b7c4eb4d899a79798f31e4a7e406b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Video/VGA_top.v"
    }
  ]
}