)]}'
{
  "commit": "63c22b1f15ae4963945b7095705dfb107e2e6a57",
  "tree": "3b5b45cfa626154c8f4641df208ea739dc17fb64",
  "parents": [
    "bddc1c1ce74edfb26a78b8812adce424c78e3303"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sun Jun 05 21:26:35 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sun Jun 05 21:26:35 2022 +0100"
  },
  "message": "Fixed an additional clock cycle being generated by the flash controller.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c59e36601027bdb7964b857eb06bcda5c04a27e3",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Flash/QSPIDevice.v",
      "new_id": "0ab1010bf8b6774f478e182b3ff0aeb434d04838",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Flash/QSPIDevice.v"
    }
  ]
}