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# Created by write_sdc
# Mon Jun  6 22:23:20 2022
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current_design WishboneInterconnect
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# Timing Constraints
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create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_propagated_clock [get_clocks {wb_clk_i}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_adr_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_cyc_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_sel_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_sel_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_sel_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_sel_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_stb_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_we_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_adr_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_cyc_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_sel_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_sel_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_sel_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_sel_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_stb_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_we_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_adr_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_cyc_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_sel_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_sel_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_sel_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_sel_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_stb_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_we_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_ack_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_error_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_stall_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_ack_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_error_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_stall_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_ack_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_error_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_stall_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_ack_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_error_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_stall_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_ack_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_o[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_error_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_stall_o}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_ack_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_error_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master0_wb_stall_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_ack_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_error_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master1_wb_stall_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_ack_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_error_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {master2_wb_stall_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master0_currentSlave[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master0_currentSlave[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master1_currentSlave[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master1_currentSlave[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master2_currentSlave[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master2_currentSlave[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master3_currentSlave[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_master3_currentSlave[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave0_currentMaster[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave0_currentMaster[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave1_currentMaster[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave1_currentMaster[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave2_currentMaster[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave2_currentMaster[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave3_currentMaster[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_slave3_currentMaster[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_adr_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_cyc_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_sel_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_sel_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_sel_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_sel_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_stb_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave0_wb_we_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_adr_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_cyc_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_sel_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_sel_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_sel_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_sel_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_stb_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave1_wb_we_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_adr_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_cyc_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_sel_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_sel_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_sel_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_sel_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_stb_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave2_wb_we_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_adr_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_cyc_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_sel_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_sel_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_sel_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_sel_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_stb_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave3_wb_we_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_adr_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_cyc_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_data_i[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_sel_i[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_sel_i[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_sel_i[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_sel_i[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_stb_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {slave4_wb_we_i}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {master0_wb_ack_i}]
set_load -pin_load 0.0334 [get_ports {master0_wb_error_i}]
set_load -pin_load 0.0334 [get_ports {master0_wb_stall_i}]
set_load -pin_load 0.0334 [get_ports {master1_wb_ack_i}]
set_load -pin_load 0.0334 [get_ports {master1_wb_error_i}]
set_load -pin_load 0.0334 [get_ports {master1_wb_stall_i}]
set_load -pin_load 0.0334 [get_ports {master2_wb_ack_i}]
set_load -pin_load 0.0334 [get_ports {master2_wb_error_i}]
set_load -pin_load 0.0334 [get_ports {master2_wb_stall_i}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_cyc_i}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_stb_i}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_we_i}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_cyc_i}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_stb_i}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_we_i}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_cyc_i}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_stb_i}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_we_i}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_cyc_i}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_stb_i}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_we_i}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_cyc_i}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_stb_i}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_we_i}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {master0_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {master1_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {master2_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {probe_master0_currentSlave[1]}]
set_load -pin_load 0.0334 [get_ports {probe_master0_currentSlave[0]}]
set_load -pin_load 0.0334 [get_ports {probe_master1_currentSlave[1]}]
set_load -pin_load 0.0334 [get_ports {probe_master1_currentSlave[0]}]
set_load -pin_load 0.0334 [get_ports {probe_master2_currentSlave[1]}]
set_load -pin_load 0.0334 [get_ports {probe_master2_currentSlave[0]}]
set_load -pin_load 0.0334 [get_ports {probe_master3_currentSlave[1]}]
set_load -pin_load 0.0334 [get_ports {probe_master3_currentSlave[0]}]
set_load -pin_load 0.0334 [get_ports {probe_slave0_currentMaster[1]}]
set_load -pin_load 0.0334 [get_ports {probe_slave0_currentMaster[0]}]
set_load -pin_load 0.0334 [get_ports {probe_slave1_currentMaster[1]}]
set_load -pin_load 0.0334 [get_ports {probe_slave1_currentMaster[0]}]
set_load -pin_load 0.0334 [get_ports {probe_slave2_currentMaster[1]}]
set_load -pin_load 0.0334 [get_ports {probe_slave2_currentMaster[0]}]
set_load -pin_load 0.0334 [get_ports {probe_slave3_currentMaster[1]}]
set_load -pin_load 0.0334 [get_ports {probe_slave3_currentMaster[0]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_adr_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_sel_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_sel_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_sel_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave0_wb_sel_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_adr_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_sel_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_sel_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_sel_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave1_wb_sel_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_adr_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_sel_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_sel_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_sel_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave2_wb_sel_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_adr_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_sel_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_sel_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_sel_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave3_wb_sel_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_adr_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[31]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[30]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[29]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[28]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[27]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[26]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[25]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[24]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[23]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[22]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[21]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[20]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[19]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[18]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[17]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[16]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[15]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[14]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[13]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[12]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[11]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[10]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[9]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[8]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[7]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[6]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[5]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[4]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_data_i[0]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_sel_i[3]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_sel_i[2]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_sel_i[1]}]
set_load -pin_load 0.0334 [get_ports {slave4_wb_sel_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_cyc_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_stb_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_we_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_cyc_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_stb_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_we_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_cyc_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_stb_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_we_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_ack_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_error_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_stall_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_ack_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_error_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_stall_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_ack_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_error_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_stall_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_ack_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_error_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_stall_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_ack_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_error_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_stall_o}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_adr_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_sel_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_sel_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_sel_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master0_wb_sel_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_adr_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_sel_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_sel_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_sel_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master1_wb_sel_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_adr_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_sel_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_sel_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_sel_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {master2_wb_sel_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave0_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave1_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave2_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave3_wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {slave4_wb_data_o[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]