diff --git a/verilog/dv/coreMemory/GenerateTestInstructions.py b/verilog/dv/coreMemory/GenerateTestInstructions.py
new file mode 100644
index 0000000..fcf7cec
--- /dev/null
+++ b/verilog/dv/coreMemory/GenerateTestInstructions.py
@@ -0,0 +1,20 @@
+
+def AddTest(address):
+	print(f"{'0x%08x' % address} -> {'0x%08x' % (address + 4)}")
+	PrintInstructionData((address & 0xFFFFF000) | (0b0_0001 << 7) | 0b0110111)
+
+def PrintInstructionData(data):
+	print("0x%08x" % data)
+
+def main():
+	AddTest(0x0000_0000)
+	AddTest(0x1000_0000)
+	AddTest(0x1100_0000)
+	AddTest(0x1200_0000)
+
+	print("Commands:")
+	PrintInstructionData((0b0000_0000_0000 << 20) | (0b0_0001 << 15) | (0b010 << 12) | (0b0_0011 << 7) | 0b0000011)
+	PrintInstructionData((0b000_0000 << 25) | (0b0_0011 << 20) | (0b0_0001 << 15) | (0b010 << 12) | (0b0_0100 << 7) | 0b0100011)
+
+if __name__ == "__main__":
+	main()
\ No newline at end of file
diff --git a/verilog/dv/coreMemory/Makefile b/verilog/dv/coreMemory/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/coreMemory/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/coreMemory/coreMemory.c b/verilog/dv/coreMemory/coreMemory.c
new file mode 100644
index 0000000..6ef204c
--- /dev/null
+++ b/verilog/dv/coreMemory/coreMemory.c
@@ -0,0 +1,181 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+#define GPIO0_OE_WRITE_ADDR ((uint32_t*)0x33031000)
+#define GPIO0_OE_SET_ADDR ((uint32_t*)0x33031004)
+#define GPIO0_OE_CLEAR_ADDR ((uint32_t*)0x33031008)
+#define GPIO0_OE_TOGGLE_ADDR ((uint32_t*)0x3303100C)
+#define GPIO0_OUTPUT_WRITE_ADDR ((uint32_t*)0x33031010)
+#define GPIO0_OUTPUT_SET_ADDR ((uint32_t*)0x33031014)
+#define GPIO0_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33031018)
+#define GPIO0_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303101C)
+#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031020)
+#define GPIO1_OE_WRITE_ADDR ((uint32_t*)0x33032000)
+#define GPIO1_OE_SET_ADDR ((uint32_t*)0x33032004)
+#define GPIO1_OE_CLEAR_ADDR ((uint32_t*)0x33032008)
+#define GPIO1_OE_TOGGLE_ADDR ((uint32_t*)0x3303200C)
+#define GPIO1_OUTPUT_WRITE_ADDR ((uint32_t*)0x33032010)
+#define GPIO1_OUTPUT_SET_ADDR ((uint32_t*)0x33032014)
+#define GPIO1_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33032018)
+#define GPIO1_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303201C)
+#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020)
+
+#define CORE0_CONFIG_ADDR ((uint32_t*)0x30800000)
+#define CORE0_STATUS_ADDR ((uint32_t*)0x30800004)
+#define CORE0_REG_PC_ADDR ((uint32_t*)0x30810000)
+#define CORE0_REG_JUMP_ADDR ((uint32_t*)0x30810004)
+#define CORE0_REG_STEP_ADDR ((uint32_t*)0x30810008)
+#define CORE0_REG_INSTR_ADDR ((uint32_t*)0x30810010)
+#define CORE0_REG_IREG_ADDR ((uint32_t*)0x30811000)
+#define CORE0_SRAM_ADDR ((uint32_t*)0x30000000)
+
+#define CORE1_CONFIG_ADDR ((uint32_t*)0x31800000)
+#define CORE1_STATUS_ADDR ((uint32_t*)0x31800004)
+#define CORE1_REG_PC_ADDR ((uint32_t*)0x31810000)
+#define CORE1_REG_JUMP_ADDR ((uint32_t*)0x31810004)
+#define CORE1_REG_STEP_ADDR ((uint32_t*)0x31810008)
+#define CORE1_REG_INSTR_ADDR ((uint32_t*)0x31810010)
+#define CORE1_REG_IREG_ADDR ((uint32_t*)0x31811000)
+#define CORE1_SRAM_ADDR ((uint32_t*)0x31000000)
+
+#define CORE0_SRAM ((uint32_t*)0x30000000)
+#define CORE1_SRAM ((uint32_t*)0x31000000)
+#define VGA_SRAM ((uint32_t*)0x32000000)
+#define SRAM_BANK_SIZE 0x200
+
+#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000)
+#define MPRJ_WB_DATA_LOCATION 0x30008000
+
+#define CORE_RUN 0x1
+#define CORE_HALT 0x0
+#define CORE_RUNNING_NOERROR 0x10
+
+#define RV32I_NOP 0x00000013
+#define RV32I_JMP_PREV 0xFFDFF06F
+
+void wbWrite (uint32_t* location, uint32_t value)
+{
+	// Write the address
+	uint32_t locationData = (uint32_t)location;
+	MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+	// Write the data
+	uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+	*((volatile uint32_t*)writeAddress) = value;
+}
+
+uint32_t wbRead (uint32_t* location)
+{
+	// Write the address
+	uint32_t locationData = (uint32_t)location;
+	MPRJ_WB_ADDRESS = locationData & 0xFFFF8000;
+
+	// Write the data
+	uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION;
+	return *((volatile uint32_t*)writeAddress);
+}
+
+void nextTest (bool testPassing)
+{
+	if (testPassing)
+	{
+		wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000);
+	}
+	else
+	{
+		wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000);
+		wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000);
+	}
+
+	wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000);
+}
+
+bool testMemory (uint32_t address, uint32_t loadAddressInstruction, uint32_t data)
+{
+	wbWrite ((uint32_t*)address, data);
+	wbWrite (CORE0_SRAM + 2, loadAddressInstruction);
+	wbWrite (CORE0_REG_PC_ADDR, 0x8);
+	wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+	wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+	wbWrite (CORE0_REG_STEP_ADDR, 0x0);
+	return wbRead ((uint32_t*)(address + 4)) == data;
+}
+
+void main ()
+{
+	/*
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+
+
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+	// https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt
+
+	// Enable the wishbone bus
+	reg_wb_enable = 1;
+
+	// Enable GPIO
+	reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1) {}
+
+	// Setup test output
+	bool testPass = true;
+	wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x01000);
+	wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000);
+
+	wbWrite (CORE0_SRAM + 3, 0x0000a183);
+	wbWrite (CORE0_SRAM + 4, 0x00312223);
+
+	if (!testMemory (0x30000000, 0x000000b7, 0x12345678)) testPass = false;
+	nextTest (testPass);
+
+	if (!testMemory (0x30000000, 0x100000b7, 0x9ABCDEF0)) testPass = false;
+	nextTest (testPass);
+
+	if (!testMemory (0x31000000, 0x110000b7, 0x849A5C12)) testPass = false;
+	nextTest (testPass);
+
+	if (!testMemory (0x32000000, 0x120000b7, 0xBE091D57)) testPass = false;
+
+	// Finish test
+	nextTest (testPass);
+}
diff --git a/verilog/dv/coreMemory/coreMemory_tb.v b/verilog/dv/coreMemory/coreMemory_tb.v
new file mode 100644
index 0000000..d3abe19
--- /dev/null
+++ b/verilog/dv/coreMemory/coreMemory_tb.v
@@ -0,0 +1,186 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module coreMemory_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+
+	wire succesOutput = mprj_io[12];
+	wire nextTestOutput = mprj_io[13];
+
+	pullup(mprj_io[3]);
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+	always #12.5 clock <= (clock === 1'b0);
+
+	// Need to add pulls (can be up or down) to all unsed io so that input data is known
+	assign mprj_io[2:0] = 3'b0;
+	assign mprj_io[11:4] = 8'b0;
+	assign mprj_io[37:14] = 24'b0;
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("coreMemory.vcd");
+
+`ifdef SIM
+		$dumpvars(0, coreMemory_tb);
+`else
+		$dumpvars(1, coreMemory_tb);
+		$dumpvars(2, coreMemory_tb.uut.mprj);
+`endif
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (500) begin
+			repeat (1000) @(posedge clock);
+			//$display("+1000 cycles");
+		end
+		$display("%c[1;35m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Core Memory Test (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Core Memory Test (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		// Wait for tests
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+
+		// Wait for management core to output a output test result
+		@(posedge nextTestOutput);
+		
+		if (succesOutput) begin
+			$display("%c[1;92m",27);
+			`ifdef GL
+				$display("Monitor: Core Memory Test (GL) Passed");
+			`else
+				$display("Monitor: Core Memory Test (RTL) Passed");
+			`endif
+			$display("%c[0m",27);
+		end else begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display ("Monitor: Core Memory Test (GL) Failed");
+			`else
+				$display ("Monitor: Core Memory Test (RTL) Failed");
+			`endif
+			$display("%c[0m",27);
+		end
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#300000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	always @(succesOutput, nextTestOutput) begin
+		#1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput);
+	end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("coreMemory.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire