)]}'
{
  "commit": "530e657f9a514d656ac6fc9d7cd4d384c0c70d1e",
  "tree": "5787bb8c9708c99595787e9b96c19c6e981aed5f",
  "parents": [
    "1fbc0bbde42def47931206124a6941bb2c291835"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Thu Jun 02 23:34:01 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Thu Jun 02 23:34:01 2022 +0100"
  },
  "message": "Added buffer to UART signals to interrupt and status register. This should help with some timing issues. Also fixed a bug where the wrong signal was being used for the Rx data available interrupt.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "62a9d5a314fd618bcc2118fc4ebe817480715705",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/UART/UARTDevice.v",
      "new_id": "07cf361300e815bc124e63817e322524fdfdd14b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/UART/UARTDevice.v"
    }
  ]
}