)]}'
{
  "commit": "5292e79345a3c1977fbbf6c677952160ced134c8",
  "tree": "6bb837072115460edc0cb16c5d24068a7795164e",
  "parents": [
    "e768ce4a4df4d80baf81c33713ddd75d066d6261"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Fri Jun 03 11:18:24 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Fri Jun 03 11:18:24 2022 +0100"
  },
  "message": "Added buffers to irq lines from GPIO and PWM peripherals.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fdfca26e63551af714054a8e34628039d0f20478",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/GPIO/GPIODevice.v",
      "new_id": "948445ef941f20756f55145dfbdc46d79f23054f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/GPIO/GPIODevice.v"
    },
    {
      "type": "modify",
      "old_id": "c1ca2e429578aab459a91d503db2932aedccb457",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/PWM/PWMOutput.v",
      "new_id": "d226582fa0561da21a560fdf70bb4917bc1c2d3a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/PWM/PWMOutput.v"
    }
  ]
}