)]}'
{
  "commit": "4dfa7912db0fd9c483ea31d0d0a4f8951112db25",
  "tree": "3944d40c61bab56f00e7ddc6e78fc0c929426732",
  "parents": [
    "2b18208b708cd51459ee46c3c1d1531eed5ddbed"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 22:33:34 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 22:33:34 2022 +0100"
  },
  "message": "Added UART test .\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3fd0b560d9be0c6502de68db4de1ee1722b3b478",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsUART/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c96a07a3281a644cd0c88b6c835938a1491f1455",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsUART/peripheralsUART.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0d5d2e9671eaac1a3cad3febe386983757db18cd",
      "new_mode": 33188,
      "new_path": "verilog/dv/peripheralsUART/peripheralsUART_tb.v"
    }
  ]
}
