diff --git a/openlane/Blink/config.tcl b/openlane/Blink/config.tcl
new file mode 100644
index 0000000..69fed62
--- /dev/null
+++ b/openlane/Blink/config.tcl
@@ -0,0 +1,58 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(ROUTING_CORES) "8"
+
+set ::env(DESIGN_NAME) Blink
+
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/Blink/Blink_top.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 100 100"
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.4
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper) 
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
+# 
+# set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(RT_MAX_LAYER) {met4}
+
+# You can draw more power domains if you need to 
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4 
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
diff --git a/openlane/Blink/pin_order.cfg b/openlane/Blink/pin_order.cfg
new file mode 100644
index 0000000..81b39b8
--- /dev/null
+++ b/openlane/Blink/pin_order.cfg
@@ -0,0 +1,8 @@
+#BUS_SORT
+
+#W
+clk
+nrst
+
+#W
+blink
\ No newline at end of file
diff --git a/verilog/rtl/Blink/Blink_top.v b/verilog/rtl/Blink/Blink_top.v
new file mode 100644
index 0000000..29d125a
--- /dev/null
+++ b/verilog/rtl/Blink/Blink_top.v
@@ -0,0 +1,15 @@
+module Blink (
+`ifdef USE_POWER_PINS
+		inout vccd1,	// User area 1 1.8V supply
+		inout vssd1,	// User area 1 digital ground
+`endif
+
+		input wire clk,
+		input wire nrst,
+
+		output wire blink
+	);
+
+counter #(.WIDTH(1), .DIV(24), .TOP(0)) ctr(.clk(clk), .rst(!nrst), .halt(1'b0), .value(blink));
+	
+endmodule
\ No newline at end of file