Fixed uart device outputting data when not enabled. Also fixed uart using the wrong cycles per bit value.
diff --git a/verilog/rtl/Peripherals/UART/UARTDevice.v b/verilog/rtl/Peripherals/UART/UARTDevice.v
index c6b6e25..e52e86f 100644
--- a/verilog/rtl/Peripherals/UART/UARTDevice.v
+++ b/verilog/rtl/Peripherals/UART/UARTDevice.v
@@ -181,7 +181,7 @@
.clk(clk),
.rst(rst || (clearWriteData[0] && clearWriteEnable && peripheralBus_byteSelect[0])),
.cyclesPerBit(cyclesPerBit),
- .rx(uart_rx),
+ .rx(uart_en ? uart_rx : 1'b1),
.dataOut(rxByteIn),
.dataAvailable(rxOutAvailable));
@@ -192,7 +192,7 @@
.rst(rst || (clearWriteData[1] && clearWriteEnable && peripheralBus_byteSelect[0])),
.cyclesPerBit(cyclesPerBit),
.tx(uart_tx),
- .blockTransmition(1'b0),
+ .blockTransmition(!uart_en),
.busy(txSendBusy),
.dataIn(txByteOut),
.dataAvailable(txByteOutAvailable));
diff --git a/verilog/rtl/Peripherals/UART/UART_rx.v b/verilog/rtl/Peripherals/UART/UART_rx.v
index 6e983ff..bf8e8ce 100644
--- a/verilog/rtl/Peripherals/UART/UART_rx.v
+++ b/verilog/rtl/Peripherals/UART/UART_rx.v
@@ -15,14 +15,15 @@
localparam STATE_WAIT_FULL = 2'b10;
localparam STATE_WAIT_HIGH = 2'b11;
- reg [1:0] state = STATE_IDLE;
- reg [CLOCK_SCALE_BITS-1:0] delayCounter = {CLOCK_SCALE_BITS{1'b0}};
- reg [2:0] bitCounter = 3'b0;
- reg [7:0] savedData = 8'b0;
+ reg[1:0] state = STATE_IDLE;
+ reg[CLOCK_SCALE_BITS-1:0] delayCounter = {CLOCK_SCALE_BITS{1'b0}};
+ wire[CLOCK_SCALE_BITS-1:0] nextDelayCounter = delayCounter + 1;
+
+ reg[2:0] bitCounter = 3'b0;
+ reg[7:0] savedData = 8'b0;
reg newData = 1'b0;
wire[CLOCK_SCALE_BITS-1:0] halfBitCounterValue = { 1'b0, cyclesPerBit[CLOCK_SCALE_BITS-1:1] };
- wire[CLOCK_SCALE_BITS-1:0] fullBitCounterValue = cyclesPerBit[CLOCK_SCALE_BITS-1:1] - 1;
always @(posedge clk) begin
if (rst) begin
@@ -51,16 +52,16 @@
end
STATE_WAIT_HALF: begin
- if (delayCounter == halfBitCounterValue) begin
+ if (nextDelayCounter == halfBitCounterValue) begin
delayCounter = 0;
state = STATE_WAIT_FULL;
end else begin
- delayCounter = delayCounter + 1;
+ delayCounter = nextDelayCounter;
end
end
STATE_WAIT_FULL: begin
- if (delayCounter == fullBitCounterValue) begin
+ if (nextDelayCounter == cyclesPerBit) begin
savedData = {rx, savedData[7:1]};
delayCounter = 0;
if (bitCounter == 3'h7) begin
@@ -68,7 +69,7 @@
newData = 1'b1;
end else bitCounter = bitCounter + 1;
end else begin
- delayCounter = delayCounter + 1;
+ delayCounter = nextDelayCounter;
end
end
diff --git a/verilog/rtl/Peripherals/UART/UART_tx.v b/verilog/rtl/Peripherals/UART/UART_tx.v
index 6c78d5b..3fc73a5 100644
--- a/verilog/rtl/Peripherals/UART/UART_tx.v
+++ b/verilog/rtl/Peripherals/UART/UART_tx.v
@@ -19,13 +19,12 @@
reg[1:0] state = STATE_IDLE;
reg[CLOCK_SCALE_BITS-1:0] delayCounter = {CLOCK_SCALE_BITS{1'b0}};
+ wire[CLOCK_SCALE_BITS-1:0] nextDelayCounter = delayCounter + 1;
+
reg[2:0] bitCounter = 3'b0;
reg[7:0] savedData = 8'b0;
reg outputBuffer = 1'b0;
- wire[CLOCK_SCALE_BITS-1:0] nextDelayCounter = delayCounter + 1;
- wire[CLOCK_SCALE_BITS-1:0] fullBitCounterValue = cyclesPerBit[CLOCK_SCALE_BITS-1:1] - 1;
-
always @(posedge clk) begin
if (rst) begin
state = STATE_IDLE;
@@ -66,7 +65,7 @@
STATE_START_BIT: begin
outputBuffer = 1'b0;
- if (delayCounter == fullBitCounterValue) begin
+ if (nextDelayCounter == cyclesPerBit) begin
delayCounter = 0;
state = STATE_DATA;
end else begin
@@ -77,7 +76,7 @@
STATE_DATA: begin
outputBuffer = savedData[bitCounter];
- if (delayCounter == fullBitCounterValue) begin
+ if (nextDelayCounter == cyclesPerBit) begin
delayCounter = 0;
if (bitCounter == 3'h7) state = STATE_STOP_BIT;
else bitCounter = bitCounter + 1;
@@ -89,7 +88,7 @@
STATE_STOP_BIT: begin
outputBuffer = 1'b1;
- if (delayCounter == fullBitCounterValue) begin
+ if (nextDelayCounter == cyclesPerBit) begin
state = STATE_IDLE;
end else begin
delayCounter = nextDelayCounter;
